Input resistance for compact packaging of semiconductor dies

Abstract

Disclosed are means of using input resistors on pads of compact packages for semiconductor dies, and methods for constructing such means and systems and apparatuses for using such means. An example means (100) includes: a substrate (102); a first semiconductor die (106-1) disposed on the substrate and implementing a first field-effect transistor having a gate terminal accessible via a first gate pad (108-G); and a second semiconductor die (106-2) disposed on the substrate and implementing a second field-effect transistor having a gate terminal accessible via a second gate pad (108-G). A conductive element (112) is configured to electrically couple the first gate pad and the second gate pad to a shared gate node, wherein a first resistor (110-1) (between the conductive element and the first gate pad) is coupled to the first gate pad (108-G), and a second resistor (110-2) (between the conductive element and the second gate pad) is coupled to the second gate pad.

Description

Background Technology

[0001] Packaging plays a crucial role in ensuring the proper functioning, reliability, and ease of use of electronic components. Proper packaging of electronic components serves various purposes. For example, one function of packaging can be to protect the delicate semiconductor dies inside the package from physical damage, contamination, electrostatic discharge (ESD), and other threats that could render the component inoperable if the dies are not properly protected. Similarly, packaging can provide a barrier against moisture and other environmental factors that can lead to component degradation and failure. Another function of packaging can be to facilitate electrical connections between external circuitry (e.g., external circuitry on a circuit board to which the electronic component is coupled) and the internal circuitry of the component. For example, metal leads, wires, bumps, and other such features allow the electrical component to be soldered onto or otherwise connected to a printed circuit board. Heat dissipation can also be provided by packaging, which is configured to facilitate the transfer of heat from the operational elements of the component (e.g., the semiconductor dies inside the device package). Summary of the Invention

[0002] Power electronic devices are configured to handle relatively large voltages and currents for automotive, industrial, and other high-power applications and use cases. To handle particularly large amounts of power, multiple transistors (e.g., power MOSFETs or other types of transistors) can be connected in parallel to efficiently share a large current load to be switched or otherwise manipulated. In this type of scenario, matching the current handled by each component in the parallel configuration can be a challenge. Therefore, specific gate resistors can be implemented at the gate of each parallel transistor in a given circuit to help balance the current. To avoid increasing the footprint of the circuit package by connecting surface-mount gate resistors to each parallel transistor in a given circuit, the systems and methods described herein utilize resistors directly disposed on the pads of the semiconductor die implementing the power transistors (e.g., on the gate pads of power FETs, etc.). In this way, proper current balance can be achieved while simultaneously providing a compact package for the circuit implementing the parallel transistors. For example, an automotive power inverter device applying the pad-to-pad input resistance principle described herein can provide effective current balance among the parallel transistors while also providing a compact form factor, correspondingly reduced complexity and cost, and other benefits described herein.

[0003] As an example implementation, an apparatus (e.g., an electronic component, such as a packaged semiconductor device) may include: 1) a substrate; 2) a first semiconductor die disposed on the substrate and implementing a first field-effect transistor having a gate terminal accessible via a first gate pad; 3) a second semiconductor die disposed on the substrate and implementing a second field-effect transistor having a gate terminal accessible via a second gate pad; 4) a conductive element configured to electrically couple the first gate pad and the second gate pad to a shared gate node; 5) a first resistor coupled between the conductive element and the first gate pad to the first gate pad; and 6) a second resistor coupled between the conductive element and the second gate pad to the second gate pad.

[0004] As another example implementation, a power inverter device (e.g., an automotive power inverter for electric or hybrid vehicles) may include: a radiator; and a plurality of power inverter units mounted on the radiator. The plurality of power inverter devices may include a power inverter device comprising: 1) a substrate; 2) a first semiconductor die disposed on the substrate and implementing a first field-effect transistor having a gate terminal accessible via a first gate pad; 3) a second semiconductor die disposed on the substrate and implementing a second field-effect transistor having a gate terminal accessible via a second gate pad; 4) a conductive element configured to electrically couple the first gate pad and the second gate pad to a shared gate node; 5) a first resistor coupled to the first gate pad between the conductive element and the first gate pad; and 6) a second resistor coupled to the second gate pad between the conductive element and the second gate pad.

[0005] As another example implementation, a method (e.g., a manufacturing process for manufacturing an apparatus or device, such as those described above) may include: 1) preparing a substrate; 2) coupling a first semiconductor die to the substrate, the first semiconductor die implementing a first field-effect transistor having a gate terminal accessible via a first gate pad; 3) coupling a second semiconductor die to the substrate, the second semiconductor die implementing a second field-effect transistor having a gate terminal accessible via a second gate pad; 4) coupling a first resistor to the first gate pad and a second resistor to the second gate pad; and 5) coupling a conductive element to the first resistor on the first gate pad and to the second resistor on the second gate pad.

[0006] Each of the foregoing exemplary embodiments should be understood as illustrative of an embodiment conforming to the type described below. It should be understood that these examples are not intended to be limiting, and any aspect mentioned above or described herein may be used in conjunction with any embodiment based on the principles described herein. Details of these and other embodiments are set forth in the accompanying drawings and the following description. Other features will also be apparent from the following description, drawings, and claims. Attached Figure Description

[0007] Figure 1 Different views of an exemplary embodiment of a device according to the principles described herein are shown, the device being characterized by input resistors on pads for a compact package of a semiconductor die.

[0008] Figure 2 Some aspects of an exemplary implementation of a power inverter device based on the principles described herein are shown, characterized by input resistance on pads for a compact package of semiconductor dies.

[0009] Figure 3 This illustrates the principles described herein. Figure 2 Additional views of certain aspects of an exemplary power inverter device.

[0010] Figure 4A Examples of conventional power inverter devices based on the principles described herein are illustrated. Figure 2 Some contrasting aspects between exemplary power inverter devices.

[0011] Figure 4B An example is illustrated in another conventional power inverter device based on the principles described herein. Figure 2 Some contrasting aspects between exemplary power inverter devices.

[0012] Figure 4C Examples are given based on the principles described in this article. Figure 4B Traditional power inverter devices and Figure 2 Additional comparison aspects between exemplary power inverter devices.

[0013] Figure 5 Different views of a power inverter device integrated with a lead frame according to the principles described herein are shown.

[0014] Figure 6 Some aspects of an encapsulated power inverter device, encapsulated in molding compound, are shown according to the principles described herein.

[0015] Figure 7 Some aspects of an exemplary power inverter device based on the principles described herein are shown, characterized by a plurality of power inverter units mounted on a heat sink.

[0016] Figure 8 An exemplary method for constructing a device based on the principles described herein is shown, the device being characterized by input resistors on pads of a compact package for a semiconductor die. Detailed Implementation

[0017] The principles described herein relate to input resistors (e.g., input resistors on pads) for compact packages of semiconductor dies. Various specific implementations of these principles include electronic components, devices, equipment, systems, etc., as well as methods, processes, and techniques for constructing such electronic components, devices, equipment, systems, etc.

[0018] Many electronic applications involve relatively small voltages and currents, allowing for the use of small, even extremely small, electronic components to handle and manipulate these voltages and currents. However, other electronic applications may involve larger voltages and currents. For example, in the automotive sector (e.g., electric vehicles (EVs), hybrid vehicles, etc.) and / or in other industrial environments with large machinery, applications and use cases may employ electronics that utilize large amounts of electricity, thus requiring components that are configured accordingly. To properly handle and manipulate these larger voltages and currents, power electronics, such as power field-effect transistors (FETs) and / or other types of power transistors, may be employed.

[0019] In some cases, sufficient current may be available during operation to allow a function that would otherwise be performed by a single component (e.g., a single power transistor) to be performed by multiple such components instead. For example, several power FETs may be connected in a way that allows transistors to share the current load of a circuit (e.g., a half-bridge or full-bridge circuit, as an example, operating within a power inverter circuit) and essentially function as a single, unified transistor in the circuit.

[0020] However, significant technical challenges can arise when multiple different transistors are configured to interact in this manner to perform a single function. This challenge involves balancing the current load between transistors connected in parallel (i.e., reducing the deviation in the amount of current flowing through different transistors) and ensuring an equal distribution of current (or other desired or predetermined distribution ratio) among the different transistors in the circuit. If different FETs are driven to different degrees due to different voltages present at their respective gate terminals, some FETs may conduct significantly more current than others, leading to various additional technical problems such as low efficiency, thermal issues, runaway current (which can cause components to be used outside of operating parameters), and shortened operating life.

[0021] At least one technical solution described herein for avoiding and / or otherwise mitigating these technical problems involves applying a gate resistor to each gate terminal of each of a plurality of parallel FETs used in a circuit. However, conventional methods of adding gate resistors to discrete power FETs can introduce additional technical problems. For example, assuming a device package comprises several parallel transistors (e.g., multiple FETs in a power inverter device, all whose gate terminals are driven by the same node or signal), these transistors can be implemented as individual semiconductor dies, all disposed on a uniform substrate of the device package. For each discrete component (e.g., a surface mount resistor, etc.) associated with each semiconductor die within the device, the device substrate typically needs to be large enough to accommodate the discrete component and any associated substrate wiring (e.g., pads and traces on the substrate, gaps between conductive pads and traces, etc.).

[0022] While such an increase in area may be appropriate for some devices and / or in certain situations, it can be costly and otherwise undesirable. For example, for device packaging designs that require a compact and efficient package (i.e., a package that is as small and inconspicuous as possible in size, weight, shape, etc.), the additional discrete components (e.g., surface mount components disposed on the substrate) defeat the design goals. More specifically, the device package tends to become less compact and efficient when a gate resistor (a discrete semiconductor die used to implement a FET within the device) is added to the design.

[0023] The technical solutions described herein address these technical problems by allowing the required gate resistance to be included (and thus current balancing within auxiliary circuitry, etc.) without requiring additional substrate area that would make the device package less compact (i.e., without making the overall size or footprint of the device larger or less efficient than it could otherwise be). For example, as described below, the specific implementations described herein use an input resistance on a pad as the gate resistance of a semiconductor die (such as a discrete FET die). For example, instead of a surface mount resistor (located near the die and connected in series with the gate of the FET), a leadless resistor component can be directly mounted on the gate pad of the semiconductor die, wherein gate interconnects (e.g., wires connecting all the gates of various FETs) are connected to the resistor. As will be illustrated and described, the gate pad provides access to the gate of the FET, allowing the leadless resistor to be directly mounted on the pad to have all the benefits of a gate resistor without any of the disadvantages and overheads associated with surface mount resistors and their placement, interconnection, etc.

[0024] The technical benefits of these solutions involve the functional benefits of gate resistors (i.e., the improved current sharing and current balancing, energy saving, increased device efficiency and effectiveness, etc., as described) and package-related benefits arising from the reduction in substrate size (e.g., more compact packages reduce cost and complexity, allow for more flexible designs, etc.). In other words, the technical solutions presented herein use stackable gate interconnects to support effective and efficient current balancing without compromising other objectives (such as those related to compact packaging).

[0025] While the principles described herein can be advantageous in a variety of contexts, applications, and use cases, specific examples of power inverter devices will be used throughout the following description as examples of application. As will be described, power inverters can be used in various contexts, such as converting direct current (DC) power from the battery of an electric vehicle into alternating current (AC) power, which can be used to perform the mechanical work involved in propelling the electric vehicle. Therefore, and as will be described in more detail below, the automotive inverter device described herein can apply the principle of input resistance on pads to provide effective current balance between parallel transistors (i.e., reduce current deviation), while also providing a compact form factor and other benefits described herein.

[0026] Various specific embodiments will now be described in more detail with reference to the accompanying drawings. It should be understood that the specific embodiments described below are provided as non-limiting examples and are applicable to a wide range of situations. Additionally, it should be understood that other specific embodiments not expressly described herein may also fall within the scope of the claims set forth below. Input resistors on pads of compact packages for semiconductor dies, based on the principles described herein, can produce any or all of the technical benefits mentioned above, as well as various additional technical benefits that will be described below and / or become apparent.

[0027] Figure 1 Different views of an exemplary embodiment of a device according to the principles described herein are shown, characterized by input resistors on pads for a compact package of a semiconductor die. More specifically, "front views" and "side views" of certain elements of device 100 are shown. Figure 1 The package is shown as including: 1) a substrate 102; 2) conductive portions 104-1 and 104-2 located on the substrate 102; 3) a first semiconductor die 106-1 and a second semiconductor die 106-2, each disposed on the substrate 102 and including various pads 108; 4) a first resistor 110-1 (associated with semiconductor die 106-1) and a second resistor 110-2 (associated with semiconductor die 106-2); and 5) a conductive element 112 that electrically couples specific elements of the semiconductor die to the substrate, as will be described. It should be understood that while the illustrated elements may be among those most relevant to the specific implementation of the input resistor on the pads of the compact package for semiconductor dies described herein, various additional and / or alternative elements may be present (not listed here). Figure 1 The elements shown herein may be included in this specific embodiment of device 100, in other specific embodiments of device 100 described herein, and in other specific embodiments of device 100 not explicitly illustrated herein but conforming to the principles described herein. Each of the illustrated elements will now be described in more detail.

[0028] Device 100 is shown as including a substrate 102 having multiple portions, specifically (in this example) including a first portion 104-1 and a second portion 104-2 electrically isolated from the first portion. Substrate 102 may be implemented from a direct-bonded metal (DBM) substrate (such as a direct-bonded copper (DBC) substrate, etc.), which employs multiple layers of conductors (e.g., metals, such as copper, etc.) on an insulating sheet (e.g., a ceramic plate, etc.). This structure can be used to facilitate electrical insulation between the different portions 104-1 and 104-2 to distribute signals to various locations (e.g., using signal traces, power planes, or ground planes, etc.), thereby providing thermal management for the device (e.g., aiding in heat dissipation due to the high thermal conductivity of the conductors), etc.

[0029] The ceramic plate of substrate 102 (i.e., the white part without shadows) includes a first side (e.g., the side visible in the orthographic view and located at the top when the plate is oriented in the side view) and a second side opposite the first side (e.g., the side not visible in the orthographic view and located at the bottom when the plate is oriented in the side view). The first side of the ceramic plate may be directly bonded to a first metal layer on the top or front side of substrate 102, and the first metal layer in this example is patterned to include different portions 104-1 and 104-2. Subsequently, the second side of the ceramic plate may be directly bonded to a second metal layer (in... Figure 1 The second metal layer (illustrated in a side view as having a single portion 104-3) is configured to facilitate heat transfer from the device (e.g., acting as a heat sink to dissipate heat from the heat-generating elements of the device, as will be described below). In other examples of substrate 102, both the first and second sides may be patterned to include various portions (e.g., traces, planes, etc.), or both sides may comprise solid metal planes without any such electrically isolated portions. Furthermore, it should be understood that the sides of the substrate may aid in heat dissipation.

[0030] Specific implementations of the DBM-based substrate 102 can provide various advantages for packaged devices, such as device 100 and / or other devices described herein. For example, this type of substrate 102 can be configured to handle relatively large currents and voltages due to the effective thermal management provided by the aforementioned heat dissipation. This can be useful for devices that generate and / or consume large amounts of power, such as power modules. For example, the devices described herein can realize power inverters for power systems or electric vehicles, motor drives for electrical appliances or electric vehicles, and various other examples that can be used to implement specific implementations. Other examples of advantages that specific implementations of the DBM-based substrate 102 can provide include: improved reliability (because a strong and reliable connection can be formed by the direct bonding process between the ceramic layer and the metal layer), reduced size and weight (because the DBM substrate is relatively thin and lightweight compared to other packaging materials), etc.

[0031] In some embodiments, a DBM substrate (e.g., a direct-bonded copper (DBC) substrate) may be used, which includes an insulating layer disposed between a first metal layer and a second metal layer. For example, the insulating layer may be a ceramic layer. In some embodiments, the insulating layer may be or may include, for example, a ceramic material, such as alumina (Al2O3) or aluminum nitride (AlN).

[0032] In some implementations, a DBM substrate can be formed by bonding one or more metal layers (e.g., a first metal layer, a second metal layer, etc.) to an insulating layer (e.g., a ceramic layer, etc.). For example, one or more metal layers can be bonded to an insulating layer using, for example, a high-temperature process.

[0033] In some embodiments, the first metal layer and / or the second metal layer may be configured to function as a heat sink. In some embodiments, the first metal layer and / or the second metal layer may be coupled to a heat sink. In some embodiments, at least a portion of one or more of the first metal layer or the second metal layer may be exposed by a molding material.

[0034] In some embodiments, the first metal layer and / or the second metal layer may be or may include a patterned metal layer, which includes one or more conductive traces. In some embodiments, the first metal layer and / or the second metal layer may be or may include a patterned layer configured to form one or more electrical circuits, one or more conductive blind vias and / or through-holes, etc.

[0035] In some embodiments, the DBM substrate may be or may include a direct-bonded copper (DBC) substrate. In some embodiments, such as in a DBC substrate embodiment, the first metal layer and / or the second metal layer may be implemented as copper layers.

[0036] Regardless of how the substrate 102 is implemented (e.g., as a DBM substrate or otherwise). Figure 1 A portion 104-1 is shown to be electrically isolated from another portion 104-2. For example, the shapes labeled portions 104-1 and 104-2 can be understood as representing separate planes of directly bonded metal on an insulator (e.g., a ceramic sheet), or in other specific embodiments, representing separate components of a lead frame (these components may be held together during the manufacturing process by connecting rods or other such mechanisms, which will later be removed and not...). Figure 1(As explicitly shown in the image). In this example, the same portion 104-1 of substrate 102 is shown as accommodating both parallel semiconductor dies 106-1 and 106-2. However, in other examples, each semiconductor die may be implemented on a separately isolated portion, and other portions of substrate 102 (forming pads and traces for other components) may also be included. In this specific embodiment, portion 104-2 is shown as connected to conductive element 112, which is coupled to the gate pads of a plurality of semiconductor dies. Thus, as will be described, portion 104-2 may be associated with a particular circuit node (e.g., a shared gate node) such that this portion can be used as a connection point for (e.g., a separate lead frame described below) package leads and / or other conductive elements.

[0037] Semiconductor dies 106-1 and 106-2 are shown disposed on substrate 102 (both located on the same portion 104-1 in this particular example). These dies may each implement a single field-effect transistor (FET), such as a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), or other suitable transistor. More specifically, where device 100 is intended for applications or use cases involving large voltages and / or currents (e.g., such as the automotive power inverter use case described herein), each of the FETs implemented by the first semiconductor dies 106-1 and 106-2 may be a power FET (e.g., a power MOSFET) or other power transistor.

[0038] In some embodiments, semiconductor dies 106-1 and 106-2 may each implement the same transistor or similar transistors made using at least the same type of semiconductor. For example, both semiconductor die 106-1 and semiconductor die 106-2 may be SiC dies made using silicon carbide (SiC) semiconductors, or both may be Si dies made using silicon (Si) semiconductors. In other embodiments, semiconductor die 106-1 and semiconductor die 106-2 may be hybrid dies made using different semiconductors. For example, semiconductor die 106-1 may be a Si die made using silicon (Si) semiconductors, while semiconductor die 106-2 may be a SiC die made using silicon carbide (SiC) semiconductors.

[0039] In some embodiments, one or more semiconductor dies (e.g., one or more semiconductor components) may be or may include power semiconductor dies. In some embodiments, semiconductor dies may implement one or more transistors or a portion thereof (or transistor-based circuitry). For example, one or more of the following may be implemented on a semiconductor die: MOSFET devices, IGBTs, ICs, inverters, power conversion circuits, bridge circuits, fast recovery diodes (FRDs), diodes, etc. In some embodiments, components implemented (or partially implemented) by one or more semiconductor dies may be used or included in electric vehicles (EVs).

[0040] More than one semiconductor die may be included in the specific embodiments described herein. In some embodiments involving more than one semiconductor die, different semiconductor substrates (e.g., silicon carbide (SiC) substrates, silicon (Si) substrates, gallium nitride (GaN) substrates, etc.) may be used to fabricate different semiconductor dies. In other words, for example, different semiconductor dies may be fabricated on different semiconductor wafers or materials. This may be referred to as a hybrid die configuration. For example, a first semiconductor die may be formed using a SiC substrate, and a second semiconductor die (different from the first semiconductor die) may be formed using a silicon substrate. As another example, an IGBT may be fabricated using a SiC substrate, while a controller may be fabricated using a silicon substrate.

[0041] In an example implementation, a first semiconductor die may be connected to a second semiconductor die, for example, via an electrical connection (e.g., a wire bond, an electrical clip, a connector, etc.) extending directly from the first die to the second die, or via a trace formed in a first conductive layer (e.g., a metal layer) of an electronic power substrate. The first semiconductor die among a plurality of semiconductor dies may also be connected to lead frame posts via electrical connections (such as wire bonds or clips).

[0042] In some exemplary embodiments, the package (e.g., a power module) may be a hybrid device package comprising one or more semiconductor dies integrated onto a uniform electronic power substrate (e.g., a ceramic substrate, DBM or DBC substrate, AMB substrate, elastomeric substrate, organic substrate, phenolic substrate, or PCB / FR-4 substrate). In some embodiments, multiple semiconductor devices may be fabricated on the same substrate (such as a SiC substrate suitable for high-power applications).

[0043] In some implementations, one or more semiconductor dies may be embedded within a layer (rather than being surface-mounted). For example, one or more semiconductor dies may be disposed within a recess or cavity of a layer (e.g., a substrate, printed circuit board, conductive layer, insulating layer, etc.).

[0044] Each semiconductor die 106-1 and 106-2 is shown as including a plurality of pads 108, which serve as (input / output) terminals for the transistors implemented on the dies. Depending on the type of transistors implemented and their specific construction (e.g., layout, etc.), the pads 108 may have various sizes, shapes, and arrangements. However, for the purposes of this embodiment and other embodiments described below, it will be assumed that each semiconductor die 106-1 and 106-2 implements a FET having at least a gate terminal, a source terminal, and a drain terminal. Figure 1 As indicated by the letters in the reference markings, the source terminal of each FET can be accessed by the corresponding source pad 108-S on the die, and the gate terminal of each FET can be accessed by the corresponding gate pad 108-G. The corresponding drain pad (which provides access to the drain of each FET) is not specified in the reference markings. Figure 1 As shown, but to be understood, is located on the back side of the die to physically and electrically contact the conductive surface of portion 104-1 of substrate 102. Other pads on each die (e.g., generally marked pads (without letters), such as pad 108) may provide access to other terminals that can be used to implement a particular specific implementation. For example, one or more Kelvin sensing pads may be electrically coupled to other terminals and configured to facilitate accurate measurement of voltage or current at various terminals of the power transistor.

[0045] Each of semiconductor dies 106-1 and 106-2 (and other components described herein and those that may be included in device 100 but not explicitly stated in the document) Figure 1 The components shown herein can be physically and electrically coupled to the substrate 102 and to other components (e.g., to each other, to other components, to leads that allow external access to the die, etc.) in any suitable manner. As some examples, the electrical connections of device 100 and other specific embodiments described herein can be achieved via soldering, sintering, conductive adhesives, other suitable coupling techniques and / or a combination of two or more of these techniques.

[0046] In some specific implementations, welding can be or may include a process of joining two surfaces (e.g., metal surfaces) together using a molten filler metal (e.g., a metal alloy, tin (Sn), lead (Pb), silver (Ag), copper (Cu)), wherein the molten filler metal may be referred to as solder or welding material.

[0047] In some embodiments, sintering can be or may include a process in which particles are melted together to form a solid block by means of, for example, a combination of pressure and / or heat (which is applied but does not melt the material). In some embodiments, sintering may include agglomerating a material (e.g., a powder material) into a solid block or porous block by heating (and in some cases, compressing) the material without liquefying it. In some embodiments, materials that can be used for sintering include metals such as silver (Ag), copper (Cu), and / or metal alloys. In some embodiments, sintered joints may have the desired electrical and / or thermal conductivity, durability, and a relatively high melting temperature.

[0048] In some specific implementations, one or more components of the components described herein may be coupled using materials such as, for example, welding materials, sintered materials (e.g., silver, copper) and / or other metal-to-metal bonding materials.

[0049] In some specific implementations, the coupling of components can be performed using processes such as welding, sintering (e.g., silver sintering, copper sintering) and / or other metal-to-metal bonding processes.

[0050] Connections between various circuit elements (e.g., pads, terminals, leads, conductive portions, etc. of a substrate) may involve conductive elements (also referred to herein as conductive components) that are themselves attached to the circuit elements to be connected. For example, conductive elements may connect different pads of a semiconductor die to each other, to other components within the device (not shown), to leads extending from the device (to facilitate connection to external circuitry), etc. Conductive elements can be implemented in any manner suitable for a particular embodiment. For example, in some examples, these conductive elements may represent wires coupled to their respective elements by means of wire bonding processes or other suitable techniques. In other examples, conductive components may represent clips of elements showing electrical connections. In still other examples, conductive elements may represent direct physical and electrical connections, whereby components are physically attached to each other by means of connection mechanisms that provide electrical connections (e.g., solder material, sintering material, conductive adhesive, etc.). In some cases, combinations of different types of conductive elements may be used within the same package or within the same embodiment. For example, some connections may use wire bonding, while others may utilize clips or direct connections.

[0051] As an example, conductive element 112 is shown in device 100 to provide a connection at a shared gate node (which can be accessed via portion 104-2, for example by a lead connected to portion 104-2, not in...) Figure 1The connection between the conductive element 112 (shown in the diagram but described in more detail below) and each of the corresponding gate pads 108-G of semiconductor dies 106-1 and 106-2 is shown. While the conductive element 112 may be illustrated and described as a wire, it should be understood that in at least some embodiments, the wire may be replaced by other conductive elements. For example, in some embodiments, one or more wire bonds may be replaced by conductive clips, which themselves may be coupled to another component (e.g., attachment pads, lead frames, semiconductor dies, etc.) in, for example, by solder (e.g., soldering process), sintering coupling (e.g., sintering process), forging, etc. In some embodiments, one or more wire bonds and / or clips may be used as input and / or output power terminals, signal terminals, power supply terminals, or other suitable terminals.

[0052] As illustrated in the front view of device 100, and even more clearly in the side view, conductive element 112 can be configured to electrically couple the first gate pad 108-G of the first semiconductor die 106-1 and the second gate pad 108-G of the second semiconductor die 106-2 via corresponding resistors 110-1 and 110-2 mounted on gate pad 108-G. In this way, resistors 110-1 and 110-2 are shown in series with conductive element 112, such that the gate terminals themselves are not directly connected to each other, but rather share a gate node connected to each gate terminal via a gate resistor (which helps current sharing / balancing). As already mentioned, and illustrated in more detail below, placing these input resistors on the pads can be very advantageous for compact packaging of semiconductor dies. Resistors 110-1 and 110-2 are not surface-mount resistors that span a dedicated and electrically isolated portion of substrate 102 (and are interconnected via patterned pads and traces or additional conductive elements such as wires or clips on substrate 102), but are directly stacked on the input pads (where resistance is required), thus not taking up additional area of ​​substrate 102.

[0053] As shown in the figure, the ability of resistors 110-1 and 110-2 to be mounted on gate pad 108-G and thereby provide these benefits stems in part from the form factor of the resistors themselves (i.e., the way the resistors are packaged). More specifically, Figure 1The diagram illustrates a first resistor and a second resistor, each with a leadless package design, wherein a first terminal is located on a first surface (e.g., a top surface), and a second terminal is located on a second surface (e.g., a bottom surface) opposite the first surface. In some examples, the first resistor 110-1 and the second resistor 110-2 may have the same resistance value. Since the two resistors are coupled between the conductive element 112 and its respective gate pad 108-G, this helps each FET to have equal gate resistance, thereby aiding current balance (e.g., reducing the deviation in the amount of current flowing through each FET during switching). In other examples, the first resistor 110-1 and the second resistor 110-2 may have different resistance values ​​(e.g., to offset differences between FETs if the FETs implemented by semiconductor dies 106-1 and 106-2 are not identical, or for other reasons).

[0054] To further illustrate the form factor or package of resistors 110 (i.e., resistors 110-1 and 110-2) mounted on pads of a semiconductor die, Figure 1 An example resistor 110 is shown in a three-dimensional close-up (in the extended dashed circle extending from resistor 110-2 in both the front and side views). This example resistor 110 represents both resistors 110-1 and 110-2, as well as other resistors used herein for input resistance on pads (for compact packages of semiconductor dies). In this figure, the first and second surfaces (the second surface opposite the first surface) serve as terminals for leadless components and are shown in black shading, while the rest of the resistor component is white. It should be understood that each surface is conductive such that it can be physically and electrically coupled to conductive surfaces (e.g., pads 108-G of semiconductor dies such as semiconductor dies 106-1 or 106-2), and / or such that it can be physically and electrically coupled to conductive elements (e.g., wires, clips, etc.), such as conductive element 112.

[0055] Leadless resistor components (such as these resistors 110) may be referred to by other names (e.g., bondable components, etc.) and can be distinguished from discrete components packaged using surface mount technology (SMT) by the fact that the component has no leads and can be electrically connected to other conductors through the terminals of the component (achieved by the conductive surfaces shown). As will become apparent through the various examples described below, the leadless form factor of resistor 110 allows the component to exhibit significant flexibility in how it is physically coupled and electrically coupled to other components of the device.

[0056] In some embodiments, resistor 110 can be reversible, such that each surface performs the same function and the orientation of the resistor is irrelevant. In other embodiments, different materials can be used for different surfaces, allowing orientation to be considered when resistor 110 is mounted and integrated with a circuit. For example, one surface can be coated with a conductive adhesive configured to adhere to gate pads 108-G; while the opposing surface can be constructed of a material configured to form a strong connection (when conductive element 112 is soldered or sintered to the material). For example, the top termination can be constructed of a nickel-gold alloy (which is well-suited for direct aluminum wire bonding or other suitable connection techniques), while the bottom termination can be well-suited for various mechanisms that (e.g., by means of soldering, silver sintering, conductive adhesive, etc.) physically and electrically couple the components to the conductive surface beneath them.

[0057] Figure 2 Some aspects of an exemplary embodiment of a power inverter device 200 according to the principles described herein are shown, characterized by input resistance on pads of a compact package for a semiconductor die. It should be understood that the power inverter device 200 is an example embodiment of the device 100 described above. More specifically, this embodiment of device 100 is an integrated circuit that implements a power inverter device (e.g., a device configured to convert DC power input to AC power output, or in other words, a device to convert DC current to AC current) configured for use in automotive applications. As will be described and illustrated in more detail below, integrated circuits (such as power inverter device 200) can be used with other similar integrated circuits and other components (e.g., a heat sink, on which a device is mounted) to construct a power inverter device configured for integration with an electric vehicle or other suitable system.

[0058] As shown in the figure, certain components of the power inverter device 200 (and similar components in other figures described below) use as described in... Figure 1 A similar numbering scheme is introduced for labeling. For example, as shown in the figure, substrate 202 (implementing...) Figure 1 The substrate 102 is shown to include a plurality of conductive portions, including: portion 204-1 (implementing...) Figure 1 Part 104-1) and Part 204-2 (implementation) Figure 1 Part 104-2). Located on part 204-1, the power inverter device 200 is shown as including a first semiconductor die 206-1 (implementing...). Figure 1 Semiconductor die 106-1 and second semiconductor die 206-2 (implementation) Figure 1The semiconductor die 106-2 and various additional semiconductor dies (not explicitly labeled). Like the semiconductor dies 106-1 and 106-2 of device 100, each semiconductor die in the power inverter device 200 (including the first semiconductor die 206-1 and the second semiconductor die 206-2) can implement a power FET (e.g., a power MOSFET, a power JFET, etc.). Therefore, each semiconductor die may include multiple pads (in... Figure 2 (Not explicitly marked in the text) These pads include at least the source pads (implementation) Figure 1 The source pad 108-S and the gate pad (implementation) Figure 1 The gate pad 108-S and drain pad (located on the bottom surface, and...) Figure 1 or Figure 2 (Not visible in the middle).

[0059] On each corresponding gate pad, a resistor (also known as a gate resistor) can be mounted to help with current sharing between the various transistor dies. More specifically, the first resistor 210-1 (implements...) Figure 1 The first resistor 110-1 is shown mounted on the gate pad of the first semiconductor die 206-1, and the second resistor 210-2 (implementing...) Figure 1 The second resistor 110-2 is shown mounted on the gate pad of the second semiconductor die 206-2. Conductive element 212 (implementing...) Figure 1 Conductive element 212 is shown as connecting a shared gate node (located in portion 204-2) to each of the gate pads of the FET implemented by the semiconductor die (including the gate pads of semiconductor dies 206-1 and 206-2). It should be understood that conductive element 212 is not directly connected to the gate pads of the die, but is coupled to gate resistors (including first resistor 210-1 and second resistor 210-2) in order to help minimize any deviation in the current flowing through the various transistors (when the transistors are operating in their parallel configuration).

[0060] The power inverter device 200 can implement a half-bridge inverter circuit, which typically includes two transistors (referred to as a high-side transistor and a low-side transistor). In a half-bridge inverter, the high-side transistor is used to switch the positive voltage rail to the load, while the low-side transistor is used to switch the negative voltage rail (e.g., the ground rail) to the load. By controlling the switching of these transistors, the inverter can generate AC voltages with various amplitudes and frequencies that can be used to implement specific implementations. The half-bridge circuit can also be specifically configured to form a full-bridge circuit. This configuration will allow for more control (e.g., the polarity and magnitude of the voltage across the load), thus enabling the power inverter to be used in applications such as motor control, power conversion, etc.

[0061] For applications or use cases involving more current than a single high-side or low-side transistor can handle, multiple power transistors can be connected in parallel to collectively handle a large amount of current. In such a configuration, there will therefore be one set of transistors connected in parallel as the high-side transistors of the circuit, another set of transistors connected in parallel as the low-side transistors of the circuit, and a connection between these two sets of transistors to form a high-current half-bridge circuit. In the example of power inverter device 200, eight individual semiconductor dies (implementing eight FETs) are connected in parallel to each other on the outer column of the device (four on the left and four on the right) and are labeled as high-side transistor 206-H ("H" stands for "high-side"). Eight additional semiconductor dies (implementing eight additional FETs) are also shown as connected in parallel to each other on the inner column of the device (but not in parallel with high-side transistor 206-H) and are labeled as low-side transistor 206-L ("L" stands for "low-side").

[0062] The FETs implemented by the first and second semiconductor dies mentioned in the general example of device 100 and other exemplary embodiments described herein (e.g., first semiconductor die 206-1 and second semiconductor die 206-2 in an exemplary embodiment of power inverter device 200) can both refer to high-side transistors of a power inverter circuit (e.g., a half-bridge circuit, etc.) or low-side transistors of a power inverter circuit. Because the high-side and low-side transistors of a power inverter circuit typically each have their own gate node, the first and second FETs in these examples (which are connected to a shared gate node via conductive elements such as conductive elements 112 or 212) are typically on the same side.

[0063] In the example of power inverter device 200, Figure 2 A first FET implemented by a first semiconductor die 206-1 and a second FET implemented by a second semiconductor die 206-2 are shown configured as high-side transistors 206-H in a power inverter circuit. These high-side transistors 206-H are electrically connected in parallel so that the power inverter circuit can handle a current greater than that any one of the high-side transistors 206-H could handle operating alone. Although in Figure 2 Although not explicitly marked, it should be understood that the first and second FETs implemented by the semiconductor dies in the inner row of the device can also be connected in the same manner. For example, both the first and second FETs will be configured as low-side transistors 206-L in a power inverter circuit, wherein the low-side transistors 206-L are also connected in parallel so that the power inverter circuit can handle more current than either of the low-side transistors 206-L could handle if either of the low-side transistors 206-L were operating alone.

[0064] It should be understood that in some specific embodiments including the power inverter device 200 (although many components are not explicitly labeled due to space constraints), the input resistance principle on the pad can be applied to transistors located on both the high-side and low-side. For example, in an example where a first FET (e.g., implemented by a first semiconductor die 206-1) and a second FET (e.g., implemented by a second semiconductor die 206-2) are configured as high-side transistors electrically connected in parallel in the power inverter circuit, the device (e.g., power inverter device 200) may also include: 1) a third semiconductor die disposed on the substrate and implementing a third FET, which is configured as a first low-side transistor (e.g., one of the low-side transistors 206-L) in the power inverter circuit; and 2) a fourth semiconductor die disposed on the substrate and implementing a fourth FET, which is configured as a second low-side transistor (e.g., another low-side transistor 206-L) electrically connected in parallel with the first low-side transistor in the power inverter circuit.

[0065] It should be understood that while this general example refers to four FETs implemented by four semiconductor dies (i.e., two FETs each on the high and low sides of the power inverter circuit), more than two FETs may also be used on each side. As shown in the example of power inverter device 200, for example, the device (implementing the power inverter circuit) may include: 1) at least eight high-side FETs electrically connected in parallel (and including the first and second FETs mentioned above); and 2) at least eight low-side FETs electrically connected in parallel (and including the third and fourth FETs mentioned above).

[0066] Although only two resistors, 210-1 and 210-2, are explicitly marked on the power inverter unit 200, Figure 2The black resistors are shown mounted on the gate pads of all eight high-side transistors 206-H (including the first semiconductor die 206-1 and the second semiconductor die 206-2) and on the gate pads of all eight low-side transistors 206-L in this example. Different conductive elements (similar to the explicitly labeled conductive element 212) are shown connected in a similar manner to the rows of resistors, as described. It should be understood that these conductive elements can be connected to two shared gate nodes, one for the high side and one for the low side. In other words, conductive element 212 can be electrically coupled (not explicitly shown) to the conductive element on the right-hand side of the power inverter device 200 that connects to the gate resistor of the high-side transistor 206-H, while the two conductive elements on the inner row of the low-side transistors 206-L that connect to the gate resistor can similarly be electrically coupled to each other at a shared node (again, not explicitly shown).

[0067] As described, these gate resistors help balance the current flowing through each of the high-side transistor 206-H and the low-side transistor 206-L, so that there is virtually no deviation between the amounts of current they help switch. For each resistor (or at least for each resistor on the high side and each resistor on the low side), the resistance value can be relatively low (e.g., 5 ohms, 10 ohms, etc.) and can be equal. The resistors can be used to decouple the gates of the FETs to prevent oscillations and help ensure that each FET turns on at a similar voltage and speed to draw a similar amount of current.

[0068] Figure 3 The above text shows about Figure 2 Additional views of certain aspects of the described power inverter device 200. First, Figure 3 Some components disposed within the power inverter unit 200 are shown (e.g., from...). Figure 2Close-up view 300-A shows the elements in the left column of the high-side transistor 206-H described and labeled in the diagram. As shown in close-up view 300-A, the substrate 202 includes a conductive portion 204-1 on which various semiconductor dies are disposed, including a first semiconductor die 206-1 and a second semiconductor die 206-2. Since these semiconductor dies implement FETs (such as power MOSFETs), they may include a set of identical pads as described. On the intermediate gate pads, close-up view 300-A shows corresponding resistors 210-1 (on the gate pad of the first semiconductor die 206-1) and 210-2 (on the gate pad of the second semiconductor die 206-2). Conductive element 212 is also shown as coupled to these resistors 210 (and indirectly coupled to the gate pads on which the resistors are mounted) and extends in both directions to couple all the gate pads (and corresponding input resistors) of the high-side transistors of the power inverter device to a shared gate node.

[0069] exist Figure 2 Some other elements depicted but not specifically identified are also illustrated and labeled. Figure 3 In the example shown, clip 314-1 (coupled to the source pad of the first semiconductor die 206-1) and corresponding clip 314-2 (coupled to the source pad of the second semiconductor die 206-2) are shown, along with conductive element 316 that connects these clips 314-1 and 314-2 (and other clips on other FETs, not shown in view 300-A) together and to the shared source node of the high-side transistor.

[0070] Figure 3 Perspective view 300-B further illustrates a resistor in resistor 210 (e.g., either resistor 210-1 or 210-2, or another resistor included in the power inverter device 200) coupled to the gate pad of semiconductor die 206 (e.g., either semiconductor die 206-1 or 206-2, or another semiconductor die included in the power inverter device 200). The substrate 202 and the portion 204 housing the semiconductor die 206 are also shown in perspective view 300-B, as are the conductive element 212 and the clip 314 (e.g., either clip 314-1 or 314-2, or another clip included in the power inverter device 200) coupled to the source pad of the die.

[0071] Figures 4A to 4C This is shown in the power inverter device 200 (as described above regarding...) Figures 2 to 3In contrast to the described and illustrated alternative power inverter devices (e.g., conventional devices, etc.), the alternative power inverter devices (different from power inverter device 200) do not implement the pad-on-pad input resistance principle for compact packages of semiconductor dies described herein.

[0072] exist Figure 4A The diagram shows a contrast between the following two: 1) a conventional power inverter device 422, which is not an implementation of device 100 and does not utilize on-pad input resistors to achieve a compact package; and 2) a power inverter device 200, which is an implementation of device 100 that utilizes on-pad input resistors as described herein to achieve a compact package.

[0073] Like power inverter device 200, power inverter device 422 includes a number of transistors (e.g., power FETs, etc.) connected in parallel to form a half-bridge circuit. Some of these transistors are labeled transistor 424 and should be understood as transistors implemented as described above on semiconductor die 206, including similar pads (although the pads are on...). Figure 4A (Not explicitly outlined or labeled in the text). For the same reasons described above for power inverter device 200 (e.g., to aid in current balance between transistors, etc.), an input resistor is provided at the gate of each of these transistors. These resistors are also drawn as black squares, and some of these resistors are labeled as resistor 426. However, while the input resistors 210 in power inverter device 200 are mounted directly on the gate pads of the transistors to support a compact package (by not taking up additional space on the substrate), the input resistors 426 of conventional power inverter device 422 are shown placed next to the respective transistors 424, on their own dedicated and isolated portions of the substrate, and connected to the transistor pads via wires.

[0074] This type of placement is shown to occupy more substrate space because each resistor 426 is mounted on a small portion of the substrate that is isolated from the portion where the transistors are mounted. Potentially, due to this placement, the substrate may be larger than it would otherwise be (thus increasing the cost of the substrate) and / or may include less space for electronic components (e.g., accommodating only 12 transistors in this example instead of the 16 transistors supported by the power inverter device 200). Furthermore, since each gate pad is connected to the gate resistor 426 via a separate wire bond, there may be more complexity, a larger error margin, lower efficiency, etc. The increased compactness of the package for the power inverter device 200, along with the corresponding increase in efficiency and current capacity (due to the presence of more transistors) and the reduction in cost and complexity (due to a smaller substrate and fewer wire connections, etc.), all contribute to significant technical effects and provide significant benefits as described.

[0075] exist Figure 4B The following are contrasted between: 1) another conventional power inverter device 428, which should also be understood as not implementing device 100 and not utilizing on-pad input resistors as described herein to achieve a compact package; and 2) the same power inverter device 200 described herein (i.e., a specific implementation of device 100 that utilizes on-pad input resistors to achieve a compact package).

[0076] While conventional power inverter device 422 includes input resistors for each transistor in the device (although the transistors are not mounted on gate pads as in power inverter device 200), conventional power inverter device 428 shows a similar arrangement to power inverter device 200, except that no gate resistors are used in the design. Specifically, as shown, the various conductive elements (including conductive element 430 located on the right side of the device) should be understood to be connected to the gate pads in a similar manner (as described for power inverter device 200). However, the difference is that without the input resistance provided by resistors (such as resistor 210), there could be more differences in current flow between the various transistors in the circuit, resulting in certain problems or at least omitting some of the benefits of on-pad input resistance described.

[0077] It is noteworthy that the top section of the conventional power inverter device 428 illustrates additional details regarding how shared nodes can be interconnected. For example, a first irregularly shaped portion of the substrate is shown connecting the ends of the leftmost and rightmost conductive elements (i.e., conductive element 430) in a single high-side shared gate node. Similarly, a second irregularly shaped portion of the substrate is shown connecting conductive elements from the inner row to form a low-side shared gate node. Similarly, other portions connect conductive elements from corresponding clips (attached to the source gate) to further parallel connect these terminals of the high-side and low-side transistors. Although these details are not depicted for power inverter device 200 (e.g., due to a shielding layer that obscures these illustrated details), it should be understood that power inverter device 200 may include the same or similar connections to form shared nodes in a similar manner.

[0078] Figure 4C Additional comparisons are shown between conventional power inverter devices (such as power inverter device 428) and specific implementations of device 100 (such as power inverter device 200). Specifically, Figure 4C Contrast 420-C is depicted between: 1) a close-up side view of a portion of power inverter device 428 showing the connection between conductive element 430 and the gate pad of semiconductor die 432; and 2) a close-up side view of a corresponding portion of power inverter device 200 showing the connection between conductive element 212 and the gate pad of semiconductor die 206. As shown, one difference between these connections is that, in the example of power inverter device 200, a resistor 210 coupled to the gate pad is connected between conductive element 212 and the gate pad of semiconductor die 206. This resistor is not present in the connection between conductive element 430 and semiconductor die 432 in power inverter device 428.

[0079] The required electrical coupling between transistors and other components of a device (e.g., power inverter device 200) is provided by conductive elements and patterned conductive portions on a substrate. The device package may include multiple leads interconnected with the circuitry to facilitate connection of the circuitry to external components (e.g., to connect the device to a printed circuit board, etc.). For this purpose, the device (such as device 100 or power inverter device 200) may also include molding compound and a lead frame including multiple leads. The molding compound at least partially encapsulates the substrate, semiconductor die, conductive elements, resistors, and multiple leads.

[0080] As used herein, a leadframe can refer to a conductive portion (e.g., conductive leads, terminals, etc.) of a device package that is configured to provide external connection points to the package. For example, wire bonding elements, clips, or other electrical connectors can be used to couple individual leads of the leadframe to circuitry within the device package (e.g., a substrate, semiconductor die, etc.), and these leads can extend from the device package (e.g., emerge from molding material) to connect to external circuitry in any suitable manner, such as by soldering or otherwise coupling to a circuit board. Therefore, a leadframe can be referred to as a conductive or metallic portion of a device package. In some embodiments, one or more portions of the leadframe can be coupled to pads (e.g., bonding pads) on at least a portion of the DBM substrate.

[0081] For example, Figure 5 A view of a power inverter device 200 integrated with a possible lead frame according to the principles described herein is shown. First, a front view 500-A shows a lead frame 542-A, which is connected to the substrate of the power inverter device 200 and provides connections to various leads 544-1, 544-2, 544-3, and 544-4 (in... Figure 5 (The extension is shown as truncated or not yet installed in the depiction). Subsequently, perspective view 500-B shows another lead frame 542-B, which is similarly connected to the substrate and provides connections to leads 544-1 to 544-4 with a similar layout.

[0082] Although Figure 5 The exact connections between these lead frames (i.e., lead frames 542-A and 542-B) and shared nodes of the power inverter device 200 (e.g., high-side shared gate node, low-side shared gate node, etc.) are not explicitly shown, but it should be understood that the lead frames can be connected to these nodes to provide the required lead arrangement (e.g., pin outputs) for the device when the package is complete. For example, this lead arrangement may receive a positive DC input (DC+) on leads 544-1 and 544-3, a negative DC input (DC- or ground) on lead 544-2, and provide an AC output (AC) on lead 544-4. Extension pins may also be included, configured to interconnect with some platform (e.g., PCB, heat sink, active cooling device, other electronic or mechanical components, etc.), as highlighted in perspective view 500-B. These leads and pins may eventually extend from the device package (e.g., emerge from the molding material after it is in place) and be connected to external circuitry in any suitable manner, such as by soldering or otherwise coupling to a circuit board or heat sink.

[0083] As an example, although referred to as a leadframe in at least some portions of this embodiment, the leadframe described herein may include any type of conductive portion of the package (e.g., conductive portion, conductive terminal) that provides external connection points from the package. Therefore, the leadframe may be referred to as a conductive portion of the package. In some embodiments, one or more portions of the leadframe may be coupled to pads (e.g., bonding pads) on at least a portion of the DBM substrate.

[0084] The semiconductor device package described herein may include multiple signal terminals. These signal terminals may be power terminals, input signal terminals, output signal terminals, etc. In some embodiments, the multiple signal terminals may be included in a lead frame. In some embodiments, the lead frame may include any type of conductive portion of the package (e.g., conductive portion, conductive terminal) that provides external connection points from the package. Therefore, the lead frame may be referred to as a conductive portion of the package or assembly. In some embodiments, one or more portions of the lead frame may be coupled to pads (e.g., bonding pads) on at least a portion of the DBM substrate and / or the semiconductor die.

[0085] Figure 6 Some aspects of a power inverter device 600 encapsulated in molding compound 546 according to the principles described herein are shown. It should be understood that the encapsulated power inverter device 600 may include various elements of the described power inverter device 200 (e.g., a substrate having semiconductor dies, conductive elements, resistors, etc.) and lead frames (e.g., lead frame 542-A or lead frame 542-B) and possibly other elements not explicitly shown or described. Additionally, molding compound 546 is shown as being added to provide protection and structural support to all the elements encapsulated therein. Each of leads 544-1 to 544-4 and the various pins mentioned above are shown as still accessible even after the molding compound 546 has been applied, thereby facilitating external connections (e.g., connections to external circuitry, heat sinks, etc.) of the power inverter circuit encapsulated in molding compound 546.

[0086] In some embodiments, the molding compound (e.g., molding material or compound, encapsulation material) may be or may include a non-conductive layer / material. In some embodiments, the molding compound is a non-conductive material that can be formed (applied, etc.) using a transfer molding process or a compression molding process. For example, the molding material may be or include: organic materials (e.g., polymers or plastic materials, such as epoxy resins, polysiloxanes, phenolic resins, etc.), inorganic materials (e.g., non-conductive ceramics or conductive metal materials, etc.), and / or other suitable materials that can be used to achieve a particular embodiment. In some embodiments, the molding compound may include a separate plastic housing that is included in a semiconductor device assembly.

[0087] In some specific implementations, spacer materials may be included between certain components of the device (such as between the lead frame and the substrate, between the semiconductor die and the substrate, between the device and the substrate, etc.). For example, such spacer materials may be or may include: epoxy resin, silicone adhesive, conductive materials, non-conductive materials, organic materials, semiconductor materials, metal alloys, metal foams, phase change materials, etc.

[0088] In some implementations, a module (e.g., a device including semiconductor devices within a package, such as device 100 or power inverter device 200) may be included in another module. A module may be referred to as a package. For example, one or more modules may be one or more sub-modules included within another module. In other words, a first module may be included as a sub-module within a second module. More specifically, with regard to modules such as those implemented by device 100, these modules may be used as sub-modules of larger modules (such as circuits, systems, or devices employing device 100) and may include multiple instances of device 100.

[0089] To illustrate an example of a module that can use power inverter device 200 (and more specifically, fully encapsulated power inverter device 600) as a submodule, Figure 7Some aspects of an exemplary power inverter device 750 are illustrated. Based on the principles described herein, the exemplary power inverter device 750 is shown as characterized by a plurality of power inverter devices mounted on a heat sink 752 (i.e., an example of a packaged power inverter device 600). More specifically, the power inverter device 750 may include a heat sink 752 and a plurality of power inverter devices 600 mounted on the heat sink 752. Each of the plurality of power inverter devices may represent an integrated circuit, such as those already described, implementing a power inverter device configured for use in automotive applications. Each of these power inverter devices may include elements such as those described for power inverter device 200. For example, among other elements that can be used to implement a particular specific implementation, a power inverter device in power inverter device 600 may include at least: 1) a substrate; 2) a first semiconductor die disposed on the substrate and implementing a first FET having a gate terminal accessible by a first gate pad; 3) a second semiconductor die disposed on the substrate and implementing a second FET having a gate terminal accessible by a second gate pad; 4) a conductive element configured to electrically couple the first gate pad and the second gate pad to a shared gate node; 5) a first resistor coupled between the conductive element and the first gate pad to the first gate pad; and 6) a second resistor coupled between the conductive element and the second gate pad to the second gate pad.

[0090] As described in other examples, in this specific embodiment, the first and second FETs may be configured as high-side transistors electrically connected in parallel in a power inverter circuit implemented by the power inverter device. Therefore, the power inverter device may further include: 1) a third semiconductor die disposed on a substrate and implementing a third FET, the third FET being configured as a first low-side transistor in the power inverter circuit, and 2) a fourth semiconductor die disposed on a substrate and implementing a fourth FET, the fourth FET being configured as a second low-side transistor electrically connected in parallel with the first low-side transistor in the power inverter circuit. As described above in other examples, the substrate of each packaged power inverter device 600 may be implemented by a DBM substrate (e.g., a DBC substrate, etc.) having a patterned metal layer bonded to a ceramic substrate, and the first and second semiconductor FETs of the device may be SiC dies manufactured using SiC semiconductors, and the first and second FETs may be power MOSFETs. In other specific implementations, other suitable components (e.g., Si die, JFET, etc.) may be used additionally or alternatively.

[0091] The heat sink 752 can be implemented as any suitable system configured to draw heat away from the encapsulated power inverter unit 600 to keep the unit within suitable temperature parameters, even when the unit is handling large currents (which tend to heat the unit). In some specific implementations, the heat sink 752 may include or be implemented by an active cooling system configured to use fluid to transfer heat away from multiple power inverter units. For example, fluid may be pumped through a cooling system (i.e., through the heat sink 752) so that the fluid can draw heat away from the encapsulated power inverter unit 600 and divert the heat elsewhere to prevent these components from overheating.

[0092] Figure 8 An exemplary method 860 for constructing a device according to the principles described herein is shown, characterized by input resistance on pads of a compact package for a semiconductor die. For example, devices (such as the packaged power inverter device 600 or any other example device implementation in other example device implementations described herein) can be assembled or constructed based on multiple steps of method 860. Figure 8 The exemplary operations 861 to 867 according to one specific implementation are shown, but other specific implementations of method 860 may omit, add, reorder, and / or modify them. Figure 8 Any of operations 861 to 867 shown. In some examples, Figure 8 As shown or about Figure 8 The multiple operations described may be performed concurrently (e.g., in parallel) with each other, rather than sequentially as illustrated and / or described. Each of operations 861 to 867 will now be described in more detail.

[0093] At operation 861, a substrate may be fabricated for use in a semiconductor package. For example, any suitable technique for substrate fabrication may be performed to produce a substrate (such as any substrate described herein). For example, in the example of a DBM substrate, operation 861 may involve: fabricating a ceramic substrate; fabricating a conductive foil (e.g., copper foil, etc.); directly bonding the foil to the ceramic substrate (e.g., using a high-temperature hard soldering process, etc.); etching a desired pattern into a metal on one side of the substrate to create various electrically isolated conductive portions; and other suitable tasks appropriate for a particular application (e.g., drilling, applying a solder resist layer, performing surface finishing, etc.). In some examples, at operation 861, fabricating the substrate may involve obtaining a prefabricated substrate from a supplier source, rather than constructing or building it in the manner described above.

[0094] At operation 862, the first semiconductor die may be coupled to a substrate prepared for this purpose at operation 861. The first semiconductor die may implement a first FET (e.g., a power MOSFET), which has a gate terminal accessible by a first gate pad and other terminals (e.g., source terminal, drain terminal, etc.) accessible by other pads, as described herein. At operation 862, the coupling of the first semiconductor die may involve: soldering the semiconductor die to a specific portion of the substrate, sintering the semiconductor die to a specific portion of the substrate, or otherwise physically and / or electrically coupling the semiconductor die to that portion of the substrate.

[0095] At operation 863, the second semiconductor die may be coupled to the substrate prepared at operation 861. Like the first semiconductor die, the second semiconductor die may implement a second FET (e.g., another power MOSFET) having various terminals accessible by various pads, including a gate terminal accessible by a second gate pad. At operation 863, the coupling of the second semiconductor die may involve soldering, sintering, or otherwise physically and / or electrically coupling the semiconductor die to a portion of the substrate. In some embodiments, the second semiconductor die may be fabricated using the same type of semiconductor as the first semiconductor die (e.g., silicon (Si), silicon carbide (SiC), etc.). In other embodiments, the two semiconductor dies may be fabricated using different types of semiconductor materials (the hybrid die scenario described above).

[0096] At operation 864, a resistor may be coupled to the gate pad of the semiconductor die applied at operations 862 and 863. More specifically, a first resistor (which has a leadless package design and a first terminal on a first surface and a second terminal on a second surface opposite the first surface) (also referred to as a bondable package) may be coupled to the first gate pad of the first semiconductor die (coupled to the substrate at operation 862). A second resistor (which has the same type of leadless package design) may be coupled to the second gate pad of the second semiconductor die (coupled to the substrate at operation 863).

[0097] At operation 865, the conductive element may be coupled to a first resistor on a first gate pad and to a second resistor on a second gate pad. For example, gate wires may be soldered or sintered to connect various gate pads for various transistors, including a first FET and a second FET (e.g., gate pads for some or all of a plurality of high-side transistors, gate pads for some or all of a plurality of low-side transistors). The conductive element may be connected to each gate pad by means of resistors coupled (i.e., mounted) to the gate pads, such that the resistors provide the FET with on-pad input resistance according to the principles described herein, which helps to provide a compact package of the semiconductor die.

[0098] At operation 866, a lead frame may be coupled to a substrate. The lead frame includes a plurality of leads that can be connected to elements of the device (e.g., a shared gate node associated with a conductive element coupled at operation 865) to allow external connection to these elements of the device.

[0099] At operation 867, molding compound may then be used to at least partially encapsulate the substrate, the first semiconductor die, the second semiconductor die, the conductive element, the first resistor, the second resistor, and the lead frame having multiple leads.

[0100] The following examples describe specific implementations (e.g., apparatus, method, device, etc.) of input resistors on pads for compact packages of semiconductor dies, based on the principles described herein.

[0101] Example 1: An apparatus comprising: a substrate; a first semiconductor die disposed on the substrate and implementing a first field-effect transistor having a gate terminal accessible via a first gate pad; a second semiconductor die disposed on the substrate and implementing a second field-effect transistor having a gate terminal accessible via a second gate pad; a conductive element configured to electrically couple the first gate pad and the second gate pad to a shared gate node; a first resistor coupled to the first gate pad between the conductive element and the first gate pad; and a second resistor coupled to the second gate pad between the conductive element and the second gate pad.

[0102] Example 2: The device according to any one of the preceding embodiments, wherein the first resistor and the second resistor each have a leadless package design, the leadless package design having a first terminal on a first surface and a second terminal on a second surface opposite to the first surface.

[0103] Example 3: The apparatus according to any one of the preceding embodiments, wherein the first field-effect transistor and the second field-effect transistor are configured as high-side transistors in a power inverter circuit, the high-side transistors being electrically connected in parallel such that the power inverter circuit can handle a current greater than that either of the high-side transistors could handle if it operated alone.

[0104] Example 4: The apparatus according to any one of the preceding embodiments, wherein the first field-effect transistor and the second field-effect transistor are configured as low-side transistors in a power inverter circuit, the low-side transistors being electrically connected in parallel such that the power inverter circuit can handle a current greater than that either of the low-side transistors could handle if it operated alone.

[0105] Example 5: The apparatus according to any one of the preceding embodiments, wherein: the first field-effect transistor and the second field-effect transistor are configured as high-side transistors connected in parallel in a power inverter circuit; and the apparatus further includes: a third semiconductor die disposed on the substrate and implementing a third field-effect transistor, the third field-effect transistor being configured as a first low-side transistor in the power inverter circuit; and a fourth semiconductor die disposed on the substrate and implementing a fourth field-effect transistor, the fourth field-effect transistor being configured as a second low-side transistor connected in parallel with the first low-side transistor in the power inverter circuit.

[0106] Example 6: An apparatus according to any one of the preceding embodiments, wherein the apparatus implements the power inverter circuit, the power inverter circuit comprising: at least eight high-side field-effect transistors, the at least eight high-side field-effect transistors being electrically connected in parallel and including a first field-effect transistor and a second field-effect transistor; and at least eight low-side field-effect transistors, the at least eight low-side field-effect transistors being electrically connected in parallel and including a third field-effect transistor and a fourth field-effect transistor.

[0107] Example 7: The apparatus according to any one of the preceding embodiments, wherein the substrate is made of a direct-bonded metal (DBM) substrate having a patterned metal layer bonded to a ceramic substrate.

[0108] Example 8: The apparatus according to any one of the foregoing embodiments, wherein the first semiconductor die and the second semiconductor die are SiC dies manufactured using silicon carbide (SiC) semiconductors.

[0109] Example 9: The apparatus according to any one of the foregoing embodiments, wherein the first semiconductor die and the second semiconductor die are hybrid dies manufactured using different semiconductors, the first semiconductor die being a Si die manufactured using silicon (Si) semiconductors, and the second semiconductor die being a SiC die manufactured using silicon carbide (SiC) semiconductors.

[0110] Example 10: The device according to any one of the preceding embodiments, wherein the first field-effect transistor and the second field-effect transistor are power metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0111] Example 11: The apparatus according to any one of the foregoing embodiments, wherein the first resistor and the second resistor have the same resistance value.

[0112] Example 12: The apparatus according to any one of the preceding embodiments further includes: a lead frame including a plurality of leads; and a molding compound that at least partially encapsulates the substrate, the first semiconductor die, the second semiconductor die, the conductive element, the first resistor, the second resistor, and the plurality of leads.

[0113] Example 13: The device according to any one of the foregoing embodiments, wherein the device is an integrated circuit that implements a power inverter device configured for use in automotive applications.

[0114] Example 14: A power inverter device, the power inverter device comprising: a heat sink; and a plurality of power inverter devices mounted on the heat sink, the plurality of power inverter devices comprising: a substrate; a first semiconductor die disposed on the substrate and implementing a first field-effect transistor having a gate terminal accessible through a first gate pad; a second semiconductor die disposed on the substrate and implementing a second field-effect transistor having a gate terminal accessible through a second gate pad; a conductive element configured to electrically couple the first gate pad and the second gate pad to a shared gate node; a first resistor coupled to the first gate pad between the conductive element and the first gate pad; and a second resistor coupled to the second gate pad between the conductive element and the second gate pad.

[0115] Example 15: A power inverter device according to any one of the preceding embodiments, wherein: the first field-effect transistor and the second field-effect transistor are configured as high-side transistors connected in parallel in a power inverter circuit implemented by the power inverter device; and the power inverter device further includes: a third semiconductor die disposed on the substrate and implementing a third field-effect transistor, the third field-effect transistor being configured as a first low-side transistor in the power inverter circuit; and a fourth semiconductor die disposed on the substrate and implementing a fourth field-effect transistor, the fourth field-effect transistor being configured as a second low-side transistor connected in parallel with the first low-side transistor in the power inverter circuit.

[0116] Example 16: A power inverter device according to any one of the preceding embodiments, wherein: the substrate is made of a direct-bonded metal (DBM) substrate having a patterned metal layer bonded to a ceramic substrate; the first semiconductor die and the second semiconductor die are SiC dies made using silicon carbide (SiC) semiconductors; and the first field-effect transistor and the second field-effect transistor are power metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0117] Example 17: A power inverter device according to any one of the preceding embodiments, wherein the heat sink includes an active cooling system configured to use a fluid to transfer heat away from the plurality of power inverter devices.

[0118] Example 18: A method comprising: fabricating a substrate; coupling a first semiconductor die to the substrate, the first semiconductor die realizing a first field-effect transistor having a gate terminal accessible via a first gate pad; coupling a second semiconductor die to the substrate, the second semiconductor die realizing a second field-effect transistor having a gate terminal accessible via a second gate pad; coupling a first resistor to the first gate pad and a second resistor to the second gate pad; and coupling a conductive element to the first resistor on the first gate pad and to the second resistor on the second gate pad.

[0119] Example 19: The method according to any one of the preceding embodiments further includes: coupling a lead frame to the substrate, the lead frame including a plurality of leads; and encapsulating the substrate, the first semiconductor die, the second semiconductor die, the conductive element, the first resistor, the second resistor and the plurality of leads at least partially within a molding compound.

[0120] Example 20: The method according to any one of the preceding examples, wherein: the substrate is made of a direct-bonded metal (DBM) substrate having a patterned metal layer bonded to a ceramic substrate; the first semiconductor die and the second semiconductor die are SiC dies made using silicon carbide (SiC) semiconductors; and the first field-effect transistor and the second field-effect transistor are power metal-oxide-semiconductor field-effect transistors (MOSFETs).

[0121] Many implementation schemes have been described. However, it should be understood that various modifications may be made without departing from the spirit and scope of this specification.

[0122] It should also be understood that when an element is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled to another element, no intermediate elements are present. Although the terms “directly on,” “directly connected to,” or “directly coupled to” may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to may be referred to so. The claims of this application may be amended to state the illustrative relationships described in the specification or shown in the drawings.

[0123] The various devices and techniques described herein can be implemented using a variety of semiconductor processing and / or packaging techniques. Some embodiments can be implemented using various types of semiconductor processing techniques associated with a semiconductor substrate, including but not limited to, silicon (Si), gallium arsenide (GaAs), silicon carbide (SiC), etc.

[0124] It should also be understood that when an element such as a layer, region, or substrate is mentioned as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, the element may be directly on, connected to, or coupled to the other element, or one or more intermediate elements may be present. Conversely, when an element is mentioned as being directly on, directly connected to, or directly coupled to another element or layer, no intermediate elements or layers are present.

[0125] Although the terms “directly on,” “directly connected to,” or “directly coupled to” may not be used throughout the detailed description, elements shown as being directly on, directly connected to, or directly coupled to may be referred to as such. The claims of this application may be amended to state the illustrative relationships described in the specification or shown in the drawings.

[0126] As used herein, the singular form may include the plural form unless the context clearly indicates otherwise. In addition to the orientations depicted in the figures, spatial relative terms (e.g., “above,” “over,” “on top,” “below,” “below,” “under,” “below,” “below,” “below,” etc.) are intended to cover different orientations of the device in use or operation. In some embodiments, the relative terms “above” and “below” may respectively include “vertically above” and “vertically below.” In some embodiments, the term “adjacent” may include “laterally adjacent” or “horizontally adjacent.”

[0127] While certain features of the described embodiments have been exemplified as described herein, many modifications, alternatives, alterations, and equivalents will now occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover all such modifications and variations falling within the scope of the embodiments. It should be understood that these modifications and variations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any part of the apparatus and / or method described herein can be combined in any combination, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described.

[0128] Furthermore, the logical flow depicted in the accompanying drawings does not require the specific or sequential order shown to achieve the desired result. Additionally, other steps may be provided, or steps may be eliminated from the described flow, and other components may be added to or removed from the described system. Therefore, other embodiments are within the scope of the following claims.

[0129] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. A first element may be referred to as a second element, and similarly, a second element may be referred to as a first element, without departing from the scope of the specific implementation of this disclosure. As used herein, the term “and / or” includes one or more of the listed associated items and any and all combinations of the listed associated items.

[0130] While certain features of the described embodiments have been exemplified as described herein, many modifications, alternatives, alterations, and equivalents will occur to those skilled in the art. Therefore, it should be understood that the appended claims are intended to cover such modifications and alterations falling within the scope of the embodiments. It should be understood that these modifications and alterations are presented by way of example only and not limitation, and various changes in form and detail are possible. Any part of the apparatus and / or method described herein can be combined in any combination, except for mutually exclusive combinations. The embodiments described herein may include various combinations and / or sub-combinations of the functions, components, and / or features of the different embodiments described. Therefore, the scope of this disclosure is not limited to the specific combinations claimed below, but extends to cover any combination of features or exemplary embodiments described herein, regardless of whether that specific combination is specifically enumerated in the appended claims.

Claims

1. An apparatus (100) comprising: substrate(102); A first semiconductor die (106-1) is disposed on the substrate (102) and implements a first field-effect transistor having a gate terminal that can be accessed through a first gate pad (108-G). A second semiconductor die (106-2) is disposed on the substrate (102) and implements a second field-effect transistor having a gate terminal that can be accessed through a second gate pad (108-G); A conductive element (112) is configured to electrically couple the first gate pad (108-G) and the second gate pad (108-G) to a shared gate node; A first resistor (110-1) is coupled to the first gate pad (108-G) between the conductive element (112) and the first gate pad (108-G); and The second resistor (110-2) is coupled to the second gate pad (108-G) between the conductive element (112) and the second gate pad (108-G).

2. The apparatus of claim 1, wherein the first resistor (110-1) and the second resistor (110-2) each have a leadless package design, the leadless package design having a first terminal on a first surface and a second terminal on a second surface opposite to the first surface.

3. The apparatus of claim 1, wherein the first field-effect transistor and the second field-effect transistor are configured as high-side transistors (206-H) in a power inverter circuit, the high-side transistors (206-H) being electrically connected in parallel such that the power inverter circuit can handle a current greater than that that either of the high-side transistors (206-H) could handle if operated alone.

4. The apparatus of claim 1, wherein the first field-effect transistor and the second field-effect transistor are configured as low-side transistors (206-L) in a power inverter circuit, the low-side transistors (206-L) being electrically connected in parallel such that the power inverter circuit can handle a current greater than that that either of the low-side transistors (206-L) could handle if operated alone.

5. The apparatus according to claim 1, wherein: The first field-effect transistor and the second field-effect transistor are configured as high-side transistors (206-H) connected in parallel in the power inverter circuit; and The device further includes: A third semiconductor die, disposed on the substrate (102), and realizing a third field-effect transistor, is configured as a first low-side transistor (206-L) in the power inverter circuit; and A fourth semiconductor die is disposed on the substrate (102) and realizes a fourth field-effect transistor, which is configured as a second low-side transistor (206-L) electrically connected in parallel with the first low-side transistor (206-L) in the power inverter circuit.

6. The apparatus of claim 5, wherein the apparatus implements the power inverter circuit, the power inverter circuit comprising: At least eight high-side field-effect transistors (206-H) are electrically connected in parallel and include the first field-effect transistor and the second field-effect transistor; and At least eight low-side field-effect transistors (206-L) are electrically connected in parallel and include the third field-effect transistor and the fourth field-effect transistor.

7. The apparatus of claim 1, wherein the substrate (102) is implemented by a direct-bonded metal DBM substrate having a patterned metal layer bonded to a ceramic substrate.

8. The apparatus of claim 1, wherein the first semiconductor die (106-1) and the second semiconductor die (106-2) are SiC dies manufactured using silicon carbide (SiC) semiconductors.

9. The apparatus of claim 1, wherein the first semiconductor die (106-1) and the second semiconductor die (106-2) are hybrid dies manufactured using different semiconductors, the first semiconductor die (106-1) being a Si die manufactured using silicon (Si) semiconductors, and the second semiconductor die (106-2) being a SiC die manufactured using silicon carbide (SiC) semiconductors.

10. The apparatus of claim 1, wherein the first field-effect transistor and the second field-effect transistor are power metal-oxide-semiconductor field-effect transistors (MOSFETs).

11. The apparatus of claim 1, wherein the first resistor (110-1) and the second resistor (110-2) have the same resistance value.

12. The apparatus according to claim 1, further comprising: A lead frame (542-A, 542-B), the lead frame comprising a plurality of leads (544-1, 544-2, 544-3, 544-4); and Molding compound (546) at least partially encapsulates the substrate (102), the first semiconductor die (106-1), the second semiconductor die (106-2), the conductive element (112), the first resistor (110-1), the second resistor (110-2), and the plurality of leads (544-1, 544-2, 544-3, 544-4).

13. The apparatus of claim 1, wherein the apparatus is an integrated circuit that implements a power inverter device (600) configured for use in an automotive application.

14. A power inverter device (750), the power inverter device comprising: Radiator (752); and A plurality of power inverter devices (600) are mounted on the heat sink (752), the plurality of power inverter devices (600) comprising: Substrate(102), A first semiconductor die (106-1) is disposed on the substrate (102) and a first field-effect transistor is implemented thereon. The first field-effect transistor has a gate terminal that can be accessed through a first gate pad (108-G). A second semiconductor die (106-2) is disposed on the substrate (102) and implements a second field-effect transistor, the second field-effect transistor having a gate terminal that can be accessed through a second gate pad (108-G). A conductive element (112) is configured to electrically couple the first gate pad (108-G) and the second gate pad (108-G) to a shared gate node. A first resistor (110-1) is coupled to the first gate pad (108-G) between the conductive element (112) and the first gate pad (108-G), and The second resistor (110-2) is coupled to the second gate pad (108-G) between the conductive element (112) and the second gate pad (108-G).

15. The power inverter device according to claim 14, wherein: The first field-effect transistor and the second field-effect transistor are configured as high-side transistors (206-H) connected in parallel in a power inverter circuit implemented by the power inverter device (600); and The power inverter device (750) also includes: A third semiconductor die, disposed on the substrate (102), and realizing a third field-effect transistor, is configured as a first low-side transistor (206-L) in the power inverter circuit. A fourth semiconductor die is disposed on the substrate (102) and realizes a fourth field-effect transistor, which is configured as a second low-side transistor (206-L) electrically connected in parallel with the first low-side transistor (206-L) in the power inverter circuit.

16. The power inverter device according to claim 14, wherein: The substrate (102) is made of a direct-bonded metal DBM substrate having a patterned metal layer bonded to a ceramic substrate. The first semiconductor die (106-1) and the second semiconductor die (106-2) are SiC dies manufactured using silicon carbide (SiC) semiconductors; and The first field-effect transistor and the second field-effect transistor are power metal-oxide-semiconductor field-effect transistors (MOSFETs).

17. The power inverter device of claim 14, wherein the heat sink (752) includes an active cooling system configured to use a fluid to transfer heat away from the plurality of power inverter devices (600).

18. A method (800), the method comprising: Prepare substrate (102); A first semiconductor die (106-1) is coupled to the substrate (102), the first semiconductor die (106-1) realizing a first field-effect transistor having a gate terminal that can be accessed through a first gate pad (108-G); A second semiconductor die (106-2) is coupled to the substrate (102), the second semiconductor die (106-2) realizing a second field-effect transistor having a gate terminal that can be accessed through a second gate pad (108-G); A first resistor (110-1) is coupled to the first gate pad (108-G), and a second resistor (110-2) is coupled to the second gate pad (108-G); and The conductive element (112) is coupled to the first resistor (110-1) on the first gate pad (108-G) and to the second resistor (110-2) on the second gate pad (108-G).

19. The method according to claim 18, further comprising: A lead frame (542-A, 542-B) is coupled to the substrate (102), the lead frame (542-A, 542-B) including a plurality of leads (544-1, 544-2, 544-3, 544-4); and The substrate (102), the first semiconductor die (106-1), the second semiconductor die (106-2), the conductive element (112), the first resistor (110-1), the second resistor (110-2), and the plurality of leads (544-1, 544-2, 544-3, 544-4) are at least partially encapsulated within a molding compound (546).

20. The method of claim 18, wherein: The substrate (102) is made of a direct-bonded metal DBM substrate having a patterned metal layer bonded to a ceramic substrate. The first semiconductor die (106-1) and the second semiconductor die (106-2) are SiC dies manufactured using silicon carbide (SiC) semiconductors; and The first field-effect transistor and the second field-effect transistor are power metal-oxide-semiconductor field-effect transistors (MOSFETs).

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