Semiconductor device

Abstract

A semiconductor device includes: a first transistor formed on a substrate, the first transistor having a first semiconductor layer, a second semiconductor layer, a first nanosheet, and a first gate electrode; a second transistor formed on the first transistor, the second transistor having a third semiconductor layer, a fourth semiconductor layer, a second nanosheet, and a first gate electrode; and a first power line, a second power line, a third power line, and a fourth power line formed on the substrate, wherein the first power line and the second power line are respectively connected to the first semiconductor layer and the second semiconductor layer, and the third power line and the fourth power line are respectively connected to one of the third semiconductor layer and the other of the fourth semiconductor layer. Thus, a power switching circuit of a transistor having a nanosheet structure can be appropriately configured in the semiconductor device.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] A known technology is CFET (Complementary Field Effect Transistor), which is formed by stacking (layering) transistors. A known technology is BPR (Buried Power Rail), which utilizes buried wiring (wiring) formed within trenches on the surface of a semiconductor substrate to supply power or ground voltage to the transistor. Furthermore, a technology is known for incorporating a power switching circuit in a semiconductor device for switching the on / off state of power supply to the circuit.

[0003] [Cited Documents]

[0004] [Patent Documents]

[0005] [Patent Document 1] U.S. Patent Application Publication No. 2023 / 0178435

[0006] [Patent Document 2] U.S. Patent Application Publication No. 2023 / 0067311

[0007] [Patent Document 3] U.S. Patent Application Publication No. 2022 / 0123023

[0008] [Patent Document 4] U.S. Patent Application Publication No. 2022 / 0181258

[0009] [Patent Document 5] International Publication No. 2020 / 065916

[0010] [Patent Document 6] International Publication No. 2020 / 066797

[0011] [Patent Document 7] International Publication No. 2020 / 217396

[0012] [Patent Document 8] International Publication No. 2020 / 217400

[0013] [Patent Document 9] U.S. Patent Application Publication No. 2021 / 0366902

[0014] [Patent Document 10] U.S. Patent Application Publication No. 2022 / 0102479

[0015] [Patent Document 11] U.S. Patent Application Publication No. 2021 / 0210600 Summary of the Invention

[0016] [Technical problem to be solved]

[0017] For certain types of power switching circuits, there has not been sufficient and detailed research on how to configure them in semiconductor devices.

[0018] The present invention was made in view of the above-mentioned problems, and its object is to properly configure the power switching circuit of the transistor having a nanosheet structure in a semiconductor device.

[0019] [Technical Solution]

[0020] In one embodiment of the present invention, a semiconductor device includes: a substrate; a first power line, a second power line, a third power line, and a fourth power line formed on the substrate; a first semiconductor layer and a second semiconductor layer having a first conductivity type formed on the substrate; a first nanosheet formed between the first semiconductor layer and the second semiconductor layer; a third semiconductor layer formed on the first semiconductor layer and having a second conductivity type different from the first conductivity type; a fourth semiconductor layer formed on the second semiconductor layer and having the second conductivity type; a second nanosheet formed between the third semiconductor layer and the fourth semiconductor layer; a first gate electrode covering the first nanosheet and the second nanosheet; and an electrically connected method. A first transistor is disposed between the first power line and the second power line and has a first semiconductor layer, a second semiconductor layer, a first nanosheet, and a first gate electrode; and a second transistor is disposed between the third power line and the fourth power line and has a third semiconductor layer, a fourth semiconductor layer, a second nanosheet, and a first gate electrode, wherein the first semiconductor layer is electrically connected to the first power line, the second semiconductor layer is electrically connected to the second power line, one of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the third power line, and the other of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the fourth power line.

[0021] [Beneficial Effects]

[0022] According to the disclosed technology, a power switching circuit for a transistor with a nanosheet structure can be appropriately configured in a semiconductor device. Attached Figure Description

[0023] [ Figure 1 [A plan view showing an example of the layout of the semiconductor device in the first embodiment.]

[0024] [ Figure 2 [Showing] Figure 1 A cross-sectional view of an example of the cross-sectional structure of a semiconductor device.

[0025] [ Figure 3 [Displays configuration in] Figure 1 A circuit diagram of an example of a standard unit block circuit.

[0026] [ Figure 4 [Illustrative diagram showing the circuit elements used in the plan view of the circuit described below.]

[0027] [ Figure 5 [Showing] Figure 3 An angle view of an example layout of a power switch circuit.

[0028] [ Figure 6 [This indicates the formation] Figure 5 A plan view of an example of a circuit layout formed on the bottom side of the substrate surface in the area of ​​the power switch circuit and standard unit.

[0029] [ Figure 7 [This indicates the formation] Figure 5 The power switch circuit and standard unit area are formed in Figure 6 A plan view of an example of the circuit layout on the top side of the circuit on the bottom side.

[0030] [ Figure 8 [Showing along] Figure 6 and Figure 7 A cross-sectional view of an example of the cross section of the X1-X1' line.

[0031] [ Figure 9 [Showing along] Figure 6 and Figure 7 A cross-sectional view of an example of the cross section of the X2-X2' line.

[0032] [ Figure 10 [Showing along] Figure 6 and Figure 7 A cross-sectional view of an example of the Y1-Y1' line.

[0033] [ Figure 11 [A perspective view showing an example of the layout of the buffer circuit in the semiconductor device of the second embodiment.]

[0034] [ Figure 12 [Showing content] Figure 11 The circuit diagram is an example of a standard unit block of a buffer circuit.

[0035] [ Figure 13 [Showing content] Figure 11 Another example of a circuit diagram illustrating the standard unit block of a buffer circuit.

[0036] [ Figure 14 [Showing content] Figure 11 Another example of a circuit diagram showing the standard unit block of a buffer circuit.

[0037] [ Figure 15 [This indicates the formation] Figure 12 A plan view of an example of the circuit layout on the bottom side of the area of ​​a standard cell block.

[0038] [ Figure 16 [This indicates the formation] Figure 12 A plan view of an example of the circuit layout on the top side of the area of ​​a standard cell block SCB. Detailed Implementation

[0039] The embodiments will now be described with reference to the accompanying drawings. In the following text, reference numerals indicating signals are also used to indicate signal lines or signal terminals. Reference numerals indicating power supply voltage are also used to indicate power lines or power terminals to which the power supply voltage is supplied.

[0040] [First Implementation Method]

[0041] Figure 1 An example of the layout of the semiconductor device in the first embodiment is shown. For example, Figure 1 The semiconductor device 100 shown can be a SoC (System on Chip) or a single FPGA (Field-Programmable Gate Array), etc.

[0042] Semiconductor device 100 has multiple I / O units IOC, IOCP, and an internal circuit region INTR. I / O units IOC are interface circuits for signal SGNL, ​​such as input signals, output signals, or input / output signals. I / O units IOCP are interface circuits for power supply voltage or ground voltage.

[0043] Each I / O unit (IOC) and IOCP is connected to the internal circuitry region (INTR). For example, the internal circuitry region (INTR) has one or more standard cell blocks (SCBs) that are equipped with standard cells. Additionally, the internal circuitry region (INTR) may also house logic circuits other than standard cells, and may also house memory. Memory may also be housed within the standard cell blocks (SCBs).

[0044] Figure 2 Show Figure 1An example of the cross-sectional structure of the semiconductor device 100. The semiconductor device 100 has a substrate SUB and a wiring layer WL1 formed on the substrate. A CFET is formed on the surface FS of the substrate SUB. The CFET has: a source / drain S / D formed on the bottom BTM side of a semiconductor layer that is close to the substrate SUB; a nanosheet NS on the bottom BTM side that connects the source S and the drain D to each other; a source / drain S / D formed on the top TOP side of a semiconductor layer that is far from the substrate SUB; and a nanosheet NS on the top TOP side that connects the source S and the drain D to each other. In addition, the CFET also has a gate insulating film (not shown) and a gate electrode GT formed on the nanosheet NS.

[0045] A nanosheet NS connecting the source S and drain D on the bottom BTM side is an example of a first nanosheet. A nanosheet NS connecting the source S and drain D on the top TOP side is an example of a second nanosheet. In the following text, the gate electrode GT is sometimes simply referred to as the gate GT. Furthermore, sometimes the reference numeral BTM is used to denote wiring and semiconductor layers disposed on the bottom BTM side, and the reference numeral TOP is used to denote wiring and semiconductor layers disposed on the top TOP side. Sometimes the wiring disposed on the bottom BTM side is called bottom wiring BTMW, and the wiring disposed on the top TOP side is called top wiring TOPW.

[0046] Furthermore, a portion of a CFET structure is sometimes referred to as an NMOS transistor or a PMOS transistor, depending on the conductivity type of the semiconductor layer. Even when it does not function as a transistor, the semiconductor layer is sometimes referred to as the source-drain S / D.

[0047] For example, the source / drain (S / D) or gate (GT) of a CFET can also be connected to wiring W1 formed on wiring layer FSM1 (FSM is an abbreviation for Frontside Metal). Furthermore, wiring layer WL1 can also have multiple wiring layers FSM (FSM1 layer and FSM2 layer, etc.). In the following text, wiring layers FSM1 and FSM2 are also referred to as FSM1 layer and FSM2 layer, respectively. A trench is formed on the surface of the substrate SUB, and a buried wiring BPR is formed in the trench. In the following text, the surface of the substrate SUB on which the buried wiring BPR is formed is also referred to as the BPR layer.

[0048] Figure 3 Showing configuration in Figure 1An example of a standard cell block (SCB) circuit. The standard cell block (SCB) has a power switch circuit (PSW) and standard cells SC1 and SC2, which have different power domains. Standard cell SC1 is an example of the first standard cell region, and standard cell SC2 is an example of the second standard cell region.

[0049] The power switch circuit PSW has a control circuit CNTL and a switching transistor SWT, and operates by receiving a power supply voltage TVDD from the power supply line TVDD and a ground voltage TVSS from the ground line TVSS. The control circuit CNTL has a buffer circuit BUF including inverters INV1 and INV2 connected in series. The buffer circuit BUF generates a control signal PSWsig for controlling the switching transistor SWT based on the output of inverter INV1.

[0050] The switching transistor SWT has a PMOS transistor PM, whose gate is connected to the control signal line PSWsig, its source is connected to the power supply line TVDD, and its drain is connected to the dummy power supply line VVDD. Additionally, the switching transistor SWT has an NMOS transistor NM, whose gate is connected to the control signal line PSWsig, its source is connected to the ground line TVSS, and its drain is connected to the dummy ground line VVSS.

[0051] The PMOS transistor PM of the SWT switching transistor turns on when it receives a low-level control signal PSWsig, connecting the power line TVDD to the virtual power line VVDD. It turns off when it receives a high-level control signal PSWsig, setting the virtual power line VVDD to a floating state. The NMOS transistor NM of the SWT switching transistor turns on when it receives a high-level control signal PSWsig, connecting the ground line TVSS to the virtual ground line VVSS. It turns off when it receives a low-level control signal PSWsig, setting the virtual ground line VVSS to a floating state.

[0052] Thus, the PMOS transistor PM and NMOS transistor NM of the switching transistor SWT operate mutually exclusively, and mutually exclusively perform the supply of power voltage TVDD to the virtual power line VVDD and the supply of ground voltage TVSS to the virtual ground line VVSS. Therefore, standard unit SC1 can operate when the control signal PSWsig is high, and standard unit SC2 can operate when the control signal PSWsig is low. Power line TVDD is an example of a first power line, virtual power line VVDD is an example of a second power line, ground line TVSS is an example of a third power line, and virtual ground line VVSS is an example of a fourth power line.

[0053] Standard unit SC1 is connected to the power line TVDD and the virtual ground line VVSS. Standard unit SC1 is located within the block of the pin-type power domain FPD, which operates upon receiving the virtual ground line VVSS. Standard unit SC2 is connected to the virtual power line VVDD and the ground line TVSS. Standard unit SC2 is located within the block of the head-type power domain HPD, which operates upon receiving the virtual power supply voltage VVDD. Standard units SC1 and SC2 contain various logic circuits, including an inverter INV.

[0054] While not specifically limited, standard units SC1 and SC2 can also be configured on either side of the power switch circuit PSW, sandwiching it between the two circuits. Furthermore, in the pin-type power domain FPD block, the power line TVDD and the virtual ground line VVSS can be configured alternately; similarly, in the head-type power domain HPD, the virtual power line VVDD and the ground line TVSS can be configured alternately. Additionally, in the area where the power switch circuit PSW is configured, the power line TVDD, the virtual power line VVDD, the ground line TVSS, and the virtual ground line VVSS can be mixed and matched.

[0055] Figure 4 A diagram illustrating the circuit elements used in the plan view of the circuit described below is provided. Additionally, in the diagram, various vias are shown as solid lines, but... Figure 6 In the subsequent plan view, the through-hole VIA, which is obscured by the wiring located on the upper side, is shown as a dashed line.

[0056] Figure 5 Show Figure 3 An example of the layout of a power switch circuit (PSW). Figure 5 The diagram of the interlayer insulating film is omitted, and the substrate SUB is simplified with thick dashed lines. The power switch circuit PSW has a semiconductor layer disposed on the bottom BTM side and a nanosheet NS (BTM) on the bottom BTM side that interconnects the semiconductor layers arranged along the Y direction. The Y direction is an example of a second direction. Figure 5 This example shows the source-drain S / D (P-type conductivity type) of a PMOS transistor PM with a CFET semiconductor layer on the bottom BTM side.

[0057] The power switch circuit PSW has a semiconductor layer disposed on the top TOP side and a nanosheet NS (TOP) on the top TOP side that interconnects the semiconductor layers arranged along the Y direction. Figure 5 This shows an example of the source-drain S / D (N-type conductivity type) of an NMOS transistor NM with a CFET semiconductor layer on the top side.

[0058] The power switch circuit PSW has a common gate electrode GT covering the nanosheet NS (TOP) on the top TOP side and the nanosheet NS (BTM) on the bottom BTM side. A gate insulating film (not shown) is formed between the gate electrode GT and the nanosheet NS on the bottom BTM side and the top TOP side.

[0059] Multiple bottom BTM-side semiconductor layers have portions connected via bottom wiring (BTMW) on the bottom BTM side. Multiple top TOP-side semiconductor layers have portions connected via top wiring (TOPW) on the top TOP side. Ground line TVSS, power line TVDD, virtual power line VVDD, and virtual ground line VVSS extend along the Y direction as buried wiring (BPR) provided in the substrate SUB. In the region forming the power switch circuit PSW, ground line TVSS and virtual ground line VVSS are disposed at both ends in the X direction, and power line TVDD and virtual power line VVDD are disposed between ground line TVSS and virtual ground line VVSS.

[0060] The ground wire TVSS can be electrically connected to the source (S) of the NMOS transistor NM in the switching transistor SWT, and the virtual ground wire VVSS can be electrically connected to the drain (D) of the NMOS transistor NM in the switching transistor SWT. The power wire TVDD can be electrically connected to the source (S) of the PMOS transistor PM in the switching transistor SWT, and the virtual power wire VVDD of the switching transistor SWT can be electrically connected to the drain (D) of the PMOS transistor PM.

[0061] exist Figure 5 In the layout shown, the source S of the NMOS transistor and the source S of the PMOS transistor are arranged overlapping in the Z direction. The drain D of the NMOS transistor and the drain D of the PMOS transistor are also arranged overlapping in the Z direction. Furthermore, the positions of the power line TVDD and the virtual power line VVDD can be interchanged, as can the positions of the ground line TVSS and the virtual ground line VVSS.

[0062] To connect the top (TOP) side semiconductor layer (S / D) to the buried wiring BPR, it is not possible to set a bottom wiring BTMW with a different voltage than the top wiring TOPW below the top wiring TOPW connected to the top (TOP) side semiconductor layer (S / D). Therefore, as Figure 5 As shown, the buried wiring BPR, which is connected to the semiconductor layer (S / D) on the top TOP side, is arranged on both sides of the power switch circuit PSW in the X direction.

[0063] Therefore, the top wiring (TOPW) and the buried wiring (BPR) can be connected via a through-hole (VIA) without being blocked by the bottom wiring (BTMW) of other voltages. Thus, the top wiring (TOPW) and the buried wiring (BPR) can be connected without the need for bypass wiring to avoid the bottom wiring (BTMW), thereby improving wiring efficiency. The X direction is an example of the first direction.

[0064] For example, with Figure 5 Conversely, when an NMOS transistor is formed on the bottom BTM side and a PMOS transistor is formed on the top TOP side, wiring efficiency can be improved by arranging the power line TVDD and the virtual power line VVDD on opposite sides in the X direction. Additionally, the transistor formed on... Figure 5 The power switch circuits (PSWs) on the four embedded wiring BPRs arranged along the X direction shown can be repeatedly configured along the X direction.

[0065] The PMOS transistor PM and NMOS transistor NM of the power switch circuit PSW are positioned on the substrate SUB at corresponding locations between the two buried wirings BPR when viewed from above (in the plan view). That is, the PMOS transistor PM and NMOS transistor NM of the power switch circuit PSW are positioned offset along the X direction relative to the buried wirings BPR when viewed from above.

[0066] Figure 6 Shown in the formation Figure 5 This is an example of a circuit layout formed on the bottom BTM side of the substrate SUB in the region of the power switch circuit PSW and standard cells SC1 and SC2. Standard cells SC1 and SC2 are formed on opposite sides of the power switch circuit PSW in the X direction. A PMOS transistor, including a P-type semiconductor layer Pdiff, is formed on the bottom BTM side. The reference numerals S and D in the semiconductor layer Pdiff represent the source and drain, respectively. Semiconductor layers Pdiff without reference numerals S or D are, for example, set to an open-circuit state, indicating that they do not function as transistors. The source S of the PMOS transistor is an example of one of the first and second semiconductor layers, and the drain D of the PMOS transistor is an example of the other of the first and second semiconductor layers.

[0067] In the region of the power switch circuit PSW, the switching transistor SWT is formed by multiple PMOS transistors, each PMOS transistor including a gate GT and a source S and a drain D adjacent to the gate GT in the Y direction. The PMOS transistor of the switching transistor SWT is an example of the first transistor, and the gate GT of the switching transistor SWT is an example of the first gate electrode.

[0068] The source S of the PMOS transistor in the switching transistor SWT is connected to the power line TVDD of the BPR layer via the bottom wiring BTMW and the via VIA (BPR-BTM). The source S of the PMOS transistor can also be connected to the bottom wiring BTMW connected to the via VIA (BPR-BTM) via the source S of other PMOS transistors.

[0069] The drain D of the PMOS transistor in the SWT switching transistor is connected to the virtual power line VVDD of the BPR layer via the bottom wiring BTMW and the via VIA (BPR-BTM). The drain D of the PMOS transistor can also be connected to the bottom wiring BTMW connected to the via VIA (BPR-BTM) via the drain D of other PMOS transistors.

[0070] exist Figure 6 In the middle, assuming Figure 3 The inverter INV shown is formed in standard cells SC1 and SC2. The source S (TVDD) of the PMOS transistor in standard cell SC1 is connected to the source S of the PMOS transistor in the switching transistor SWT via the bottom wiring BTMW, and is electrically connected to the power line TVDD of the BPR layer. The source S (VVDD) of the PMOS transistor in standard cell SC2 is connected to the drain D of the switching transistor SWT via the bottom wiring BTMW, and is electrically connected to the virtual power line VVDD of the BPR layer.

[0071] Figure 7 Shown in the formation Figure 5 The power switch circuit PSW and standard units SC1 and SC2 are formed in the area of Figure 6 This is an example of a circuit layout on the top (TOP) side of the circuit on the bottom (BTM) side. An NMOS transistor, including an N-type semiconductor layer Ndiff, is formed on the top side. The reference numerals S and D in the semiconductor layer Ndiff represent the source and drain, respectively. Semiconductor layers Ndiff without reference numerals S or D are, for example, set to an open-circuit state, indicating that they do not function as transistors. An example where the source S of the NMOS transistor is one of the third and fourth semiconductor layers, and the drain D of the NMOS transistor is the other of the third and fourth semiconductor layers. Furthermore, in... Figure 7 In the diagram, the diamond-shaped through-hole VIA that connects the top wiring TOPW to the wiring FSM1W is obscured by the wiring FSM1W located on the upper side, but it is shown as a solid line instead of a dashed line for ease of observation.

[0072] In the power switch (PSW) region, the gate of the switching transistor SWT is connected to wiring FSM1W on the FSM1 layer via via VIA (GT-FSM1), and further connected to wiring FSM2W on the FSM2 layer via via (FSM1-FSM2). Wiring FSM2W, electrically connected to the gate of the switching transistor SWT, receives the control signal PSWsig. The NMOS transistor of the switching transistor SWT is an example of a second transistor.

[0073] exist Figure 7 In the same assumption Figure 3 The inverter INV shown is formed in standard cells SC1 and SC2. The source S (VVSS) of the NMOS transistor in standard cell SC1 is connected to the drain D of the NMOS transistor in switching transistor SWT via top wiring TOPW, via VIA (TOP-FSM1), wiring FSM1W, via VIA (TOP-FSM1), and top wiring TOPW. The gates GT of the NMOS transistor and PMOS transistor in standard cell SC1 are connected to wiring FSM1W via via VIA (GT-FSM1).

[0074] The source S (TVSS) of the NMOS transistor in standard cell SC2 is connected to the source S of the NMOS transistor in switching transistor SWT via top wiring TOPW, via VIA (TOP-FSM1), wiring FSM1W, via VIA (TOP-FSM1), and top wiring TOPW. The gates of the NMOS and PMOS transistors in standard cell SC2 are connected to wiring FSM1W via via VIA (GT-FSM1).

[0075] Figure 8 Show along Figure 6 and Figure 7 An example of the cross-section of the X1-X1' line. In the power switch circuit PSW, the P-type semiconductor layer Pdiff formed on the bottom BTM side functions as the drain D of the PMOS transistor of the switching transistor SWT and is connected to each other via the bottom wiring BTMW. In the power switch circuit PSW, the N-type semiconductor layer Ndiff formed on the top TOP side functions as the drain D of the NMOS transistor of the switching transistor SWT and is connected to each other via the top wiring TOPW.

[0076] The P-type semiconductor layer Pdiff, formed on the bottom BTM side of the standard cell SC1, functions as the drain D of the PMOS transistor in the inverter INV, for example. The N-type semiconductor layer Ndiff, formed on the top TOP side of the standard cell SC1, functions as the drain D of the NMOS transistor in the inverter INV, for example. Furthermore, the drain D of the PMOS transistor in the inverter INV of the standard cell SC1 and the drain D of the NMOS transistor NM are connected to each other via a top wiring TOPW (not shown), a via VIA (BTM-TOP), and a bottom wiring BTMW.

[0077] The P-type semiconductor layer Pdiff, formed on the bottom BTM side of standard cell SC2, functions as the source S of the PMOS transistor in inverter INV and is connected to the drain D of the PMOS transistor in switching transistor SWT via bottom wiring BTMW. The N-type semiconductor layer Ndiff, formed on the top TOP side of standard cell SC2, functions as the source S of the NMOS transistor in inverter INV and is connected to the top wiring TOP that supplies the ground voltage TVSS.

[0078] Figure 9 Show along Figure 6 and Figure 7 An example of the cross-section of the X2-X2' line. The gates GT of the switching transistor SWT are connected to the wiring FSM2W via vias (GT-FSM1), wiring FSM1W, and vias VIA (FSM1-FSM2). The wiring FSM1W, etc., connected to the gate GT via vias (GT-FSM1) in the standard cells SC1 and SC2, will not be described in detail (it has been omitted).

[0079] Figure 10 Show along Figure 6 and Figure 7 An example of a cross-section of the Y1-Y1' line. For example... Figure 9 The gate GT of the switching transistor SWT is connected to the wiring FSM2W via a via (GT-FSM1), wiring FSM1W, and via VIA (FSM1-FSM2).

[0080] In summary, in the first embodiment, by, for example, employing Figure 5 The layout shown connects the power switch circuit (PSW) of the nanosheet-structured transistor to the power lines (TVSS, TVDD, VVDD, VVSS) of the BPR layer, allowing the PSW to be appropriately configured within the standard cell block (SCB). Furthermore, as... Figure 6 and Figure 7As shown, the standard cell SC1 or SC2 that receives the virtual ground voltage VVSS or virtual power supply voltage VVDD from the power switch circuit PSW can also be appropriately configured in the standard cell block SCB together with the power switch circuit PSW.

[0081] For example, such as Figure 5 As shown, by connecting the buried wiring BPR (in the top TOP side semiconductor layer (S / D) to the semiconductor layer (S / D) on the top side) Figure 5 In the example, TVSS and VVSS are configured on both sides of the power switch circuit PSW in the X direction. The top wiring TOPW can be connected to the buried wiring BPR without setting up detour wiring to avoid the bottom wiring BTMW, thereby improving wiring efficiency.

[0082] [Second Implementation]

[0083] Figure 11 An example of a buffer circuit layout in a semiconductor device according to a second embodiment is shown. For... Figure 5 The same constituent elements will not be described in detail again. (Includes...) Figure 11 The semiconductor device of the buffer circuit BUF and Figure 1 Similar to the semiconductor device 100, it has the same Figure 2 Similar cross-sectional structure, and has the same Figure 3 Similar to the standard cell block SCB.

[0084] The output of the inverter INV1 in the buffer circuit BUF, namely the drains D (PSWsig) of the PMOS transistor PM and the NMOS transistor NM, are connected to each other via the bottom wiring BTMW, via VIA, and top wiring TOPW, and further connected to wiring FSM1W via via VIA. For example, Figure 5 The shown switching transistor SWT is configured in Figure 11 It is located in front of the Y direction and operates by receiving the control signal PSWsig output from the inverter INV1.

[0085] Although not visible in the oblique view due to being obscured by foreground elements (components), the source S (TVDD) of the PMOS transistor PM of the inverters INV1 and INV2 in the buffer circuit BUF can be shared with the source of the PMOS transistor PM of the switching transistor SWT. Similarly, the source S (TVSS) of the NMOS transistor NM of the inverters INV1 and INV2 can also be shared with the source of the NMOS transistor NM of the switching transistor SWT. In other words, the switching transistor SWT of the power switch circuit PSW can be configured at the front boundary of the buffer circuit BUF along the Y direction.

[0086] Figure 12 Showing contains Figure 11 This is an example of a circuit diagram of the standard unit block SCB of a buffer circuit. Figure 12 In this circuit, the power switch circuit PSW is configured, for example, in two regions ROW1 and ROW2.

[0087] In region ROW1, an inverter INV1 with a buffer circuit BUF and a switching transistor SWT1 as part of the switching transistor SWT are configured. In region ROW2, an inverter INV2 with a buffer circuit BUF and a switching transistor SWT2 as another part of the switching transistor SWT are configured. For example, inverter INV1 is configured at the interface of switching transistor SWT1, and inverter INV2 is configured at the interface of switching transistor SWT2.

[0088] Therefore, as Figure 15 and Figure 16 As shown, for example, the source of the switching transistor SWT can be shared with the sources of the transistors in inverters INV1 and INV2, thereby enabling efficient transistor configuration. Furthermore, the switching transistors SWT1 and SWT2 are configured within the same power domain.

[0089] As shown in bold, the output (PSWsig) of inverter INV1 is connected to the input of switching transistor SWT1, the input of inverter INV2 in region ROW2, and the input of switching transistor SWT2 in region ROW2. The output of inverter INV2 can also be connected to another control circuit CNTL (not shown). Figure 3 ).

[0090] The drains of the PMOS transistor PM in switching transistors SWT1 and SWT2 are connected to the virtual power line VVDD. The drains of the NMOS transistor NM in switching transistors SWT1 and SWT2 are connected to the virtual ground line VVSS. Each standard cell SC1 is connected to the power line TVDD and the virtual ground line VVSS. Each standard cell SC2 is connected to the virtual power line VVDD and the ground line TVSS. Figure 12 Each circuit element shown is connected to one or both of the common power line TVDD and the common virtual power line VVDD, and one or both of the common ground line TVSS and the common virtual ground line VVSS.

[0091] Figure 13 Showing contains Figure 11 Another example of the circuit diagram of the standard unit block SCB of the buffer circuit shown. For... Figure 12 The same constituent elements will not be described in detail again. Figure 13 In this circuit, the power switch circuit PSW is configured, for example, in two regions ROW1 and ROW2.

[0092] In region ROW1, an inverter INV1 with a buffer circuit BUF, a dummy circuit DMY1, and a switching transistor SWT1 as part of the switching transistor SWT are configured. In region ROW2, an inverter INV2 with a buffer circuit BUF, a dummy circuit DMY2, and a switching transistor SWT2 as another part of the switching transistor SWT are configured. Furthermore, switching transistors SWT1 and SWT2 are located within the same power domain.

[0093] For example, dummy circuit DMY1 is configured between switching transistor SWT1 and inverter INV1. Dummy circuit DMY2 is configured between switching transistor SWT2 and inverter INV2. That is, dummy circuit DMY1 is configured at the interface of switching transistor SWT1, and dummy circuit DMY2 is configured at the interface of switching transistor SWT2.

[0094] This makes it easier to achieve electrical isolation between the switching transistor SWT1 and the inverter INV1, and also makes it easier to achieve electrical isolation between the switching transistor SWT2 and the inverter INV2. In other words, the switching transistor SWT can be appropriately configured within the standard cell block SCB.

[0095] As shown in bold, the output (PSWsig) of inverter INV1 is connected to the input of dummy circuit DMY1, the input of switching transistor SWT1, the input of inverter INV2, the input of dummy circuit DMY2, and the input of switching transistor SWT2. The output of inverter INV2 can also be connected to another control circuit CNTL (not shown). Figure 3 ).

[0096] The dummy circuits DMY1 and DMY2 have a PMOS transistor PM and an NMOS transistor NM. The source and drain of the PMOS transistor PM in the dummy circuits DMY1 and DMY2 are fixed to the power supply voltage TVDD, and its gate is connected to the control signal line PSWsig. The source and drain of the NMOS transistor NM in the dummy circuits DMY1 and DMY2 are fixed to the ground voltage TVSS, and its gate is connected to the control signal line PSWsig.

[0097] Figure 14 Showing contains Figure 11 This is another example of a circuit diagram of the standard unit block SCB of the buffer circuit shown. For... Figure 12 The same constituent elements will not be described in detail again. Figure 14 In this circuit, the power switch circuit PSW is configured, for example, in two regions ROW1 and ROW2.

[0098] In region ROW1, inverters INV1 (INV11, INV12) with buffer circuits (BUF) and switching transistor SWT1 as part of the switching transistor SWT are configured. In region ROW2, inverters INV2 (INV21, INV22) with buffer circuits (BUF) and switching transistor SWT2 as another part of the switching transistor SWT are configured. Furthermore, switching transistors SWT1 and SWT2 are configured within the same power domain. Additionally, region ROW1 may also have... Figure 13 Similar to the dummy circuit DMY1, region ROW2 can also have the same... Figure 13 A similar dummy circuit, DMY2.

[0099] The output (PSWsig) of inverter INV11 is connected to the input of inverter INV12 and the input of switching transistor SWT1. The output of inverter INV12 is connected to the input of inverter INV21. The output of inverter INV21 is connected to the input of inverter INV22 and the input of switching transistor SWT2. The output of inverter INV22 can also be connected to another control circuit CNTL (not shown). Figure 3 ).

[0100] Switching transistor SWT1 operates by receiving the output of inverter INV11, while switching transistor SWT2 operates by receiving the output of inverter INV11 via inverters INV12 and INV21. Therefore, compared to the control signal PSWsig received by switching transistor SWT1, the control signal PSWsig received by switching transistor SWT2 is delayed by a delay equivalent to two stages of propagation time in inverters INV12 and INV21. By staggering the operating timing of switching transistors SWT1 and SWT2, the peak power supply current flowing through them can be avoided, thereby suppressing power supply noise.

[0101] Figure 15 Showing the formation Figure 12 An example of the bottom BTM-side circuit layout in the region of the standard cell block SCB shown. For... Figure 6 The same constituent elements will not be described in detail again. Figure 15 The circuit layout shown, except that inverters INV1 and INV2 are arranged adjacent to the power switch circuit PSW, is otherwise identical to... Figure 6 similar.

[0102] exist Figure 15In the power switch circuit PSW, among the six PMOS transistors PM, the sources of two PMOS transistors PM are shared with the sources of the PMOS transistors PM of inverters INV1 and INV2, respectively. The drain of the PMOS transistor PM of inverter INV1 outputs the control signal PSWsig. The gate GT of inverter INV2 receives the control signal PSWsig. The drains D of the PMOS transistors PM of inverters INV1 and INV2 are connected to the top wiring TOPW (not shown) via the bottom wiring BTMW and the via VIA (BTM-TOP), respectively.

[0103] Figure 16 Showing the formation Figure 12 An example of the circuit layout on the top (TOP) side of the area in a standard cell block (SCB). For... Figure 7 The same constituent elements will not be described in detail again. Figure 16 The circuit layout shown, except that inverters INV1 and INV2 are positioned adjacent to the power switch circuit PSW, is similar to... Figure 7 Similarly. Additionally, in Figure 16 Although the diamond-shaped through-hole VIA that connects the top wiring TOPW to the wiring FSM1W is obscured by the wiring FSM1W located above, it is still represented by a solid line rather than a dashed line for easy observation.

[0104] exist Figure 16 In the power switch circuit PSW, among the six NMOS transistors NM, the sources of two NMOS transistors NM are shared with the sources of the NMOS transistors NM in inverters INV1 and INV2, respectively. The drain of the NMOS transistor NM in inverter INV1 outputs the control signal PSWsig.

[0105] The drain D of the NMOS transistor NM in inverter INV1 is connected to the gate of the switching transistor SWT via top wiring TOPW, via VIA (TOP-FSM1), wiring FSM1W, via VIA (FSM1-FSM2), wiring FSM2W, via VIA (FSM1-FSM2), wiring FSM1W, and via (GT-FSM1). The drain D of inverter INV2 is connected to the bottom wiring BTMW (not shown) via top wiring TOPW and via VIA (BTM-TOP).

[0106] The gate GT of inverter INV2 receives the control signal PSWsig via wiring FSM2W, via VIA (FSM1-FSM2), wiring FSM1W, and via (GT-FSM1) located in the SWT region of the switching transistor. The drain D of the NMOS transistor NM of inverter INV2 is connected to the top wiring TOPW and via VIA (BTM-TOP) to the... Figure 15The bottom wiring BTMW is shown.

[0107] In summary, in the second embodiment, similar to the first embodiment, the power switch circuit PSW with a nanosheet structure can be appropriately configured within the standard cell block SCB. Furthermore, standard cells SC1 or SC2, which receive the virtual ground voltage VVSS or virtual power supply voltage VVDD from the power switch circuit PSW, can also be appropriately configured within the standard cell block SCB together with the power switch circuit PSW.

[0108] Furthermore, in the second embodiment, by configuring inverters INV1 and INV2 at the interface of the switching transistor SWT, the transistor source of the switching transistor SWT can be shared with the transistor sources of inverters INV1 and INV2, thereby enabling efficient transistor configuration. Additionally, inverter INV1, which outputs the control signal PSWsig to the power switching circuit PSW, can be appropriately configured together with the power switching circuit PSW and standard cells SC1 and SC2 within the standard cell block SCB.

[0109] The present invention has been described above with reference to various embodiments, but the present invention is not limited to the configurations shown in the above embodiments. Various modifications can be made to the above embodiments without departing from the spirit of the present invention, and appropriate determinations can be made according to specific application forms.

[0110] [Explanation of reference numerals in the attached figures]

[0111] 100 Semiconductor Devices

[0112] BPR Embedded Cabling

[0113] BTM bottom

[0114] BTMW bottom wiring

[0115] BUF buffer circuit

[0116] CNTL control circuit

[0117] COUT, / COUT control signals

[0118] D drain

[0119] DMY1, DMY2 are dummy circuits

[0120] FPD Foot Type Power Domain

[0121] FS surface

[0122] FSM1 and FSM2 cabling layers

[0123] FSM1W, FSM1W cabling

[0124] GT gate electrode

[0125] HPD head power domain

[0126] IN input signal line

[0127] INTR internal circuit area

[0128] Inverters: INV, INV1, INV11, INV12, INV2, INV21, INV22

[0129] IOC, IOCP I / O unit

[0130] Ndiff semiconductor layer

[0131] NM NMOS transistor

[0132] NS nanosheets

[0133] OUT output signal line

[0134] PAD pads

[0135] Pdiff semiconductor layer

[0136] PM PMOS transistor

[0137] PSW power switch circuit

[0138] PSWsig control signal

[0139] ROW1 and ROW2 areas

[0140] S source pole

[0141] SC1 and SC2 standard units

[0142] SCB Standard Unit Block

[0143] SGNL signal

[0144] SUB substrate

[0145] SWT, SWT1, SWT2 switching transistors

[0146] TOP

[0147] TOPW Top Wiring

[0148] TVDD power cord

[0149] TVSS grounding wire

[0150] VIA through hole

[0151] VVDD Virtual Power Line

[0152] VVSS Virtual Grounding Wire

[0153] W1 wiring

[0154] WL1 wiring layer.

Claims

1. A semiconductor device comprising: substrate; The first power line, the second power line, the third power line, and the fourth power line are formed on the substrate; A first semiconductor layer and a second semiconductor layer having a first conductivity type are formed on the substrate; A first nanosheet formed between the first semiconductor layer and the second semiconductor layer; A third semiconductor layer formed on the first semiconductor layer and having a second conductivity type different from the first conductivity type; A fourth semiconductor layer formed on the second semiconductor layer and having the second conductivity type; A second nanosheet formed between the third semiconductor layer and the fourth semiconductor layer; A first gate electrode covering the first nanosheet and the second nanosheet; A first transistor is electrically connected between the first power line and the second power line and has a first semiconductor layer, a second semiconductor layer, a first nanosheet and a first gate electrode; as well as A second transistor, which is electrically connected between the third power line and the fourth power line and has the third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode, is disposed therebetween. in, The first semiconductor layer is electrically connected to the first power line. The second semiconductor layer is electrically connected to the second power line. One of the third semiconductor layer and the fourth semiconductor layer is electrically connected to the third power line. The third semiconductor layer and the other of the fourth semiconductor layer are electrically connected to the fourth power line.

2. The semiconductor device according to claim 1, comprising: A first standard unit area is configured with the first power line and the fourth power line; The second standard unit area is configured with the second power line and the third power line; and A power switching circuit including the first transistor and the second transistor. in, The first standard cell region and the second standard cell region are arranged in a first direction in a plan view such that they sandwich the power switch circuit.

3. The semiconductor device according to claim 1 or claim 2, wherein, The first power line, the second power line, the third power line, and the fourth power line are arranged along a first direction in the plan view, and extend along a second direction different from the first direction in the plan view. The first semiconductor layer, the second semiconductor layer, the first nanosheet, and the first gate electrode of the first transistor are arranged along the second direction. The third semiconductor layer, the fourth semiconductor layer, the second nanosheet, and the first gate electrode of the second transistor are arranged along the second direction.

4. The semiconductor device according to claim 3, wherein, In the region where the first transistor and the second transistor are formed, the third power line and the fourth power line are disposed at both ends in the first direction. The first power line and the second power line are disposed between the third power line and the fourth power line.

5. The semiconductor device according to claim 1 or claim 2, comprising: A control circuit configured adjacent to the region where the first transistor and the second transistor are configured. in, The output of the control circuit is connected to the first gate electrode of the first transistor and the second transistor.

6. The semiconductor device according to claim 5, wherein, The control circuit has an inverter that outputs a control signal. in, The source of the PMOS transistor in the inverter is shared with the first semiconductor layer. The source of the NMOS transistor in the inverter is shared with one of the third semiconductor layer and the fourth semiconductor layer.

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