Photovoltaic device and method of manufacturing the same

Abstract

A photovoltaic device includes: - a silicon substrate (1); - a tunneling layer (2) disposed on the silicon substrate (1); - a passivation layer (3) disposed on the tunneling layer (2); - an electrical contact structure (12, 5, 9) located on the passivation layer (3); - a dielectric layer (4) disposed on the passivation layer (3); according to the invention, the electrical contact structure (12, 5, 9) includes: - a patterned metal seed layer (12) disposed on the passivation layer (3) and defining a seeding area (14); - a metal particle paste (5) disposed only in the seeding area (14) on the patterned metal seed layer (12), the dielectric layer (4) extending discontinuously over the metal particle paste (5); and - a metal plating layer (9) disposed in the seeding area (14) on the dielectric layer (4) and electrically connected to the metal particle paste (5).

Description

Technical Field

[0001] This invention relates to the field of photovoltaics. More specifically, this invention relates to photovoltaic devices including non-burn-through electrical contact structures, and methods for manufacturing the same. Background Technology

[0002] Conventional solar cells (such as PERC (passivated emitter and back cell)) have metallized grids in direct contact with the silicon substrate. This direct contact leads to recombination of photogenerated carriers beneath the metal grid, limiting photoelectric conversion efficiency. By implementing layers that simultaneously provide selective carrier conduction and efficient passivation of the silicon surface, these recombination losses are reduced and higher efficiencies can be achieved.

[0003] There are two main types of cells with passivated contacts. The first type is a heterojunction solar cell, which has an amorphous, nanocrystalline, or microcrystalline silicon layer and a thin transparent conductive oxide (TCO) layer as a passivation and conductive layer. These cells are processed at low temperatures (typically around 200°C) and accordingly require a low-temperature metal paste for screen printing the contacts, which forms the contacts only on top of the TCO without penetrating into the underlying layers. The second type is a cell with high-temperature passivated contacts, which can be processed at temperatures above 800°C, the so-called TOPCon (tunnel oxide passivated contact) or POLO (polycrystalline silicon on oxide) cells.

[0004] In TOPCon cells, the stacked layers typically consist of a thin silicon oxide interlayer (a so-called "tunnel oxide" layer) of 1.0–1.5 nm thickness and a polycrystalline silicon (poly-Si) layer, which may contain other elements such as carbon, oxygen, and hydrogen and be doped with elements such as boron or phosphorus. Silicon nitride is deposited on top of the poly-Si layer as an anti-reflective coating and optionally as a hydrogen source. Hydrogen is released from the silicon nitride during high-temperature annealing and diffuses within the stacked layers, providing additional passivation.

[0005] The standard metallization technique for TOPCon cells involves screen printing silver particle paste onto the grid. This paste is then "burned through" the silicon nitride at approximately 850°C to form contacts within the poly-Si passivation layer. The paste must penetrate deeply enough into the poly-Si layer to form low-resistivity contacts, preferably below 10 mΩ. cm 2 However, it is crucial to avoid forming spikes that penetrate the poly-Si layer to reach the bulk c-Si substrate, as this would lead to recombination losses. Therefore, a relatively thick poly-Si layer is required, typically around 100 nm thick. This type of cell... Figure 1As shown, the left image represents the contact immediately after printing the silver particle paste 5, and the right image represents the structure after burn-through contact. In this figure, a crystalline silicon (c-Si) substrate 1 is provided, on which a tunnel oxide layer 2 (typically 1-1.5 nm thick SiOx) is provided, on which a passivation layer 3 (typically about 100 nm thick poly-Si) is provided, and on which a dielectric layer (typically about 100 nm thick SiN) is deposited. x The contact is formed by screen printing a metal particle paste 5 (typically about 10 μm thick). It is then burned through at about 850°C to obtain the structure on the right, in which the burned-through paste region 6 penetrates the dielectric layer 4 and forms a contact with the underlying passivation layer 3.

[0006] Another metallization method is as follows Figure 2 As shown, and involving the electrodeposition of nickel and copper on the passivation layer 3 of the poly-Si layer after laser patterning of the dielectric layer 4 to create an opening, as described by B. Grübel et al., “Direct Contact Electroplating Sequence Without Initial Seed Layer for Bifacial TOPCon SolarCell Metallization”, DOI: 10.1109 / JPHOTOV.2021.3051636. This laser exposure results in laser damage to the passivation layer 3 in region 7. Nickel 8 (typically about 1 μm thick) is electroplated on the exposed portion of the passivation layer 3, which serves as a barrier layer between the poly-Si and the subsequently electroplated copper 9 (typically about 10 μm thick). Due to the laser damage in region 7, a relatively thick passivation layer 3 is required, at least 70 nm thick.

[0007] The drawback of the poly-Si passivation layer 3 is its parasitic light absorption. Every 10 nm of poly-Si causes a significant loss of photocurrent in the final device, ranging from 0.5 mA / cm². Due to this parasitic absorption, the poly-Si layer is typically applied only to the back of the solar cell, while a conventional diffused doped layer is formed on the front side, such as a boron emitter on n-type c-Si coated with aluminum oxide (Al₂O₃) and silicon nitride (SiN₂). x ).

[0008] Research focuses on reducing parasitic absorption, patterning and localizing poly-Si layers only below the metal grid, and developing alternative, more transparent passivation layers, such as transition metal oxides (TMOs), for example, molybdenum oxide (MO). x This allows for the production of high-efficiency solar cells with passivated contacts on both sides.

[0009] In addition to the standard process used for high-temperature cells with laser nitride openings and nickel and copper plating directly on silicon doped in a diffusion process (e.g., on PERC cells) or on a poly-Si passivation layer, several methods for copper plating metallization have been developed to replace silver in solar cell manufacturing.

[0010] For heterojunction solar cells, processes for reinforcing screen-printed seed grids using chemically or electrochemically deposited metals and dielectric layers as plating masks are described in EP2489076B1 and US9246026B2. The corresponding contact structures are as follows: Figure 3 As shown. This process on a heterojunction cell precursor with a passivation layer 3 and a thin transparent conductive oxide (TCO) 10 on a c-Si substrate 1 includes the following steps: printing a seed grid using a metal particle paste 5, depositing a dielectric layer 4 over the entire wafer, and chemically or electrochemically reinforcing the printed seed grid with electrodeposited copper 9. Due to the rough surface morphology and discontinuity of the printed paste 5 (because it is composed of metal particles of different shapes and organic components, similar to a sponge structure), the dielectric layer 4 is discontinuous, i.e., it has voids on top of the paste, and at the deposition site, its thickness is significantly lower than that on the TCO 10 (because the surface area per unit area is much larger than the surrounding, typically pyramidal, wafer surface). This allows for current flow for electrodeposition and ensures good contact between the cured metal paste 5 and the electrodeposited copper 9. In fact, the latter even penetrates into the structure of the paste 5 where the dielectric layer 4 is absent, further ensuring excellent contact between them. These methods are only applicable to substrates with TCO 10 on the surface. The metal particle paste 5 is heat-treated at about 200°C, resulting in contact formation only on top of TCO10 without burn-through.

[0011] Figure 4 The contact structure obtained by the plating process described in US8236604B2 is shown. The contact is formed on a substrate 1, which is a photovoltaic structure having intrinsic and doped passivation layers and optionally an intermediate layer, on its surface having a TCO 10 and a patterned sputtered metal seed layer 12. After patterning a dielectric layer 4 as a plating mask, nickel 8 (optional) and copper 9 are electroplated on the metal seed layer. The dielectric layer 4 is approximately 100 nm thick, while several micrometers of metal are electrodeposited. The resulting line has a lower aspect ratio than lines defined by conventional thick organic resists.

[0012] The object of this invention is to provide a photovoltaic device with a contact structure that is cost-effective to manufacture, exhibits low resistivity and well-adhered metal contacts, and allows for the use of a thin passivation layer, preferably thinner than 50 nm, to minimize parasitic absorption and achieve higher photocurrent and therefore higher photoelectric conversion efficiency. It is also desirable to reduce or completely eliminate the use of relatively expensive silver by utilizing copper as the primary conductive material for the photocurrent. Summary of the Invention

[0013] More specifically, the present invention relates to a photovoltaic device as defined in independent claim 1. The photovoltaic device comprises: - Silicon-based substrate, typically monocrystalline silicon; - Tunneling layer, typically SiO x The tunneling layer is disposed on the silicon substrate, typically directly thereon; - A passivation layer, typically poly-Si, is disposed on the tunneling layer, typically directly on top of it, but the presence of at least one intermediate layer is not excluded; other possible materials include SiC, poly-Si, and poly-SiO. x a-Si / nc-Si / µc-Si, MO x WO x TiO x The passivation layer may optionally be doped with elements such as boron or phosphorus; - An electrical contact structure located on the passivation layer; - Dielectric layer, typically SiO x SiN x SiO x N y Or Al2O3, the dielectric layer is disposed on the passivation layer, typically directly on it, but the presence of at least one intermediate layer is not excluded.

[0014] According to the present invention, the electrical contact structure includes: - A patterned metal seed layer, typically applied by sputtering and comprising one or more of Ag, Al, Co, Cr, Mo, Ni, NiV, Ta, Ti, W, WTi, Cu, Ni and alloys thereof, the patterned metal seed layer being disposed on the passivation layer and defining a seeding region therein, the patterned metal seed layer typically being directly on the passivation layer, but the presence of at least one intermediate layer is not excluded; - A metal particle paste, typically silver or silver-containing metal particles, typically defining conductive traces and / or busbars, said metal particle paste being disposed only in the seeding area on the patterned metal seed layer, typically by printing. The dielectric layer extends discontinuously over the metal particle paste; and - A metal plating layer, typically copper, nickel, tin, or an alloy thereof, is disposed on the dielectric layer in the seeding zone and electrically connected to the metal particle slurry.

[0015] This arrangement eliminates the need for a TCO layer (although an alternative layer can be provided on the passivation layer) and allows for a relatively thin passivation layer because burn-through of the metal particle paste is not required. This reduces parasitic losses in the photovoltaic device. The metal seed layer is in close contact with the passivation layer (providing good adhesion and low contact resistivity) and is also well electrically connected to the overlying metal particle paste and the plated / electrodeposited layer, forming an overall low-resistivity contact. Furthermore, since the metal particle paste can be used as an etch mask for etching the metal seed layer outside the seed area, additional masking steps can be eliminated. Moreover, since the deposition of the dielectric layer does not require masking and / or selective removal, additional masking steps can be eliminated, and photovoltaic devices can be manufactured economically. Finally, compared to some prior art contact structures, the use of silver can be reduced because most of the conductivity is provided by the metal plating layer, which can be copper, nickel, tin, or the like, further reducing costs.

[0016] Advantageously, the silicon-based substrate is monocrystalline silicon.

[0017] Advantageously, the patterned metal seed layer comprises multiple sublayers of at least two different metals. This is particularly useful for further improving the adhesion of the seed layer, as a first metal (e.g., Ag, Al, Co, Cr, Mo, Ni, NiV, Ta, Ti, W, WTi and / or alloys thereof), such as a contact and adhesion layer, can be positioned in direct contact with the passivation layer, and then capped with a second metal (e.g., Cu, Ni, Sn and / or alloys thereof) having a higher specific conductivity to support a uniform distribution of the current used for electrodeposition, and as the uppermost metal, this metal forms a low resistivity contact with the subsequently printed metal particle paste disposed thereon.

[0018] Advantageously, the metal particle slurry comprises metal particles with a diameter of 1 μm to 10 μm, preferably 2 μm to 5 μm. Smaller metal particles in the nanometer range may also be present. This particle size range helps ensure sufficient openings in the discontinuous dielectric layer above the metal particle slurry to ensure good electrical contact between the metal particle slurry and the plated metal layer.

[0019] Advantageously, the thickness of the tunneling layer is between 1 nm and 1.5 nm, and is preferably made of SiO2. x Made.

[0020] Advantageously, the passivation layer comprises (and actually mainly comprises) SiC, a-Si, nc-Si, μc-Si, poly-Si, poly-SiO x Alternatively, the passivation layer may be one of a transition metal oxide (e.g., tungsten oxide, molybdenum oxide, or titanium oxide), and may be optionally doped with a dopant, such as boron or phosphorus.

[0021] Advantageously, the passivation layer has a thickness of less than 50 nm and is preferably polycrystalline silicon. This relatively low thickness helps to reduce parasitic losses that are typically caused by the passivation layer.

[0022] Advantageously, the passivation layer is thinner outside the seeding zone than inside the seeding zone, further reducing parasitic losses that are typically caused by the passivation layer.

[0023] Advantageously, the dielectric layer outside the seeding area has a thickness of 50 nm to 150 nm, and is preferably SiO2. x SiN x SiO x N y Or one of Al2O3. Al2O3 is typically applied in the thickness range of 5-20 nm. Further advantageously, the dielectric layer can be a stack of layers comprising sublayers of these materials.

[0024] The present invention also relates to a method for manufacturing the photovoltaic device as defined above. The method includes the following steps: - A silicon-based substrate, typically monocrystalline silicon, is provided, on which a tunneling layer (typically SiOx) is provided and a passivation layer (typically poly-Si) is provided on the tunneling layer; subsequently - A metal seed layer is deposited on the passivation layer, the metal seed layer being deposited over the entire surface and typically comprising one or more of Ag, Al, Co, Cr, Mo, Ni, NiV, Ta, Ti, W, WTi, Cu, Ni, or alloys thereof; subsequently - A metal particle paste, typically silver or silver-containing metal particles, is printed onto the metal seed layer and defines conductive traces and / or busbars. The metal particle paste is arranged to serve as an etching mask to define a seed area in which the seed layer will remain in the final device; subsequently... - Etch away the metal seed layer outside the seeding area to expose the passivation layer outside the seeding area; subsequently - A dielectric layer is deposited on the exposed passivation layer (i.e., the portion of the passivation layer outside the seeding area and not covered by the patterned metal seed layer) and the metal particle slurry, such that the dielectric layer is discontinuous on the metal particle slurry, i.e., has voids; subsequently - A metal plating layer is formed, typically by electroplating or electroless plating of copper, nickel, tin or the like, said metal plating layer being superimposed on the metal particle slurry (i.e., at least in the seeding zone) and electrically connected to the metal particle slurry.

[0025] This method eliminates the need for a TCO layer (although an alternative layer can be deposited on the passivation layer in a corresponding step) and allows for a relatively thin passivation layer because burn-through of the metal particle paste is not required. This reduces parasitic losses in photovoltaic devices. The metal seed layer is in close contact with the passivation layer (providing good adhesion and low contact resistivity) and also has good electrical connection with the overlying metal particle paste and metal plating layer, further reducing resistivity. Furthermore, since the printed metal particle paste serves as an etch mask for etching the metal seed layer outside the seed area, an additional masking step for forming the metal seed layer can be eliminated. Moreover, since the deposition of the dielectric layer does not require masking and / or selective removal, additional masking steps can be eliminated, and photovoltaic devices can be manufactured economically. Finally, compared to some prior art contact structures, the use of silver can be reduced because most of the conductivity is provided by the metal plating layer, which can be copper, nickel, tin, or the like (or alloys thereof), further reducing costs.

[0026] Advantageously, prior to the step of depositing the dielectric layer, the passivation layer is etched back outside the seeding area to reduce its thickness outside the seeding area. This can further reduce parasitic losses caused by the passivation layer.

[0027] Advantageously, an annealing step is performed after the deposition of the dielectric layer, either directly after deposition or after the deposition of the metal plating layer, in order to improve passivation by allowing hydrogen to migrate from the dielectric layer to the passivation layer. This step can also be used simultaneously to cure the metal particle slurry, which is efficient in terms of process.

[0028] Advantageously, the metal seed layer is formed by physical vapor deposition, preferably by sputtering.

[0029] Advantageously, the metal seed layer is deposited as at least two sub-layers of different metals. This is particularly useful for improving the adhesion of the seed layer because a first metal (e.g., Ag, Al, Co, Cr, Mo, Ni, NiV, Ta, Ti, W, WTi and alloys thereof), such as a contact and adhesion layer, can be positioned in direct contact with the passivation layer, and then capped with a second metal (e.g., Cu, Ni, Sn and / or alloys thereof) having high lateral conductivity to allow for uniform distribution of the current used for electrodeposition, and as the uppermost metal, this metal forms a low resistivity contact with the subsequently printed metal particle paste layer disposed thereon.

[0030] Advantageously, the silicon-based substrate is monocrystalline silicon.

[0031] Advantageously, at least one of the following is true: The metal particle slurry also includes metal particles with a diameter of 1 μm to 10 μm, preferably 2 μm to 5 μm, but smaller particles are not excluded. The thickness of the tunneling layer is between 1 nm and 1.5 nm, and it is preferably made of SiO2. x Made; The passivation layer has a thickness of less than 50 nm, and is preferably made of polycrystalline silicon, SiC, or poly-SiO2. x a-Si / nc-Si / µc-Si, MO x WO x TiO x The passivation layer may optionally be doped with elements such as boron or phosphorus; The dielectric layer outside the seeding area has a thickness of 50 nm to 150 nm, and is preferably SiO2. x SiN x SiO x N y Or one or more of Al2O3, which has a thickness of 5 to 20 nm. The dielectric layer can be a multilayer structure comprising multiple sublayers of these materials. Attached Figure Description

[0032] Further details of the invention will become clear upon reading the detailed description with reference to the following figures, in which: - Figures 1 to 4 The prior art contact structure of a photovoltaic device is shown; - Figure 5 An embodiment of the photovoltaic device according to the present invention is shown in a partial view, with emphasis on its contact structure; - Figure 6 Another embodiment of the photovoltaic device according to the present invention is shown in partial view, focusing on its contact structure; - Figure 7 and Figure 8 A manufacturing method according to the present invention is shown, and - Figure 9 A partial view shows another embodiment of the photovoltaic device according to the present invention, focusing on its contact structure. Detailed Implementation

[0033] In the following text, unless otherwise stated, additional intermediate layers may exist between any two given layers (one described as “on” or “above” the other). Furthermore, for clarity and to follow common practice in the art, surface textures of layers are not shown. This typically includes pyramidal shapes, as is generally known.

[0034] Figure 5 A first embodiment of a photovoltaic cell according to the present invention is shown, illustrating the contact structure that forms the basis of the invention.

[0035] The photovoltaic cell includes a substrate 1, which is appropriately doped (typically n-type, i.e., phosphorus-doped) crystalline silicon (c-Si), on which a tunneling layer 2 of oxide (typically SiO2 with a thickness of 1-1.5 nm) is disposed. x The tunneling layer is covered by a passivation layer 3 with a thickness of less than 50 nm, which is typically polycrystalline silicon (poly-Si). Other materials that can be used for the passivation layer 3 are SiC and poly-SiO2. x a-Si / nc-Si / µc-Si, MO x WO x TiO x Optionally, it may be doped with elements such as boron or phosphorus. Optionally, a transparent conductive oxide (TCO) layer (not shown) may be disposed on the passivation layer 3, which may be deposited by any suitable known process; however, this is not required.

[0036] A patterned metal seed layer 12 is disposed in the location where electrical contacts are desired to form, referred to as the “seeding region” 14, because these are the areas where the metal seed layer 12 will be present in the final device. The patterned metal seed layer 12 is typically formed by sputtering, and more generally by any suitable form of physical vapor deposition (PVD).

[0037] The metal seed layer 12 can be formed as a monolayer of, for example, Cu, Ni, Sn or the like, or formed as... Figure 9The stacked layers of multiple sublayers 12a, 12b of different metals shown include contact and adhesion layers (e.g., Ag, Al, Co, Cr, Mo, Ni, NiV, Ta, Ti, W, or WTi or alloys thereof) in direct contact with the passivation layer 3, and a second metal (e.g., Cu, Ni, Sn, and / or alloys thereof) with relatively high specific conductivity to support a uniform distribution of current for electrodeposition. As the uppermost metal, this metal forms a low-resistivity contact with a subsequently printed metal particle paste 5 disposed thereon, which is typically printed in the desired area to define traces and / or busbars. The typical thickness of the metal seed layer 12 is approximately 100 nm.

[0038] The metal particle paste 5 can be a classic silver particle paste, or a less expensive paste type, such as silver-plated copper, silver-plated nickel, or silver-plated silicon particles. It is applied wet, dried, and then cured at a relatively low temperature between 150°C and 500°C, which does not substantially alter the contact structure except for curing the metal particle paste. Annealing at this moderate temperature does not cause (detectable) interdiffusion between the passivation layer 3 and the metal seed layer 12, and no paste diffusion into the passivation layer 3 has been observed. Nevertheless, an improvement in contact resistivity, i.e., a reduction, has been observed, likely due to changes at the interface between the two layers. The typical width of the metal particle paste 5 lines is 10-20 μm, with typical larger particle diameters ranging from 1 μm to 10 μm, and typically a few micrometers, i.e., 2 μm to 5 μm; however, the possibility of smaller particles in the nanometer range also exists. As will become clear below, the metal particle paste serves as an etching mask defining the seed area 14.

[0039] Dielectric layer 4, typically SiO x SiN x SiO x N yAlternatively, Al2O3 is deposited over the entire surface of the passivation layer 3 and the metal particle paste 5, the latter being selected to support / promote the discontinuity of the dielectric layer 4 above the metal particle paste 5, thereby allowing electrical contact with the metal particle paste. The dielectric layer 4 is deposited over a general range (thickness, etc.) ensuring this discontinuity. Furthermore, the irregular surface of the metal particle paste 5 results in the dielectric layer 4 being thinner when deposited on the metal particle paste 5 than on the regular (typically pyramidal textured) surface of the exposed passivation layer 3 outside the seeding area 14, where the dielectric layer is continuous and typically 50 nm to 150 nm thick (except in the case of Al2O3, which is typically 5 nm to 20 nm). Due to the discontinuity and porosity of the dielectric layer 4 on the metal particle paste 5, it does not need to be removed but remains within the electrical contact. PECVD, PVD, and ALD are the most commonly used methods for depositing dielectric layer 4, with PECVD being preferred because, generally, directional deposition rather than conformal deposition helps ensure that the metal particle slurry 5 is not completely covered by dielectric layer 5.

[0040] Finally, a metal plating layer 9 is disposed above the metal particle slurry 5, encapsulating the portion of the dielectric layer 4 disposed on the metal particle slurry. Since the dielectric layer 4 is discontinuous above the metal particle slurry 5, good electrical contact between the latter and the metal plating layer 9 is ensured. It has been observed that the metal plating layer 9 is not only electrodeposited on the surface of the metal particle slurry 5, but also electrodeposited within its structure, even down to the metal seed layer 12. This further improves the electrical contact between the metal plating layer 9, the metal particle slurry 5, and even the metal seed layer 12. Typical materials for the metal plating layer 9 are nickel and copper. Additional solderable capping layers, not shown, such as Ag or Sn, can also be deposited by electrodeposition, chemical reduction, or ion exchange (e.g., "immersion tin" or "immersion silver"), with typical thicknesses as follows: electrodeposited Sn 2-4 µm, electrodeposited Ag <0.5 µm, immersed Sn 0.8-1.0 µm, immersed Ag 200-300 nm. This helps prevent oxidation of the metal plating layer 9, especially when it is copper. Another example of a capping layer that prevents copper oxidation and thus maintains solderability is the so-called organic solderability protectant (OSP), used, for example, in the manufacture of printed circuit boards. This OSP layer comprises an ordered network of organic molecules (e.g., benzotriazole) intercalated with copper ions, and the layer thickness is typically <1 µm, more specifically typically 0.1 μm to 0.6 μm.

[0041] Figure 6 A variation of the photovoltaic device according to the present invention is shown, which is similar to... Figure 5The difference is that the passivation layer 3 is etched back in the portion not covered by the metal seed layer 12, i.e. outside the seed area 14, so as to reduce its thickness typically to between 5 nm and 20 nm, and thus further reduce parasitic absorption.

[0042] Figure 7 and Figure 8 A method for manufacturing a photovoltaic device according to the present invention is shown. The thickness, properties, and materials of each layer are described above. Figure 5 and Figure 6 The context is given.

[0043] In step 100, a silicon substrate 1 is provided, which has been previously etched, textured (not shown), and chemically cleaned to remove sawing damage, and has a tunneling layer 2 and a passivation layer 3 provided as is generally known to those skilled in the art. A TCO layer (not shown) may also be provided on the passivation layer 3.

[0044] In step 101, a metal seed layer 12 is formed on the entire surface of the passivation layer 3 by physical vapor deposition (PVD), particularly by sputtering. This can be done in a single step or in several steps to obtain a stack of several (typically two) sublayers 12a, 12b of different metals constituting the metal seed layer 12 (e.g., ...). Figure 9 (As shown).

[0045] In step 102, the metal particle paste 5 is printed in a patterned manner by screen printing, pattern transfer printing (PTP), or any other suitable method. Typically, the metal particle paste 5 is printed to define grid lines and / or busbars, as is commonly known, and serves as an etching mask to define seed areas 14 in which the metal seed layer 12 is retained after step 103.

[0046] The metal particle slurry 5 is then dried, for example at 100-150°C, and subsequently cured, typically between 150°C and 500°C. Since the metal seed layer 12 is interposed between the metal particle slurry 5 and the passivation layer 3, there is no contact between the two. Therefore, the passivation layer 3 can be relatively thin, typically less than 50 nm thick, preferably about 20 nm thick, because, as mentioned above, burn-through or other migration of the metal particle slurry 5 into the passivation layer 3 will not occur.

[0047] In step 103, the metal seed layer 12 is etched away in the area not covered by the metal particle slurry 5, that is, outside the seeding area 14.

[0048] Optionally, in the steps not shown, if the product is to be produced Figure 6 For devices that are not covered by the patterned metal seed layer 12, the passivation layer 3 can be etched back to a reduced thickness.

[0049] In step 104, an insulating transparent dielectric layer 4 is deposited over the entire surface (i.e., over the exposed passivation layer 3 and the metal particle paste 5, that is, inside and outside the seeding zone 14). As described above, the size / type of the metal paste particles is selected such that the surface roughness of the metal particle paste 5 makes the dielectric layer 4 thinner over the metal particle paste 5 than over the passivation layer 3, and is also discontinuous (i.e., has voids) over the metal particle paste 5.

[0050] In a variant not shown, the step of curing the metal particle slurry 5 can be performed after the deposition of the dielectric layer 4 in step 104. In this case, annealing occurs, and hydrogen is released from the dielectric layer 4 into the passivation layer 3, which further improves passivation.

[0051] Dielectric layer 4 is used as an anti-reflective coating and plating mask in the next step.

[0052] In step 105, a metal plating layer 9 is formed, for example by electroplating or electroless plating. This eliminates the need for further masking: due to the rough surface of the metal particle slurry 5, the dielectric layer 4 on top of the metal particle slurry 5 is not continuous. These gaps expose portions of the metal particle slurry 5, allowing current for electroplating (applied to the traces of the metal particle slurry 5) to pass through, and copper and / or other metals can be deposited, while the surfaces between the metal particle slurry 5 lines are tightly covered by the dielectric layer and completely protected from the electrolyte. As a result, a metal plating layer 9 is formed according to the pattern defined by the metal particle slurry 5. In the case of electroless plating (e.g., autocatalytic plating), the exposed portions of the metal particle slurry 5 are exposed to the plating solution and initiate the formation of the metal plating layer 9.

[0053] This eliminates the need for further masking and mask removal steps, which makes the method of the present invention particularly economical to implement.

[0054] The current applied to the cell for electrodeposition is typically significantly lower than the photocurrent in the final device, usually less than 10% of the photocurrent. Therefore, a metal particle paste 5 with a lower conductivity than standard silver paste can be used to form the grid, such as a paste with silver-plated copper particles, silver-plated nickel, or silver-plated silicon particles. The use of silver-free pastes is also conceivable.

[0055] Depending on whether a back etch of dielectric layer 3 was performed, the result is obtained according to... Figure 5 or Figure 6 Devices.

[0056] Finally, an annealing step can also be performed after step 105 to release hydrogen from dielectric layer 4 into passivation layer 3 to further improve passivation.

[0057] Although the invention has been described in conjunction with specific embodiments, modifications may be made thereto without departing from the scope of protection defined by the appended claims.

Claims

1. A photovoltaic device, the photovoltaic device comprising: - Silicon substrate (1); - Tunneling layer (2), the tunneling layer being disposed on the silicon substrate (1); - Passivation layer (3), the passivation layer is disposed on the tunneling layer (2); - Electrical contact structures (12, 5, 9), said electrical contact structures being located on the passivation layer (3); - Dielectric layer (4), the dielectric layer is disposed on the passivation layer (3); The electrical contact structure (12, 5, 9) is characterized in that it comprises: - A patterned metal seed layer (12) is disposed on the passivation layer (3) and defines a seeding area (14). - A metal particle slurry (5), wherein the metal particle slurry is disposed only in the seeding area (14) on the patterned metal seed layer (12), and the dielectric layer (4) extends discontinuously above the metal particle slurry (5); and - A metal plating layer (9) is disposed on the dielectric layer (4) in the seeding area (14) and electrically connected to the metal particle slurry (5).

2. The photovoltaic device according to claim 1, wherein the photovoltaic device further comprises a transparent conductive oxide layer located on the passivation layer (3).

3. The photovoltaic device according to any of the preceding claims, wherein, The patterned metal seed layer (12) comprises multiple sublayers (12a, 12b) of at least two different metals.

4. The photovoltaic device according to any of the preceding claims, wherein, The metal particle slurry (5) comprises metal particles with a diameter of 1 μm to 10 μm, preferably 2 μm to 5 μm.

5. The photovoltaic device according to any of the preceding claims, wherein, The passivation layer (3) comprises one of SiC, a-Si, nc-Si, μc-Si, poly-Si, poly-SiOx or a metal oxide such as tungsten oxide, molybdenum oxide or titanium oxide, and the passivation layer is optionally doped with a dopant such as boron or phosphorus.

6. The photovoltaic device according to any of the preceding claims, wherein, The passivation layer (3) has a thickness of less than 50 nm.

7. The photovoltaic device according to claim 6, wherein, The passivation layer (3) is thinner outside the seeding area (14) than inside the seeding area (14).

8. The photovoltaic device according to any of the preceding claims, wherein, The dielectric layer (3) outside the seeding area (14) has a thickness of 50 nm to 150 nm, and is preferably SiO2. x SiN x SiO x N y Or one of Al2O3, which has a thickness of 5 to 20 nm.

9. A method for manufacturing a photovoltaic device according to any of the preceding claims, the method comprising the following steps: - A silicon substrate (1) is provided, wherein a tunneling layer (2) is provided on the silicon substrate and a passivation layer (3) is provided on the tunneling layer (2). - Deposit a metal seed layer (12) on the passivation layer; - A metal particle paste (5) is printed on the metal seed layer (12), the metal particle paste (5) being arranged to serve as an etching mask to define the seed area (14). - Etch away the metal seed layer (12) outside the seeding area (14) to expose the passivation layer (3) outside the seeding area (14); - Deposit a dielectric layer (4) on the exposed passivation layer (3) and the metal particle slurry (5) such that the passivation layer (4) is discontinuous on the metal particle slurry (5); - A metal plating layer (9) is formed, which is superimposed on the metal particle slurry (5) and electrically connected to the metal particle slurry.

10. The method according to claim 9, wherein, Prior to the step of depositing the dielectric layer (5), the passivation layer (3) is etched back outside the seed area (14) to reduce the thickness of the passivation layer outside the seed area (14).

11. The method according to any one of claims 9 or 10, wherein, An annealing step is performed after the dielectric layer (4) is deposited.

12. The method according to any one of claims 9 to 11, wherein, The metal seed layer (12) is formed by physical vapor deposition, preferably by sputtering.

13. The method according to any one of claims 9 to 12, wherein, The metal seed layer (12) is deposited as at least two sublayers (12a, 12b) of different metals.

14. The method according to any one of claims 9 to 13, the method further comprising the step of depositing a transparent conductive oxide layer on the passivation layer (3).

15. The method according to any one of claims 9 to 14, wherein, At least one of the following is true: - The metal particle slurry (5) comprises metal slurry particles with a diameter of 1 μm to 10 μm, preferably 2 μm to 5 μm; - The thickness of the tunneling layer (2) is between 1 nm and 1.5 nm, and is preferably made of SiO2. x Made; - The passivation layer (3) has a thickness of less than 50 nm, and is preferably made of polycrystalline silicon, SiC, or poly-SiO2. x , a-Si / nc-Si / µc-Si, such as MO x WO x TiO x The passivation layer is a metal oxide, and optionally doped with elements such as boron or phosphorus; - The dielectric layer (4) outside the seeding area has a thickness of 50 nm to 150 nm, and preferably includes SiO2. x SiN x SiO x N y Or one or more of Al2O3, which has a thickness of 5 to 20 nm.

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