Enhanced integrated circuit heat dissipation using passive metal wires

Abstract

An electronic device includes one or more substrates carrying active circuitry; a heat sink structure; one or more thermal through-substrate vias (TTSVs) forming a first set of one or more thermally conductive paths between the one or more substrates and the heat sink structure; and one or more metallized lines disposed in the one or more substrates, wherein in a first operating mode of the active circuitry, the one or more metallized lines carry active signals of the active circuitry, and in a second operating mode of the active circuitry in which the one or more metallized lines do not carry active signals of the active circuitry, the one or more metallized lines are connected as thermally conductive branches that form a second set of one or more thermally conductive paths in thermal contact with the first set of one or more thermally conductive paths.

Description

Technical Field

[0001] This disclosure relates generally to integrated circuit technology, and more specifically to heat dissipation structures for dissipating heat generated in integrated circuits. Background Technology

[0002] Integrated circuit (IC) technology has made significant strides in improving computing power through the miniaturization of electronic components. An IC can be implemented as an IC chip on which a set of circuits is integrated. In some implementations, one or more IC chips can be physically carried and protected by an IC package, where the various power and signal nodes of the one or more IC chips can be electrically coupled to corresponding conductive terminals of the IC package via electrical paths formed in the package substrate. Various packaging technologies are found in many electronic devices, including processors, servers, radio frequency (RF) integrated circuits, etc. Advanced packaging and processing technologies can be used to realize complex devices such as multi-electro-component devices and system-on-a-chip (SoC) devices, which may include multiple functional blocks, each designed to perform a specific function, such as microprocessor functions, graphics processing unit (GPU) functions, communication functions (e.g., WiFi, Bluetooth, and other communications), etc.

[0003] As these circuits become more complex and densely packaged, they inherently generate significant amounts of heat during operation. This heat generation presents significant challenges that can impact the performance, reliability, and lifespan of the IC. For ICs comprising a single substrate, the heat generated is primarily due to the active transistors within the circuitry. However, as the number of transistors on a single substrate increases, so does the heat generated. Stacked substrates present even more complex heat dissipation challenges. Stacking multiple substrates increases component density, leading to even higher heat generation. The proximity of substrates in a stacked configuration can hinder effective heat dissipation, causing heat to accumulate both within and between layers. Summary of the Invention

[0004] The following is a simplified summary of the invention relating to one or more aspects disclosed herein. Therefore, this summary should not be considered an exhaustive overview relating to all conceived aspects, nor should it be considered to identify key or decisive elements relating to all conceived aspects or to depict the scope associated with any particular aspect. Thus, the sole purpose of this summary is to present, in a simplified form, certain concepts relating to one or more aspects involving the mechanisms disclosed herein, prior to the detailed description presented below.

[0005] In one aspect, an electronic device includes one or more substrates carrying active circuitry; a heat sink structure disposed outside the one or more substrates; one or more thermally penetrating substrate vias (TTSVs) forming a first set of one or more thermally conductive paths between the one or more substrates and the heat sink structure; and one or more metallized lines disposed in the one or more substrates, wherein in a first operating mode of the active circuitry, the one or more metallized lines carry an active signal of the active circuitry, and in a second operating mode of the active circuitry in which the one or more metallized lines do not carry an active signal of the active circuitry, the one or more metallized lines are connected as thermally conductive branches forming a second set of one or more thermally conductive paths in thermal contact with the first set of one or more thermally conductive paths.

[0006] In one aspect, a heat dissipation structure includes: a heat sink structure disposed outside one or more substrates carrying an active circuit; one or more thermal through-substrate vias (TTSVs) forming a first set of one or more thermally conductive paths between the one or more substrates and the heat sink structure; and one or more metallized lines disposed in the one or more substrates, wherein in a first operating mode of the active circuit, the one or more metallized lines carry an active signal of the active circuit, and in a second operating mode of the active circuit, the one or more metallized lines do not carry an active signal of the active circuit, and the one or more metallized lines are connected as thermally conductive branches forming a second set of one or more thermally conductive paths in thermal contact with the first set of one or more thermally conductive paths.

[0007] In one aspect, a method of operating a heat dissipation structure to dissipate heat generated by an active circuit of one or more substrates includes: providing one or more thermally penetrating substrate vias (TTSVs) through at least one of the one or more substrates to form a first set of one or more thermally conductive paths between at least one of the one or more substrates and a heat sink structure; configuring one or more metallized lines of at least one substrate to carry an active signal of the active circuit in a first operating mode of the active circuit; and in a second operating mode of the active circuit in which one or more metallized lines do not carry an active signal of the active circuit, connecting one or more metallized lines as thermally conductive branches to one or more TTSVs as thermally conductive lines, and disconnecting one or more metallized lines so that they do not operate as signal-carrying lines.

[0008] Based on the accompanying drawings and detailed description, other objects and advantages associated with the aspects disclosed herein will be apparent to those skilled in the art. Attached Figure Description

[0009] When considered in conjunction with the accompanying drawings, a more complete understanding of the various aspects of this disclosure and its many advantages therefrom will become better understood by referring to the following detailed description, which is presented for illustrative purposes only and does not constitute any limitation on this disclosure.

[0010] Figure 1 An example of a thermal management architecture that can be used in the context of an electronic package having a single die mounted on a substrate, according to various aspects of this disclosure, is shown.

[0011] Figure 2 An example of a thermal management architecture that can be used in the context of an electronic package having a single die mounted on a substrate, according to various aspects of this disclosure, is shown.

[0012] Figure 3 Examples of three-dimensional electronic packages according to various aspects of this disclosure are shown.

[0013] Figure 4 Examples of stacked substrate electronic packages having through-substrate vias (TSVs) according to various aspects of this disclosure are shown.

[0014] Figure 5 Examples of thermally penetrating substrate vias (TTSVs) and thermally conductive branches of exemplary heat dissipation structures according to various aspects of this disclosure are shown.

[0015] Figure 6A An electronic package with an example heat dissipation structure according to various aspects of the present disclosure is shown, wherein the active circuitry of the substrate of the electronic package is in a first operating mode.

[0016] Figure 6B An example heat dissipation structure is shown in which the active circuitry of the substrate of the electronic package is in a second operating mode, according to various aspects of the present disclosure.

[0017] Figure 7A and Figure 7B Examples are shown in respect of various aspects of this disclosure in which an antifuse wire can be used to connect a metallized wire as part of a heat dissipation structure.

[0018] Figure 8A and Figure 8B Another example according to various aspects of this disclosure is shown, in which multiple antifuse wires can be used to connect multiple metallized lines as heat-conducting branches of a heat dissipation structure.

[0019] Figure 9An example of a nanoelectromechanical system (NEMS) switch according to various aspects of this disclosure is shown, which can be used to selectively connect and disconnect metallized lines as heat-conducting branches of a heat-dissipating structure.

[0020] Figure 10 Examples of how NEMS switches can be embedded in electronic packages according to various aspects of this disclosure are illustrated.

[0021] Figure 11 This is a flowchart illustrating an example method of using an operational heat dissipation structure according to various aspects of this disclosure to dissipate heat generated by active circuitry on one or more substrates.

[0022] Figure 12 A cross-sectional view of a package including a surface mount substrate, an integrated device, and an integrated passive device, according to various aspects of this disclosure, is illustrated.

[0023] Figure 13 Example methods for providing or manufacturing packages comprising integrated devices having electronic components mounted in a core, according to various aspects of this disclosure, are illustrated.

[0024] Figure 14 Examples of various electronic devices that may integrate any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked packages (PoP), system-in-package (SiP), or system-on-a-chip (SoC).

[0025] By convention, the features depicted in the accompanying drawings may not be drawn to scale. Accordingly, for clarity, the dimensions of the depicted features may be arbitrarily enlarged or reduced. By convention, some drawings are simplified for clarity. Therefore, the drawings may not depict all components of a particular device or method. Furthermore, similar reference numerals are used throughout the specification and drawings to represent similar features. Detailed Implementation

[0026] Various aspects of this disclosure are illustrated in the following description and related figures with respect to specific embodiments. Alternative aspects or embodiments may be designed without departing from the scope of this teaching. Furthermore, well-known elements of the illustrative embodiments herein will not be described in detail or will be omitted to avoid obscuring the relevant details of the teachings in this disclosure.

[0027] In some of the described example implementations, instances are identified where various component structures and operational parts are available from known conventional techniques and are then arranged according to one or more exemplary embodiments. In such instances, internal details of known conventional component structures and / or operational parts may be omitted to help avoid potential confusion with the concepts illustrated in the exemplary embodiments disclosed herein.

[0028] Advanced semiconductor manufacturing nodes, particularly those reaching 4nm and 3nm specifications, have enabled the integration of over 100 million transistors per square millimeter on silicon substrates. This technological advancement allows a significant number of functional logic components to be housed within a minimized silicon footprint, thereby enhancing space efficiency and performance capabilities in microelectronic devices.

[0029] However, the increase in logic density introduces significant engineering challenges, particularly regarding power density and thermal management. Thermal constraint has become a major bottleneck in modern semiconductor design, surpassing other design parameters. High power density leads to increased heat generation, necessitating innovative thermal mitigation strategies to maintain device integrity and performance. In the absence of effective heat dissipation mechanisms, semiconductor devices are prone to performance throttling, reliability issues, and reduced operational lifetime.

[0030] These challenges are further amplified by the implementation of advanced packaging technologies such as 3D stacking, observed in some modern processors. While these approaches optimize die space and enable vertical IC integration, they also exacerbate thermal challenges due to limited heat dissipation, as evidenced by the thermal thresholds (limited to 89°C to 95°C) in variants equipped with 3D caches. This configuration leads to heat buildup within the stacked layers, requiring more sophisticated and efficient cooling solutions.

[0031] Enhanced thermal dissipation design is needed to support the ongoing trend of vertical IC scaling and to improve the performance of 2D designs by providing additional thermal headroom. The key to optimizing thermal dissipation lies in effectively managing heat sources within the system-on-chip (SoC). Greater dissipation efficiency is achieved when heat generation is evenly distributed across the die, preventing the formation of concentrated hot spots. This uniform heat distribution facilitates more efficient heat transfer processes, making it easier to extract heat from the SoC, thereby improving overall system performance and reliability.

[0032] In the field of flip chip design, there are two main architectures for facilitating heat dissipation from silicon dies, each of which utilizes thermal interface materials (TIMs) to enhance thermal conductivity and manage heat flow. Figure 1An example of a thermal management architecture according to aspects of this disclosure is shown for use in an electronic package 100 having a single die 102 mounted on a substrate 104. In one aspect, the die 102 is directly coupled to a heat sink 106 using a layer of thermal interface material (TIM) 108. The TIM 108 acts as a thermally conductive medium, filling the small air gap between the die 102 and the heat sink 106 to reduce thermal resistance. Figure 1 The heat transfer efficiency in the example shown depends on the characteristics of the selected TIM 108. In one aspect, the TIM 108 is formed of a material with high thermal conductivity to effectively absorb heat from the die 102, which is then dissipated through the heat sink 106.

[0033] Figure 2 An example of a thermal management architecture, according to various aspects of this disclosure, can be used in the context of an electronic package 200 having a single die 202 mounted on a substrate 204. Figure 1 Compared to the direct connection method shown in the thermal management architecture, Figure 2 The illustrated thermal management architecture incorporates an integrated heat sink (IHS) 206 as an intermediate heat conductor. The die 202 is first mated to the IHS 206 via a TIM layer 208, effectively distributing the heat generated by the active circuitry of the die 202 over a larger surface area to homogenize heat distribution. On the other hand, a second TIM layer 210 is applied between the IHS 206 and the heat sink 212 to further facilitate heat transfer. This two-stage dissipation process tends to be more efficient in managing hot spots and distributing heat evenly, although it results in a slight increase in thermal resistance due to the additional layers.

[0034] In the field of 3D ICs, the complexity of multi-layer chip architectures presents another set of engineering challenges in managing heat dissipation. Figure 3 An example of a three-dimensional electronic package 300 according to various aspects of the present disclosure is shown. In this example, the electronic package 300 is a multi-substrate configuration consisting of three vertically stacked substrates, each substrate including a die and a corresponding interconnect layer. Here, substrate 302 is the bottom substrate, substrate 304 is the middle substrate, and substrate 306 is the top substrate. Each substrate 302, 304, and 306 includes dies 303, 305, and 307 carrying active circuitry and corresponding interconnect layers 308, 310, and 312. Interconnect layers 308, 310, and 312 function in routing signals and providing power to the circuitry on dies 303, 305, and 307.

[0035] In this example, micro-connection structures 314 and 316 are used to interconnect substrates 302, 304, and 306, establishing mechanical and electrical connections between the upper surface of one substrate and an interconnection layer above it. These structures are used to maintain vertical connectivity and power flow between substrates 302, 304, and 306.

[0036] Embedded within each substrate 302, 304, 306 and its corresponding interconnect layers 308, 310, 312 are through-substrate vias (TSVs) (see, for example, TSV 318). These through-substrate vias (TSVs) are vertical metallized pathways that carry power and signals to the active circuitry on the dies 303, 305, 307, thereby facilitating efficient layer-to-layer connectivity and power distribution within the stacked substrate.

[0037] The interconnect layer 308 of the bottom substrate 302 is mated to the package substrate 320 using C4 (Controlled Collapse Chip Connector) solder bumps 322. The C4 solder bumps 322 provide both mechanical support and electrical connectivity, ensuring signal and power continuity from the bottom substrate 302 to the package substrate 320. Furthermore, the package substrate 320 is mounted on a printed circuit board (PCB) 324 using CV GAA (Vertical Grid Array Compatible Assembly) connectors 326. These dedicated CV GAA connectors 326 provide reliable, high-density interconnects that accommodate thermal and mechanical stresses between the package substrate and the PCB, ensuring the integrity of signal and power transmission to the wider electronic system.

[0038] The electronic package 300 also includes structures for managing heat dissipation. In this example, a TIM layer 328 is applied to the upper surface of the substrate 306 to establish a thermal link between the substrate 306 and the vapor chamber 330. The vapor chamber 330 is directly connected to the heat sink 332.

[0039] On one hand, the signal carrier TSV helps transfer heat from the lower layers to substrate 306. However, the heat sink 332 is located only at the top layer of the stack (e.g., substrate 306) and is isolated from the lower layers (e.g., substrates 302, 304). Some aspects of this disclosure were made with the understanding that this arrangement severely limits the direct path of heat conduction from the lower substrates 302, 304 to the heat sink 332, resulting in suboptimal heat dissipation. Therefore, the lower substrates 302, 304 maintain a high thermal load, which directly affects and limits their operating frequency. The inability to efficiently extract accumulated heat from the lower substrates 302, 304 means that the IC cannot operate at its maximum potential without the risk of thermal failure.

[0040] Some aspects of this disclosure relate to an electronic package with a heat dissipation structure that establishes a more direct conduction path from the underlying substrate to a heat sink structure (e.g., a vapor chamber, a TIM layer, a heat sink, or a combination thereof) responsible for dissipating heat from the electronic package to the environment (e.g., the ambient environment, a cooling fluid environment, etc.). However, some aspects of this disclosure are achieved in recognition of the challenges posed by potential solutions such as incorporating multiple metallization layers specifically dedicated to heat conduction within each die. While theoretically feasible, implementing such multiple dedicated layers can be extremely expensive, increasing manufacturing process complexity, slowing down manufacturing, and adding unnecessary thickness to the IC.

[0041] In IC manufacturing technology, through-substrate vias (TSVs) are vertical electrical connections (vias) that pass completely through the substrate, thereby providing high-performance data traversal and better packaging density. Figure 4 An example of a stacked substrate electronic package 400 having a TSV 402 according to various aspects of this disclosure is shown. In this example, the TSV 402 (to avoid cluttering the diagram, in...) Figure 4 The via network (not all TSVs are labeled) forms a plurality of substrates (shown as substrates 1 to 5) forming an interconnect electronic package 400. In one aspect, each substrate may include one or more dies disposed on a corresponding interconnect layer. Figure 4 The TSV 402 shown carries active signals (e.g., power signals, logic signals, etc.) associated with active circuitry formed on the die of the substrate.

[0042] According to various aspects of this disclosure, the heat dissipation structure is integrated into the basic structure of the electronic package 400, such as Figure 4 As shown. The heat dissipation structure includes structures that form thermally conductive paths within and between the substrates, which facilitate the extraction of heat from the electronic package 400.

[0043] According to various aspects of this disclosure, a thermally conductive path within the context of a heat dissipation structure in an electronic package refers to a specially designed route or medium within the electronic package that facilitates efficient heat transfer away from heat-generating components (e.g., active circuitry of the die). In one aspect, the thermally conductive path may be characterized by materials or structures with high thermal conductivity, thereby enabling rapid and efficient heat transfer. These materials or structures may include, but are not limited to, metal layers, thermal vias, specialized gels or pastes, and composite materials designed to absorb heat from critical areas of the electronic package.

[0044] According to certain aspects of this disclosure, example heat dissipation structures may include various types of thermally conductive elements interconnected to serve as heat conduction paths that collect heat from the die and conduct it to a heat sink structure for dissipation from the electronic package 400. In one aspect, the heat dissipation structure may include dedicated thermal TSVs (TTSVs) that extend between different levels of the electronic package to facilitate heat transfer from lower to uppermost levels, the uppermost level having a heat sink structure available for dissipating heat from the electronic package. Figure 4 Unlike the TSV 402 shown, the TTSV with the heat dissipation structure is dedicated to collecting heat and forming thermal paths between the layers of the electronic package 400.

[0045] According to certain aspects of this disclosure, the heat dissipation structure includes thermally conductive branches that form a thermally conductive path for conducting heat from the substrate to the TTSV. Figure 5 Examples of TTSVs and thermally conductive branches of an example heat dissipation structure 500 according to various aspects of this disclosure are shown. In one aspect, the heat dissipation structure 500 may include a plurality of TTSVs 502 extending through all substrates. In some scenarios, a given TTSV 502 does not need to extend through all substrates, provided that the given TTSV has a thermally conductive path that connects it to other TTSVs that ultimately conduct heat to the heat dissipation module.

[0046] The example heat dissipation structure 500 also includes permanent thermally conductive branches 504 disposed between layers. In one aspect, the permanent thermally conductive branches 504 are fixed during the manufacturing stage and are dedicated to heat transfer. Figure 5 In the example shown, the permanent thermally conductive branches 504 of the heat dissipation structure 500 extend between the TTSVs 502 and provide a thermal path to the TTSVs 502. However, based on the teachings of this disclosure, it will be understood that some of the permanent thermally conductive branches 504 may contact a single TTSV 502 and, as will be discussed in further detail below, still serve as part of the heat dissipation structure 500.

[0047] Some aspects of this disclosure are realized in the understanding that metallization lines associated with a die of an electronic package can carry active signals of the active circuitry of the die at one time while being prohibited from carrying active signals at another time. For the purposes of this disclosure, the state of the metallization lines can be described in the context of the state (e.g., operating mode) of the active circuitry served by the metallization lines. According to aspects of this disclosure, metallization lines carry active signals of the active circuitry in a first operating mode of the active circuitry, in which the active circuitry associated with the active circuitry operates for a given purpose. In one aspect, metallization lines do not carry active signals of the active circuitry associated with them in a second operating mode of the active circuitry, because the active circuitry no longer needs to be connected to the metallization lines for a given purpose. Some aspects of this disclosure recognize that metallization lines that no longer carry active signals can be used as thermal branches during the second operating mode of the active circuitry. Such metallization lines can be used as part of a heat dissipation structure to provide a set of thermal paths to the TTSV (e.g., by direct attachment to the TTSV or by permanent thermal branches).

[0048] In one aspect, the first operating mode may be associated with a diagnostic mode (e.g., a debugging and / or quality control mode) in which components of the electronic package are tested. In such cases, when the electronic package undergoes diagnostic testing, certain metallized lines carry only active signals. Once such diagnostic operations are completed, the metallized lines are no longer needed to carry active signals from the active circuitry. At this point, the active circuitry is effectively in a second operating mode, where the metallized lines no longer carry active signals, but the active circuitry is used for its intended end purpose (e.g., the active circuitry operates in normal mode). Such unused metallized lines (e.g., metallized lines used to carry diagnostic control signals in the first mode no longer need to be used to carry active signals for standard operation of the corresponding active control circuitry) can be connected as thermally conductive branches of a heat dissipation structure.

[0049] In view of the foregoing, certain aspects of this disclosure relate to a heat dissipation structure configured to dissipate heat generated by active circuitry of one or more dies. In one aspect, the heat dissipation structure includes a heat sink structure. The heat dissipation structure also includes one or more thermal through-substrate vias (TTSVs) forming a first set of one or more thermally conductive paths between at least one die carrying the active circuitry and the heat sink structure. In another aspect, the heat dissipation structure also includes one or more metallized lines disposed in at least one die, wherein 1) in a first operating mode of the active circuitry, the one or more metallized lines carry an active signal of the active circuitry, and 2) in a second operating mode of the active circuitry in which the one or more metallized lines do not carry an active signal of the active circuitry, the one or more metallized lines are connected as thermally conductive branches forming a second set of one or more thermally conductive paths in thermal contact with the first set of one or more thermally conductive paths.

[0050] Figure 6A An electronic package 600 with an exemplary heat dissipation structure according to aspects of the present disclosure is shown, wherein the active circuitry of the substrate of the electronic package is in a first operating mode. In this example, the electronic package 600 includes two substrates 602 and 604. Substrate 602 includes a die 606 carrying active circuitry (not shown) and an interconnect structure 608. Similarly, substrate 604 includes a die 610 carrying active circuitry (not shown) and an interconnect structure 612. A heat sink structure 614 is disposed at the upper portion of the electronic package 600 and is configured to dissipate heat generated in the electronic package 600 from the electronic package 600 to, for example, the surrounding environment or other heat dissipation medium. In one aspect, the heat sink structure 614 may include a vapor chamber, a heat sink, or a combination thereof.

[0051] In this example, the electronic package 600 includes signal-carrying metallized lines, thermally conductive elements, and actuable thermal interconnects, as indicated in the illustration. Here, the signal-carrying metallized lines include multiple TSVs 616 and metallized lines 618a and 618b (not all metallized lines are labeled), which carry electronic signals associated with active circuitry on substrates 602 and 604. The thermally conductive elements include one or more TTSVs 620 and corresponding thermally conductive branches 622. The TTSVs 620 and thermally conductive branches 622 form a thermally conductive path between substrates 602 and 604 and the heat sink structure 614.

[0052] An actuable thermal interconnect 624 is disposed between the metallization line 618b and the thermally conductive branch 622. However, the actuable thermal interconnect 624 is... Figure 6AThe circuit is inactive because the active circuitry of the substrate is in a first operating mode, in which the metallization line 618b carries signals associated with the active circuitry.

[0053] Figure 6B An example heat dissipation structure is shown in which the active circuitry of the substrate of the electronic package, according to various aspects of the present disclosure, is in a second operating mode. In this second operating mode, the metallization line 618b no longer carries signals from the active circuitry and can therefore be incorporated into the heat dissipation structure. For this purpose, the actuable thermal interconnect 624 is activated, thereby providing a thermal path between the metallization line 618b and the TTSV 620 via a thermally conductive branch 622.

[0054] In scenarios where the metallization line 618b is dedicated to diagnostic functions, the actuable thermal interconnect 624 can be permanently activated after the diagnostic operation is completed to include the metallization line 618b as part of the heat dissipation structure. For this purpose, fuses and / or antifuse wires can be inserted between the metallization line and other structures of the heat dissipation structure (e.g., permanently thermally conductive branches). Figure 7A and Figure 7B An example is shown whereby, according to various aspects of this disclosure, the antifuse 702 can be used to connect the metallized wire 704 as part of a heat dissipation structure. Figure 7A In this configuration, the active circuit associated with the metallized line 704 operates in the first mode and therefore carries the active signal associated with the corresponding active circuit. Therefore, the antifuse 702 is non-conductive and does not provide a thermal path to other parts of the heat dissipation structure (shown here as the permanent thermally conductive branch 706 and TTSV 708). Once the diagnostic operation is complete, the metallized line 704 is no longer needed by the associated active circuit and can be connected as part of the heat dissipation structure. For this purpose, the antifuse 702 is actuated, such that the metallized line 704 is placed in thermal contact with other parts of the heat dissipation structure (e.g., the permanent thermally conductive branch 706). The actuated antifuse 702 thus provides a thermal path to the heat dissipation structure. Therefore, the metallized line 704 is now as... Figure 7B This is part of the heat dissipation structure shown. In some scenarios, the metallized line 704 may be connected during the first mode to carry an active signal of the associated active circuit via a fuse (not shown). In the second mode, the fuse may be actuated to electrically disconnect the metallized line 704 from the associated active circuit.

[0055] Figure 8A and Figure 8BAnother example according to aspects of this disclosure is shown, in which multiple antifuses can be used to connect multiple metallized lines as thermally conductive branches of a heat dissipation structure. In this example, metallized lines 802, 804, and 806 may be associated with a redundant version of an active circuit used in an electronic package. Here, antifuses 808 and 810 are respectively disposed between metallized lines 802 and 804 and a permanent thermally conductive branch 812. Additionally, antifuses 814 and 816 are respectively disposed between metallized line 806 and metallized lines 802 and 804.

[0056] Once diagnostic operations have been completed and / or it has been determined that such redundant versions of the active circuitry are not required for further operation of the device embodied in the electronic package, antifuses 808, 810, 814, and 816 can be actuated to join metallized lines 802, 804, and 806 as heat-conducting branches of the heat dissipation structure, such as Figure 8B As shown. In this example, the actuated antifuses 814 and 816 provide a thermal path between metallization line 806 and metallization lines 802, 804. Furthermore, the actuated antifuses 808, 810 provide a thermal path between metallization lines 802, 804 and a permanent thermally conductive branch 812, which provides a thermal path to the TTSV 818. Based on the teachings of this disclosure, it will be appreciated that when a standard TSV is no longer needed to carry an active signal, the standard TSV can be similarly connected as a thermally conductive branch serving as a heat dissipation structure.

[0057] Some aspects of this disclosure recognize that certain portions of an active circuit may be active at one time but enter a static state at another time. Furthermore, some aspects of this disclosure recognize that when a portion of the active circuit is in a static state, certain metallization lines associated with those portions typically do not carry the active signals associated with those portions. Therefore, some aspects of this disclosure are implemented based on the recognition that metallization lines not carrying active signals when a portion of the active circuit is in a static state (e.g., when a portion of the active circuit is in a second mode) can be temporarily incorporated into a heat dissipation structure as thermally conductive branches. Therefore, some aspects of this disclosure relate to temporarily incorporating metallization lines associated with an active circuit into a heat dissipation structure when at least a portion of the active circuit is in a static state. Once such a portion of the active circuit exits the static state, the corresponding metallization lines can be disconnected as thermally conductive branches and used to carry the active signals of the active circuit.

[0058] In some aspects of this disclosure, metallized lines operating in the foregoing manner may be selectively interconnected with heat dissipation structures using nanoelectromechanical systems (NEMS) switches. Figure 9An example of a nanoelectromechanical system (NEMS) switch 900 according to various aspects of this disclosure is shown. The nanoelectromechanical system (NEMS) switch can be used to selectively connect and disconnect metallized lines as heat-conducting branches of a heat-dissipating structure. Figure 9 The NEMS switch 900 shown is merely an example of the NEMS structure and is incorporated herein for illustrative purposes. Therefore, based on the teachings of this disclosure, it will be appreciated that other configurations of the NEMS can be utilized.

[0059] In this example, the NEMS switch 900 includes a movable beam 902 fixed at one end to an anchor pad 904. In one aspect, the anchor pad 904 is connected to one or more thermally conductive branches of a heat dissipation structure. The movable beam 902 is movable between a static position (e.g., a first switching state shown at 906) and an active position (e.g., a second switching state shown at 908), in which the movable beam 902 is independent, and in which the movable beam 902 is in contact with a terminal element 910. In one aspect, the terminal element 910 is in thermal contact with a metallized wire 912, which is selectively connected and removed as a thermally conductive branch of the heat dissipation structure.

[0060] The NEMS switch 900 can be actuated at terminal 916 to move the movable beam 902 between a static position 906 and an active position 908 in response to a control signal provided at terminal 916. Here, terminal 916 receives a control signal carried by line 914. The control signal carried by line 914 provides an indication of whether the active circuit associated with the metallized line 912 is in a stationary state. When the active circuit associated with the metallized line 912 is in a stationary state, the movable beam 902 is driven to the active position 908, such that the movable beam 902 and the anchor pad 904 provide a thermal path to one or more components of the heat dissipation structure. When the active circuit associated with the metallized line 912 exits the stationary state, this change of state is indicated by a signal at line 914, which allows the movable beam 902 to return to the static position 906. In the static position 906, the metallization line 912 is disconnected from the heat dissipation structure and does not operate as a heat-conducting branch. At this time, the metallization line freely carries the active signal of the associated active circuit.

[0061] According to certain aspects of this disclosure, signals associated with active circuitry (such as reset and power gate signals) may be provided on line 914 to activate and deactivate the NEMS switch 900, as such signals typically indicate whether the active circuitry is in an active or inactive state. Alternatively, control signals on line 914 may be provided by a thermal control system configured to control the operation of the NEMS switch 900 by activating and deactivating the NEMS of the heat-dissipating structure.

[0062] Although the metallization line 912 is described as being associated with active circuitry, the NEMS switch 900 can be used to selectively provide thermal paths between different parts of the heat dissipation structure. In one example, a standard TSV can be connected to the anchor pad 904 via a thermal path and acts as a TTSV during times when the standard TSV is not used to carry an active signal.

[0063] Figure 10 An example of how a NEMS switch can be embedded in an electronic package according to various aspects of this disclosure is illustrated. Here, the NEMS switch 1000 is embedded in a substrate 1002 having a plurality of metallization layers 1004 and corresponding insulating layers 1006.

[0064] Materials used for permanent, one-off, and dynamic branches can be selected such that both electrical conductivity when carrying electrical signals for processing and thermal conductivity when absorbing heat as part of the ETCN in the desired direction are within the corresponding performance constraints.

[0065] The heat dissipation structure disclosed herein can be used to reduce the temperature of isolated hot spots in system-on-chip (SoC) devices and provides greater flexibility in thermal design. In some respects, the thermally conductive branches of the heat dissipation structure can be focused on such potential hot spots.

[0066] Furthermore, the disclosed heat dissipation structure can be used to mitigate differential aging issues observed in SoCs. On one hand, differential aging can occur because circuitry associated with hot spots ages faster than other circuitry. Since differential aging is specific to the user's workload, it is typically not compensable during the design phase. Because heat is absorbed by surrounding logic components and metal wires, aging becomes quite similar across different circuits. This also reduces power consumption due to lower operating temperatures and lower voltage requirements resulting from the slow and nearly uniform aging of all components, which in turn leads to a better SoC lifetime. In some scenarios, the estimated TTSV area overhead is less than 0.3% to 0.5%, and greater thermal stability is provided by adding more TTSV.

[0067] Figure 11This is a flowchart illustrating an example method 1100 for dissipating heat generated by active circuitry of one or more substrates using an operational heat dissipation structure according to various aspects of this disclosure. At operation 1102, one or more thermally penetrating substrate vias (TTSVs) are provided through at least one of the one or more substrates to form a first set of one or more thermally conductive paths between at least one of the one or more substrates and a heat sink structure. At operation 1104, in a first operating mode of the active circuitry, one or more metallized lines of at least one substrate are configured to carry active signals of the active circuitry. At operation 1106, in a second operating mode of the active circuitry where one or more metallized lines do not carry active signals of the active circuitry, one or more metallized lines are connected as thermally conductive branches to one or more TTSVs as thermally conductive lines, and one or more metallized lines are disconnected so that they do not operate as signal-carrying lines.

[0068] The technical advantage of method 1100 is that it provides a robust heat dissipation structure that utilizes the existing structure of the electronic package to realize the heat dissipation structure, thereby limiting the number of structures that need to be added to the electronic package to realize the heat dissipation structure.

[0069] Figure 12 A cross-sectional view of a package 1200, including a surface mount substrate 1202, an integrated device 1203, and an integrated passive device 1205, is illustrated according to various aspects of this disclosure. The package 1200 may be coupled to a printed circuit board (PCB) 1206 via a plurality of solder interconnects 1210. The PCB 1206 may include at least one board dielectric layer 1260 and a plurality of board interconnects 1262.

[0070] Surface mount substrate 1202 includes at least one dielectric layer 1220 (e.g., a substrate dielectric layer), a plurality of interconnects 1222 (e.g., substrate interconnects), a solder mask layer 1240, and a solder mask layer 1242. Integrated device 1203 can be coupled to surface mount substrate 1202 via a plurality of solder interconnects 1230. Integrated device 1203 can be coupled to surface mount substrate 1202 via a plurality of pillar interconnects 1232 and a plurality of solder interconnects 1230. Integrated passive device 1205 can be coupled to surface mount substrate 1202 via a plurality of solder interconnects 1250. Integrated passive device 1205 can be coupled to surface mount substrate 1202 via a plurality of pillar interconnects 1252 and a plurality of solder interconnects 1250.

[0071] The package (e.g., 1200) may be implemented in a radio frequency (RF) package. This RF package may be a radio frequency front-end (RFFE) package. The package (e.g., 1200) may be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 1200) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). The package (e.g., 1200) may be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0072] Figure 13 An example method 1300 for providing or manufacturing a package including an integrated device having electronic components mounted in a core, according to various aspects of this disclosure, is illustrated. In some specific embodiments, Figure 13 Method 1300 can be used to provide or manufacture the invention described in this disclosure. Figure 12 Package 1200. However, method 1300 can be used to provide or manufacture any package described in this disclosure.

[0073] It should be noted that, according to all aspects of this disclosure, Figure 13 The method may combine one or more processes to simplify and / or clarify the method for providing or manufacturing a package that includes an integrated device having electronic components mounted in a core. In some specific implementations, the order of the processes may be changed or modified.

[0074] The method (at 1305) provides a substrate (e.g., 1202). The substrate 1202 may be supplied by a vendor or manufactured in-house. The substrate 1202 includes at least one dielectric layer 1220 and a plurality of interconnects 1222. The substrate 1202 may include an embedded trace substrate (ETS). In some embodiments, at least one dielectric layer 1220 may include a prepreg layer.

[0075] The method (at 1310) couples at least one integrated device (e.g., 1203) to a first surface of a substrate (e.g., 1202). For example, the integrated device 1203 may be coupled to the substrate 1202 via a plurality of pillar interconnects 1232 and a plurality of solder interconnects 1230. The plurality of pillar interconnects 1232 may be optional. The plurality of solder interconnects 1230 are coupled to a plurality of interconnects 1222. A solder reflow process may be used to couple the integrated device 1203 to the plurality of interconnects via the plurality of solder interconnects 1230.

[0076] The method (at 1310) also couples at least one integrated passive device (e.g., 1205) to a first surface of a substrate (e.g., 1202). For example, the integrated passive device 805 can be coupled to the substrate 1202 via a plurality of pillar interconnects 1252 and a plurality of solder interconnects 1250. The plurality of pillar interconnects 1252 may be optional. The plurality of solder interconnects 1250 are coupled to a plurality of interconnects 1222. A solder reflow process can be used to couple the integrated passive device 1205 to the plurality of interconnects via the plurality of solder interconnects 1250.

[0077] The method (at 1315) couples a plurality of solder interconnects (e.g., 1210) to a second surface of a substrate (e.g., 1202). A solder reflow process can be used to couple the plurality of solder interconnects 1210 to the substrate.

[0078] Figure 14 Examples of various electronic devices that may integrate any of the following: the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, electronic components, interposer packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1402, laptop computer device 1404, fixed-location terminal device 1406, wearable device 1408, or motor vehicle 1414 may include device 1400 as described herein. For example, device 1400 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 14 The illustrated devices 1402, 1404, 1406, and 1408, as well as vehicle 1410, are merely exemplary. Other electronic devices may also feature device 1400, including but not limited to devices (e.g., electronic devices) comprising the following group: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (such as watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (such as autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0079] Specific implementation examples are described in the following numbering section: Aspect 1. An electronic device comprising: one or more substrates carrying an active circuit; a heat sink structure disposed outside the one or more substrates; one or more thermal through-substrate vias (TTSVs) forming a first set of one or more thermally conductive paths between the one or more substrates and the heat sink structure; and one or more metallized lines disposed in the one or more substrates, wherein in a first operating mode of the active circuit, the one or more metallized lines carry an active signal of the active circuit, and in a second operating mode of the active circuit in which the one or more metallized lines do not carry an active signal of the active circuit, the one or more metallized lines are connected as thermally conductive branches forming a second set of one or more thermally conductive paths in thermal contact with the first set of one or more thermally conductive paths.

[0080] Aspect 2. The electronic device according to aspect 1, wherein: the one or more TTSVs include a plurality of TTSVs; and the second set of one or more thermally conductive paths is positioned to thermally contact the first set of one or more thermally conductive paths through one or more permanent thermally conductive branches extending between the plurality of TTSVs.

[0081] Aspect 3. The electronic device according to any one of Aspects 1 to 2, the electronic device further comprising: one or more antifuse wires configured to connect the one or more metallized lines as the thermally conductive branches; and one or more fuses configured to disconnect the one or more metallized lines so that they do not carry the active signal of the active circuit.

[0082] Aspect 4. The electronic device according to any one of Aspects 1 to 3, the electronic device further comprising: a group of one or more nanoelectromechanical systems (NEMS) switches, the group of one or more NEMS switches having a first switching state and a second switching state, wherein in the first switching state, the first group of one or more NEMS switches is configured to connect the one or more metallized lines as the thermally conductive branches, and in the second switching state, the first group of one or more NEMS switches is configured to remove the one or more metallized lines serving as the thermally conductive branches.

[0083] Aspect 5. The electronic device according to any one of Aspects 1 to 4, wherein: the first operating mode of the active circuit is a diagnostic operating mode of the active circuit; and the second operating mode of the active circuit is a normal operating mode of the active circuit.

[0084] Aspect 6. The electronic device according to any one of Aspects 1 to 5, wherein: the first operating mode of the active circuit is the normal operating mode of the active circuit; and the second operating mode of the active circuit is associated with one or more portions of the active circuit that are in a static state.

[0085] Aspect 7. The electronic device according to Aspect 6, wherein: the one or more metallized lines carry active signals associated with the one or more portions of the active circuit when the active circuit is in the first operating mode, and do not carry active signals associated with the one or more portions of the active circuit when the active circuit is in the second operating mode.

[0086] Aspect 8. An electronic device according to any one of Aspects 1 to 7, wherein: the one or more substrates include a plurality of stacked substrates; the one or more TTSVs extend through the plurality of stacked substrates to form a first set of one or more thermal conductive paths; and the first set of one or more thermal conductive paths includes at least one thermal conductive path located between each of the plurality of stacked substrates and the heat sink structure.

[0087] Aspect 9. An electronic device according to any one of Aspects 1 to 8, wherein the electronic device comprises at least one of: a music player; a video player; an entertainment unit; a navigation device; a communication device; a mobile device; a mobile phone; a smartphone; a personal digital assistant; a fixed-location terminal; a tablet computer; a computer; a wearable device; a laptop computer; a server; an Internet of Things (IoT) device; or a device in a motor vehicle.

[0088] Aspect 10. A heat dissipation structure comprising: a heat sink structure disposed outside one or more substrates carrying an active circuit; one or more thermal through-substrate vias (TTSVs) forming a first set of one or more thermally conductive paths between the one or more substrates and the heat sink structure; and one or more metallized lines disposed in the one or more substrates, wherein in a first operating mode of the active circuit, the one or more metallized lines carry an active signal of the active circuit, and in a second operating mode of the active circuit, the one or more metallized lines do not carry an active signal of the active circuit, and the one or more metallized lines are connected as thermally conductive branches forming a second set of one or more thermally conductive paths in thermal contact with the first set of one or more thermally conductive paths.

[0089] Aspect 11. The heat dissipation structure according to aspect 10, wherein: the one or more TTSVs include a plurality of TTSVs; and the second set of one or more heat conduction paths is positioned to thermally contact the first set of one or more heat conduction paths through one or more permanent heat conduction branches extending between the plurality of TTSVs.

[0090] Aspect 12. The heat dissipation structure according to any one of Aspects 10 to 11, the heat dissipation structure further comprising: one or more antifuse wires configured to connect the one or more metallized lines as the heat-conducting branches; and one or more fuses configured to disconnect the one or more metallized lines so that they do not carry the active signal of the active circuit.

[0091] Aspect 13. The heat dissipation structure according to any one of Aspects 10 to 12, the heat dissipation structure further comprising: a group of one or more nanoelectromechanical systems (NEMS) switches having a first switching state and a second switching state, wherein in the first switching state, the first group of one or more NEMS switches is configured to connect the one or more metallized lines as the heat-conducting branches, and in the second switching state, the first group of one or more NEMS switches is configured to disconnect the one or more metallized lines so that they do not act as the heat-conducting branches.

[0092] Aspect 14. The heat dissipation structure according to any one of Aspects 10 to 13, wherein: the first operating mode of the active circuit is a diagnostic operating mode of the active circuit; and the second operating mode of the active circuit is a normal operating mode of the active circuit.

[0093] Aspect 15. The heat dissipation structure according to any one of Aspects 10 to 14, wherein: the first operating mode of the active circuit is the normal operating mode of the active circuit; and the second operating mode of the active circuit is associated with one or more portions of the active circuit that are in a static state.

[0094] Aspect 16. The heat dissipation structure according to aspect 15, wherein: the one or more metallization lines carry active signals associated with the one or more portions of the active circuit when the active circuit is in the first operating mode, and do not carry active signals associated with the one or more portions of the active circuit when the active circuit is in the second operating mode.

[0095] Aspect 17. The heat dissipation structure according to any one of Aspects 10 to 16, wherein: the one or more substrates include a plurality of stacked substrates; the one or more TTSVs extend through the plurality of stacked substrates to form a first set of one or more thermally conductive paths; and the first set of one or more thermally conductive paths includes at least one thermally conductive path located between each of the plurality of stacked substrates and the heat sink structure.

[0096] Aspect 18. The heat dissipation structure according to any one of Aspects 10 to 17, wherein the heat sink structure comprises: a heat spreader; a heat sink; or a combination thereof.

[0097] Aspect 19. A method of operating a heat dissipation structure to dissipate heat generated by an active circuit of one or more substrates, the method comprising: providing one or more thermally penetrating substrate vias (TTSVs) through at least one of the one or more substrates to form a first set of one or more thermally conductive paths between the at least one substrate and a heat sink structure; configuring one or more metallized lines of the at least one substrate to carry an active signal of the active circuit in a first operating mode of the active circuit; and in a second operating mode of the active circuit in which the one or more metallized lines do not carry an active signal of the active circuit, connecting the one or more metallized lines as thermally conductive branches to the one or more TTSVs as thermally conductive lines, and disconnecting the one or more metallized lines so that they do not operate as signal-carrying lines.

[0098] Aspect 20. The method according to aspect 19, the method further comprising: actuating one or more antifuse wires to connect the one or more metallized lines as the thermally conductive branches; and actuating one or more fuse wires to disconnect the one or more metallized lines so that they do not carry the active signal of the active circuit.

[0099] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. The term “electrical coupling” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can travel between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term “encapsulation” means that an object may partially or completely encapsulate another object. The terms “top” and “bottom” are arbitrary. A component located at the top may be above a component located at the bottom. A top component may be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component may mean that the first component is above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, and a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component may be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. The terms "about 'value X'" or "approximately value X" as used in this disclosure mean within 10% of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9 to 1.1.

[0100] In some embodiments, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some embodiments, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metallization layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0101] It should also be noted that the various disclosures contained herein can be described as processes depicted as flowcharts, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0102] As can be seen in the detailed description above, different features are grouped together in the examples. This manner of disclosure should not be construed as an intention to have more features in the example aspects than are explicitly mentioned in each aspect. Rather, the various aspects of this disclosure may include fewer features than those in the individual example aspects disclosed. Therefore, the following aspects should be regarded accordingly as incorporated into the description, where each aspect can be considered as a separate example on its own. Although each dependent aspect may refer in the aspect to a particular combination with one aspect of other aspects, the aspect of the dependent aspect is not limited to that particular combination. It should be understood that other example aspects may also include combinations of the subject matter of a dependent aspect with any other dependent or independent aspect, or any feature combined with other dependent and independent aspects. The various aspects disclosed herein expressly include these combinations unless explicitly stated or readily inferred that a particular combination is not intended for use (e.g., contradictory aspects, such as defining an element as both an electrical insulator and an electrical conductor). Furthermore, it is contemplated that aspects of an aspect may be included in any other independent aspect, even if that aspect does not directly depend on the independent aspect.

[0103] While the foregoing disclosure illustrates exemplary aspects of this disclosure, it should be noted that various changes and modifications may be made herein without departing from the scope of this disclosure as defined by the appended claims. The functions, steps, and / or actions of the method claims according to the aspects of this disclosure described herein need not be performed in any particular order. Furthermore, although elements of this disclosure may be described or claimed in the singular, the plural form may also be considered unless expressly stated as limited to the singular.

Claims

1. An electronic device, the electronic device comprising: One or more substrates, the one or more substrates having active circuitry; A heat sink structure, wherein the heat sink structure is disposed outside the one or more substrates; One or more thermally penetrating substrate vias (TTSVs) form a first set of one or more thermally conductive paths between the one or more substrates and the heat sink structure; and One or more metallization lines are disposed in the one or more substrates, wherein... In the first operating mode of the active circuit, the one or more metallized lines carry the active signals of the active circuit, and In a second operating mode of the active circuit in which one or more metallized lines do not carry active signals of the active circuit, the one or more metallized lines are connected as thermally conductive branches, which form a second set of one or more thermally conductive paths that are in thermal contact with the first set of one or more thermally conductive paths.

2. The electronic device according to claim 1, wherein: The one or more TTSVs include multiple TTSVs; and The second group of one or more heat conduction paths is positioned to thermally contact the first group of one or more heat conduction paths via one or more permanent heat conduction branches extending between the plurality of TTSVs.

3. The electronic device according to claim 1, further comprising: One or more antifuse wires, the one or more antifuse wires being configured to connect the one or more metallized wires as the heat-conducting branches; and One or more fuses configured to disconnect the one or more metallized lines so that they do not carry the active signal of the active circuit.

4. The electronic device according to claim 1, further comprising: A group of one or more nanoelectromechanical systems (NEMS) switches having a first switching state and a second switching state, wherein in the first switching state, the first group of one or more NEMS switches is configured to connect the one or more metallized lines as the thermally conductive branches, and in the second switching state, the first group of one or more NEMS switches is configured to remove the one or more metallized lines serving as the thermally conductive branches.

5. The electronic device according to claim 1, wherein: The first operating mode of the active circuit is the diagnostic operating mode of the active circuit; and The second operating mode of the active circuit is the normal operating mode of the active circuit.

6. The electronic device according to claim 1, wherein: The first operating mode of the active circuit is the normal operating mode of the active circuit; and The second operating mode of the active circuit is associated with one or more portions of the active circuit that are in a static state.

7. The electronic device according to claim 6, wherein: The one or more metallized lines carry active signals associated with the one or more portions of the active circuit when the active circuit is in the first operating mode, and do not carry active signals associated with the one or more portions of the active circuit when the active circuit is in the second operating mode.

8. The electronic device according to claim 1, wherein: The one or more substrates include multiple stacked substrates; The one or more TTSVs extend through the plurality of stacked substrates to form the first set of one or more thermal conductive paths; and The first group of one or more thermal paths includes at least one thermal path located between each of the plurality of stacked substrates and the heat sink structure.

9. The electronic device of claim 1, wherein the electronic device comprises at least one of the following: Music player; Video player; Entertainment section; Navigation equipment; Communication equipment; mobile device; Mobile phones; Smartphone; Personal digital assistant; Fixed-location terminal; Tablet computers, computers; Wearable devices; Laptop computers; server; Internet of Things (IoT) devices; or Equipment in motor vehicles.

10. A heat dissipation structure, the heat dissipation structure comprising: A heat sink structure disposed outside one or more substrates having active circuitry; One or more thermally penetrating substrate vias (TTSVs) form a first set of one or more thermally conductive paths between the one or more substrates and the heat sink structure; and One or more metallization lines are disposed in the one or more substrates, wherein... In the first operating mode of the active circuit, the one or more metallized lines carry the active signals of the active circuit, and In the second operating mode of the active circuit, the one or more metallized lines do not carry the active signal of the active circuit, and the one or more metallized lines are connected as thermally conductive branches, which form a second set of one or more thermally conductive paths that are in thermal contact with the first set of one or more thermally conductive paths.

11. The heat dissipation structure according to claim 10, wherein: The one or more TTSVs include multiple TTSVs; and The second group of one or more heat conduction paths is positioned to thermally contact the first group of one or more heat conduction paths via one or more permanent heat conduction branches extending between the plurality of TTSVs.

12. The heat dissipation structure according to claim 10, further comprising: One or more antifuse wires, the one or more antifuse wires being configured to connect the one or more metallized wires as the heat-conducting branches; and One or more fuses configured to disconnect the one or more metallized lines so that they do not carry the active signal of the active circuit.

13. The heat dissipation structure according to claim 10, further comprising: A group of one or more nanoelectromechanical systems (NEMS) switches having a first switching state and a second switching state, wherein in the first switching state, the first group of one or more NEMS switches is configured to connect the one or more metallized lines as the thermally conductive branches, and in the second switching state, the first group of one or more NEMS switches is configured to disconnect the one or more metallized lines so that they do not act as the thermally conductive branches.

14. The heat dissipation structure according to claim 10, wherein: The first operating mode of the active circuit is the diagnostic operating mode of the active circuit; and The second operating mode of the active circuit is the normal operating mode of the active circuit.

15. The heat dissipation structure according to claim 10, wherein: The first operating mode of the active circuit is the normal operating mode of the active circuit; and The second operating mode of the active circuit is associated with one or more portions of the active circuit that are in a static state.

16. The heat dissipation structure according to claim 15, wherein: The one or more metallized lines carry active signals associated with the one or more portions of the active circuit when the active circuit is in the first operating mode, and do not carry active signals associated with the one or more portions of the active circuit when the active circuit is in the second operating mode.

17. The heat dissipation structure according to claim 10, wherein: The one or more substrates include multiple stacked substrates; The one or more TTSVs extend through the plurality of stacked substrates to form the first set of one or more thermal conductive paths; and The first group of one or more thermal paths includes at least one thermal path located between each of the plurality of stacked substrates and the heat sink structure.

18. The heat dissipation structure according to claim 10, wherein the heat sink structure comprises: Heat exchanger; Heat sink; or Their combination.

19. A method of operating a heat dissipation structure to dissipate heat generated by active circuitry of one or more substrates, the method comprising: One or more thermally penetrating substrate vias (TTSVs) are provided through at least one of the one or more substrates to form a first set of one or more thermally conductive paths between the at least one of the one or more substrates and the heat sink structure. In the first operating mode of the active circuit, one or more metallization lines of the at least one substrate are configured to carry active signals of the active circuit. as well as In a second operating mode of the active circuit in which one or more metallized lines do not carry active signals of the active circuit, the one or more metallized lines are connected to the one or more TTSVs as thermally conductive branches to act as thermally conductive lines, and the one or more metallized lines are disconnected so that they do not operate as signal-carrying lines.

20. The method of claim 19, further comprising: Actuate one or more antifuse wires to connect the one or more metallized wires as the heat-conducting branches; as well as Actuate one or more fuses to disconnect the one or more metallized lines so that they do not carry the active signal of the active circuit.

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