Package including a base portion and an integrated device

Abstract

A package includes a base portion including a plurality of base interconnects, a first integrated device coupled to the base portion, a second integrated device coupled to the base portion, a fill material coupled to the base portion, the first integrated device, and the second integrated device, and a metallization portion coupled to the first integrated device and the second integrated device.

Description

Cross-references to related applications

[0001] This application claims priority and benefit to U.S. Non-Provisional Application Serial No. 18 / 590,637, filed with the U.S. Patent and Trademark Office on February 28, 2024, the entire contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0002] Various features relate to devices with integrated components. Background Technology

[0003] A package may include a substrate and integrated devices. These components are coupled together to provide a package capable of performing various electrical functions. There has always been a need to provide packages with better performance. There has also been a need to reduce the overall size of packages. Summary of the Invention

[0004] Various features relate to devices with integrated components.

[0005] One example provides a package comprising: a base portion including a plurality of base interconnects; a first integrated device coupled to the base portion; a second integrated device coupled to the base portion; a filler material coupled to the base portion, the first integrated device, and the second integrated device; and a metallized portion coupled to the first integrated device and the second integrated device.

[0006] Another example provides a method for manufacturing a package. The method provides a base portion including a plurality of base interconnects. The method couples a first integrated device to the base portion. The method couples a second integrated device to the base portion. The method couples a filler material to the base portion, the first integrated device, and the second integrated device. The method couples a metallized portion to the first integrated device and the second integrated device. Attached Figure Description

[0007] The various features, essence, and advantages will become apparent when the detailed description set forth below is understood in conjunction with the accompanying drawings, in which similar reference characters are used for corresponding identification throughout.

[0008] Figure 1 An exemplary cross-sectional profile view of a package including a base portion and integrated devices is shown.

[0009] Figure 2 An exemplary cross-sectional profile view of a package including a base portion and integrated devices is shown.

[0010] Figure 3An exemplary cross-sectional profile view of a package including a base portion and integrated devices is shown.

[0011] Figure 4 An exemplary cross-sectional profile view of an integrated device is shown.

[0012] Figures 5A to 5C Exemplary steps for manufacturing a package that includes a base portion and integrated devices are illustrated.

[0013] Figure 6 An exemplary flowchart illustrating a method for manufacturing a package including a base portion and integrated devices is shown.

[0014] Figures 7A to 7C An exemplary process for manufacturing metallized parts is illustrated.

[0015] Figure 8 An exemplary redistribution section is illustrated.

[0016] Figure 9 An exemplary flowchart illustrating a method for manufacturing metallized portions is shown.

[0017] Figures 10A to 10B An exemplary process for manufacturing integrated devices is illustrated.

[0018] Figures 11A to 11B An exemplary process for manufacturing the base portion is illustrated.

[0019] Figure 12 Examples are given of various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages and / or device packages described herein. Detailed Implementation

[0020] In the following description, specific details are set forth to provide a thorough understanding of the various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid complicating these aspects with unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid complicating these aspects of this disclosure.

[0021] This disclosure describes a package comprising: a base portion including a plurality of base interconnects; a first integrated device coupled to the base portion; a second integrated device coupled to the base portion; a filler material coupled to the base portion, the first integrated device, and the second integrated device; and a metallization portion coupled to the first integrated device and the second integrated device. As will be further described below, the device has a compact form factor while still providing high-density interconnects and / or improved performance.

[0022] Exemplary package including base portion and integrated device Figure 1 A cross-sectional outline view of package 100 is illustrated, which includes a base portion 102, integrated devices 103 and 105, filler material 106, a metallization portion 104, a plurality of pillar interconnects 107, and a plurality of solder interconnects 109. Integrated device 103 is coupled to the base portion 102. Integrated device 105 is coupled to the base portion 102. The metallization portion 104 is coupled to integrated devices 103 and 105. The plurality of pillar interconnects 107 are coupled to the metallization portion 104. The plurality of solder interconnects 109 are coupled to the plurality of pillar interconnects 107. Package 100 may be an integrated device package. In some embodiments, package 100 may be coupled to a board (e.g., a printed circuit board) via the plurality of pillar interconnects 107 and the plurality of solder interconnects 109.

[0023] The base portion 102 includes a base substrate 120, a plurality of base interconnects 121, and at least one base dielectric layer 122. The base substrate 120 may include silicon (Si). The base substrate 120 may include glass. The base dielectric layer 122 is coupled to the base substrate 120. The base dielectric layer 122 may include a prepreg and / or polyimide. The plurality of base interconnects 121 are located on the base substrate 120. The base portion 102 may be configured as a base bridging portion. The plurality of base interconnects 121 may include a plurality of bridging interconnects (e.g., base bridging interconnects). Some of the base interconnects from the base interconnects 121 may be configured to operate as one or more inductors. The plurality of base interconnects 121 may include a plurality of damascene interconnects. The plurality of base interconnects 121 may have a minimum pitch of about 25 nanometers (nm). The plurality of base interconnects 121 may have a pitch smaller than that of the plurality of metallized interconnects of the metallized portion 104. In some embodiments, the base interconnects on the metal layers of the plurality of base interconnects 121 may have a thickness in the range of about 20 nanometers to 5 micrometers. In some embodiments, the base dielectric layer 122 may have a thickness in the range of about 20 nanometers to 5 micrometers. For example, the dielectric layer between two adjacent metal layers of the plurality of base interconnects 121 may have a thickness in the range of about 20 nanometers to 5 micrometers. In some embodiments, the plurality of base interconnects 121 include interconnects having a width and spacing of less than 1 micrometer.

[0024] The integrated device 103 includes a front side and a back side. The integrated device 103 includes a plurality of pads 130 and a plurality of through-substrate vias 132. The front side of the integrated device 103 may include a side including the plurality of pads 130. The back side of the integrated device 103 may include a side including the plurality of through-substrate vias 132.

[0025] The front side of integrated device 103 is coupled to base portion 102 such that the front side of integrated device 103 contacts base portion 102. Multiple pads 130 are coupled to and contact multiple base interconnects 121. In some embodiments, hybrid bonding may be used to couple the multiple pads 130 to the multiple base interconnects 121. In some embodiments, copper-to-copper bonding may be used to couple the multiple pads 130 to the multiple base interconnects 121. (The following at least...) Figure 4 More detailed examples of integrated devices are illustrated and described in the text.

[0026] The integrated device 105 includes a front side and a back side. The integrated device 105 includes a plurality of pads 150 and a plurality of through-substrate vias 152. The front side of the integrated device 105 may include a side comprising the plurality of pads 150. The back side of the integrated device 105 may include a side comprising the plurality of through-substrate vias 152.

[0027] The front side of the integrated device 105 is coupled to the base portion 102 such that the front side of the integrated device 105 contacts the base portion 102. A plurality of pads 150 are coupled to and contact a plurality of base interconnects 121. In some embodiments, hybrid bonding may be used to couple the plurality of pads 150 to the plurality of base interconnects 121. In some embodiments, copper-to-copper bonding may be used to couple the plurality of pads 150 to the plurality of base interconnects 121. (The following at least...) Figure 4 More detailed examples of integrated devices are illustrated and described in the text.

[0028] Metallization portion 104 is coupled to the back side of integrated device 103 and the back side of integrated device 105. Metallization portion 104 includes a plurality of metallized interconnects 142 and at least one dielectric layer 140. The plurality of metallized interconnects 142 may be coupled to (i) a plurality of through-substrate vias 132 of integrated device 103 and (ii) a plurality of through-substrate vias 152 of integrated device 105. Further details will be provided below. Figure 4 As described herein, the integrated device may include back-side metallized interconnects. In some specific embodiments, a plurality of metallized interconnects 142 may be coupled to (i) the back-side metallized interconnects of integrated device 103 and (ii) the back-side metallized interconnects of integrated device 105.

[0029] The metallized portion 104 may include a redistribution portion comprising a plurality of redistribution interconnects. In some embodiments, using Figures 7A to 7C The multiple metallized interconnects used in the metallized portion 104, manufactured using a specific process, can have a minimum width ranging from approximately 2 micrometers to 10 micrometers. In some specific implementations, using... Figures 7A to 7C The plurality of metallized interconnects 142 for metallized portion 104 manufactured by a process may have a minimum gap (e.g., minimum pitch) in the range of about 2 micrometers to 10 micrometers. In some specific embodiments, the plurality of base interconnects 142 may include metallized interconnects having a pitch greater than that of the interconnects from the plurality of base interconnects 121.

[0030] Filler material 106 may be located between base portion 102 and metallized portion 104. Filler material 106 may contact base portion 102 and metallized portion 104. Filler material 106 may at least partially encapsulate integrated device 103 and integrated device 105. Filler material 106 may at least laterally surround at least a portion of integrated device 103. Filler material 106 may at least laterally surround at least a portion of integrated device 105. Filler material 106 may contact side surfaces of integrated device 103 and / or side surfaces of integrated device 105. Filler material 106 may be laterally located between integrated device 103 and integrated device 105. Filler material 106 may include inorganic materials. Filler material 106 may include silicon oxide. In some embodiments, as used in this disclosure, silicon oxide may refer to SiOx, where x may be one or greater. For example, silicon oxide may also mean including silicon dioxide. Using filler material 106, which includes inorganic materials having superior thermal properties to organic materials, can help improve the performance of integrated devices and / or packages by providing improved heat dissipation for integrated devices and / or packages.

[0031] In some embodiments, filler material 106 may include an encapsulating layer (such as a mold, resin, and / or epoxy resin). Filler material 106 may be a component for encapsulation. Filler material 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. Organic materials may include polyimide, underfill filler, and / or molding compound.

[0032] The electrical path between integrated device 103 and integrated device 105 may include pads from a plurality of pads 130, at least one base interconnect from a plurality of base interconnects 121 and / or pads from a plurality of pads 150.

[0033] The electrical path between integrated device 103 and integrated device 105 may include through-substrate vias from a plurality of through-substrate vias 132, at least one metallized interconnect from a plurality of metallized interconnects 142 and / or through-substrate vias from a plurality of through-substrate vias 152.

[0034] Electrical paths (e.g., for power, ground, or signal) between integrated device 103 and multiple solder interconnects 109 may include through-substrate vias from multiple through-substrate vias 132, at least one metallized interconnect from multiple metallized interconnects 142, pillar interconnects from multiple pillar interconnects 107, and / or solder interconnects from multiple solder interconnects 109. Electrical paths (e.g., for power, ground, or signal) between integrated device 105 and multiple solder interconnects 109 may include through-substrate vias from multiple through-substrate vias 152, at least one metallized interconnect from multiple metallized interconnects 142, pillar interconnects from multiple pillar interconnects 107, and / or solder interconnects from multiple solder interconnects 109. Power to integrated device 103 may be provided via the back side of integrated device 103 (e.g., through multiple through-substrate vias 132). Power to the integrated device 105 can be provided through the back side of the integrated device 105 (e.g., through a plurality of through-substrate vias 152).

[0035] Package 100 offers several technical advantages. First, package 100 provides improved thermal performance, which helps improve the overall performance of package 100. Second, the base portion 102 helps provide precise-pitch integrated device-to-integrated device electrical connections, which helps improve the performance of package 100. Third, providing power to integrated devices via the back side of the integrated devices helps provide improved power delivery, which improves the performance of package 100. Fourth, the structure and / or configuration of the package can be manufactured using more integrated manufacturing processes, which helps reduce the cost of the package and / or improve the manufacturing yield of the package. Fifth, using inorganic materials for the filler material 106 helps provide improved thermal performance (e.g., improved heat dissipation), which helps improve the performance of the package.

[0036] Figure 2 A cross-sectional outline view of package 200 is illustrated, which includes a base portion 202, integrated device 103, integrated device 105, filler material 106, metallization portion 104, multiple pillar interconnects 107, and multiple solder interconnects 109. Integrated device 103 is coupled to the base portion 202. Integrated device 105 is coupled to the base portion 202. Metallization portion 104 is coupled to integrated device 103 and integrated device 105. Multiple pillar interconnects 107 are coupled to metallization portion 104. Multiple solder interconnects 109 are coupled to multiple pillar interconnects 107. Package 200 may be an integrated device package. In some embodiments, package 200 may be coupled to a board (e.g., a printed circuit board) via multiple pillar interconnects 107 and multiple solder interconnects 109.

[0037] Figure 2 The package 200 is similar to Figure 1The package 100 may include components arranged in a similar and / or similar manner as described with respect to the package 100. The package 200 includes a base portion 202. The base portion 202 includes a base substrate 120, a plurality of base interconnects 121, a base dielectric layer 122, passive devices 223 and / or passive devices 225. Passive device 223 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 223 may be located on the base substrate 120 and / or within the base dielectric layer 122. Passive device 223 may be configured to be electrically coupled to integrated device 103. For example, passive device 223 may be electrically coupled to integrated device 103 via base interconnects from the plurality of base interconnects 121. Passive device 225 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 225 may be located on base substrate 120 and / or within base dielectric layer 122. Passive device 225 may be configured to be electrically coupled to integrated device 105. For example, passive device 225 may be electrically coupled to integrated device 105 via base interconnects from a plurality of base interconnects 121.

[0038] The base substrate 120 may include silicon (Si). A base dielectric layer 122 is coupled to the base substrate 120. The base dielectric layer 122 may include a prepreg. A plurality of base interconnects 121 are located on the base substrate 120. A base portion 102 may be configured as a base bridging portion. The plurality of base interconnects 121 may include a plurality of bridging interconnects (e.g., base bridging interconnects). Some of the base interconnects from the plurality of base interconnects 121 may be configured to operate as one or more inductors.

[0039] Figure 3 A cross-sectional outline view of package 300 is illustrated, which includes a base portion 302, integrated device 103, integrated device 105, filler material 106, metallization portion 104, multiple pillar interconnects 107, and multiple solder interconnects 109. Integrated device 103 is coupled to the base portion 302. Integrated device 105 is coupled to the base portion 302. Metallization portion 104 is coupled to integrated device 103 and integrated device 105. Multiple pillar interconnects 107 are coupled to metallization portion 104. Multiple solder interconnects 109 are coupled to multiple pillar interconnects 107. Package 300 may be an integrated device package. In some embodiments, package 300 may be coupled to a board (e.g., a printed circuit board) via multiple pillar interconnects 107 and multiple solder interconnects 109.

[0040] Figure 3 The package 300 is similar to Figure 1 Package 100 and / or Figure 2The package 200 may include components arranged in a similar and / or similar manner as described for package 100 and / or package 200. Package 300 includes a base portion 302. Base portion 302 includes a base substrate 120, a plurality of base interconnects 121, a base dielectric layer 122, passive devices 223, passive devices 225, and / or active regions 320.

[0041] Passive device 223 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 223 may be located on the base substrate 120 and / or within the base dielectric layer 122. Passive device 223 may be configured to be electrically coupled to integrated device 103. For example, passive device 223 may be electrically coupled to integrated device 103 via base interconnects from a plurality of base interconnects 121. Passive device 225 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 225 may be located on the base substrate 120 and / or within the base dielectric layer 122. Passive device 225 may be configured to be electrically coupled to integrated device 105. For example, passive device 225 may be electrically coupled to integrated device 105 via base interconnects from a plurality of base interconnects 121.

[0042] The base substrate 120 may include silicon (Si). A base dielectric layer 122 is coupled to the base substrate 120. The base dielectric layer 122 may include a prepreg. A plurality of base interconnects 121 are located on the base substrate 120. A base portion 102 may be configured as a base bridging portion. The plurality of base interconnects 121 may include a plurality of bridging interconnects (e.g., base bridging interconnects). Some of the base interconnects from the plurality of base interconnects 121 may be configured to operate as one or more inductors.

[0043] Active region 320 may include multiple logic cells, multiple transistors, and / or multiple filters. Active region 320 may be implemented within and / or on base substrate 120. Active region 320 may be configured to be electrically coupled to passive device 223 and / or passive device 225. Active region 320 may be configured to be electrically coupled to integrated device 103 and / or integrated device 105. For example, active region 320 may be configured to be electrically coupled to integrated device 103 and / or integrated device 105 via base interconnects from multiple base interconnects 121. Active region 320 may be configured to be electrically coupled to integrated device 103 and / or integrated device 105 via multiple base interconnects 121. Active region 320 may be similar to active region 422 of integrated device 400.

[0044] The electrical path between the active region 320 and the integrated device 103 may include at least one base interconnect from the plurality of base interconnects 121 and pads from the plurality of pads 130. The electrical path between the active region 320 and the integrated device 105 may include at least one base interconnect from the plurality of base interconnects 121 and pads from the plurality of pads 150.

[0045] As mentioned above, the package (e.g., 100, 200, 300) offers several technical advantages. First, the package provides improved thermal performance, which helps improve the overall performance of the package. Second, the base portion 102 helps provide precise-pitch integrated device-to-integrated device electrical connections, which helps improve package performance. Third, providing power to the integrated device via the back side of the integrated device helps provide improved power delivery, which improves package performance. Fourth, the structure and / or configuration of the package can be manufactured using more integrated manufacturing processes, which helps reduce package cost and / or improve package manufacturing yield. Fifth, using inorganic materials for the filler material 106 helps provide improved thermal performance (e.g., improved heat dissipation), which helps improve package performance.

[0046] Exemplary integrated device Figure 4 A cross-sectional outline view of an integrated device 400 including a die substrate is illustrated. Integrated device 400 may represent integrated device 103 and / or integrated device 105. Integrated device 400 includes a die substrate portion 402 and a die interconnect portion 404. Die substrate portion 402 includes a die substrate 420, an active region 422, and a plurality of through-substrate vias 421. Active region 422 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. Different embodiments may use different types of transistors, such as field-effect transistors (FETs), planar FETs, finned FETs, and gate-all-around FETs. In some embodiments, front-end process (FEOL) technology may be used to fabricate the active region 422 of die substrate 420.

[0047] The die substrate 420 may include silicon (Si). The die substrate 420 may include bulk silicon. Bulk silicon may include monolithic silicon. A plurality of through-substrate vias 421 may extend through the die substrate 420. Different embodiments may have different thicknesses for the die substrate 420. In some embodiments, the integrated device 400 may include a back-side metallization portion coupled to the die substrate 420. The back-side metallization portion may include a plurality of back-side metallization interconnects coupled to a plurality of through-substrate vias 421.

[0048] The die interconnect portion 404 includes at least one dielectric layer 440 and a plurality of die interconnects 442. The die interconnect portion 404 is coupled to the die substrate portion 402. The plurality of die interconnects 442 are coupled to an active region 422 of the die substrate portion 402. The die interconnect portion 404 may also include a plurality of pad interconnects 401 and a passivation layer 406. In some embodiments, a back-end processing (BEOL) process may be used to fabricate the die interconnect portion 404. A plurality of metallized interconnects 423 may be coupled to a plurality of through-substrate vias 421. The plurality of metallized interconnects 423 may be part of a back-side metallization portion formed and coupled to the back side of the die substrate 420.

[0049] In some embodiments, the electrical path to and / or from the active region 422 may include at least one die interconnect from a plurality of die interconnects 442 and at least one through-substrate via from a plurality of through-substrate vias 421. In some embodiments, the electrical path to and / or from the active region 422 may include at least one die interconnect from a plurality of die interconnects 442 and at least one pad interconnect from a plurality of pad interconnects 401. The integrated device 400 includes a front side and a back side. The front side of the integrated device 400 may be the side including a plurality of pad interconnects 401. The back side of the integrated device 400 may be the side including a die substrate 420, through-substrate vias 421 and / or a plurality of metallized interconnects 423.

[0050] Integrated devices (e.g., 103, 105) may include dies (e.g., bare semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs) based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si) based integrated devices, silicon carbide (SiC) based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include input / output (I / O) hubs. Integrated devices may include transistors. Integrated devices may be examples of electronic components and / or electronic devices.

[0051] In some embodiments, the integrated device may be a chiplet. Chipslets can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chiplets. Different chiplets may have different sizes and / or shapes. Different chiplets may be configured to provide different functions. Different chiplets may have different interconnect densities (e.g., interconnects with different widths and / or pitches). In some embodiments, several chiplets may be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chiplets performing several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some embodiments, one or more chiplets and / or one or more integrated devices (e.g., 103) of the chiplets described in this disclosure may be manufactured using the same technology node or two or more different technology nodes. For example, an integrated device may be manufactured using a first technology node, and a chiplet may be manufactured using a second technology node that is less advanced than the first technology node. In such examples, the integrated device may include components (e.g., interconnects, transistors) having a first minimum size, and the chiplet may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is larger than the first minimum size. In some embodiments, the first and second integrated devices of the package may be manufactured using the same or different technology nodes. In some embodiments, the chiplets and another chiplet of the package may be manufactured using the same or different technology nodes.

[0052] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or chiplets. A technology node can specify the minimum possible size (e.g., minimum size) that can be manufactured (e.g., transistor size, trace width, gap width between two transistors). Different technology nodes may have different yield losses. Different technology nodes may have different costs. Technology nodes for components with finer manufacturing details are more expensive and may have higher yield losses compared to technology nodes for components with less fine manufacturing details (e.g., traces, transistors). Therefore, more advanced technology nodes may be more expensive and may have higher yield losses compared to less advanced technology nodes. When all functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require manufacturing using that specific technology node. Therefore, the integrated device is locked to a single technology node. To optimize the cost of the package, some functions can be implemented in different integrated devices and / or chiplets, where different technology nodes can be used to manufacture different integrated devices and / or chiplets to reduce the overall cost. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more chiplets. An example would be an integrated device manufactured using a first technology node (e.g., a more advanced technology node) and configured to provide computing applications, and at least one chiplet manufactured using a second technology node and configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the second technology node manufactures a component with a minimum size larger than the minimum size of a component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packing as many transistors as possible into the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced available technology nodes, while other chiplets can be manufactured using less advanced technology nodes, as these chiplets may not require as many transistors to be manufactured in the chiplet. Therefore, using a combination of different technology nodes (which may have different associated yield losses) for different integrated devices and / or chiplets can reduce the overall cost of the package compared to using a single integrated device to perform all the functions of the package.

[0053] Another advantage of dividing functionality into several integrated devices and / or chiplets is that it allows for improvements in package performance without having to redesign each individual integrated device and / or chiplet. For example, if a package configuration uses a first integrated device and a first chiplet, it may be possible to improve package performance by changing the design of the first integrated device while keeping the design of the first chiplet unchanged. Therefore, the first chiplet can be reused along with improved and / or differently configured first integrated devices. This saves costs when manufacturing packages with improved integrated devices because the first chiplet does not need to be redesigned.

[0054] The package (e.g., 100, 200, 300) may be implemented in a radio frequency (RF) package. This RF package may be a radio frequency front-end (RFFE) package. The package (e.g., 100, 200, 300) may be configured to provide wireless fidelity (WiFi) communication and / or cellular communication (e.g., 2G, 3G, 4G, 5G). The package (e.g., 100, 200, 300) may be configured to support Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), and / or Long Term Evolution (LTE). The package (e.g., 100, 200, 300) may be configured to transmit and receive signals with different frequencies and / or communication protocols.

[0055] Exemplary process for manufacturing a package including a base portion and integrated devices. In some specific implementations, manufacturing the package involves several processes. Figures 5A to 5C Exemplary processes for providing or manufacturing packages are illustrated. In some specific implementations, [the following can be used]. Figures 5A to 5C The process of providing or manufacturing package 300 is used. However, it is possible to use... Figures 5A to 5C The process of providing or manufacturing any of the packages (e.g., 100, 200) described in this disclosure.

[0056] It should be noted that Figures 5A to 5C The processes may be combined in one or more stages to simplify and / or clarify the processes for providing or manufacturing the package. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0057] Figure 5APhase 1 illustrates the state after the base portion 302 is provided. The base portion 302 includes a base substrate 120, a plurality of base interconnects 121, a base dielectric layer 122, passive devices 223 and 225, and / or active regions 320. Passive device 223 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 223 may be located on the base substrate 120 and / or within the base dielectric layer 122. Passive device 223 may be configured to be electrically coupled to integrated device 103. Passive device 225 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 225 may be located on the base substrate 120 and / or within the base dielectric layer 122. Passive device 225 may be configured to be electrically coupled to integrated device 105. The base substrate 120 may include silicon (Si). A base dielectric layer 122 is coupled to a base substrate 120. The base dielectric layer 122 may include a prepreg. A plurality of base interconnects 121 are located on the base substrate 120. A base portion 102 may be configured as a base bridging portion. The plurality of base interconnects 121 may include a plurality of bridging interconnects (e.g., base bridging interconnects). Some of the base interconnects from the base interconnects 121 may be configured to operate as one or more inductors. An active region 320 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. The active region 320 may be implemented in and / or on the base substrate 120. In some embodiments, the base portion 302 may be fabricated and / or provided using FEOL and / or BEOL processes.

[0058] Phase 2 illustrates the state after integrated devices 103 and 105 are coupled to the base portion 302. Integrated device 103 can be coupled to the base portion 302 using a hybrid bonding process. Multiple pads 130 of integrated device 103 can be coupled to and contact multiple base interconnects 121 of the base portion 302. Integrated device 105 can be coupled to the base portion 302 using a hybrid bonding process. Multiple pads 150 of integrated device 103 can be coupled to and contact the multiple base interconnects 121 of the base portion 302.

[0059] Phase 3 illustrates the state after the filler material 106 has been provided and formed. The filler material 106 may be coupled to and contact the base portion 302, integrated device 103, and integrated device 105. The filler material 106 may include inorganic materials. The filler material 106 may include silicon oxide (e.g., a silicon oxide layer). In some embodiments, the filler material 106 may include an encapsulation layer (such as a mold, resin, and / or epoxy resin). The filler material 106 may be a component for encapsulation. The filler material 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0060] like Figure 5BAs shown, stage 4 illustrates the state after removing portions of the filler material 106. The filler material 106 may be ground and / or polished. In some embodiments, portions of integrated device 103 and / or integrated device 105 may also be removed. For example, portions of the back side of integrated device 103 and / or the back side of integrated device 105 may be removed. Removing portions of the back side of integrated device 103 may include removing portions of the die substrate and / or multiple through-substrate vias 132. Removing portions of the back side of integrated device 105 may include removing portions of the die substrate and / or multiple through-substrate vias 152. Removing portions of integrated devices may expose portions of the through-substrate vias of integrated devices. For example, grinding and / or polishing processes may expose multiple through-substrate vias 132 of integrated device 103 and / or multiple through-substrate vias 152 of integrated device 105.

[0061] Phase 5 illustrates the state after forming the metallization portion 104 and coupling the metallization portion to the integrated device 103, integrated device 105, and filler material 106. The metallization portion 104 may include at least one dielectric layer 140 and a plurality of metallized interconnects 142. The metallization portion 104 may include a redistribution portion comprising a plurality of redistribution interconnects. Figures 7A to 7C Examples of processes for manufacturing metallized portions and / or redistributed portions are illustrated. Multiple metallized interconnects 142 may be coupled to multiple through-substrate vias 132 of integrated device 103 and / or multiple through-substrate vias 152 of integrated device 105.

[0062] like Figure 5C As shown, stage 6 illustrates the state after forming a plurality of pillar interconnects 107 and coupling the plurality of pillar interconnects to the metallized portion 104. The plurality of pillar interconnects 107 are coupled to a plurality of metallized interconnects 142. A plating process can be used to form the plurality of pillar interconnects 107. The process for forming the plurality of pillar interconnects 107 can be similar to the process for forming the plurality of metallized interconnects 142.

[0063] Stage 7 illustrates the state after multiple solder interconnects 109 are coupled to multiple pillar interconnects 107. Multiple solder interconnects 109 can be formed using a solder reflow process, and these multiple solder interconnects can be coupled to the multiple pillar interconnects 107. Stage 7 can illustrate... Figure 3 The packaging component is 300.

[0064] An exemplary flowchart of a method for manufacturing a package including a base portion and integrated devices. In some specific implementations, manufacturing the package involves several processes. Figure 6 An exemplary flowchart illustrating a method 600 for providing or manufacturing a package is shown. In some specific implementations, it is possible to use... Figure 6Method 600 is used to provide or manufacture the package 300 described in this disclosure. However, method 600 can be used to provide or manufacture any of the packages described in this disclosure (e.g., 100, 200, 300).

[0065] It should be noted that Figure 6 Method 600 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture packages. In some implementations, the order of processes may be changed or modified.

[0066] The method (at 605) provides a base portion including a base substrate, a plurality of base interconnects, and a base dielectric layer. The base portion may include at least one passive device and an active region. Figure 5A Phase 1 illustrates and describes an example of the state after the base portion 302 is provided. The base portion 302 includes a base substrate 120, a plurality of base interconnects 121, a base dielectric layer 122, passive devices 223 and 225, and / or active regions 320. Passive device 223 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 223 may be located on the base substrate 120 and / or within the base dielectric layer 122. Passive device 223 may be configured to be electrically coupled to integrated device 103. Passive device 225 may include a capacitor. The capacitor may include a metal-insulator-metal (MIM) capacitor. Passive device 225 may be located on the base substrate 120 and / or within the base dielectric layer 122. Passive device 225 may be configured to be electrically coupled to integrated device 105. The base substrate 120 may include silicon (Si). A base dielectric layer 122 is coupled to a base substrate 120. The base dielectric layer 122 may include a prepreg. A plurality of base interconnects 121 are located on the base substrate 120. A base portion 102 may be configured as a base bridging portion. The plurality of base interconnects 121 may include a plurality of bridging interconnects (e.g., base bridging interconnects). Some of the base interconnects from the base interconnects 121 may be configured to operate as one or more inductors. An active region 320 may include a plurality of logic cells, a plurality of transistors, and / or a plurality of filters. The active region 320 may be implemented in and / or on the base substrate 120.

[0067] This method (at 610) couples multiple integrated devices to the base portion. A first integrated device and a second integrated device can be coupled to the base portion. Figure 5APhase 2 illustrates and describes an example of the state after integrated devices 103 and 105 are coupled to the base portion 302. Integrated device 103 can be coupled to the base portion 302 using a hybrid bonding process. Multiple pads 130 of integrated device 103 can be coupled to and contact multiple base interconnects 121 of the base portion 302. Integrated device 105 can be coupled to the base portion 302 using a hybrid bonding process. Multiple pads 150 of integrated device 103 can be coupled to and contact multiple base interconnects 121 of the base portion 302.

[0068] The method (at 615) provides a filler material that is coupled to integrated device 103, integrated device 105 and base portion 102. Figure 5A Phase 3 illustrates and describes an example of the state after the filler material 106 has been provided and formed. The filler material 106 may be coupled to and contact the base portion 302, integrated device 103, and integrated device 105. The filler material 106 may include inorganic materials. The filler material 106 may include silicon oxide (e.g., silicon dioxide). The filler material 106 may include an encapsulation layer (such as a mold, resin, and / or epoxy resin). The filler material 106 may be a component for encapsulation. The filler material 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0069] This method (at 620) removes portions of the filler material. Removing portions of the filler material may include performing a planarization process. Removing portions of the filler material can remove portions of the integrated device. Figure 5B Stage 4 illustrates and describes an example of the state after removing portions of the filler material 106. The filler material 106 may be ground and / or polished. In some embodiments, portions of integrated device 103 and / or integrated device 105 may also be removed. For example, portions of the back side of integrated device 103 and / or portions of the back side of integrated device 105 may be removed. Removing portions of the back side of integrated device 103 may include removing portions of the die substrate and / or multiple through-substrate vias 132. Removing portions of the back side of integrated device 105 may include removing portions of the die substrate and / or multiple through-substrate vias 152. Removing portions of integrated devices may expose portions of the through-substrate vias of integrated devices. For example, grinding and / or polishing processes may expose multiple through-substrate vias 132 of integrated device 103 and / or multiple through-substrate vias 152 of integrated device 105.

[0070] The method forms a metallized portion (at 625) and couples the metallized portion to the filler material and the integrated device. Figure 5BPhase 5 illustrates and describes an example of the state after the metallization portion 104 is formed and coupled to the integrated device 103, integrated device 105, and filler material 106. The metallization portion 104 may include at least one dielectric layer 140 and a plurality of metallized interconnects 142. The metallization portion 104 may include a redistribution portion comprising a plurality of redistribution interconnects. Figures 7A to 7C Examples of processes for manufacturing metallized portions and / or redistributed portions are illustrated. Multiple metallized interconnects 142 may be coupled to multiple through-substrate vias 132 of integrated device 103 and / or multiple through-substrate vias 152 of integrated device 105.

[0071] The method (at 630) forms a plurality of pillar interconnects and couples the plurality of pillar interconnects to the metallized portion. Figure 5C Stage 6 illustrates and describes an example of the state after forming a plurality of pillar interconnects 107 and coupling the plurality of pillar interconnects to the metallized portion 104. The plurality of pillar interconnects 107 are coupled to a plurality of metallized interconnects 142. A plating process can be used to form the plurality of pillar interconnects 107. The process for forming the plurality of pillar interconnects 107 can be similar to the process for forming the plurality of metallized interconnects 142.

[0072] This method (at 635) couples multiple solder interconnects to multiple pillar interconnects. Figure 5C Stage 7 illustrates and describes an example of the state after multiple solder interconnects 109 are coupled to multiple pillar interconnects 107. A solder reflow process can be used to form the multiple solder interconnects 109 and couple them to the multiple pillar interconnects 107. Stage 7 can be illustrated... Figure 3 The packaging component is 300.

[0073] Exemplary process for manufacturing metallized parts In some specific implementations, manufacturing the metallized parts involves several processes. Figures 7A to 7C Exemplary processes for providing or manufacturing metallized portions are illustrated. In some specific implementations, the following methods may be used: Figures 7A to 7C The process is used to provide or manufacture the metallized part 104.

[0074] It should be noted that Figures 7A to 7C The processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the metallized portion. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0075] like Figure 7AAs shown, stage 1 illustrates the state after the substrate 700 and the silicon oxide layer 710 are provided. The substrate 700 may include a silicon substrate. The silicon oxide layer 710 may include silicon dioxide (SiO2).

[0076] Stage 2 illustrates the state after the seed layer 720 is formed and coupled to the silicon oxide layer 710. The seed layer 720 may include copper. The seed layer 720 may be disposed on the silicon oxide layer 710.

[0077] Stage 3 illustrates the state after the photoresist layer 730 is formed and coupled to the seed layer 720. The photoresist layer 730 can be formed using deposition and / or lamination processes.

[0078] like Figure 7B As shown, stage 4 illustrates the state after multiple openings 732 are formed in the photoresist layer 730. The multiple openings 732 expose portions of the seed layer 720. The multiple openings 732 can be formed using an exposure process and / or a development process.

[0079] Stage 5 illustrates the state after the formation of multiple interconnects 740. Multiple interconnects 740 can be formed in multiple openings 732 of the photoresist layer 730. Multiple interconnects 740 can be coupled to the seed layer 720. A plating process can be used to form the multiple interconnects 740.

[0080] Stage 6 illustrates the state after removing photoresist layer 730. Photoresist layer 730 can be removed using a photoresist stripping process.

[0081] Stage 7 illustrates the state after removing portions of the seed layer 720. Etching processes can be used to remove portions of the seed layer 720. In some implementations, portions of the seed layer 720 not covered by the multiple interconnects 740 can be removed.

[0082] like Figure 7C As shown, stage 8 illustrates the state after a dielectric layer 750 has been formed over the silicon oxide layer 710 and / or over the plurality of interconnects 740. The dielectric layer 750 can be formed over the silicon oxide layer 710 and / or the plurality of interconnects 740 using deposition and / or lamination processes.

[0083] Stage 9 illustrates the state after a plurality of openings 752 have been formed in the dielectric layer 750. The plurality of openings 752 expose portions of the plurality of interconnects 740. The plurality of openings 752 can be formed using an exposure process and / or a development process.

[0084] Stage 10 illustrates the state after the formation of multiple interconnects 760. The multiple interconnects 760 may be coupled to multiple interconnects 740. The multiple interconnects 760 may be located in multiple openings 752 of the dielectric layer 750. The multiple interconnects 760 may be located on the surface of the dielectric layer 750. The multiple interconnects 760 may be formed using photolithography, plating, lift-off, and / or etching processes.

[0085] In some embodiments, the steps shown in stages 8 to 10 may be performed iteratively to form additional dielectric layers for metallized portions comprising several metal layers and / or additional interconnects. The multiple interconnects 740 and / or multiple interconnects 760 may include multiple metallized interconnects. In some embodiments, instead of being formed on substrate 700 and / or silicon oxide layer 710, the multiple interconnects may be formed on filler material and / or one or more integrated devices.

[0086] In some specific implementations, the use Figures 7A to 7C Multiple metallized interconnects for metallized portions, manufactured using advanced processes, can have a minimum width ranging from approximately 2 micrometers to 10 micrometers. In some specific implementations, [the process involves using...]. Figures 7A to 7C Multiple metallized interconnects for metallized portions manufactured using the process can have a minimum gap (e.g., minimum spacing) in the range of about 2 micrometers to 10 micrometers.

[0087] Different specific implementations may have metallized interconnects with different shapes.

[0088] Figure 8 An example is a metallized portion 800, which includes at least one dielectric layer 810 and a plurality of metallized interconnects 812. The plurality of metallized interconnects 812 may include those having characteristics consistent with this disclosure. Figures 1 to 3 Metallized interconnects 812 of different shapes are shown. Metallized portions 800 may include redistributed portions. Multiple metallized interconnects 812 may include multiple redistributed interconnects. In some embodiments, metallized portions 800 may replace metallized portions 104. Multiple metallized interconnects 812 may replace multiple metallized interconnects 142. Metallized portions 800 may include metallized interconnects having a shape different from that of metallized portions 104. In some embodiments, metallized portions 800 may use... Figures 7A to 7C Manufactured using the same and / or similar processes.

[0089] Exemplary flowchart of a method for manufacturing metallized portions In some specific implementations, manufacturing the metallized parts involves several processes. Figure 9 An exemplary flowchart illustrating a method 900 for providing or manufacturing a metallized portion is shown. In some specific implementations, it is possible to use... Figure 9 Method 900 is used to provide or manufacture the metallized portion 104 described in this disclosure. However, method 900 can be used to provide or manufacture any metallized portion (e.g., 800) described in this disclosure.

[0090] It should be noted that Figure 9 Method 900 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture the metallized portion. In some specific implementations, the order of the processes may be changed or modified.

[0091] This method (at 905) provides a substrate and a silicon oxide layer. Figure 7A Stage 1 illustrates and describes an example of the state after the substrate 700 and the silicon oxide layer 710 are provided. The substrate 700 may include a silicon substrate. The silicon oxide layer 710 may include silicon dioxide (SiO2).

[0092] This method (at 910) forms a seed layer. Figure 7A Stage 2 illustrates and describes an example of the state after the seed layer 720 is formed and coupled to the silicon oxide layer 710. The seed layer 720 may include copper. The seed layer 720 may be disposed on the silicon oxide layer 710.

[0093] This method (at 915) forms a photoresist layer with an opening. Figure 7A Stage 3 illustrates and describes an example of the state after the photoresist layer 730 is formed and coupled to the seed layer 720. The photoresist layer 730 can be formed using deposition and / or lamination processes. Figure 7B Stage 4 illustrates and describes an example of the state after multiple openings 732 have been formed in the photoresist layer 730. The multiple openings 732 expose portions of the seed layer 720. The multiple openings 732 can be formed using an exposure process and / or a development process.

[0094] This method (at 920) forms multiple interconnects. Figure 7B Stage 5 illustrates and describes an example of the state after the formation of multiple interconnects 740. Multiple interconnects 740 may be formed in multiple openings 732 of the photoresist layer 730. Multiple interconnects 740 may be coupled to a seed layer 720. A plating process may be used to form the multiple interconnects 740.

[0095] This method (at 925) removes the photoresist layer and a portion of the seed layer. Figure 7B Stage 6 illustrates and describes an example of the state after the removal of photoresist layer 730. Photoresist layer 730 can be removed using a photoresist stripping process. Figure 7BStage 7 illustrates and describes an example of the state after removing portions of the seed layer 720. Etching processes can be used to remove portions of the seed layer 720. In some implementations, portions of the seed layer 720 not covered by the multiple interconnects 740 can be removed.

[0096] This method (at 930) forms a dielectric layer with an opening. Figure 7C Stage 8 illustrates and describes an example of the state after a dielectric layer 750 has been formed over the silicon oxide layer 710 and / or over the plurality of interconnects 740. The dielectric layer 750 can be formed over the silicon oxide layer 710 and / or the plurality of interconnects 740 using deposition and / or lamination processes.

[0097] Figure 7C Stage 9 illustrates and describes an example of the state after multiple openings 752 have been formed in the dielectric layer 750. The multiple openings 752 expose portions of multiple interconnects 740. The multiple openings 752 can be formed using an exposure process and / or a development process.

[0098] This method (at 935) forms multiple interconnects. Figure 7C Stage 10 illustrates and describes an example of the state after the formation of multiple interconnects 760. Multiple interconnects 760 may be coupled to multiple interconnects 740. Multiple interconnects 760 may be located in multiple openings 752 of dielectric layer 750. Multiple interconnects 760 may be located on the surface of dielectric layer 750. Multiple interconnects 760 may be formed using photolithography, plating, stripping, and / or etching processes.

[0099] In some embodiments, the formation of a dielectric layer with an opening (at 930) and the formation of multiple interconnects (at 935) can be performed iteratively to form additional dielectric layers and / or additional interconnects for metallized portions including several metal layers. Multiple interconnects 740 and / or multiple interconnects 760 may include multiple metallized interconnects. In some embodiments, instead of being formed on substrate 700 and / or silicon oxide layer 710, multiple interconnects may be formed on filler material and / or one or more integrated devices.

[0100] Exemplary process for manufacturing integrated devices In some specific implementations, manufacturing integrated devices involves several processes. Figures 10A to 10B Exemplary steps for providing or manufacturing integrated devices are illustrated. In some specific implementations, the following can be used: Figures 10A to 10B The process is used to provide or manufacture integrated device 103 and / or integrated device 105.

[0101] It should be noted that Figures 10A to 10BThe processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture integrated devices. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0102] like Figure 10A As shown, stage 1 illustrates the state after the die substrate 420 has been provided. The die substrate 420 may include a silicon substrate.

[0103] Phase 2 illustrates the state after the active region 422 is formed in and on the die substrate 420. The active region 422 may include multiple logic cells, multiple transistors, and / or multiple filters. Different implementations may use different types of transistors, such as field-effect transistors (FETs), planar FETs, fin FETs, and gate-all-around FETs. In some implementations, a front-end process (FEOL) may be used to fabricate the active region 422 of the die substrate 420.

[0104] Phase 3 illustrates the state after forming a plurality of through-substrate vias 421 in the die substrate 420. The plurality of through-substrate vias 421 extend through the die substrate 420. Laser etching and / or plating processes can be used to form the plurality of through-substrate vias 421. A plurality of back-side interconnects can be formed and coupled to the plurality of through-substrate vias 421. For example, Phase 3 may also illustrate the state after forming a plurality of metallized interconnects 423 and coupling the plurality of metallized interconnects to the plurality of through-substrate vias 421. Plating processes can be used to form the plurality of metallized interconnects 423. Phase 3 may illustrate a die substrate portion 402, which includes the die substrate 420, an active region 422, a plurality of through-substrate vias 421, and a plurality of metallized interconnects 423.

[0105] Phase 4 illustrates the state after forming the die interconnect portion 404 and coupling it to the die substrate portion 402. The die interconnect portion 404 includes at least one dielectric layer 440 and a plurality of die interconnects 442. The die interconnect portion 404 is coupled to the die substrate portion 402. The plurality of die interconnects 442 are coupled to the active region 422 of the die substrate portion 402. In some embodiments, a back-to-end (BEOL) process can be used to fabricate the die interconnect portion 404. Figures 11A to 11B The process shown is used to manufacture die interconnect portion 404, including forming at least one dielectric layer 440 and a plurality of die interconnects 442.

[0106] like Figure 10BAs shown, stage 5 illustrates the state after forming a plurality of pad interconnects 401 and coupling the plurality of pad interconnects to a plurality of die interconnects 442. In some embodiments, a plating process may be used to form the plurality of pad interconnects 401.

[0107] Stage 6 illustrates the state after a passivation layer 406 has been formed over portions of the plurality of pad interconnects 401. The passivation layer 406 can be formed using deposition and / or lamination processes. In some embodiments, the die interconnect portion 404 may also include a plurality of pad interconnects 401 and a passivation layer 406. Stage 6 may illustrate an integrated device 400.

[0108] Exemplary process for manufacturing the base portion In some specific implementations, the manufacturing of the base portion includes several processes. Figures 11A to 11B Exemplary processes for providing or manufacturing the base portion are illustrated. In some specific implementations, the following can be used: Figures 11A to 11B The process involves providing or manufacturing at least a portion of the base portion 102. At least a portion of the base portion 102 can be manufactured using a mosaic process that provides high-density interconnects (e.g., mosaic interconnects). In some embodiments, the process may use... Figures 11A to 11B The process is used to manufacture the metallized parts (e.g., 104).

[0109] It should be noted that Figures 11A to 11B The processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture at least a portion of the base portion. In some embodiments, the order of the processes may be changed or modified. In some embodiments, one or more of these processes may be substituted or replaced without departing from the scope of this disclosure.

[0110] like Figure 11A As shown, Stage 1 illustrates the state after dielectric layer 1100, pad layer 1102, interconnect 1104, coating 1106, dielectric layer 1108, coating 1110, photoresist layer 1120, and opening 1112 have been provided and formed. Dielectric layer 1100 and / or dielectric layer 1108 may comprise SiCOH (e.g., Si, C, O, and H). Coating 1106 may comprise silicon carbide (SiCN). Coating 1106 helps protect interconnect 1104 from oxidation. Coating 1110 may comprise silicon oxide (e.g., silicon dioxide). Pad layer 1102 may comprise a barrier layer (e.g., TaN / Ta). Pad layer 1102 helps prevent metal from interconnect 1104 from diffusing into dielectric layer 1100. Stage 1 illustrates the opening 1112 formed through coating 1110, dielectric layer 1108, and / or coating 1106.

[0111] Phase 2 illustrates the state after (i) removing photoresist layer 1120 and (ii) forming antireflective coating 1130 and forming another photoresist layer 1140. Antireflective coating 1130 is formed in the opening 1112 and on the coating 1110. Photoresist layer 1140 is formed on portions of antireflective coating 1130.

[0112] Stage 3 illustrates the state after the removal of portions of the anti-reflective coating 1130. Stage 3 also illustrates the state after the formation of the opening 1118 in the dielectric layer 1108.

[0113] like Figure 11B As shown, stage 4 illustrates the state after the formation of the pad layer 1150 and the seed layer 1160. The pad layer 1150 may include a barrier layer (e.g., TaN / Ta). The seed layer 1160 is formed on top of the pad layer 1150. The seed layer 1160 may include copper. The pad layer 1150 may be formed using a deposition process. The seed layer 1160 may be formed using a deposition process.

[0114] Phase 5 illustrates the state after interconnect 1170 has been formed. Interconnect 1170 may include copper. Interconnect 1170 may be coupled to seed layer 1160. Interconnect 1170 may be formed using a plating process.

[0115] Phase 6 illustrates the state after interconnect 1170 is planarized and coating 1180 is formed over interconnect 1170 and dielectric layer 1108. Coating 1180 may include silicon carbide (SiCN). The processes of phases 1 through 6 may be repeated iteratively to form additional dielectric layers and / or additional interconnects.

[0116] It should be noted that the pad layer 1150 can be considered as part of the interconnect 1170. Therefore, in some embodiments, the pad layer that contacts the interconnect can be considered as part of the interconnect. Similarly, the seed layer that contacts the interconnect can be considered as part of the interconnect.

[0117] It should be noted that any conductive material can be considered part of the interconnect. Therefore, conductive material contacting the interconnect can be considered part of the interconnect. For example, seed layer 1160 can be considered part of interconnect 1170. Multiple interconnects formed using the process described above can have a minimum pitch of approximately 25 nanometers (nm). In some embodiments, the interconnects can have a thickness ranging from approximately 20 nanometers to 5 micrometers. In some embodiments, the dielectric can have a thickness ranging from approximately 20 nanometers to 5 micrometers. For example, the dielectric layer between two adjacent metal layers of multiple interconnects can have a thickness ranging from approximately 20 nanometers to 5 micrometers. Therefore, the base portion manufactured using the damascene process described above can have interconnects with a minimum pitch of approximately 25 nanometers (nm).

[0118] In some specific implementations, it can be used Figures 11A to 11B The metallized portion 104 is manufactured using a process that includes a plurality of metallized interconnects 142. In such cases, the metallized portion manufactured using the damascene process described above may have metallized interconnects with a minimum pitch of approximately 25 nanometers (nm).

[0119] Exemplary electronic devices Figure 12 Examples are illustrated of various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, stacked packages (PoP), system-in-packages (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1202, laptop computer device 1204, fixed-location terminal device 1206, wearable device 1208, or motor vehicle 1210 may include device 1200 as described herein. For example, device 1200 may be any of the devices and / or integrated circuit (IC) packages described herein. Figure 12 The illustrated devices 1202, 1204, 1206, and 1208, as well as vehicle 1210, are merely exemplary. Other electronic devices may also feature device 1200, including but not limited to devices (e.g., electronic devices) comprising the following group: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (such as watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (such as autonomous vehicles), or any other device or any combination thereof that stores or retrieves data or computer instructions.

[0120] Figures 1 to 4 , Figures 5A to 5C , Figure 6 , Figures 7A to 7C , Figures 8 to 9 , Figures 10A to 10B , Figures 11A to 11B and Figure 12 One or more of the illustrated components, processes, features, and / or functions may be rearranged and / or combined into a single component, process, feature, or function, or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figures 1 to 4 , Figures 5A to 5C , Figure 6 , Figures 7A to 7C , Figures 8 to 9 , Figures 10A to 10B , Figures 11A to 11B and Figure 12 The corresponding descriptions herein are not limited to dies and / or ICs. In some specific implementations, Figures 1 to 4 , Figures 5A to 5C , Figure 6 , Figures 7A to 7C , Figures 8 to 9 , Figures 10A to 10B , Figures 11A to 11B and Figure 12 The descriptions and their corresponding information can be used to manufacture, create, supply, and / or produce devices and / or integrated devices. In some specific implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices, and / or interposers.

[0121] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some specific embodiments, the various components and / or parts in the drawings may be optional.

[0122] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any specific implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupling” is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, objects A and C can still be considered coupled to each other, even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term “electrical coupling” may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can flow between the two objects. Electrically coupled objects may or may not have current traveling between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above the fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The terms “enclosing,” “enclosing,” and / or any derivative meaning can refer to an object that partially or completely encloses another object. The terms “top” and “bottom” are arbitrary. A component located at the top can be above a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component can be located above (e.g., above) a first surface of a second component, and a third component can be located above (e.g., below) a second surface of a second component, where the second surface is opposite to the first surface. It should also be noted that the term “above” as used in this application in the context of one component being above another component can be used to mean that a component is on and / or in another component (e.g., on the surface of a component or embedded in a component). Therefore, for example, "the first component is on top of the second component" can mean: (1) the first component is on top of the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located "in" the second component can be partially or completely located in the second component. Values ​​from about X to XX can refer to values ​​between X and XX, including both X and XX. Values ​​between X and XX can be discrete or continuous. As used in this disclosure, the terms "about 'value X'" or "approximately value X" mean within 10% of "value X".For example, a value of approximately 1 or roughly 1 would mean a value in the range of 0.9 to 1.1.

[0123] In some embodiments, an interconnect is an element or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some embodiments, an interconnect may include traces (e.g., trace interconnects), vias (e.g., via interconnects), pads (e.g., pad interconnects), pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some embodiments, an interconnect may include a conductive material configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different embodiments may use different processes and / or steps to form interconnects. In some embodiments, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0124] It should also be noted that the various disclosures contained herein can be described as processes depicted as work diagrams, flowcharts, structure diagrams, or block diagrams. Although flowcharts may describe operations as sequential processes, many operations within an operation can be performed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0125] Further examples are described below to facilitate understanding of the invention.

[0126] Aspect 1: A package comprising: a base portion including a plurality of base interconnects; a first integrated device coupled to the base portion; a second integrated device coupled to the base portion; a filler material coupled to the base portion, the first integrated device, and the second integrated device; and a metallized portion coupled to the first integrated device and the second integrated device.

[0127] Aspect 2: The package according to aspect 1, wherein the first integrated device includes a first front side coupled to and contacting the base portion, and wherein the second integrated device includes a second front side coupled to and contacting the base portion.

[0128] Aspect 3: The package according to aspects 1 to 2, wherein the filler material is coupled to and contacts the first integrated device, the second integrated device and the base portion.

[0129] Aspect 4: The package according to aspects 1 to 3, wherein the base portion includes at least one passive device.

[0130] Aspect 5: The package according to aspect 4, wherein the at least one passive device comprises a capacitor and / or an inductor.

[0131] Aspect 6: The package according to aspects 1 to 5 further includes a plurality of pillar interconnects coupled to the metallized portion.

[0132] Aspect 7: The package according to aspects 1 to 6, wherein the metallized portion comprises: at least one dielectric layer; and a plurality of metallized interconnects.

[0133] Aspect 8: The package according to aspect 7, wherein the plurality of metallized interconnects includes a plurality of embedded interconnects.

[0134] Aspect 9: The package according to aspects 7 to 8, wherein the plurality of metallized interconnects includes interconnects having a width and pitch of less than 1 micrometer.

[0135] Aspect 10: The package according to aspects 7 to 9, wherein the plurality of metallized interconnects includes a plurality of redistributed interconnects.

[0136] Aspect 11: The package according to aspects 1 to 10, wherein the plurality of base interconnects includes a plurality of embedded interconnects.

[0137] Aspect 12: The package according to aspects 1 to 11, wherein the metallized portion is coupled to a first back side of the first integrated device and a second back side of the second integrated device.

[0138] Aspect 13: The package according to aspects 1 to 12, wherein the first integrated device and the second integrated device are configured to be electrically coupled through the plurality of base interconnects of the base portion.

[0139] Aspect 14: The package according to aspects 1 to 13, wherein the base portion further includes a plurality of logic units and / or transistors.

[0140] Aspect 15: A method for manufacturing a package. The method provides a base portion including a plurality of base interconnects. The method couples a first integrated device to the base portion. The method couples a second integrated device to the base portion. The method couples a filler material to the base portion, the first integrated device, and the second integrated device. The method couples a metallized portion to the first integrated device and the second integrated device.

[0141] Aspect 16: According to the method of aspect 15, wherein the first integrated device includes a first front side coupled to and contacting the base portion, and wherein the second integrated device includes a second front side coupled to and contacting the base portion.

[0142] Aspect 17: The method according to aspects 15 to 16, wherein the filler material is coupled to and contacts the first integrated device, the second integrated device and the base portion.

[0143] Aspect 18: The method according to aspects 15 to 17, wherein the base portion includes at least one passive device.

[0144] Aspect 19: The method according to aspects 15 to 18, wherein the plurality of base interconnects comprises a plurality of embedded interconnects.

[0145] Aspect 20: The method according to aspects 15 to 19, wherein the metallized portion is coupled to a first back side of the first integrated device and a second back side of the second integrated device.

[0146] Aspect 21: The package according to aspects 1 to 10, wherein the package is implemented in a device selected from the group consisting of: music player, video player, entertainment unit, navigation device, communication device, mobile device, mobile phone, smartphone, personal digital assistant, fixed-location terminal, tablet computer, computer, wearable device, laptop computer, server, Internet of Things (IoT) device, and device in motor vehicle.

[0147] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings herein are readily applicable to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, the package comprising: The base portion includes a plurality of base interconnects; A first integrated device, the first integrated device being coupled to the base portion; A second integrated device, the second integrated device being coupled to the base portion; A filler material coupled to the base portion, the first integrated device, and the second integrated device; and The metallized portion is coupled to the first integrated device and the second integrated device.

2. The packaging component according to claim 1, The first integrated device includes a first front side, which is coupled to and contacts the base portion, and The second integrated device includes a second front side that is coupled to and contacts the base portion.

3. The package of claim 1, wherein the filler material is coupled to and contacts the first integrated device, the second integrated device, and the base portion.

4. The package of claim 1, wherein the base portion comprises at least one passive device.

5. The package of claim 4, wherein the at least one passive device comprises a capacitor and / or an inductor.

6. The package according to claim 1, further comprising a plurality of pillar interconnects coupled to the metallized portion.

7. The package of claim 1, wherein the metallized portion comprises: At least one dielectric layer; and Multiple metallized interconnects.

8. The package of claim 7, wherein the plurality of metallized interconnects comprises a plurality of embedded interconnects.

9. The package of claim 7, wherein the plurality of metallized interconnects comprises interconnects having a width and spacing of less than 1 micrometer.

10. The package of claim 7, wherein the plurality of metallized interconnects comprises a plurality of redistributed interconnects.

11. The package of claim 1, wherein the plurality of base interconnects comprises a plurality of embedded interconnects.

12. The package of claim 1, wherein the metallized portion is coupled to a first back side of the first integrated device and a second back side of the second integrated device.

13. The package of claim 1, wherein the first integrated device and the second integrated device are configured to be electrically coupled through the plurality of base interconnects of the base portion.

14. The package of claim 1, wherein the base portion further comprises a plurality of logic units and / or transistors.

15. A method for manufacturing a package, the method comprising: A base portion is provided, the base portion including a plurality of base interconnects; Couple the first integrated device to the base portion; Couple the second integrated device to the base portion; The filler material is coupled to the base portion, the first integrated device, and the second integrated device; as well as The metallized portion is coupled to the first integrated device and the second integrated device.

16. The method according to claim 15, The first integrated device includes a first front side, which is coupled to and contacts the base portion, and The second integrated device includes a second front side that is coupled to and contacts the base portion.

17. The method of claim 15, wherein the filler material is coupled to and contacts the first integrated device, the second integrated device, and the base portion.

18. The method of claim 15, wherein the base portion comprises at least one passive device.

19. The method of claim 15, wherein the plurality of base interconnects comprises a plurality of embedded interconnects.

20. The method of claim 15, wherein the metallized portion is coupled to a first back side of the first integrated device and a second back side of the second integrated device.

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