Wafer level packaging structure of piezoelectric drive electric field sensor and preparation method thereof

Abstract

The application provides a wafer-level packaging structure of a piezoelectric drive electric field sensor and a preparation method thereof, and belongs to the technical field of semiconductor packaging. Three functions of air-tight sealing, electrical isolation and electrode lead-out are integrated in a composite functional layer by constructing a composite stacking area on an SOI wafer. A vertical direction layering design is adopted to physically isolate the bonding ring layer and the electrode lead wire, and the lead wire window position and the bonding ring do not overlap in the vertical direction, thereby fundamentally avoiding contact short circuit between the bonding ring metal and the electrode lead wire metal. By setting a top electrode lead wire window and a bottom electrode lead wire window in the composite stacking area and etching to different depths, respectively, the top electrode and the bottom electrode are separately led out from the same functional layer, and the process complexity of the traditional scheme in which the bottom electrode must be separately led out from the side of the PZT layer is avoided. Through the structural improvement, the measurement accuracy of the sensor is ensured, and a preparation method corresponding to the structure is provided.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a wafer-level packaging structure for a piezoelectric driven electric field sensor and its fabrication method. Background Technology

[0002] Electric field detection has wide applications in many fields such as meteorology, power, aerospace, and petrochemicals. MEMS electric field sensors have become an important means of electric field detection due to their advantages such as small size, low power consumption, mass production capability, and compatibility with IC processes. However, MEMS electric field sensors have the following drawbacks in packaging: Selection of encapsulation cover material: Although metal covers have good sealing performance and mechanical strength, they will have a shielding effect on the external electric field being measured, which will seriously interfere with the measurement accuracy of the sensor; while non-metallic insulating covers do not shield the electric field, but the accumulation of charge on the surface of the insulating cover that is difficult to eliminate will affect the long-term stable operation of the sensor.

[0003] Electrode lead design: When using gold-silicon eutectic bonding to achieve a hermetic seal, the bonding ring needs to provide direct contact between the metal layer and the underlying SOI wafer silicon surface to form an Au-Si eutectic liquid phase at the eutectic temperature. However, both the top and bottom electrodes of the PZT piezoelectric film are located on the upper surface of the SOI wafer, posing a potential electrical cross-contamination risk between the lead metal of the electrical signal leads and the bonding ring metal region. Especially when the leads must pass laterally beneath the bonding ring, short circuits are highly likely to occur between the bonding ring metal layer and the electrode lead metal layer, or the bonding ring metal layer may overflow into the electrode region at high temperatures, leading to electrical failure.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0005] The main objective of this application is to propose a wafer-level packaging structure and its fabrication method for a piezoelectric driven electric field sensor, which can prevent the package cover from shielding the detected electric field and avoid short-circuit crossing between the lead metal and the bonding sealing ring metal during the packaging process, so as to achieve the integration of three functions: hermetic sealing, electrical isolation and electrode lead-out.

[0006] To achieve the above objectives, this application proposes a wafer-level packaging structure for a piezoelectric driven electric field sensor, including an SOI wafer, an insulating isolation layer, and a silicon cover plate. The SOI wafer and the insulating isolation layer, as well as the insulating isolation layer and the silicon cover plate, are connected by bonding rings to achieve a hermetic seal. The SOI wafer, the insulating isolation layer, and the silicon cover plate are correspondingly placed and packaged through through-holes. The SOI wafer includes a substrate layer, a buried oxide layer, and a device layer, wherein a composite stacking region and a comb structure are formed on the device layer. The comb structure includes movable comb teeth and fixed comb teeth; The composite stacked region covers at least a portion of the comb structure and includes an electrode layer, a dielectric insulating layer, and a bonding metal layer. The entire surface of the electrode layer is deposited with a dielectric insulating layer, and the entire surface of the dielectric insulating layer is deposited with a bonding metal layer. At least one top electrode lead window is provided on the composite stack region for leading out the top electrode electrical signal, and at least one bottom electrode lead window is provided for leading out the bottom electrode electrical signal; the top electrode lead window and the bottom electrode lead window are separated from each other in a horizontal position, and neither overlaps with the bonding ring in the vertical direction.

[0007] Preferably, the electrode layer includes a PZT bottom electrode layer, a PZT piezoelectric thin film layer, and a PZT top electrode layer, penetrating from top to bottom through the dielectric insulating layer and the bonding metal layer, exposing the lower PZT top electrode layer to form a top electrode lead window; and penetrating from top to bottom through the dielectric insulating layer, the bonding metal layer, the PZT top electrode layer, and the PZT piezoelectric thin film layer, exposing the lower PZT bottom electrode layer to form a bottom electrode lead window.

[0008] Preferably, a dielectric insulating layer is deposited on the entire surface of the PZT top electrode layer. The dielectric insulating layer is composed of one or more materials selected from SiO, SiN, and AlO, and has a thickness of 300nm to 600nm. It is used to achieve electrical isolation between the bonding metal layer, the lower surface bonding region, and the underlying PZT top electrode layer.

[0009] Preferably, the bonding metal layer is patterned into at least one closed annular bonding ring, and the insulating isolation layer includes a lower surface bonding region and an upper surface bonding region. The SOI wafer and the insulating isolation layer are hermetically connected by bonding the bonding metal layer to the lower surface bonding region; the insulating isolation layer and the silicon cover plate are hermetically connected by bonding the upper surface bonding region to the silicon cover plate.

[0010] Preferably, the bonding metal layer and the lower surface bonding area are sealed by gold-gold hot-press bonding; the upper surface bonding area and the silicon cover plate are sealed by gold-silicon eutectic bonding.

[0011] Preferably, the central region of the insulating layer has a central hollow area that penetrates the insulating layer, and the central hollow area is used to provide movement space for the vertical vibration of the movable comb teeth.

[0012] Preferably, a gap is reserved in the horizontal direction between the sidewall of the central hollow area and the outermost edge of the movable comb teeth.

[0013] Preferably, a second through electrode hole is provided through the insulating isolation layer, corresponding to the position of the top electrode lead window and the bottom electrode lead window in the vertical direction, and a first through electrode hole is provided through the silicon cover plate, corresponding to the position of the second through electrode hole in the vertical direction, so that the electrode lead of the PZT top electrode is led out to the upper surface of the silicon cover plate through the top electrode lead window, the second through electrode hole and the first through electrode hole.

[0014] To achieve the above objectives, this application also proposes a method for fabricating a wafer-level packaging structure for a piezoelectric driven electric field sensor, the method comprising: A comb-shaped structure is fabricated on an SOI wafer to form a stacked structure including a PZT bottom electrode layer, a PZT piezoelectric thin film layer and a PZT top electrode layer. A dielectric insulating layer is deposited over the entire surface of the PZT top electrode layer; A bonding metal layer is deposited over the entire surface of the dielectric insulating layer; A closed-loop bonding ring is formed by patterning the bonding metal layer; At least one top electrode lead window is fabricated in the bonding metal layer and the dielectric insulating layer; At least one bottom electrode lead window is fabricated in the bonding metal layer, dielectric insulating layer, PZT top electrode layer and PZT piezoelectric thin film layer; An insulating layer is prepared, and a central hollow area and a second through electrode hole are machined on the insulating layer. The second through electrode hole corresponds to the positions of the top electrode lead window and the bottom electrode lead window. Prepare a silicon cover plate, and process a second through electrode hole corresponding to the first through electrode hole on the silicon cover plate; The wafer surface is cleaned and activated, and the SOI wafer, insulating layer and silicon cover plate are aligned and stacked in sequence. A bonding interface is formed by sealing and bonding between the SOI wafer and the insulating isolation layer, and between the insulating isolation layer and the silicon cover plate, to obtain a packaged piezoelectric driven electric field sensor.

[0015] Preferably, the bonding interface is activated by oxygen plasma before bonding.

[0016] This application offers at least the following advantages: It provides a wafer-level packaging structure and fabrication method for a piezoelectric driven electric field sensor. This scheme integrates hermetic sealing, electrical isolation, and electrode lead-out into a single composite functional layer by constructing a composite stacked region on an SOI wafer. A vertical layered design physically isolates the bonding ring layer from the electrode leads, and the lead-out window position does not overlap with the bonding ring in the vertical direction, fundamentally avoiding short circuits between the bonding ring metal and the electrode lead-out metal. By setting a top electrode lead-out window and a bottom electrode lead-out window in the composite stacked region and etching them to different depths, the top and bottom electrodes are separately led out from the same functional layer, avoiding the process complexity of having the bottom electrode separately led out from the side of the PZT layer in traditional solutions. This application, through structural improvements, ensures the measurement accuracy of the sensor and provides a corresponding fabrication method. Attached Figure Description

[0017] Figure 1 This is a cross-sectional schematic diagram of a wafer-level packaging structure for a piezoelectric driven electric field sensor provided in an embodiment of this application; Figure 2 This is a schematic cross-sectional view of the composite stack and comb structure integrated on the SOI wafer device layer according to an embodiment of this application; Figure 3 This is a schematic cross-sectional view of the insulating layer in an embodiment of this application; Figure 4 This is a schematic cross-sectional view of the encapsulated silicon cover plate structure according to an embodiment of this application; Figure 5 This is a schematic diagram illustrating the fabrication steps of a wafer-level packaging structure for a piezoelectric driven electric field sensor provided in this application embodiment.

[0018] The following are explanations of the labels in the figure: Substrate layer 1, Buried oxide layer 2, Device layer 3, Movable comb teeth 4, Fixed comb teeth 5, PZT bottom electrode layer 6, PZT piezoelectric thin film layer 7, PZT top electrode layer 8, Dielectric insulating layer 9, Bonding metal layer 10, Insulating layer 11, Lower surface bonding area 12, Upper surface bonding area 13, Silicon capping plate 14, Top electrode lead window 15, Bottom electrode lead window 16, Central hollow area 17, First through electrode hole 18, Second through electrode hole 19, Electrode lead 20. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements.

[0020] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0021] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0022] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0023] Before providing a detailed description of the embodiments of this application, some of the nouns and terms used in the embodiments of this application will be explained first. The nouns and terms used in the embodiments of this application shall be interpreted as follows: Bonding ring: A bonding ring is an annular sealing structure used in MEMS / semiconductor wafer-level packaging to achieve hermetically tight bonding between wafers. In the embodiments of this application, the bonding ring is an annular structure disposed between the SOI wafer, the insulating isolation layer, and the silicon cover plate. Adjacent wafers / layers are permanently connected through specific bonding processes such as metal hot-press bonding and anodic bonding to form a continuous and sealed annular interface, thereby achieving hermetically tight isolation between the inside and outside of the packaging cavity and providing a stable vacuum / inert gas environment for MEMS sensitive components such as internal comb structures.

[0024] Existing MEMS electric field sensors suffer from several packaging defects. Firstly, the choice of cover material is problematic. While metal covers offer excellent sealing and mechanical strength, they can shield the external electric field being measured, severely interfering with the sensor's accuracy. Non-metallic insulating covers, while not shielding the electric field, can lead to persistent charge buildup on their surface, affecting long-term sensor stability. Secondly, the electrode lead design is problematic. When using gold-silicon eutectic bonding for hermetic sealing, the bonding ring needs to provide direct contact between the metal layer and the underlying SOI wafer's silicon surface to form an Au-Si eutectic liquid phase at the eutectic temperature. However, the top and bottom electrodes of the PZT piezoelectric film are located on the upper surface of the SOI wafer, creating a potential electrical cross-contamination risk between the lead metal and the bonding ring metal region. Especially when the lead must pass laterally beneath the bonding ring, short circuits can easily occur between the bonding ring metal layer and the electrode lead metal layer, or the bonding ring metal layer may overflow into the electrode region at high temperatures, leading to electrical failure.

[0025] In view of this, this application provides a wafer-level packaging structure and fabrication method for a piezoelectric driven electric field sensor. This scheme integrates hermetic sealing, electrical isolation, and electrode lead-out into a single composite functional layer by constructing a composite stacked region on an SOI wafer. A vertical layered design physically isolates the bonding ring layer from the electrode leads, and the lead-out window position does not overlap with the bonding ring in the vertical direction, fundamentally avoiding contact short circuits between the bonding ring metal and the electrode lead-out metal. By setting a top electrode lead-out window and a bottom electrode lead-out window in the composite stacked region and etching them to different depths, the top and bottom electrodes are separately led out from the same functional layer, avoiding the process complexity of having the bottom electrode separately led out from the side of the PZT layer in traditional solutions. This application, through structural improvements, ensures the measurement accuracy of the sensor and provides a corresponding fabrication method.

[0026] Please see Figure 1-4 As shown, this application embodiment provides a wafer-level packaging structure for a piezoelectric driven electric field sensor, including an SOI wafer, an insulating isolation layer 11, and a silicon cover plate 14. The SOI wafer and the insulating isolation layer 11, as well as the insulating isolation layer 11 and the silicon cover plate 14, are connected by bonding rings to achieve a hermetic seal. The SOI wafer, the insulating isolation layer 11, and the silicon cover plate 14 are correspondingly placed and packaged through through holes. SOI wafers include a substrate layer 1, a buried oxide layer 2 and a device layer 3, with a composite stacking region and a comb structure formed on the device layer 3; The comb structure includes movable comb teeth 4 and fixed comb teeth 5; The composite stacked region covers at least a portion of the comb structure and includes an electrode layer, a dielectric insulating layer 9 and a bonding metal layer 10. The dielectric insulating layer 9 is deposited on the entire surface of the electrode layer, and the bonding metal layer 10 is deposited on the entire surface of the dielectric insulating layer 9. At least one top electrode lead window 15 is provided on the composite stack region for leading out the top electrode electrical signal, and at least one bottom electrode lead window 16 is provided for leading out the bottom electrode electrical signal; the top electrode lead window 15 and the bottom electrode lead window 16 are separated from each other in a horizontal position, and neither overlaps with the bonding ring in the vertical direction.

[0027] The overall structure of an SOI wafer consists of a substrate layer 1, a buried oxide layer 2, and a device layer 3 from bottom to top. The movable comb teeth 4 can be excited by a PZT piezoelectric thin film to generate vertical vibration, while the fixed comb teeth 5 are used to sense an external electric field.

[0028] It should be noted that the corresponding placement and installation through the through-holes means that the lead window set on the SOI wafer composite stacking area, the second through electrode hole 19 set on the insulating isolation layer 11, and the first through electrode hole 18 set on the silicon cover plate 14 are placed in corresponding positions, so that the SOI wafer, the insulating isolation layer 11, and the silicon cover plate 14 are stacked according to the corresponding positions of the through-holes.

[0029] It should be noted that the composite stacking region covering at least a portion of the comb structure means that the composite stacking region is stacked vertically above the comb structure and covers a portion of the comb structure. The electrode layer of the composite stacking region is the core electrical path for providing excitation signals to the PZT piezoelectric film of the movable comb 4 via piezoelectric drive, and for the output induced electrical signals of the fixed comb 5 via electric field induction. Covering the comb structure with the composite stacking region directly provides electrical connection to the comb structure without additional wiring, simplifying the device structure. The bonding metal layer 10 at the top of the composite stacking region is a key component for achieving hermetically tight bonding with the upper insulating isolation layer 11 and silicon cover plate 14. By covering the comb area with the composite stacking region, the metal interface required for bonding can be directly constructed above the comb structure, achieving integrated device structure, electrodes, and bonding interface. The movable comb tooth 4 needs to vibrate freely in a vacuum environment. If the composite stacking area completely covers the comb tooth structure area, it may restrict the vibration space, increase damping, or cause mechanical interference. In this embodiment, the comb tooth structure area is covered to reserve enough space for the vibration of the movable comb tooth 4, while ensuring the integrity of the bonding interface and taking into account both device function and packaging process requirements.

[0030] This embodiment of the application achieves hermetic bonding between the SOI wafer, the insulating isolation layer 11, and the silicon cover plate 14 by using a bonding ring, forming a continuous and leak-free annular sealed interface. This provides a stable vacuum / inert gas environment for sensitive elements such as the internal movable comb teeth 4 and fixed comb teeth 5, effectively isolating external moisture, impurities, and electromagnetic interference, and avoiding the deterioration of the vibration characteristics of the movable comb teeth 4 due to damping changes and contamination, thus significantly improving the long-term stability and measurement accuracy of the electric field sensor.

[0031] This embodiment of the application achieves independent signal extraction from the upper and lower electrodes by setting a top electrode lead window 15 and a bottom electrode lead window 16 in the composite stacking region, and limiting them to not overlapping in the vertical direction and being separated from each other in the horizontal position from the bonding ring. This avoids damage or contamination of the electrode lead area by the bonding process and ensures the integrity of the electrical signal extraction. The physical isolation of the upper and lower electrode lead windows can eliminate the risk of signal crosstalk. At the same time, separation from the bonding ring area avoids interference of the conductivity / insulation characteristics of the bonding material on the electrode signals, thereby improving the reliability of electrical signal transmission.

[0032] This application adopts a wafer-level through-hole bonding packaging scheme, which integrates the SOI wafer, insulating isolation layer 11 and silicon cover plate 14 through bonding ring. At the same time, the electrode layer, dielectric insulating layer, bonding metal layer and lead window of the composite stack region are integrated into the design, realizing the integrated integration of device sensitive structure, electrode lead-out and hermetic packaging. No additional wire bonding or discrete packaging process is required, which greatly simplifies the packaging process and reduces packaging cost. The bonding metal layer is also adapted to the bonding ring process requirements, realizing material and process reuse, avoiding the introduction of additional process steps, and improving compatibility with standard semiconductor / MEMS processes.

[0033] Please see Figure 1-2 As shown, in some embodiments, the electrode layer includes a PZT bottom electrode layer 6, a PZT piezoelectric thin film layer 7, and a PZT top electrode layer 8, penetrating from top to bottom through the dielectric insulating layer 9 and the bonding metal layer 10, exposing the lower PZT top electrode layer 8 to form a top electrode lead window 15; and penetrating from top to bottom through the dielectric insulating layer 9, the bonding metal layer 10, the PZT top electrode layer 8, and the PZT piezoelectric thin film layer 7, exposing the lower PZT bottom electrode layer 6 to form a bottom electrode lead window 16.

[0034] In some embodiments, a dielectric insulating layer 9 is deposited on the entire surface of the PZT top electrode layer 8. The dielectric insulating layer 9 is composed of one or more materials selected from SiO2, Si3N4 and Al2O3, and has a thickness of 300nm to 600nm. It is used to achieve electrical isolation between the bonding metal layer 10, the lower surface bonding region 12 and the underlying PZT top electrode layer 8.

[0035] A bonding metal layer 10 is deposited on the entire surface of the dielectric insulating layer 9. The bonding metal layer 10 is made of gold or gold-tin eutectic layer and has a thickness of 500 nm to 2000 nm. The bonding metal layer 10 is patterned into at least one closed annular bonding ring.

[0036] This application achieves the integration of hermetic sealing and electrode lead-out functions by longitudinally layering and bonding a metal layer 10, a dielectric insulating layer 9, and a top electrode layer 8 within a single composite stack region. Simultaneously, electrical signals are safely led out laterally by selectively opening the top electrode lead window 15 and the bottom electrode lead window 16. The entire structure completely avoids the risk of short circuit between the bonding ring metal and the electrode lead 20. Hermetic sealing and electrical interconnection do not interfere with each other, realizing the integration of hermetic sealing, electrical isolation, and electrode lead-out functions on the same layer.

[0037] Please see Figure 3 As shown, in some embodiments, the bonding metal layer 10 is patterned as at least one closed annular bonding ring, and the insulating isolation layer 11 includes a lower surface bonding region 12 and an upper surface bonding region 13. The SOI wafer and the insulating isolation layer 11 are hermetically connected by bonding the bonding metal layer 10 to the lower surface bonding region 12; the insulating isolation layer 11 and the silicon cover plate 14 are hermetically connected by bonding the upper surface bonding region 13 to the silicon cover plate 14.

[0038] The bonding metal layer 10 is processed into a specific ring pattern using semiconductor processes such as photolithography and etching. The processed bonding metal layer 10 forms a closed, unbroken ring structure, i.e., a bonding ring, which completely surrounds the internal comb-like device areas, isolating them from external moisture, gas, and impurities. The patterning process precisely avoids the top and bottom electrode lead windows, preventing short circuits caused by the bonding metal layer 10 covering them. Simultaneously, it ensures that the bonding ring and lead windows do not overlap vertically, solving the problem of interference from the bonding process to electrode extraction.

[0039] In some embodiments, the bonding metal layer 10 and the lower surface bonding region 12 are sealed by gold-to-gold hot-press bonding at a bonding temperature of 350-450°C; the upper surface bonding region 13 and the silicon cover plate 14 are sealed by gold-silicon eutectic bonding, forming an Au-Si eutectic liquid phase at a bonding temperature of 363°C to 400°C, and forming an airtight bonding interface after cooling.

[0040] In the embodiments of this application, gold-silicon eutectic bonding uses Ti, Pt, or TiW metal stacks as adhesion layers and diffusion barrier layers, wherein the thickness of the Ti or TiW layer is 20nm to 50nm, the thickness of the Pt layer is 20nm to 50nm, the thickness of the Au layer is 500nm to 2000nm, and the bonding temperature is 363℃ to 400℃.

[0041] An adhesion layer is a transition layer deposited between two materials at their interface. Its function is to significantly enhance the bonding force between the two materials and prevent the upper metal film from detaching from the substrate, peeling, or cracking. In gold-silicon eutectic bonding, the substrate is typically an insulating barrier layer 11 or a silicon capping plate 14, made of materials such as silicon oxide, while the bonding metal is gold. Gold has poor natural adhesion to silicon and silicon oxide, and direct deposition can easily lead to detachment. Metals such as titanium (Ti) or titanium-tungsten alloys (TiW) can form strong chemical bonds with silicon and silicon oxide substrates, as well as good intermetallic bonds with the upper gold layer. By using Ti or TiW as an adhesion layer, the substrate and metal are firmly bonded together, ensuring the mechanical stability of the bonding ring.

[0042] A diffusion barrier layer is a dense thin film sandwiched between two materials to prevent atomic interdiffusion between the two materials during high-temperature processes, thus avoiding material failure or performance degradation. At the gold-silicon eutectic bonding temperature of 363-400℃, two key risks arise: first, gold diffuses into the silicon substrate, meaning gold atoms diffuse rapidly into silicon, forming deep-level impurities, causing device leakage and performance degradation; second, the substrate material diffuses into the gold layer, meaning impurity atoms in the silicon substrate may also diffuse upwards, contaminating the gold layer and affecting the hermeticity and reliability of the eutectic bond. Platinum (Pt) has extremely high chemical stability and a very low atomic diffusion rate, making it a typical noble metal barrier layer that effectively prevents interdiffusion between Au and Si. TiW is a commonly used barrier layer material in titanium-tungsten alloy semiconductor processes; it has good density and can simultaneously block the diffusion of Au, Si, and substrate impurities, and has better compatibility with subsequent bonding processes. Therefore, this application uses Pt and TiW as diffusion barrier layers to effectively prevent atomic interdiffusion between the gold layer and the silicon substrate, ensuring bonding performance.

[0043] Please see Figure 3 As shown, in some embodiments, the central region of the insulating isolation layer 11 is provided with a central hollow region 17 that penetrates the insulating isolation layer 11. The central hollow region 17 is used to provide motion space for the vertical vibration of the movable comb teeth 4.

[0044] The insulating layer 11 is made of quartz, sapphire or BF33 glass insulating dielectric material, with a thickness of 200μm to 500μm. The thickness of the insulating layer 11 is the same as the depth of the central hollow area 17.

[0045] In some embodiments, a gap is reserved in the horizontal direction between the sidewall of the central hollow area 17 and the outermost edge of the movable comb teeth 4.

[0046] The central hollow area 17 refers to the cavity area reserved in the insulating layer 11 for the vertical vibration of the lower movable comb teeth 4; the outermost edge of the movable comb teeth 4 refers to the maximum outer contour edge of the piezoelectrically driven movable comb tooth structure in the horizontal direction. In this embodiment, the reserved gap is greater than or equal to 50 μm, that is, the horizontal distance between the sidewall of the central hollow area 17 and the outermost edge of the movable comb teeth 4 is greater than or equal to 50 μm.

[0047] The movable comb tooth 4, under the excitation of the PZT piezoelectric film, will vibrate vertically. Simultaneously, due to processing errors, assembly stress, or environmental interference, it may introduce slight horizontal offset or wobbling. This application provides a gap of ≥50μm between the sidewall of the central hollow area 17 and the outer edge of the movable comb tooth 4 in the horizontal direction. This provides sufficient safety margin for the vibration offset and thermal expansion deformation of the movable comb tooth 4, ensuring that it never contacts the sidewall under design conditions and within the error range. If the gap is too small, the movable comb tooth 4 may collide with the sidewall of the central hollow area 17 during vibration, leading to breakage of the movable comb tooth 4, abrupt changes in vibration damping, and directly damaging the working performance of the electric field sensor. Furthermore, there is a certain deviation in the alignment accuracy of the equipment during wafer-level bonding, and multi-layer wafer stacking also introduces cumulative errors. If the gap is smaller than the alignment error range of the bonding process, the sidewall of the central hollow area 17 may directly press against the movable comb tooth 4 during bonding, causing permanent damage to the device.

[0048] Please see Figure 3-4 As shown, in some embodiments, a second through electrode hole 19 corresponding to the vertical position of the top electrode lead window 15 and the bottom electrode lead window 16 is provided through the insulating isolation layer 11, and a first through electrode hole 18 corresponding to the vertical position of the second through electrode hole 19 is provided through the silicon cover plate 14, so that the electrode lead 20 of the PZT top electrode is led out to the upper surface of the silicon cover plate 14 through the top electrode lead window 15, the second through electrode hole 19 and the first through electrode hole 18.

[0049] To reduce parasitic capacitance and residual charge interference introduced by the packaging, the silicon cover plate 14 is preferably made of a low resistivity silicon material with a resistivity of less than 100 Ω·cm.

[0050] Please see Figure 5 As shown in the figure, this application provides a method for fabricating a wafer-level packaging structure for a piezoelectric driven electric field sensor, the method comprising: Step 1: A comb structure driven by a PZT piezoelectric thin film is fabricated on an SOI wafer to form a stacked structure including a PZT bottom electrode layer 6, a PZT piezoelectric thin film layer 7 and a PZT top electrode layer 8. A standard 4-inch SOI wafer is used, and a comb structure is fabricated on the SOI wafer using standard MEMS micromachining processes. Specifically, the patterns of fixed comb teeth 5 and movable comb teeth 4 are etched and defined on the device layer 3 of the SOI wafer. Then, a PZT piezoelectric thin film layer 7 is deposited and patterned using a sol-gel method or sputtering. Finally, a PZT bottom electrode layer 6 and a PZT top electrode layer 8 are fabricated using electron beam evaporation or sputtering. The PZT bottom electrode layer 6 can be made of Pt or Ti, with a thickness of approximately 100-200 nm; the PZT top electrode layer 8 can be made of Cr or Au, or Cr, Pt, Au, with a thickness of approximately 50-200 nm. After step one, a three-layer stacked structure of PZT bottom electrode layer 6, PZT piezoelectric thin film layer 7, and PZT top electrode layer 8 is formed on the surface of the SOI wafer.

[0051] Step 2: Deposit a dielectric insulating layer 9 over the entire surface of the PZT top electrode layer 8; A dielectric insulating layer 9 is deposited across the entire surface of the PZT top electrode layer 8 using PECVD or ALD processes. The material of the dielectric insulating layer 9 can be SiO2, Si3N4, or Al2O3, with a thickness of 300nm to 600nm. When using the PECVD SiO2 process, the deposition temperature is 250℃ to 300℃, and Si3N4 and N2O are used as reaction gases. When using the ALD Al2O3 process, the deposition temperature is room temperature to 200℃, and TMA and H2O are used as precursors, which can achieve excellent conformal step coverage.

[0052] Before depositing the dielectric insulating layer 9, it is preferable to deposit a 50 nm thick TiO2 buffer layer on the PZT surface using magnetron or reactive ion sputtering to protect the PZT from chemical corrosion in the PECVD plasma environment and ensure that the piezoelectric properties do not degrade.

[0053] Step 3: Deposit a bonding metal layer 10 over the entire surface of the dielectric insulating layer 9; A bonding metal layer 10 is deposited on the entire surface of the dielectric insulating layer 9 by electron beam evaporation or sputtering. The material of the bonding metal layer 10 is a gold layer or a gold-tin eutectic layer, and the thickness is 500 nm to 2000 nm.

[0054] Step 4: Pattern the bonding metal layer 10 using photolithography and etching processes to form a closed ring-shaped bonding ring; Through photolithography and etching processes, the bonding metal layer 10 is patterned into a closed annular bonding ring with a width of 50μm to 300μm, arranged along the periphery of the chip, completely surrounding the PZT comb structure area.

[0055] Step 5: At least one top electrode lead window 15 is fabricated in the bonding metal layer 10 and the dielectric insulating layer 9 by photolithography and RIE dry or wet etching processes to expose the underlying PZT top electrode layer 8. At least one top electrode lead window 15 is formed in the bonding metal layer 10 and the dielectric insulating layer 9 using photolithography and RIE etching processes, exposing the underlying PZT top electrode layer 8. The etching gas can be selected from CF4, O2, or a mixture of CHF3 and O2. The etching endpoint is controlled by endpoint detection (EPD) or time control.

[0056] Step 6: Using photolithography and RIE dry or wet etching processes, at least one bottom electrode lead window 16 is processed in the bonding metal layer 10, dielectric insulating layer 9, PZT top electrode layer 8 and PZT piezoelectric thin film layer 7 to expose the underlying PZT bottom electrode layer 6. At least one bottom electrode lead window 16 is formed in the bonding metal layer 10, the dielectric insulating layer 9, the PZT top electrode layer 8, and the PZT piezoelectric thin film layer 7 using photolithography and RIE etching processes, exposing the underlying PZT bottom electrode layer 6. The etching depth in this step is deeper than in step five and requires segmented etching. First, the bonding metal layer 10, the dielectric insulating layer 9, and the PZT top electrode layer 8 are etched, the process being the same as in step five. Then, the etching gas is switched to etch the PZT piezoelectric thin film layer 7, finally stopping at the surface of the PZT bottom electrode layer 6.

[0057] It should be noted that both the top electrode lead window 15 and the bottom electrode lead window 16 are located in the inner region surrounded by the bonding ring and do not overlap with the bonding ring in the vertical direction.

[0058] Step 7: Prepare an insulating layer 11, and process a central hollow area 17 and a second through electrode hole 19 on the insulating layer 11. The second through electrode hole 19 corresponds to the positions of the top electrode lead window 15 and the bottom electrode lead window 16. On a quartz, sapphire, or BF33 glass wafer, a central hollow region 17 and a second through electrode hole 19 are formed using deep reactive ion etching (DRIE) or laser drilling processes, creating an insulating layer 11. The central hollow region 17 is rectangular, with dimensions corresponding to the movable comb tooth 4 region, and a depth equal to the thickness of the insulating layer 11. The horizontal distance between the sidewall and the outermost edge of the movable comb tooth 4 is not less than 50 μm, ensuring that the movable comb tooth 4 has sufficient space to move during vertical vibration without colliding with the sidewall of the insulating layer 11. The position of the second through electrode hole 19 corresponds to the position of the lead window formed in steps five and six, that is, the position of the second through electrode hole 19 corresponds to the positions of the top electrode lead window 15 and the bottom electrode lead window 16.

[0059] Step 8: Prepare silicon cover plate 14, and process second through electrode hole 19 on silicon cover plate 14 corresponding to first through electrode hole 18; On the silicon cover plate 14 wafer, a first through electrode hole 18 is fabricated using the DRIE process. The hole diameter and position correspond to the second through electrode hole 19 on the insulating isolation layer 11.

[0060] Step nine: Clean and activate the wafer surface, and then stack the SOI wafer, insulating isolation layer 11 and silicon cover plate 14 in sequence according to the through holes; The SOI wafer, insulating isolation layer 11, and silicon cover plate 14 are sequentially aligned and stacked. Specifically, the top electrode lead window 15 and bottom electrode lead window 16 on the SOI wafer are aligned with the second through electrode hole 19 on the insulating isolation layer 11 and the first through electrode hole 18 on the silicon cover plate 14, respectively. The alignment accuracy is controlled by alignment marks on the wafer and is required to be within ±5μm. Before stacking, the wafer surface needs to be cleaned and activated with oxygen plasma.

[0061] Step 10: Seal bonding is performed between the SOI wafer and the insulating isolation layer 11, and between the insulating isolation layer 11 and the silicon cover plate 14 to form a bonding interface, thereby obtaining the packaged piezoelectric driven electric field sensor.

[0062] The stacked SOI wafers, insulating isolation layer 11, and silicon cover plate 14 are placed into a bonding device, and gold-silicon eutectic bonding is performed in a vacuum or inert gas protected environment. The bonding parameters are set as follows: bonding temperature 363℃~400℃, bonding pressure 1000N~2500N, and bonding time 10min~30min. During the bonding process, the bonding area 12 on the lower surface of the insulating isolation layer 11 forms Au-Au bonds with the bonding metal layer 10 on the surface of the SOI wafer at the eutectic temperature, forming a gold-gold bonding interface; simultaneously, the bonding area 13 on the upper surface of the insulating isolation layer 11 and the bonding area on the lower surface of the silicon cover plate 14 are bonded through Au-Si eutectic bonding, forming a gold-silicon eutectic bonding interface.

[0063] After bonding is completed, the bonding interface is annealed at a temperature 50°C to 100°C lower than the bonding temperature. For example, if the bonding temperature is 365°C, the annealing temperature is 280°C to 315°C, and the annealing time is 30 to 60 minutes. This is to release the thermal stress at the bonding interface, eliminate some of the interfacial polarization charge induced by thermal stress, and further reduce the residual charge level.

[0064] In some embodiments, before bonding, the bonding interface is subjected to oxygen plasma activation treatment, with the power of the oxygen plasma activation treatment being 80W to 150W and the time being 10s to 60s.

[0065] It should be noted that oxygen plasma activation treatment refers to a process in which oxygen is introduced into a low-vacuum environment and a radio frequency electric field is applied to ionize the oxygen and form high-energy oxygen plasma, which then bombards and treats the bonding interface. During processing and storage, photoresist residue, organic contaminants, moisture, and particles may remain on the wafer surface. The high-energy particles and reactive oxygen free radicals of oxygen plasma can efficiently etch and decompose organic contaminants, while simultaneously physically bombarding and removing particles, resulting in an ultra-clean bonding interface. This prevents contaminants from forming weak points at the bonding interface, which could lead to subsequent leakage or delamination.

[0066] Oxygen plasma can introduce numerous highly active sites such as hydroxyl groups and oxygen dangling bonds onto the surfaces of metals and insulating layers. For metal bonding interfaces, the activated surfaces are more prone to interatomic diffusion and metallic bonding, significantly improving the interfacial strength of hot-pressing / eutectic bonding. For insulating layer bonding interfaces, hydroxyl sites can promote hydrogen bonding between interfaces, and during subsequent high-temperature bonding, dehydration forms stable covalent bonds, further enhancing bonding strength and airtightness. Organic contaminants can make bonding interfaces hydrophobic, leading to insufficient interfacial contact and localized voids during bonding. Oxygen plasma treatment can significantly improve the hydrophilicity of the interface, making the bonded materials easier to spread uniformly during hot pressing / melting, reducing interfacial void defects, and ensuring the airtightness and consistency of ring-shaped bonds.

[0067] This application provides a wafer-level packaging structure and fabrication method for a piezoelectric driven electric field sensor. This scheme integrates hermetic sealing, electrical isolation, and electrode lead-out into a single composite functional layer by constructing a composite stacked region on an SOI wafer. A vertically layered design physically isolates the bonding ring layer from the electrode leads, and the lead-out window position does not overlap with the bonding ring in the vertical direction, fundamentally avoiding contact short circuits between the bonding ring metal and the electrode lead metal. By setting top and bottom electrode lead-out windows in the composite stacked region and etching them to different depths, the top and bottom electrodes are separately led out from the same functional layer, avoiding the process complexity of having the bottom electrode separately led out from the side of the PZT layer in traditional solutions. This application ensures the measurement accuracy of the sensor through structural improvements and provides a corresponding fabrication method.

[0068] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0069] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0070] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0071] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0072] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A wafer-level packaging structure for a piezoelectric driven electric field sensor, characterized in that, The package includes an SOI wafer, an insulating isolation layer, and a silicon cover plate. The SOI wafer and the insulating isolation layer, as well as the insulating isolation layer and the silicon cover plate, are connected by bonding rings to achieve a hermetic seal. The SOI wafer, the insulating isolation layer, and the silicon cover plate are placed and packaged through through-holes. The SOI wafer includes a substrate layer, a buried oxide layer, and a device layer, wherein a composite stacking region and a comb structure are formed on the device layer. The comb structure includes movable comb teeth and fixed comb teeth; The composite stacked region covers at least a portion of the comb structure and includes an electrode layer, a dielectric insulating layer, and a bonding metal layer. The entire surface of the electrode layer is deposited with a dielectric insulating layer, and the entire surface of the dielectric insulating layer is deposited with a bonding metal layer. At least one top electrode lead window is provided on the composite stack region for leading out the top electrode electrical signal, and at least one bottom electrode lead window is provided for leading out the bottom electrode electrical signal; the top electrode lead window and the bottom electrode lead window are separated from each other in a horizontal position, and neither overlaps with the bonding ring in the vertical direction.

2. The wafer-level packaging structure of a piezoelectric driven electric field sensor according to claim 1, characterized in that, The electrode layer includes a PZT bottom electrode layer, a PZT piezoelectric thin film layer, and a PZT top electrode layer. It penetrates the dielectric insulating layer and the bonding metal layer from top to bottom, exposing the PZT top electrode layer below to form a top electrode lead window; it also penetrates the dielectric insulating layer, the bonding metal layer, the PZT top electrode layer, and the PZT piezoelectric thin film layer from top to bottom, exposing the PZT bottom electrode layer below to form a bottom electrode lead window.

3. The wafer-level packaging structure of a piezoelectric driven electric field sensor according to claim 2, characterized in that, The entire surface of the PZT top electrode layer is deposited with a dielectric insulating layer. The dielectric insulating layer is composed of one or more materials selected from SiO, SiN, and AlO, and has a thickness of 300nm to 600nm. It is used to achieve electrical isolation between the bonding metal layer, the lower surface bonding region, and the underlying PZT top electrode layer.

4. The wafer-level packaging structure of a piezoelectric driven electric field sensor according to claim 1, characterized in that, The bonding metal layer is patterned into at least one closed annular bonding ring. The insulating isolation layer includes a lower surface bonding region and an upper surface bonding region. The SOI wafer and the insulating isolation layer are hermetically connected by bonding the bonding metal layer to the lower surface bonding region. The insulating isolation layer and the silicon cover plate are hermetically connected by bonding the upper surface bonding region to the silicon cover plate.

5. The wafer-level packaging structure of a piezoelectric driven electric field sensor according to claim 4, characterized in that, The bonding metal layer is sealed to the lower surface bonding area by gold-gold hot-press bonding; the upper surface bonding area is sealed to the silicon cover plate by gold-silicon eutectic bonding.

6. The wafer-level packaging structure of a piezoelectric driven electric field sensor according to claim 1, characterized in that, The central region of the insulating layer has a central hollow area that penetrates the insulating layer. The central hollow area is used to provide movement space for the vertical vibration of the movable comb teeth.

7. The wafer-level packaging structure of a piezoelectric driven electric field sensor according to claim 6, characterized in that, A horizontal gap is reserved between the sidewall of the central hollow area and the outermost edge of the movable comb teeth.

8. The wafer-level packaging structure of a piezoelectric driven electric field sensor according to claim 1, characterized in that, The insulating isolation layer is provided with a second through electrode hole that corresponds to the position of the top electrode lead window and the bottom electrode lead window in the vertical direction. The silicon cover plate is provided with a first through electrode hole that corresponds to the position of the second through electrode hole in the vertical direction, so that the electrode lead of the PZT top electrode is led out to the upper surface of the silicon cover plate through the top electrode lead window, the second through electrode hole and the first through electrode hole.

9. A method for fabricating a wafer-level packaging structure for a piezoelectric driven electric field sensor, applied to the wafer-level packaging structure for a piezoelectric driven electric field sensor as described in any one of claims 1-8, characterized in that, The preparation method includes: A comb-shaped structure is fabricated on an SOI wafer to form a stacked structure including a PZT bottom electrode layer, a PZT piezoelectric thin film layer and a PZT top electrode layer. A dielectric insulating layer is deposited over the entire surface of the PZT top electrode layer; A bonding metal layer is deposited over the entire surface of the dielectric insulating layer; A closed-loop bonding ring is formed by patterning the bonding metal layer; At least one top electrode lead window is fabricated in the bonding metal layer and the dielectric insulating layer; At least one bottom electrode lead window is fabricated in the bonding metal layer, dielectric insulating layer, PZT top electrode layer and PZT piezoelectric thin film layer; An insulating layer is prepared, and a central hollow area and a second through electrode hole are machined on the insulating layer. The second through electrode hole corresponds to the positions of the top electrode lead window and the bottom electrode lead window. Prepare a silicon cover plate, and process a second through electrode hole corresponding to the first through electrode hole on the silicon cover plate; The wafer surface is cleaned and activated, and the SOI wafer, insulating isolation layer and silicon cover plate are aligned and stacked in sequence according to the through holes; A bonding interface is formed by sealing and bonding between the SOI wafer and the insulating isolation layer, and between the insulating isolation layer and the silicon cover plate, to obtain a packaged piezoelectric driven electric field sensor.

10. The method for fabricating a wafer-level packaging structure for a piezoelectric driven electric field sensor according to claim 9, characterized in that, Before bonding, the bonding interface is activated by oxygen plasma.

Images