Radiation resistant optical MEMS device and method of making the same

Abstract

The application discloses an anti-radiation optical MEMS device and a preparation method thereof. The device is composed of a substrate support layer (9) and a device structure layer (10). A gradient impurity polysilicon isolation ring (1) is arranged on the structure layer. A multi-stage attenuated anti-radiation isolation framework is formed by using a doped gradient and a ring-shaped covering oxide layer field plate and an outer metal field plate. The application blocks the radiation-induced carriers by the gradient energy band in multiple stages, combines the double-layer composite field plate to homogenize the surface electric field and inhibit the interface charge accumulation, and effectively solves the problems of the large leakage current, the serious electrode crosstalk and the large optical and electrical parameter drift of the optical MEMS device in the strong radiation and high voltage extreme environment. The overall preparation process relies on mature MEMS mass production processes such as photolithography, deep silicon etching, LPCVD doped deposition, CMP planarization, wafer bonding, metal sputtering and structure release, and can be widely applied to the scenes of the onboard optical communication, the space laser radar, the high-energy radiation medical imaging and the extreme industrial detection strong radiation working conditions.

Description

Technical Field

[0001] This invention belongs to the field of microelectromechanical systems (MEMS) microelectronics and micro-nano optics technology, specifically relating to a radiation-resistant optical MEMS device suitable for extreme conditions of strong radiation and high pressure, and its fabrication method. It is mainly applied to scenarios such as spaceborne optical communication, aerospace lidar, space projection, high-energy radiation field medical imaging, and extreme industrial inspection. Background Technology

[0002] Optical MEMS devices are core integrated devices combining micromachining technology and micro-nano optics principles. Mainstream products include MEMS micromirrors, arrayed optical switches, micromirror arrays, and tunable optical attenuators. With their advantages of small size, low power consumption, high integration, and high optical control precision, they have become core components in optical communication, lidar, high-definition projection, and precision medical imaging systems. With the rapid development of aerospace, deep space exploration, and nuclear industry inspection, optical MEMS devices are gradually shifting from conventional ground-based operating conditions to extreme and complex environments such as space ionizing radiation, high-energy particle radiation, and high-voltage electric fields. This places extremely high demands on the devices' radiation resistance, electrical insulation, and optical precision consistency.

[0003] Currently, existing commercial and research-grade optical MEMS device structures generally suffer from technical shortcomings such as a lack of radiation resistance design and a single isolation structure. The current mainstream technical solutions and their inherent defects are as follows: First, conventional optical MEMS devices without isolation structures typically consist only of a movable micromirror structure, metal electrodes, a dielectric oxide layer, and a silicon substrate, lacking dedicated radiation-resistant isolation and electric field shielding structures. Under high-energy proton, electron, and gamma-ray irradiation in space, a large number of radiation-induced excess carriers are generated within the silicon substrate, while interface state charges accumulate on the device surface. Since conventional devices lack carrier blocking paths, excess carriers easily form lateral leakage currents, leading to a surge in leakage current and severe crosstalk between electrodes. This directly causes problems such as drive voltage shift, micromirror deflection angle drift, and optical response hysteresis. In extreme cases, device jamming and optical path failure may occur.

[0004] Secondly, for optical MEMS devices with a single uniformly doped isolation structure, some existing technologies add a uniformly doped polysilicon isolation ring around the active region of the device to improve leakage current. However, this type of isolation structure has a uniform doping concentration and a flat band structure, and it lacks the ability to progressively block irradiated carriers of different energies and diffusion depths, only achieving single-level leakage resistance isolation. Under high-intensity, long-term irradiation, carriers can easily break through the single-layer isolation barrier, and the isolation performance decays rapidly, making it unsuitable for long-term extreme service scenarios. At the same time, uniformly doped polysilicon is prone to causing local electric field concentration, exacerbating the risk of oxide layer breakdown and resulting in poor stability under high-voltage conditions.

[0005] Third, for single-field-isolated optical MEMS radiation-resistant structures, existing radiation-resistant improvement schemes only employ a single oxide layer field plate or a single metal field plate structure. These can only optimize the surface electric field distribution of the device and cannot solve the core problems of bulk leakage and carrier diffusion within the silicon substrate. The single-field-plate structure has no effect on suppressing radiation-induced bulk leakage, and there is a technical bottleneck of "surface electric field optimization but uncontrolled bulk leakage." The overall improvement in radiation resistance is limited and cannot meet the high reliability standards for aerospace applications.

[0006] In summary, existing optical MEMS devices generally suffer from core defects such as a single isolation mechanism, no bandgap modulation, and the inability to synergistically suppress bulk leakage and surface electric field. They also suffer from large parameter drift, poor operational stability, and short service life under extreme irradiation and high-voltage environments, which severely limit the large-scale application of optical MEMS devices in high-end extreme scenarios. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of existing optical MEMS devices, such as weak radiation resistance, large leakage current under extreme high-voltage irradiation, severe signal crosstalk, significant drift in optical and electrical parameters, poor operational stability, and short service life. This invention provides a radiation-resistant optical MEMS device structure and its fabrication method. The invention constructs a wave-shaped bandgap structure through multi-gradient doping of polycrystalline materials, and combines this with an oxide layer and a metal double-layer field plate to form a multi-level attenuation and segmented discharge composite isolation system. This achieves graded blocking of irradiated carriers and uniform control of the surface electric field, significantly improving the device's adaptability to extreme environments. Simultaneously, the process is compatible with mature MEMS mass production lines, possessing extremely high engineering application value.

[0008] This invention designs a composite isolation architecture with a single-ring multi-gradient impurity polycrystalline structure and a double-layer field plate. By using a wave-shaped energy band to block carriers in stages and dissipate charges in segments, combined with the double-layer field plate to homogenize the surface electric field, it solves the device failure problem under extreme operating conditions from both the bulk and interface dimensions.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: First, this invention provides a radiation-resistant MEMS device, comprising a device structure layer and a substrate support layer, wherein the device structure layer and the substrate support layer are integrally bonded together by wafer bonding, characterized in that: (1). The substrate support layer is made of double-polished silicon wafer, and a deep cavity is formed inside the substrate support layer to accommodate the displacement of the movable structure; (2). The device structure layer is based on SOI wafer fabrication, including a gradient impurity polysilicon isolation ring on the top silicon layer. The gradient impurity polysilicon isolation ring is arranged in the annular deep trench of the top silicon layer and surrounds the active region of the structure device. The gradient impurity polysilicon isolation ring is composed of polysilicon segments filled with at least three types of doping concentration gradients. The doping concentration decreases step by step from the outer ring to the inner ring, forming a wave-shaped energy band structure with continuous undulation in the lateral direction based on the doping concentration gradient. An oxide field plate is provided on the inner side of the isolation ring on the top silicon layer, and a metal field plate is provided on the oxide field plate; The top silicon center is surrounded by a movable structure corresponding to the deep cavity 4. The top silicon center forms an island, and a mirror metal layer is formed on the island. A first metal electrode is formed on the top silicon layer outside the movable structure. An annular groove covering the isolation ring 1 is formed on the top silicon layer. A second metal electrode is formed in the annular groove and communicates with the isolation ring and the top silicon layer.

[0010] The metal field plate and the metal electrode are formed in the same layer. The isolation ring, the oxide layer field plate, and the metal field plate together constitute a multi-level attenuation and segmented discharge in vivo-interface integrated radiation-resistant isolation architecture.

[0011] Based on the above technical solutions, the following further technical solutions are proposed: 1. The ring width of the gradient impurity polycrystalline silicon isolation ring is 12μm to 18μm, and the top surface of the isolation ring is provided with a gap lower than the top surface of the top silicon layer, the depth of the gap being 0.4μm to 0.6μm, so that the isolation ring is spaced 0.4μm to 0.6μm from the substrate support layer.

[0012] 2. The gradient impurity polycrystalline silicon isolation ring adopts a three-segment phosphorus doping gradient structure, with the outer ring having a doping concentration of 5e. 20 cm -3 The doping concentration of the middle ring is 5e. 18 cm -3 The inner ring doping concentration is 5e 16 cm -3 .

[0013] 3. The thickness of the substrate support layer is 350μm to 450μm, and the depth of the internal cavity is 70μm to 90μm; the thickness of the top silicon layer of the SOI wafer in the device structure layer is 20μm to 30μm, and the thickness of the buried oxide layer 10a is 1.5μm to 2.5μm.

[0014] 4. The metal field plate and metal electrode are aluminum metal thin films with a thickness of 0.6μm to 1.0μm, and the mirror metal layer is a gold-plated reflective layer with a thickness of 80nm to 120nm.

[0015] Secondly, the present invention also provides a method for fabricating a radiation-resistant MEMS device, comprising the following steps: S1. Fabrication of the substrate support layer: Selecting <100> A crystal-oriented double-polished silicon wafer is used to define the deep cavity pattern by photolithography. The deep cavity is prepared by KOH wet etching or dry deep silicon etching. After removing the resist, cleaning and drying, a substrate support layer with a closed deep cavity is obtained. S2. Preparation of gradient impurity polysilicon isolation ring: Select an SOI wafer with preset parameters, define the ring groove pattern by photolithography, and etch deep silicon to the buried oxide layer to form a single ring deep groove; adopt a staged in-situ doping deposition process to deposit at least three types of doped polysilicon with decreasing concentration gradients from the inner ring to the outer ring to fill and form a gradient impurity polysilicon isolation ring. After CMP planarization, wet etching will etch the top surface of the polysilicon to a gap below the top surface. S3. Wafer bonding: The substrate support layer is directly bonded to the SOI device layer that has been fabricated with gradient impurity polycrystalline silicon isolation rings, and the bonding interface is strengthened by high-temperature annealing. S4. Substrate Removal and Field Plate Forming: Mechanical thinning combined with wet etching removes the original SOI substrate silicon, retaining the buried oxide layer and top silicon; using the gradient impurity polysilicon isolation ring as the alignment reference, selectively etches the buried oxide layer, retaining the buried oxide layer to form an oxide field plate and forming an annular groove covering the isolation ring 1. S5. Metallization fabrication: A metal thin film is sputtered on the top silicon layer, and after patterning, a metal field plate is formed on the oxide field plate. A first metal electrode is formed on the top silicon layer inside the metal field plate. A second metal electrode connecting the isolation ring and the top silicon layer is formed in the annular groove. The mirror metal layer pattern is then photolithographically patterned again, and a mirror metal thin film is sputtered to form a high-reflectivity mirror metal layer in the center of the top silicon layer. S6. Structure Release: The top silicon is photolithographically released to create a movable structural pattern. The top silicon is then etched through deep silicon to release the suspended movable structure, thus completing the device fabrication.

[0016] Based on the above technical solutions, the following further technical solutions are proposed: 1. In S2, LPCVD process is used to deposit doped polysilicon. The thickness of polysilicon deposition in each section is 4μm to 6μm. After etching, the overall surface flatness is ≤0.1μm.

[0017] 2. The wafer bonding temperature in S3 is 1000℃~1100℃, the holding time is 1.5h~2.5h, and the entire process is protected by a nitrogen atmosphere.

[0018] 3. The KOH wet corrosion temperature in S1 is 80℃~90℃, and the corrosion rate is 1.0μm~1.5μm / min.

[0019] 4. Deep silicon etching in S2 adopts ICP etching process with etching power of 700W~900W and etching rate of 2.0μm~3.0μm / min.

[0020] Compared with the prior art, the present invention has the following significant advantages: 1. Excellent radiation resistance and strong stability under extreme conditions. This invention innovatively adopts a single-ring, multi-gradient impurity polycrystalline structure to construct a continuous wave-shaped energy band, breaking the single isolation limitation of traditional flat energy bands. The energy level difference formed by different gradient doping can achieve multi-level blocking of irradiation-induced electrons and holes with different energies and diffusion depths, gradually attenuating carrier energy and dissipating interface accumulated charge in segments, fundamentally suppressing leakage current diffusion from within the silicon substrate; at the same time, combined with an oxide layer field plate + metal field plate double-layer composite field plate structure, it effectively homogenizes the peak electric field on the device surface, weakens interface charge accumulation and electric field distortion, and solves the core problems of irradiation leakage current, electrode crosstalk, and parameter drift in traditional devices, enabling long-term tolerance to extreme environments of strong ionizing radiation and high voltage and strong electric field.

[0021] 2. Integrated structural design, high compatibility and reliability. The radiation-resistant isolation structure of this invention is integrated with the device body, eliminating the need for additional external protective structures and resulting in no additional increase in device size or power consumption. The overall fabrication process relies entirely on mature MEMS mass production processes such as photolithography, etching, thin film deposition, wafer bonding, and CMP polishing, requiring no special customized equipment or processes. It is perfectly compatible with existing optical MEMS device mass production lines, exhibiting excellent mass production capability and consistency.

[0022] 3. Wide range of applications and high engineering practical value. The device of this invention can effectively solve the problem of extreme environment adaptation for spaceborne optical switches, aerospace lidar micro-mirrors, optical detection equipment for nuclear radiation environments, and high-energy medical imaging MEMS chips, significantly improving the environmental adaptability and service life of high-end optical MEMS devices, and breaking through the technical bottleneck that traditional optical MEMS devices cannot be applied to strong radiation extreme scenarios. Attached Figure Description

[0023] Figure 1 This is a schematic cross-sectional view of the radiation-resistant MEMS device of the present invention. Figures 2-6 This is a flowchart illustrating the fabrication process of the radiation-resistant MEMS device of the present invention. Figure 7 for Figure 4 A magnified view of a polycrystalline isolation ring with multiple gradient impurities; Figure 8 This is a diagram of the band structure of a multi-gradient impurity polycrystalline isolation ring.

[0024] Wherein: 1-Multi-gradient impurity polycrystalline isolation ring, 2-Oxide field plate, 3-Metal field plate, 4-Deep cavity, 5-Mirror metal, 6-Modible structure, 7-First metal electrode, 8-Second metal electrode, 9-Substrate silicon, 10-Top layer silicon. Detailed Implementation

[0025] The present invention will be further described in detail and completely below with reference to the accompanying drawings and specific preferred embodiments. These embodiments are implemented under the premise of the technical solution of the present invention, and provide detailed implementation methods and specific operating parameter ranges. However, the protection scope of the present invention is not limited to the following embodiments. Example 1

[0026] like Figure 1 As shown, the radiation-resistant MEMS device of the present invention has a double-layer bonding structure, consisting of an upper device structure layer 10 and a lower substrate support layer 9. The lower substrate support layer 9 is 350μm to 450μm thick and has a crystal orientation of [missing information]. <100> The double-polished silicon wafer has a rectangular deep cavity 4 with a depth of 70μm to 90μm formed inside. The deep cavity 4 is positioned directly opposite the movable structure 6 above, providing sufficient displacement space for the micromirror to deflect and vibrate. At the same time, it effectively avoids friction and adhesion between the structure and the substrate during the movement of the structure, ensuring the dynamic working stability of the device.

[0027] The upper device structure layer 10 is fabricated based on an SOI wafer. The thickness of the top silicon layer 10 on the SOI wafer is 20μm to 30μm, and the thickness of the buried oxide layer 10b is 1.5μm to 2.5μm. The core radiation-resistant structure of the device structure layer is a gradient impurity polycrystalline silicon isolation ring 1. This structure is a fully enclosed ring structure, arranged around the movable structure 6 and the active electrode region. The width of the isolation ring is 12μm to 18μm, and it is embedded in the annular deep groove of the top silicon layer 10. The top surface of the polycrystalline structure has a gap 1a that is 0.4μm to 0.6μm lower than the surface of the top silicon layer, which effectively avoids the risk of short circuit between the top surface of the polycrystalline structure and the substrate support layer, avoids affecting silicon-silicon bonding, and improves the electrical reliability of the device.

[0028] In this embodiment, see Appendix Figure 7 The multi-gradient impurity polycrystalline isolation ring 1 adopts a three-segment gradient doping design, consisting of an outer ring with a high concentration of doped regions (gray rectangular portion), a middle ring with a medium concentration of doped regions (yellow ring portion), and an inner ring with a low concentration of doped regions (gray ring portion). All dopants are phosphorus ions, with the inner ring having a doping concentration of 5e⁻¹. 16 cm -3 The doping concentration in the middle section is 5e 18 cm -3 The outer ring doping concentration is 5e 20 cm -3The doping concentration decreases gradually from the outside to the inside. The specific preparation method is as follows: polycrystalline fillers are deposited layer by layer along the trench sidewalls. Therefore, highly doped polycrystalline fillers are deposited on the silicon sidewalls, moderately doped polycrystalline fillers are deposited on the surface of highly doped polycrystalline fillers, and lowly doped polycrystalline fillers are deposited on the surface of moderately doped polycrystalline fillers. Finally, the lowly doped polycrystalline fillers complete the trench sealing. The function and effect of the multi-gradient impurity polycrystalline isolation ring structure: 1. Gradient doping constructs multi-level potential barriers, segmentally blocking carrier diffusion: The doping concentration decreases gradually from the outside to the inside of the deep trench (high doping → moderate doping → low doping → moderate doping → high doping), forming a continuously changing band structure. Different doping concentrations of polycrystalline silicon correspond to different energy levels, equivalent to connecting multiple potential barriers and equivalent high-resistance regions in series along the leakage path. Carriers generated during the operation of optical MEMS devices, leakage carriers under high voltage, and additional carriers excited by irradiation are continuously blocked and have their energy consumed as they pass through the gradient polycrystalline layer, achieving multi-level attenuation, significantly reducing lateral leakage current, and preventing leakage current from spreading to the core optical and driving regions of the device. 2. A single-ring surround forms a ring-shaped isolation region, cutting off lateral leakage current from the substrate: This structure is a surrounding single-ring layout that completely surrounds the functional area of ​​the device, blocking bulk silicon leakage current and surface lateral leakage current between the silicon substrate and the active area of ​​the device. The design of etching the polycrystalline structure below the silicon surface further cuts off the dual conductive paths between the bulk silicon and the surface, solving the problem of aggravated leakage crosstalk in traditional optical MEMS.

[0029] like Figure 8 As shown, based on the semiconductor band structure principle, the Fermi level of silicon-based polycrystalline silicon is positively correlated with the doping concentration. The gradually varying doping distribution with high, medium, and low doping levels causes the Fermi level to fluctuate continuously in the lateral direction, forming a periodic wave-shaped band structure. This structure can construct multi-level potential barriers to intercept and attenuate high-energy carriers generated by irradiation step by step, avoiding the problems of limited isolation capability and susceptibility to breakdown by carriers in a single flat band structure, thus fundamentally suppressing the lateral diffusion of irradiation leakage current.

[0030] See Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 The oxide field plate 2 (which is a ring) is formed by patterning and retaining the original SOI buried oxide layer 10b. It is located on the top silicon 10 inside the gradient impurity polysilicon isolation ring. The oxide layer thickness is the same as the buried oxide layer thickness. A metal field plate 3 is provided on the oxide field plate, which can effectively isolate the silicon substrate from the metal field plate 3 provided on the oxide field plate 2, thereby reducing the field concentration effect at the edge of the device.

[0031] A movable structure 6 corresponding to the deep cavity 4 is provided around the center of the top silicon 10. The center of the top silicon forms an island, and a mirror metal layer 5 is formed on the island. See Figure 4 , Figure 5 and Figure 6A first metal electrode 7 (arranged at the four corners of the die area, which is related to the design layout) is formed on the top silicon layer 10 outside the movable structure 6. An annular groove 1b covering the isolation ring 1 is formed on the top silicon layer 10. A second metal electrode 8 is formed in the annular groove and communicates with the isolation ring 1 and the top silicon layer 10.

[0032] The metal field plate and the metal electrode are formed in the same layer. The isolation ring, the oxide layer field plate, and the metal field plate together constitute a multi-level attenuation and segmented discharge in vivo-interface integrated radiation-resistant isolation architecture.

[0033] The metal field plate 3, the first metal electrode 7, and the second metal electrode 8 are formed by simultaneous sputtering of aluminum metal thin films with a thickness of 0.6 μm to 1.0 μm. The metal field plate is arranged in a ring on the outer side of the oxide layer field plate to further homogenize the surface electric field of the device and suppress the accumulation of interface state charges. The movable structure 6 is a suspended and hollow silicon micromirror frame structure. The surface of the central island of the top silicon 10 is sputtered with gold-plated mirror metal 5 with a thickness of 80 nm to 120 nm, which has high optical reflectivity and oxidation resistance, meeting the requirements of precision optical control. Example 2

[0034] The preparation process of this invention is as follows: Figures 2-6 As shown, the specific operation steps are as follows: (1) Substrate support layer preparation like Figure 3 As shown, a thickness of 350μm to 450μm was selected. <100> A crystal-oriented, double-polished silicon wafer 9 undergoes standard RCA cleaning to remove surface impurities, oil, and oxide layers. Positive photoresist is spin-coated, and after exposure and development, the deep cavity pattern is defined. A KOH wet etching process is used at an etching temperature of 80℃~90℃ and an etching rate of 1.0μm~1.5μm / min to prepare a well-defined deep cavity 4 with a depth of 70μm~90μm. After etching, the photoresist is removed sequentially using acetone, ethanol, and deionized water, followed by drying with high-purity nitrogen to complete the fabrication of the substrate support layer 9. This process produces a deep cavity with high sidewall flatness and no obvious burrs or defects, effectively ensuring the accuracy and structural stability of subsequent wafer bonding.

[0035] (2) Fabrication of gradient polycrystalline structure layer on the back side of the device like Figure 2 , Figure 3 As shown, an SOI wafer consisting of a 20μm-30μm top silicon layer 10, a 1.5μm-2.5μm buried oxide layer 10b, and a substrate silicon 10a is selected. After cleaning and drying, photoresist is spin-coated, and a ring-shaped deep trench pattern is defined by photolithography. An inductively coupled plasma (ICP) deep silicon etching process is used with an etching power of 700W-900W and an etching rate of 2.0μm-3.0μm / min to precisely etch to the surface of the buried oxide layer, forming a closed ring-shaped deep trench with a width of 12μm-18μm.

[0036] like Figure 7 As shown, low-pressure chemical vapor deposition (LPCVD) is used to deposit doped polycrystalline silicon in a closed annular deep trench in three stages, with gradient doping in three sections: the first stage deposits a high-concentration polycrystalline outer ring with a phosphorus doping concentration of 5e. 20 cm -3 The deposition thickness is 4μm to 6μm; the second step deposition section has a medium concentration of polycrystalline material with a doping concentration of 5e. 18 cm -3 The deposition thickness is 4μm to 6μm; the third step involves depositing a low-concentration polycrystalline inner ring with a doping concentration of 5e. 16 cm -3 The deposition thickness is 2μm to 3μm. Because the two sides fill towards the center, the total thickness is 4μm to 6μm. The complete filling of the annular deep trench forms a gradient impurity polycrystalline silicon isolation ring 1.

[0037] After deposition, the surface is planarized using CMP (chemical mechanical polishing) to remove excess polycrystalline and protruding structures, ensuring a surface flatness of ≤0.1μm. Subsequently, a light etching process using dilute hydrofluoric acid is employed to etch the gradient impurity polycrystalline silicon isolation ring to 0.4μm~0.6μm below the top silicon surface, forming a gap 1a, which completely eliminates the risk of short circuits in subsequent bonding processes.

[0038] like Figure 8 As shown, when a device is irradiated, the ionization effect generates a large number of electron-hole pairs in the band gap. These charge carriers are rapidly separated by the dual built-in electric fields and directionally swept to the highly doped regions at both ends, thereby effectively suppressing leakage channels and device parameter drift caused by irradiation defects, thus achieving excellent radiation resistance.

[0039] (3) Wafer bonding process See Figure 3 The prepared substrate support layer 9 and the SOI device semi-finished product are precisely aligned on both sides. The alignment reference is the center of the multi-gradient impurity polycrystalline isolation ring 1 and the deep cavity 4 of the substrate. The movable structure 6 and the mirror metal 5 are located in the center of the deep cavity. The silicon-silicon direct bonding process is adopted, the bonding temperature is 1000℃~1100℃, the holding time is 1.5h~2.5h, and the nitrogen atmosphere is protected to ensure that there are no voids or misalignments at the bonding interface and the bonding strength meets the mechanical reliability requirements of MEMS devices.

[0040] (4) Substrate removal and oxide layer forming like Figure 4 , Figure 5As shown, the original SOI substrate silicon 10a is removed by mechanical grinding and thinning. The remaining part is completely removed by wet etching, leaving only the buried oxide layer 10b and the top silicon 10 structure. Using the multi-gradient impurity polycrystalline isolation ring 1 below as a precise alignment reference, the buried oxide layer is patterned by photolithography, and excess oxide layer is selectively etched to remove it. The silicon dioxide layer above and inside the gradient polycrystalline layer is completely preserved in the ring, forming a full-coverage annular oxide field plate 2, ensuring that the oxide field plate 2 and the multi-gradient impurity polycrystalline isolation ring 1 are precisely aligned.

[0041] Simultaneously, the gradient impurity polycrystalline isolation ring 1 is etched to make it lower than the top silicon surface and form a shallow trench 1b with a trench width greater than that of the gradient impurity polycrystalline isolation ring 1 and concentric with it.

[0042] (5) Metal structure preparation On the top silicon layer 10 of the device layer, an aluminum metal thin film with a thickness of 0.6μm to 1.0μm is sputtered using a magnetron sputtering process. After photolithography and wet etching patterning, a metal field plate 3 on the oxide layer field plate 2, a metal electrode 8 covering the polysilicon ring groove 1 in the shallow trench 1b, and a first metal electrode 7 on the top silicon layer 10 are formed simultaneously. The metal electrode 8 and the metal field plate 3 are grounded separately. The metal electrode 7 is a driving metal electrode including positive and negative electrodes, which is related to the design wiring. Subsequently, a high-reflectivity gold thin film with a thickness of 80nm to 120nm is sputtered at the center of the top silicon layer of the device layer. After patterning and etching, a flat and highly reflective mirror metal layer 5 is obtained, which ensures the excellent optical performance of the device.

[0043] (6) Structural release molding Around the mirror metal layer 5 on the top silicon layer, a micromirror movable structure release pattern is defined by photolithography. The top silicon layer is then etched using ICP deep silicon etching to release the suspended micromirror movable structure 6. After etching, the resist is removed, the surface is cleaned, and dried to complete the overall fabrication of the radiation-resistant MEMS device.

[0044] Example 3: Test Results of Device Radiation Resistance The device prepared according to this invention was subjected to aerospace-grade space ionizing irradiation testing with a total irradiation dose of 100 klad (Si), and the test environment simulated the intense irradiation conditions of deep space. The test results show that conventional non-isolated optical MEMS devices experience a leakage current increase of over 400% and a micromirror deflection angle drift of >5% after irradiation, exhibiting significant malfunctions and response lag. In contrast, the device of this invention shows a leakage current increase of less than 30% after irradiation, an optical deflection accuracy drift of <0.8%, no significant shift in driving voltage, and no crosstalk, jamming, or failures. Its electrical and optical performance stability is far superior to that of traditional devices, fully meeting the high reliability requirements of aerospace extreme irradiation conditions.

[0045] The function and effect of the gradient impurity polycrystalline silicon isolation ring 1 are as follows: The chip edge is where the interface state density and electric field are most concentrated. Irradiation-generated charges drift along the die edge towards the active region, causing edge leakage; high doses can lead to edge breakdown, resulting in a complete short circuit. A grounded polysilicon ring forms a barrier between the die edge and the active region, absorbing drifting charges. Any charge drifting along the interface is directly absorbed by the ring. The interfaces between polysilicon with different doping concentrations contain numerous defects, resulting in significantly higher absorption of drifting charges compared to traditional injection. Furthermore, gradient-doped polysilicon forms a gradual potential barrier, flattening the electric field distribution and significantly increasing the breakdown voltage by 2-3 times.

[0046] The metal and oxide field plate is responsible for absorbing the stray electric field generated by the internal charge of the device, while the polysilicon isolation ring is responsible for shielding the external electric field and charge of the device. The superposition of the two can effectively shield the influence on the comb drive electric field.

[0047] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A radiation-resistant MEMS device, comprising a device structure layer and a substrate support layer, wherein the device structure layer and the substrate support layer are integrally bonded together by wafer bonding, characterized in that: (1). The substrate support layer (9) is made of double-polished silicon wafer, and a deep cavity (4) is formed inside the substrate support layer to accommodate the displacement of the movable structure of the device structure layer. (2). The device structure layer is based on SOI wafer fabrication, including a gradient impurity polysilicon isolation ring (1) on the top silicon (10). The gradient impurity polysilicon isolation ring is arranged in the annular deep trench of the top silicon and surrounds the active region of the structure device. The gradient impurity polysilicon isolation ring is composed of polysilicon segments filled with at least three types of doping concentration gradients. The doping concentration decreases step by step from the outer ring to the inner ring, and a wave-shaped energy band structure with continuous undulation in the lateral direction is formed by relying on the doping concentration gradient. An oxide field plate (2) is provided on the inner side of the isolation ring on the top silicon layer, and a metal field plate (3) is provided on the oxide field plate. A movable structure (6) corresponding to the deep cavity (4) is provided around the top silicon center, and an island is formed in the top silicon center, with a mirror metal layer (5) on the island. A first metal electrode (7) is formed on the top silicon layer (10) on the outside of the movable structure (6). An annular groove (1b) covering the isolation ring (1) is formed on the top silicon layer (10). A second metal electrode (8) formed in the annular groove is connected to the isolation ring (1) and the top silicon layer (10).

2. The radiation-resistant MEMS device according to claim 1, characterized in that: The gradient impurity polycrystalline silicon isolation ring has a ring width of 12μm to 18μm. The top surface of the isolation ring is provided with a gap (1a) lower than the top surface of the top silicon layer. The depth of the gap (1a) is 0.4μm to 0.6μm, so that the isolation ring is spaced 0.4μm to 0.6μm from the substrate support layer (9).

3. The radiation-resistant optical MEMS device structure according to claim 1 or 2, characterized in that: The gradient impurity polycrystalline silicon isolation ring adopts a three-segment phosphorus doping gradient structure, with an outer ring doping concentration of 5e. 20 cm -3 The doping concentration of the middle ring is 5e. 18 cm -3 The inner ring doping concentration is 5e 16 cm -3 .

4. The radiation-resistant MEMS device according to claim 1, characterized in that: The substrate support layer (9) has a thickness of 350μm to 450μm and the depth of the internal deep cavity (4) is 70μm to 90μm; the SOI wafer top silicon (10) of the device structure layer has a thickness of 20μm to 30μm and the buried oxide layer (10a) has a thickness of 1.5μm to 2.5μm.

5. The radiation-resistant MEMS device according to claim 1, characterized in that: The metal field plate and metal electrode are aluminum metal thin films with a thickness of 0.6μm to 1.0μm, and the mirror metal layer is a gold-plated reflective layer with a thickness of 80nm to 120nm.

6. A method for fabricating a radiation-resistant MEMS device according to any one of claims 1 to 5, characterized in that, Includes the following steps: S1. Fabrication of the substrate support layer: Selecting <100> A crystal-oriented double-polished silicon wafer is used to define the deep cavity pattern by photolithography. The deep cavity 4 is prepared by KOH wet etching or dry deep silicon etching. After removing the resist, cleaning and drying, a substrate support layer with a closed deep cavity is obtained (9). S2. Preparation of gradient impurity polysilicon isolation ring: Select an SOI wafer with preset parameters, define the ring groove pattern by photolithography, and etch deep silicon to the buried oxide layer (10b) to form a single ring deep groove; adopt a step-by-step in-situ doping deposition process to deposit at least three types of doped polysilicon with decreasing concentration gradients from the outer ring to the inner ring, fill and form a gradient impurity polysilicon isolation ring (1), after CMP planarization, wet etching will etch the top surface of the polysilicon to a gap (1a) below the surface of the top layer (10). S3. Wafer bonding: The substrate support layer is directly bonded to the SOI device layer that has been fabricated with gradient impurity polycrystalline silicon isolation rings, and the bonding interface is strengthened by high-temperature annealing. S4. Substrate Removal and Field Plate Forming: Mechanical thinning combined with wet etching removes the original SOI substrate silicon (10a), retaining the buried oxide layer (10b) and the top silicon layer (10); using the gradient impurity polysilicon isolation ring (1) as the alignment reference, selectively etch the buried oxide layer, retaining the buried oxide layer to form an oxide field plate (2) and forming an annular groove (1b) covering the isolation ring 1. S5, Metallization preparation: A metal thin film is sputtered on the top silicon (10), and after patterning, a metal field plate (3) is formed on the oxide field plate (2). A first metal electrode (7) is formed on the top silicon (10) inside the metal field plate (3). A second metal electrode (8) connecting the isolation ring (1) and the top silicon (10) is formed in the annular groove (1b). The mirror metal layer pattern is photolithographically patterned again, and a mirror metal thin film is sputtered to form a high-reflectivity mirror metal layer (5) in the center of the top silicon (10). S6. Structure release: Photolithography releases the movable structure pattern on the top silicon (10), deep silicon etching hollows out the top silicon, releases the suspended movable structure (6), and completes the device fabrication.

7. The method for fabricating a radiation-resistant optical MEMS device structure according to claim 6, characterized in that: In S2, LPCVD process is used to deposit doped polycrystalline silicon. The thickness of polycrystalline silicon deposition in each section is 4μm to 6μm, and the overall surface flatness after etching is ≤0.1μm.

8. The method for fabricating a radiation-resistant optical MEMS device structure according to claim 6, characterized in that: The wafer bonding temperature in S3 is 1000℃~1100℃, the holding time is 1.5h~2.5h, and the entire process is protected by a nitrogen atmosphere.

9. The method for fabricating a radiation-resistant optical MEMS device structure according to claim 6, characterized in that: The KOH wet corrosion temperature in S1 is 80℃~90℃, and the corrosion rate is 1.0μm~1.5μm / min.

10. The method for fabricating a radiation-resistant optical MEMS device structure according to claim 6, characterized in that: The deep silicon etching in S2 uses ICP etching technology with an etching power of 700W to 900W and an etching rate of 2.0μm to 3.0μm / min.

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