Electroplating control method and device, electronic equipment, storage medium, program and circuit board

Abstract

The application provides a kind of electroplating control method, device, electronic equipment, storage medium, program and circuit board, its method includes: according to electroplating total time length, the electroplating process of circuit board is divided into pre-plating stage, deep plating stage and dense stage, and corresponding electroplating parameters are configured to each stage;In the pre-plating stage of electroplating process, the electroplating parameters corresponding to the pre-plating stage are used for electroplating control to form an initial plating layer on the hole wall of the circuit board;In the deep plating stage of electroplating process, the electroplating parameters corresponding to the deep plating stage are used for electroplating control to generate a reinforced plating layer based on the initial plating layer;In the dense stage of electroplating process, the electroplating parameters corresponding to the dense stage are used for electroplating control to generate a dense plating layer based on the reinforced plating layer.Based on the method, the problem that the existing electroplating technology cannot meet the uniformity, density and reliability requirements of the plating layer under high aspect ratio conditions can be solved.

Description

Technical Field

[0001] This application relates to the field of circuit board electroplating technology, and in particular to an electroplating control method, apparatus, electronic device, storage medium, computer program product, and circuit board. Background Technology

[0002] With the continuous improvement of the integration of electronic components, circuit boards (PCBs) are widely used in high-density, miniaturized electronic products. The high-end PCB industry is rapidly developing towards high-density interconnect (HDI), IC substrates, and multilayer boards, which places increasingly higher demands on board thickness. The aspect ratio of through-holes has reached 50:1 or even higher, which directly affects the depth plating capability, plating uniformity, density, and reliability of the electroplating process. Existing PCB electroplating technologies typically employ single-direct current plating mode and single-pulse / bidirectional pulse plating mode. However, under high aspect ratio conditions, there is a significant difference in plating deposition rate between the hole opening area and the hole center area, resulting in plating thickness uniformity that does not meet the requirements of high-end products. While single-pulse / bidirectional pulse plating modes solve the uniformity problem to some extent, they also introduce other shortcomings in plating quality. Summary of the Invention

[0003] In view of this, embodiments of this application provide an electroplating control method, apparatus, electronic device, storage medium, program, and circuit board, aiming to solve the problem that existing electroplating technologies cannot meet the requirements for coating uniformity, density, and reliability under high aspect ratio conditions.

[0004] The first aspect of this application provides an electroplating control method, including: Based on the total electroplating time, the electroplating process of the circuit board is divided into a pre-plating stage, a deep plating stage, and a densification stage, and corresponding electroplating parameters are configured for each stage. In the pre-plating stage of the electroplating process, electroplating control is performed using the electroplating parameters corresponding to the pre-plating stage to form an initial plating layer on the hole wall of the circuit board. In the deep plating stage of the electroplating process, electroplating parameters corresponding to the deep plating stage are used for electroplating control in order to generate a reinforced plating layer based on the initial plating layer. During the densification stage of the electroplating process, electroplating parameters corresponding to the densification stage are used for electroplating control in order to generate a dense coating based on the enhanced coating.

[0005] In one possible implementation, the electroplating parameters include at least one of the following parameters: electric field parameters, flow field parameters, and motion field parameters.

[0006] In one possible implementation, the pre-plating stage includes at least one pre-plating DC current cycle, and a pre-plating pulse current cycle executed after the pre-plating DC current cycle.

[0007] In one possible implementation, the deep plating stage includes a first sub-stage and a second sub-stage; the first sub-stage includes electroplating control using a first pulse waveform to rapidly deposit and thicken the plating layer on top of the initial plating layer to form a first reinforced plating layer; the second sub-stage includes electroplating control using a second pulse waveform to selectively dissolve the first reinforced plating layer, so that the plating thickness at the orifice and the plating thickness at the center of the orifice tend to be balanced to form a second reinforced plating layer.

[0008] In one possible implementation, the first pulse waveform includes at least one first reverse pulse; the second pulse waveform includes at least one second reverse pulse; wherein the reverse peak current density of the second reverse pulse is greater than the reverse peak current density of the first reverse pulse, and / or the reverse current application duration of the second reverse pulse is greater than the reverse current application duration of the first reverse pulse.

[0009] In one possible implementation, the first pulse waveform includes at least one first positive pulse; the second pulse waveform includes at least one second positive pulse; wherein the duty cycle of the first positive pulse and the second positive pulse during their respective positive periods is greater than the duty cycle of any reverse pulse during its reverse periods; and the duty cycle of the second reverse pulse during its reverse periods is greater than the duty cycle of the first reverse pulse during its reverse periods.

[0010] In one possible implementation, the deep plating stage further includes at least one deep plating DC current cycle, executed in a preset order with the first sub-stage and the second sub-stage; the densification stage includes at least one densification DC current cycle.

[0011] In one possible implementation, the pre-plating stage includes at least one pre-plating DC current cycle and a pre-plating pulse current cycle executed after the pre-plating DC current cycle; the deep plating stage uses a deeper plating DC current density greater than the pre-plating DC current density used in the pre-plating stage; the deep plating stage uses a deeper plating DC current density greater than the denser DC current density used in the denser stage; and the deep plating stage uses a deeper plating pulse peak current density greater than the pre-plating pulse peak current density used in the pre-plating stage.

[0012] In one possible implementation, the ratio of the forward to reverse amplitude of the second pulse waveform is greater than the ratio of the forward to reverse amplitude of the first pulse waveform.

[0013] In one possible implementation, fluid flow control is performed using the deep plating jet velocity in the deep plating stage, the pre-plating jet velocity in the pre-plating stage, and the dense plating stage; wherein the deep plating jet velocity is greater than the pre-plating jet velocity, and the pre-plating jet velocity is greater than the dense plating jet velocity.

[0014] In one possible implementation, the motion field parameters include vibration parameters of the cathode, which are configured differently according to each stage, wherein: in the pre-plating stage, the cathode is controlled to vibrate at a first vibration frequency, which is synchronized with the pre-plating pulse current cycle to suppress preferential deposition in the orifice region; in the deep plating stage, the cathode is controlled to vibrate at a second vibration frequency, which is greater than the first vibration frequency, to promote ion transport; and in the densification stage, the cathode is controlled to stop vibrating or to vibrate slightly at a third vibration frequency, which is less than the first vibration frequency, to avoid the impact of disturbance on the crystal smoothness of the plating layer.

[0015] In one possible implementation, the running time of the pre-plating stage accounts for 20% to 30% of the total electroplating time; the running time of the deep plating stage accounts for 65% to 80% of the total electroplating time; and the running time of the densification stage accounts for 3% to 15% of the total electroplating time.

[0016] A second aspect of this application provides an electroplating control device, the device comprising: The parameter configuration module is used to divide the electroplating process of the circuit board into a pre-plating stage, a deep plating stage, and a densification stage according to the total electroplating time, and to configure the corresponding electroplating parameters for each stage. An electroplating control module is used to control electroplating in the pre-plating stage of the electroplating process by using electroplating parameters corresponding to the pre-plating stage to form an initial plating layer on the hole walls of the circuit board; in the deep plating stage of the electroplating process by using electroplating parameters corresponding to the deep plating stage to generate a reinforced plating layer based on the initial plating layer; and in the densification stage of the electroplating process by using electroplating parameters corresponding to the densification stage to generate a dense plating layer based on the reinforced plating layer.

[0017] A third aspect of this application provides a circuit board including at least one through-hole. The sidewall of the through-hole includes an initial plating layer formed by the electroplating control method as described in any one of the first aspects, a reinforcing plating layer on the initial plating layer, and a dense plating layer on the reinforcing plating layer. The initial plating layer is in a first thickness range, the reinforcing plating layer is in a second thickness range, and the second thickness range is greater than the first thickness range. The reinforcing plating layer is in a first density range, the dense plating layer is in a second density range, and the second density range is greater than the first density range.

[0018] A fourth aspect of this application provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the electronic device, wherein the processor executes the computer program to implement the steps of the electroplating control method provided in the first aspect.

[0019] A fifth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the electroplating control method provided in the first aspect.

[0020] A sixth aspect of this application provides a computer program product that, when run on an electronic device, causes the electronic device to execute the steps of the electroplating control method provided in the first aspect.

[0021] The electroplating control method, apparatus, electronic device, storage medium, program, and circuit board provided in this application have the following beneficial effects: The electroplating process of a circuit board is divided into a pre-plating stage, a deep plating stage, and a densification stage based on the total electroplating time, and corresponding electroplating parameters are configured for each stage. In the pre-plating stage, the electroplating parameters corresponding to the pre-plating stage are used for electroplating control to form an initial plating layer on the hole walls of the circuit board. In the deep plating stage, the electroplating parameters corresponding to the deep plating stage are used for electroplating control to generate a reinforced plating layer based on the initial plating layer. In the densification stage, the electroplating parameters corresponding to the densification stage are used for electroplating control to generate a dense plating layer based on the reinforced plating layer. Based on this method, the problem of existing electroplating technologies failing to meet the requirements for plating uniformity, density, and reliability under high aspect ratio conditions can be solved. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating the implementation of an electroplating control method provided in an embodiment of this application.

[0024] Figure 2 This is a basic structural block diagram of an electroplating control device provided in an embodiment of this application.

[0025] Figure 3 This is a basic structural block diagram of an electronic device provided in an embodiment of this application. Detailed Implementation

[0026] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of this application with unnecessary detail.

[0027] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0028] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0030] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0031] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. "A plurality" means "two or more."

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] In some embodiments of this application, please refer to Figure 1 , Figure 1 This is a flowchart illustrating the implementation of an electroplating control method provided in an embodiment of this application. Figure 1 As shown, it may specifically include steps S11 to S14.

[0034] S11: Based on the total electroplating time, the electroplating process of the circuit board is divided into a pre-plating stage, a deep plating stage, and a densification stage, and corresponding electroplating parameters are configured for each stage.

[0035] The electroplating process of the circuit board can specifically employ Vertical Continuous Plating (VCP) technology. The total plating time can be determined according to the actual processing requirements of the circuit board. For example, the total plating time can be manually set based on experience, or it can be calculated according to the electroplating process objectives of the circuit board combined with the actual electroplating processing environment factors using a specific time conversion method. In this embodiment, when controlling the electroplating, the entire VCP electroplating process can be divided into three stages: the pre-plating stage, the deep plating stage, and the densification stage. The pre-plating stage is to form an initial plating layer on the hole walls of the circuit board; the deep plating stage is to form a reinforced plating layer that meets the preset thickness requirements of the circuit board based on the initial plating layer; and the densification stage is to form a dense plating layer that meets the preset density requirements of the circuit board based on the reinforced plating layer. In some specific embodiments, the runtime of the pre-plating stage can be configured to account for 20% to 30% of the total electroplating time; the runtime of the deep plating stage can be configured to account for 65% to 80% of the total electroplating time; and the runtime of the densification stage can be configured to account for 3% to 15% of the total electroplating time. For each stage, corresponding electroplating parameters can be configured separately to achieve the process objectives of each stage. It should be noted that the thickness of the strengthening coating is greater than the thickness of the initial coating, and the density of the dense coating is greater than the density of the strengthening coating.

[0036] In some specific embodiments, the electroplating parameters may include at least one of electric field parameters, flow field parameters, and motion field parameters. The electric field parameters are used to control the current during the electroplating process, the flow field parameters are used to control the fluid flow state during the electroplating process, and the motion field parameters are used to control the motion during the electroplating process. In this embodiment, by combining the electroplating parameters obtained from the electric field parameters, flow field parameters, and motion field parameters, the synergistic effect of the electric field, flow field, and motion field can be achieved to control the electroplating process of the circuit board. This effectively solves the matching defects caused by independent parameter settings during the electroplating process, significantly reducing the thickness deviation of the plating layer on the same board and the deviation between boards, which is beneficial to improving the yield of circuit board products.

[0037] In this embodiment, electric field parameters refer to the set of parameters used to control the characteristics of the electroplating current, and may include, but are not limited to: current type (DC / pulse), current density, pulse waveform parameters (forward / reverse amplitude, pulse width, duty cycle), etc. Flow field parameters refer to the set of parameters used to control the flow state of the plating solution, and may include, but are not limited to: jet velocity, Reynolds number, and the angle between the jet direction and the plate surface, etc. Motion field parameters refer to the set of parameters used to control the motion state of the cathode, and may include, but are not limited to: vibration frequency, vibration amplitude, and moving speed, etc.

[0038] S12: In the pre-plating stage of the electroplating process, electroplating control is performed using the electroplating parameters corresponding to the pre-plating stage to form an initial plating layer on the hole wall of the circuit board.

[0039] In this embodiment, the electroplating time of the circuit board can be monitored to determine whether the electroplating process has entered the pre-plating stage. The start time of the electroplating task on the circuit board is the time of entering the pre-plating stage. During the pre-plating stage, electroplating control can be achieved by using the corresponding electroplating parameters to form an initial plating layer on the hole walls of the circuit board. This initial plating layer has low thickness, good uniformity, and high density. Forming an initial plating layer through the pre-plating stage can suppress excessively rapid deposition at the hole openings during the electroplating process, preventing scorching, protrusion, or premature closure of the hole openings during subsequent electroplating, thus improving the deep plating capability for the subsequent deep plating stage. It can be understood that deep plating capability refers to the ability of the electroplating solution to deposit a metal plating layer inside difficult-to-plating areas such as high aspect ratio through holes, blind holes, and grooves on the workpiece.

[0040] In some specific embodiments, the pre-plating stage includes at least one pre-plating DC current cycle, and a pre-plating pulse current cycle executed after the pre-plating DC current cycle. In this embodiment, a composite current control mode can be used for current control in the pre-plating stage. Specifically, the pre-plating DC current is first used for current control for a seventh duration until the seventh duration expires, and then the current control is switched to the pre-plating pulse current for current control for an eighth duration until the eighth duration expires, at which point the current control of the pre-plating stage ends. The sum of the seventh and eighth durations equals the duration of the pre-plating stage.

[0041] When using a pre-plating DC current for current control, the pre-plating DC current is specifically a small current with a constant value. When using a pre-plating pulse current for current control, the control is specifically performed according to preset parameters such as the ratio of forward and reverse current duration, the ratio of forward and reverse current waveform amplitude, the forward current duty cycle, and the reverse current duty cycle. It should be noted that this pre-plating DC current can directly generate a uniform and thin initial plating layer in vias without copper (i.e., without a seed layer). In other words, the electroplating control method of this application embodiment does not rely on traditional seed layer formation processes such as chemical plating (chemical copper deposition), physical vapor deposition (sputtering), or flash plating (rapid pre-plating), and can achieve the establishment of an initial conductive layer in vias of bare substrates. This not only simplifies the process flow but also avoids problems such as insufficient interfacial adhesion and poor thickness uniformity that may be introduced by seed layer processes.

[0042] Furthermore, the method in this application embodiment does not exclude the application of the plating on top of an existing chemical plating layer, sputtering seed layer, flash plating layer, or other initial conductive layer. In some alternative embodiments, the following can be flexibly selected based on factors such as the specific type of circuit board, via aspect ratio, target plating performance requirements, and existing production line configuration: (1) applying a pre-plating DC current directly to bare vias without a seed layer to form an initial plating layer; (2) applying a pre-plating DC current to an existing chemically plated copper layer to enhance interfacial adhesion and improve plating uniformity; (3) applying a pre-plating DC current to a sputtering seed layer to fill any microscopic defects that may exist in the sputtered layer; (4) applying a pre-plating DC current to a flash plating pre-plating layer to further level and improve density. The above flexible selection methods make the electroplating control method of this application widely compatible with production lines and adaptable to processes.

[0043] For example, in one specific implementation, the pre-plating stage duration can be configured to account for 25% of the total electroplating time. The pre-plating stage duration is divided into a seventh duration and an eighth duration. The seventh duration accounts for 10% of the pre-plating stage duration, and during this seventh duration, a pre-plating DC current is used for current control. The eighth duration accounts for 90% of the pre-plating stage duration, and during this eighth duration, a pre-plating pulse current is used for current control. Within this eighth duration, the forward current duration of the pre-plating pulse current accounts for 99%, and the reverse current duration accounts for 1%. The ratio of the waveform amplitude of the forward current to the waveform amplitude of the reverse current is 1:3, the forward current duty cycle is 5%-10%, and the reverse current duty cycle is 35%-40%. In this embodiment, the deep plating DC current density used in the deep plating stage is greater than the pre-plating DC current density used in the pre-plating stage. The deep plating pulse peak current density used in the deep plating stage is greater than the pre-plating pulse peak current density used in the pre-plating stage.

[0044] This allows for the formation of a thin (micrometer or submicrometer level), complete, uniform, and dense initial plating layer on the walls of vias in circuit boards. This initial plating layer serves a dual purpose in subsequent deep plating stages: acting as a uniform conductive substrate and a grain nucleation template. It avoids the "dog bone effect" caused by preferential deposition at the via opening from the source, providing crucial process assurance for the deep plating capability of high aspect ratio vias.

[0045] S13: In the deep plating stage of the electroplating process, electroplating control is performed using the electroplating parameters corresponding to the deep plating stage, so as to generate a reinforced plating layer based on the initial plating layer.

[0046] In this embodiment, the electroplating time of the circuit board can be monitored to determine whether the electroplating process has entered the deep plating stage. The end time of the pre-plating stage is the time when the deep plating stage begins. During the deep plating stage, electroplating control can be achieved by using the corresponding electroplating parameters to generate a reinforced plating layer based on the initial plating layer. Specifically, the process of generating the reinforced plating layer involves using the electroplating parameters corresponding to the deep plating stage to enhance ion deposition at the center of high aspect ratio holes during electroplating. The high peak value and short conduction characteristics of the pulsed current are utilized to break the diffusion boundary layer within the holes. Through multiple forward and then reverse pulsed current cycles, a dense and smooth plating layer meeting the preset thickness requirements is generated. Generating a reinforced plating layer through the deep plating stage can solve the problems of ion scarcity and excessively thin plating layers at the center of high aspect ratio holes on the circuit board.

[0047] In some specific embodiments, the deep plating stage may include a first sub-stage and a second sub-stage. The first sub-stage specifically employs a first pulse waveform for electroplating control to rapidly deposit and thicken the plating layer on top of the initial layer, forming a first reinforced plating layer. The second sub-stage specifically employs a second pulse waveform for electroplating control to selectively dissolve the first reinforced plating layer, making the plating thickness at the orifice and the plating thickness at the center of the orifice tend to be balanced, forming a second reinforced plating layer.

[0048] In this embodiment, by controlling the electroplating in the first sub-stage, positive ions (such as copper ions) can be forced to migrate and deposit into the low electric field region within the hole using a pulsed peak current. A short-duration reverse pulse current widens the ion transport channels within the hole, while simultaneously pausing high-current deposition to allow time for ion replenishment and eliminate concentration polarization. Although the first sub-stage achieves rapid deposition and thickness increase through high current density, atoms do not have sufficient time to diffuse to the lowest energy lattice positions on the surface. This can easily lead to problems such as high vacancy concentration and high grain boundary ratio in the coating. Furthermore, while adding organic additives such as brighteners, inhibitors, and leveling agents during the electroplating process can increase the deposition amount to some extent under high current density, it can also cause localized stress concentration, and the pulse can also induce cyclic stress in the coating. To address the aforementioned issues, this embodiment utilizes a second sub-stage electroplating control to continuously and rapidly form a coating layer on top of the first enhanced coating layer. This second sub-stage allows for selective dissolution of the coating layer at protruding locations such as orifices and plate surfaces, forming newly deposited atoms on the surface. The newly deposited atoms are then driven by an electric field to diffuse and enhance their diffusion on the surface, filling vacancies and causing dislocations to annihilate. This achieves the goal of adjusting surface grain boundaries and making grains equiaxed, which helps to level the coating layer, reduce coating stress, and further ensure the density of the coating layer.

[0049] Furthermore, from the perspective of the action window of plating solution additives, the first and second sub-stages mentioned above have a clear temporal division of labor in terms of additive synergy. Specifically, the first sub-stage is the main action window of the accelerator (also known as brightener). Under the high-peak positive pulse current applied in the first sub-stage, the accelerator preferentially adsorbs in high current density areas within the hole (such as the hole opening and hole wall protrusions), reducing the local deposition overpotential through its catalytic effect and promoting the rapid reduction and deposition of copper ions in this area, thereby achieving the rapid thickness increase target required in the deep plating stage. At the same time, the short conduction characteristics of the pulse current in this stage are conducive to the gradient distribution of the accelerator along the depth direction within the hole, avoiding excessive concentration at the hole opening. The second sub-stage is the main action window of the suppressor (also known as carrier) and leveler. Under the enhanced reverse pulse current applied in the second sub-stage, the adsorption of the inhibitor at the orifice and the high-potential region of the plate surface is enhanced, effectively inhibiting further deposition in these areas. Simultaneously, the leveling agent selectively adsorbs onto microscopic protrusions, synergizing with the selective dissolution effect of the reverse pulse to directionally reduce the protruding coating. The continuous activation of the accelerator in the low-potential region within the orifice (such as the orifice center) and the selective inhibition of the inhibitor / leveling agent in the high-potential region at the orifice form a complementary gradient, effectively controlling the deposition rate difference between the orifice and the orifice center, ultimately achieving uniform coating thickness and improved surface smoothness. It should be noted that the above description of the additive's mechanism of action is merely illustrative; the electroplating control method of this application is also applicable to other types of electroplating additive systems, and is not limited to specific additive chemical compositions.

[0050] In some specific embodiments, the waveform amplitude and duration of the reverse current in the second pulse waveform are greater than the waveform amplitude and duration of the reverse current in the first pulse waveform. Specifically, the first pulse waveform includes at least one first reverse pulse, and the second pulse waveform includes at least one second reverse pulse, wherein the reverse peak current density of the second reverse pulse is greater than the reverse peak current density of the first reverse pulse, and / or, the reverse current application duration of the second reverse pulse is greater than the reverse current application duration of the first reverse pulse. In this embodiment, the deep plating stage may include at least one deep plating DC current cycle, executed in a preset order with the first sub-stage and the second sub-stage. Specifically, the duration of the second sub-stage may be configured to be twice the duration of the first sub-stage. For example, the duration of the deep plating stage may be configured to account for 72% of the total electroplating time, and the deep plating stage may be configured with three deep plating DC current cycles of equal duration, with the duration of the first sub-stage plus one deep plating DC current cycle accounting for 1 / 3 of the deep plating stage duration, and the duration of the second sub-stage plus two deep plating DC current cycles accounting for 2 / 3 of the deep plating stage duration. During the deep plating stage, current control can be initiated by first using a first DC current for a first duration until that duration expires. Then, the current is controlled using a first pulse waveform for a second duration until that duration expires, ending the first sub-stage of current control. The first duration is the length of one deep plating DC current cycle, and the second duration is the duration of the first sub-stage. For example, the first duration accounts for 0.5% of the total deep plating stage duration (1 / 3), and the second duration accounts for 99.5% of the total deep plating stage duration (1 / 3). After the first sub-stage ends, current control is initiated by a second DC current for a third duration until that duration expires. Then, the current is controlled using a second pulse waveform for a fourth duration until that duration expires. This is repeated for a fifth duration until that duration expires, and finally, the current is controlled using a second pulse waveform for a sixth duration until that duration expires, ending the second sub-stage of current control. It should be noted that the third duration is the duration of one deep plating DC current cycle, the fourth duration is half the duration of the second sub-stage, the fifth duration is the duration of one deep plating DC current cycle, and the sixth duration is half the duration of the second sub-stage. The third and fifth durations each account for 0.5% of the 1 / 3 deep plating stage duration, and the fourth and sixth durations each account for 99.5% of the 1 / 3 deep plating stage duration. The first and second DC currents can be set to be the same magnitude. In this embodiment, the second sub-stage is divided into two micro-circulation segments of equal duration, with each micro-circulation segment having the same duration as the first sub-stage. In the second sub-stage, the two repeated micro-circulation segments further ensure the density of the enhanced plating layer. By utilizing the increased directional pulse peak value and duration, selective dissolution of the plating layer at the orifice and protrusions on the board surface is achieved, which helps to level the board surface.Based on this embodiment, the repeated micro-circulation segment realizes multiple micro-circulations and the application of multi-level reverse current, which can continuously optimize the electric field distribution, ensure that the coating produced in each stage remains dense, and effectively improve the deep plating capability.

[0051] In some specific embodiments, the deep plating stage can be configured with only a short deep plating DC current cycle (e.g., 15 seconds). By setting this deep plating DC current cycle before the first sub-stage, pre-polarization can be achieved through DC current control, so that the pulse current of the subsequent first and second sub-stages can directly enter steady-state deposition from the first pulse, providing a stable deposition rate.

[0052] In some specific embodiments, the deep plating stage can be configured with only one long deep plating DC current cycle. This deep plating DC current cycle is set after the first sub-stage and before the second sub-stage. DC control after the first sub-stage and before the second sub-stage can homogenize the surface state of the hole wall and maintain a uniform deposition substrate. Moreover, by adjusting the duration ratio of the deep plating DC current cycle, the ratio of the overall net deposition rate to the selective dissolution rate of the deep plating stage can be precisely controlled.

[0053] In one specific embodiment, the ratio of the forward to reverse amplitude of the second pulse waveform is greater than the ratio of the forward to reverse amplitude of the first pulse waveform. For example, in this embodiment, the ratio of the waveform amplitude of the forward current to the waveform amplitude of the reverse current of the first pulse waveform can be configured as 1:3, and the ratio of the waveform amplitude of the forward current to the waveform amplitude of the reverse current of the second pulse waveform can be configured as 1:5.

[0054] In one specific embodiment, the first pulse waveform further includes at least one first positive pulse, and the second pulse waveform further includes at least one second positive pulse. The duty cycle of each of the first and second positive pulses during its positive period is greater than the duty cycle of any reverse pulse during its reverse period, and the duty cycle of the second reverse pulse during its reverse period is greater than the duty cycle of the first reverse pulse during its reverse period. For example, in this embodiment, the positive current duty cycle in the first pulse waveform can be configured to 5%-10%, and the reverse current duty cycle can be configured to 35%-40%. The positive current duty cycle in the second pulse waveform can be configured to 3%-5%, and the reverse current duty cycle can be configured to 50%-60%, thereby increasing the waveform amplitude and duration of the reverse current in the second sub-stage.

[0055] Therefore, the embodiments of this application achieve efficient ion transport and uniform deposition along the depth direction in through-holes with high aspect ratios (e.g., 50:1 and above). The rapid deposition in the first sub-stage and the selective dissolution in the second sub-stage form a "deposition-leveling" micro-cycle, which enables the coating thickness in the center region of the hole to effectively catch up with the hole opening region. The resulting reinforced coating has both a main structure that meets the preset thickness and a uniform and dense microstructure, significantly improving the deep plating capability and coating uniformity.

[0056] S14: In the densification stage of the electroplating process, electroplating control is performed using the electroplating parameters corresponding to the densification stage, so as to generate a dense coating based on the enhanced coating.

[0057] In this embodiment, the plating time of the circuit board can be monitored to determine whether the plating process has entered the densification stage. The end time of the deep plating stage is the time when the densification stage begins. During the densification stage, plating parameters corresponding to this stage can be used for plating control, achieving the generation of a dense plating layer based on a reinforced plating layer. Specifically, the process of generating a dense plating layer involves eliminating internal stress in the reinforced plating layer, refining grains, improving the density and ductility of the plating layer, reducing porosity, and leveling the plating layer based on the plating parameters corresponding to the densification stage. This ultimately generates a plating layer that meets the preset density requirements. Generating a dense plating layer through the densification stage solves the problems of high plating brittleness and easy cracking inherent in traditional plating processes.

[0058] As can be seen from the above, the electroplating control method provided in this application divides the electroplating process of the circuit board into a pre-plating stage, a deep plating stage, and a densification stage according to the total electroplating time, and configures corresponding electroplating parameters for each stage. By controlling the electroplating according to different electroplating parameters at different stages, an initial plating layer with low thickness, good uniformity, and high density is first formed on the hole walls and board surface of the circuit board. Then, the plating thickness is increased on the basis of the initial plating layer to generate a dense and flat reinforced plating layer that meets the preset thickness requirements. Finally, the internal stress of the plating layer is eliminated on the basis of the reinforced plating layer to generate a dense plating layer that meets the preset density requirements. Based on the above method, the problem that existing electroplating technologies cannot meet the requirements of plating uniformity, density, and reliability under high aspect ratio conditions can be solved.

[0059] In some embodiments of this application, the densification stage includes at least one densification DC current cycle. This densification DC current cycle uses a relatively small DC current, allowing the coating to crystallize slowly at a low current density. This enables atomic rearrangement at an extremely low deposition rate, giving newly deposited atoms sufficient time to reach the lowest energy level on the surface. Existing vacancies in the surface layer can be filled by subsequent atoms, reducing the probability of vacancy formation in newly deposited atoms, fully releasing internal stress, achieving grain refinement and densification of the coating, eliminating residual internal stress generated in the deep plating stage, improving density, and simultaneously ensuring the smoothness and mechanical reliability of the coating. This effectively solves the problems of high brittleness and easy cracking in traditional coating processes. In this embodiment, the deep plating DC current density used in the deep plating stage is greater than the densification DC current density used in the densification stage.

[0060] Therefore, this embodiment achieves sufficient surface diffusion and lattice relaxation of coating atoms at an extremely low deposition rate. Residual internal stress generated during the deep plating stage is effectively released, and the coating grains transform from columnar or fibrous to an equiaxed fine-grained structure, significantly reducing porosity and improving ductility and tensile strength. The resulting dense coating combines high density, low internal stress, and excellent mechanical reliability, meeting the stringent requirements of high-end circuit boards for the comprehensive performance of the coating.

[0061] In some embodiments of this application, during the pre-plating stage, a transitional flow mode can be used to control the fluid flow state. Specifically, during the pre-plating stage, the Reynolds number can be configured to 2000-3500, and fluid flow control can be performed according to the pre-plating jet velocity. A weak flow field is achieved through low disturbance, thereby suppressing turbulence development and balancing the ion concentration distribution on the circuit board surface and at the orifice. During the deep plating stage, a turbulent flow mode can be used to control the fluid flow state. Specifically, during the deep plating stage, the Reynolds number can be configured to 8000-12000, and fluid flow control can be performed according to the deep plating jet velocity. High disturbance ensures the fluid is in a fully turbulent state, such as a high-pressure counter-current / mixed / vortex state, to disrupt the diffusion boundary layer within the orifice and promote ion replenishment in the orifice center region, rapidly removing dissolved products and preventing redeposition. During the densification stage, a laminar flow mode can be used to control the fluid flow state. Specifically, during the densification stage, the Reynolds number can be configured to 1000-2000, and fluid flow control can be performed according to the densification jet velocity. This, combined with a small DC current, forms a stable flow field with low pressure and low velocity, creating a undisturbed crystallization environment. In this embodiment, the deep plating jet velocity is greater than the pre-plating jet velocity, and the pre-plating jet velocity is greater than the densification jet velocity.

[0062] In some embodiments of this application, the motion field parameters may include, but are not limited to, the vibration parameters of the cathode, which can be configured differently according to each stage. In the pre-plating stage, a first motion control mode can be used for motion control. Specifically, the first motion control mode can be configured to control the cathode to vibrate at a first vibration frequency, and to control the first vibration frequency to be synchronized with the pre-plating pulse current cycle, so as to suppress preferential deposition in the orifice region. Alternatively, the cathode can be controlled to reciprocate in the plating tank at a first moving speed. Thus, through the weak coupling synergy of the electric field and the flow field, combined with low-frequency, small-amplitude motion control of the motion field, the preferential deposition phenomenon in the orifice region can be effectively suppressed, preventing premature thickening of the orifice from the source and solving the core problem of uneven crystallization in the initial stage of traditional processes. In the deep plating stage, a second motion control mode can be used for motion control. Specifically, the second motion control mode can be configured to control the cathode to vibrate at a second vibration frequency, wherein the second vibration frequency is greater than the first vibration frequency, using high-frequency vibration to promote ion transport. Furthermore, the vibration direction can be controlled to form a first angle with the jet direction, thereby enhancing the vortex effect of the fluid. For example, the first angle can be 45°. Therefore, by utilizing a large DC current and a large pulse current in conjunction with a strongly disturbed flow field, a strong coupling and synergistic effect between the electric field and the flow field is achieved. Simultaneously, combined with high-frequency, large-amplitude motion control of the motion field, a closed loop can be formed to replenish ions during deposition and rapidly remove products during dissolution, effectively solving the problems of ion scarcity at the center of high aspect ratio holes and excessively thin coatings. During the densification stage, a third motion control mode can be used for motion control. Specifically, the third motion control mode can be configured to control the cathode to stop vibrating or to perform micro-vibration at a third vibration frequency, where the third vibration frequency is lower than the first vibration frequency, to avoid the impact of disturbance on the smoothness of the coating crystallization. Therefore, by using a low-pressure, low-velocity steady flow field formed by a small DC current and laminar flow mode, combined with motion control that stops vibration or maintains low-frequency micro-amplitude vibration, it is possible to avoid strong disturbances that could damage the smoothness of the coating crystallization, eliminate flow field fluctuations, and allow the coating to crystallize slowly at low current density, fully releasing internal stress, achieving finer and denser coating grains, eliminating residual internal stress generated during the deep plating stage, improving density, and simultaneously taking into account the smoothness and mechanical reliability of the coating, effectively solving the problems of high brittleness and easy cracking of coatings in traditional processes. In one specific implementation, the low-pressure, low-velocity steady flow field can also be achieved by adjusting the angle between the jet and the circuit board surface to 15°~30° in laminar flow mode.

[0063] It is understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0064] In some embodiments of this application, please refer to Figure 2, Figure 2 This is a basic structural block diagram of an electroplating control device provided in an embodiment of this application. In this embodiment, the device includes units used to perform the steps in the above-described method embodiments. Please refer to the relevant descriptions in the above-described method embodiments for details. For ease of explanation, only the parts relevant to this embodiment are shown. Figure 2 As shown, the electroplating control device includes a parameter configuration module 21 and an electroplating control module 22. The parameter configuration module 21 is used to divide the electroplating process of the circuit board into a pre-plating stage, a deep plating stage, and a densification stage according to the total electroplating time, and configure corresponding electroplating parameters for each stage. The electroplating control module 22 is used to control the electroplating process in the pre-plating stage using the electroplating parameters corresponding to the pre-plating stage to form an initial plating layer on the hole walls of the circuit board; in the deep plating stage, it uses the electroplating parameters corresponding to the deep plating stage to control the electroplating process to generate a reinforced plating layer based on the initial plating layer; and in the densification stage, it uses the electroplating parameters corresponding to the densification stage to control the electroplating process to generate a dense plating layer based on the reinforced plating layer.

[0065] It should be understood that the above-mentioned electroplating control device corresponds one-to-one with the above-mentioned electroplating control method, and will not be described again here.

[0066] In some embodiments of this application, a circuit board is also provided, which includes at least one through-hole. The sidewall of the through-hole includes an initial plating layer formed by any of the aforementioned electroplating control methods or devices, a reinforcing plating layer on the initial plating layer, and a dense plating layer on the reinforcing plating layer. In this embodiment, the initial plating layer is in a first thickness range, the reinforcing plating layer is in a second thickness range, and the second thickness range is greater than the first thickness range. The reinforcing plating layer is in a first density range, and the dense plating layer is in a second density range, and the second density range is greater than the first density range.

[0067] In some embodiments of this application, please refer to Figure 3 , Figure 3 This is a basic structural block diagram of an electronic device provided in an embodiment of this application. Figure 3 As shown, the electronic device 3 of this embodiment includes: a processor 31, a memory 32, and a computer program 33 stored in the memory 32 and executable on the processor 31, such as a program for an electroplating control method. When the processor 31 executes the computer program 33, it implements the steps in each embodiment of the above-described electroplating control method. Alternatively, when the processor 31 executes the computer program 33, it implements the functions of each module in the embodiment corresponding to the above-described electroplating control device. Please refer to the relevant descriptions in the embodiments for details, which will not be repeated here.

[0068] For example, the computer program 33 can be divided into one or more modules (units) for performing the various steps in the above method embodiments. The one or more modules are stored in the memory 32 and executed by the processor 31 to complete this application. The one or more modules can be a series of computer program instruction segments capable of performing specific functions, which describe the execution process of the computer program 33 in the electronic device 3.

[0069] The electronic device may include, but is not limited to, a processor 31 and a memory 32. Those skilled in the art will understand that... Figure 3 This is merely an example of electronic device 3 and does not constitute a limitation on electronic device 3. It may include more or fewer components than shown, or combine certain components, or different components. For example, the electronic device may also include input / output devices, network access devices, buses, etc.

[0070] The processor 31 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0071] The memory 32 can be an internal storage unit of the electronic device 3, such as a hard disk or memory. The memory 32 can also be an external storage device of the electronic device 3, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on the electronic device 3. Furthermore, the memory 32 can include both internal and external storage units of the electronic device 3. The memory 32 is used to store the computer program and other programs and data required by the electronic device. The memory 32 can also be used to temporarily store data that has been output or will be output.

[0072] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0073] This application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, can implement the steps in the various method embodiments described above. In this embodiment, the computer-readable storage medium can be either non-volatile or volatile.

[0074] This application provides a computer program product that, when run on a mobile terminal, enables the mobile terminal to implement the steps described in the various method embodiments.

[0075] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0076] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0077] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0078] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An electroplating control method, characterized in that, include: Based on the total electroplating time, the electroplating process of the circuit board is divided into a pre-plating stage, a deep plating stage, and a densification stage, and corresponding electroplating parameters are configured for each stage. In the pre-plating stage of the electroplating process, electroplating control is performed using the electroplating parameters corresponding to the pre-plating stage to form an initial plating layer on the hole wall of the circuit board. In the deep plating stage of the electroplating process, electroplating parameters corresponding to the deep plating stage are used for electroplating control in order to generate a reinforced plating layer based on the initial plating layer. During the densification stage of the electroplating process, electroplating parameters corresponding to the densification stage are used for electroplating control in order to generate a dense coating based on the enhanced coating.

2. The electroplating control method according to claim 1, characterized in that, The electroplating parameters include at least one of the following parameters: electric field parameters, flow field parameters, and motion field parameters.

3. The electroplating control method according to claim 1, characterized in that, The pre-plating stage includes at least one pre-plating DC current cycle, and a pre-plating pulse current cycle executed after the pre-plating DC current cycle.

4. The electroplating control method according to claim 1, characterized in that, The deep plating stage includes a first sub-stage and a second sub-stage; The first sub-stage includes electroplating control using a first pulse waveform to rapidly deposit and thicken the initial coating to form a first reinforced coating. The second sub-stage includes electroplating control using a second pulse waveform to selectively dissolve the first reinforced coating, so that the coating thickness at the orifice and the coating thickness at the center of the orifice tend to be balanced, thus forming a second reinforced coating.

5. The electroplating control method according to claim 4, characterized in that, The first pulse waveform includes at least one first reverse pulse; The second pulse waveform includes at least one second reverse pulse; Wherein, the reverse peak current density of the second reverse pulse is greater than the reverse peak current density of the first reverse pulse, and / or, the reverse current application duration of the second reverse pulse is greater than the reverse current application duration of the first reverse pulse.

6. The electroplating control method according to claim 5, characterized in that, The first pulse waveform includes at least one first positive pulse; The second pulse waveform includes at least one second positive pulse; Wherein, the duty cycle of the first positive pulse and the second positive pulse during their respective positive periods is greater than the duty cycle of any negative pulse during its negative periods; The duty cycle of the second reverse pulse during its reverse period is greater than the duty cycle of the first reverse pulse during its reverse period.

7. The electroplating control method according to claim 4, characterized in that, The deep plating stage also includes at least one deep plating DC current cycle, which is executed in a preset order with the first sub-stage and the second sub-stage. The compaction phase includes at least one compaction DC current cycle.

8. The electroplating control method according to claim 7, characterized in that, The pre-plating stage includes at least one pre-plating DC current cycle, and a pre-plating pulse current cycle executed after the pre-plating DC current cycle. The DC current density used in the deep plating stage is greater than the DC current density used in the pre-plating stage. The DC current density used in the deep plating stage is greater than the DC current density used in the dense plating stage. The peak current density of the deep plating pulse used in the deep plating stage is greater than the peak current density of the pre-plating pulse used in the pre-plating stage.

9. The electroplating control method according to claim 3 or 8, characterized in that, The motion field parameters include the vibration parameters of the cathode, which are configured differently according to each stage, wherein: In the pre-plating stage, the cathode is controlled to vibrate at a first vibration frequency, and the first vibration frequency is synchronized with the pre-plating pulse current period to suppress preferential deposition in the orifice region. In the deep plating stage, the cathode is controlled to vibrate at a second vibration frequency, wherein the second vibration frequency is greater than the first vibration frequency, to promote ion transport. During the densification stage, the cathode is controlled to stop vibrating or to vibrate slightly at a third vibration frequency, wherein the third vibration frequency is less than the first vibration frequency, so as to avoid the impact of disturbance on the smoothness of the coating crystallization.

10. The electroplating control method according to claim 4, characterized in that, The ratio of the forward and reverse amplitudes of the second pulse waveform is greater than the ratio of the forward and reverse amplitudes of the first pulse waveform.

11. The electroplating control method according to claim 1, characterized in that, Fluid flow control is achieved by using the deep plating jet velocity in the deep plating stage, the pre-plating jet velocity in the pre-plating stage, and the dense plating stage. Among them, the jet velocity of deep plating is greater than that of pre-plating, and the jet velocity of pre-plating is greater than that of dense plating.

12. The electroplating control method according to claim 1, characterized in that, The pre-plating stage accounts for 20% to 30% of the total electroplating time. The duration of the deep plating stage accounts for 65% to 80% of the total electroplating time; The duration of the densification stage accounts for 3% to 15% of the total electroplating time.

13. An electroplating control device, characterized in that, The device includes: The parameter configuration module is used to divide the electroplating process of the circuit board into a pre-plating stage, a deep plating stage, and a densification stage according to the total electroplating time, and to configure the corresponding electroplating parameters for each stage. An electroplating control module is used to control electroplating in the pre-plating stage of the electroplating process by using electroplating parameters corresponding to the pre-plating stage to form an initial plating layer on the hole walls of the circuit board; in the deep plating stage of the electroplating process by using electroplating parameters corresponding to the deep plating stage to generate a reinforced plating layer based on the initial plating layer; and in the densification stage of the electroplating process by using electroplating parameters corresponding to the densification stage to generate a dense plating layer based on the reinforced plating layer.

14. A circuit board, characterized in that, The circuit board includes: At least one through hole, the sidewall of which includes an initial plating layer formed by the electroplating control method as described in any one of claims 1-12, a strengthening plating layer on the initial plating layer, and a dense plating layer on the strengthening plating layer; The initial coating is within a first thickness range, and the strengthening coating is within a second thickness range, wherein the second thickness range is greater than the first thickness range; The reinforced coating is in a first density range, and the dense coating is in a second density range, the second density range being greater than the first density range.

15. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method as described in any one of claims 1-12.

16. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method as described in any one of claims 1-12.

17. A computer program product, when run on an electronic device, causes the electronic device to perform the steps of the method as described in any one of claims 1-12.

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