Method and system for detecting anomalies of a thimble

Abstract

The present application provides a method and system for detecting abnormality of a probe. The method comprises: providing a wafer, adsorbing the wafer by a chuck; repeatedly performing a simulation probe operation on the wafer by using a probe; measuring a probe mark on the wafer after performing the simulation probe operation; and judging whether the probe is abnormal according to the position distribution of the probe mark. The present application can timely find abnormality of the probe by repeatedly performing the simulation probe operation and measuring the distribution of the mark, overcomes the hysteresis problem of the prior art relying on feedback of a downstream photolithography process, avoids generation of a large number of pattern distortion wafers, reduces scrap cost and improves process yield.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit manufacturing, and in particular to a method and system for detecting pin malfunctions. Background Technology

[0002] In wafer bonding processes, pins are typically used to apply mechanical force to the wafers to trigger the diffusion of bonding waves, thereby bonding the two wafers together. If the pins malfunction (such as being off-center or having unstable force), it can lead to abnormal bonding wave diffusion, resulting in pattern distortion after wafer bonding.

[0003] Currently, monitoring of ejector pin anomalies mainly relies on delayed detection in downstream processes. Specifically, the production line typically needs to wait for the wafer to move to the photolithography station. Only after detecting an asymmetrical abnormal morphology in the Litho OVLmap can the anomaly information be fed back to the bonding process to troubleshoot ejector pin problems.

[0004] The aforementioned detection methods, which rely on downstream feedback, suffer from significant latency. Due to the long process cycle, the bonding equipment continues to run until an anomaly is detected and the machine is shut down, resulting in a large number of wafers with pattern distortion, causing severe yield losses and high scrap costs.

[0005] Therefore, the industry urgently needs a method to detect pin malfunctions in a timely manner in order to prevent large-scale wafer scrapping incidents. Summary of the Invention

[0006] In view of the technical problem that the existing technology relies on the downstream photolithography process to detect abnormalities in wafer bonding pins, resulting in a large number of wafers with pattern distortion, causing serious yield loss and high scrap costs, the purpose of this invention is to provide a method and system for detecting abnormal bonding wave diffusion in wafer bonding caused by pin abnormalities.

[0007] This invention provides a method for detecting pin abnormalities, comprising:

[0008] Step 1: Provide a wafer and use a chuck to pick up the wafer;

[0009] Step 2: Repeat the simulated ejector pin operation on the wafer using ejector pins;

[0010] Step 3: Measure the pin marks on the wafer after performing the simulated pin operation;

[0011] Step 4: Determine whether the ejector pin is abnormal based on the location and distribution of the ejector pin marks.

[0012] Preferably, in step one, the chuck includes a top chuck or a bottom chuck.

[0013] Preferably, in step two, the simulated pin operation is repeated 10 to 50 times on the wafer using the pin.

[0014] Preferably, in step four, determining whether the pin is abnormal based on the positional distribution of the pin marks includes: determining whether all the pin marks are located within a preset central area.

[0015] Preferably, in step four, if all the pin marks are located within the preset central area, the pin is determined to be normal; if there are pin marks located outside the preset central area, the pin is determined to be abnormal.

[0016] Preferably, in step four, determining that the ejector pin is abnormal is used to indicate the risk of abnormal bonding wave diffusion during the wafer bonding process.

[0017] Preferably, the abnormal diffusion of the bonding wave will cause the lithography overlay error distribution map obtained in the subsequent lithography process to exhibit an asymmetrical morphology.

[0018] This invention provides a system for detecting pin malfunctions, comprising:

[0019] The adsorption module is used to adsorb wafers using a chuck;

[0020] The simulation module is used to repeatedly perform simulated pin operations on the wafer using pins;

[0021] The measurement module is used to measure the pin marks on the wafer after the simulated pin operation is performed;

[0022] The judgment module is used to determine whether there is any abnormality in the ejector pin based on the positional distribution of the ejector pin imprint.

[0023] Preferably, the chuck includes a top chuck or a bottom chuck.

[0024] Preferably, the judgment module includes: a region comparison unit, used to determine whether all the pin marks are located within a preset central region; and a logic judgment unit, used to determine that the pin is normal when all the pin marks are located within the preset central region; and to determine that the pin is abnormal when there are pin marks located outside the preset central region.

[0025] As described above, the method and system for detecting pin abnormalities of the present invention have the following beneficial effects:

[0026] This invention directly detects the status of the ejector pins during the bonding process, replacing the delayed feedback mechanism that typically requires the wafer to reach the photolithography stage before notifying the bonding station. By repeatedly simulating ejector pin operations and measuring the imprint distribution, abnormalities such as positional deviations or inconsistencies in the force applied by the ejector pin mechanism can be detected in a timely manner. This monitoring method avoids the generation of a large number of wafers with abnormal patterns due to continuous operation of intermediate equipment, preventing large-scale wafer scrap events, thereby reducing the production cost of the semiconductor manufacturing process and improving the overall process yield. Attached Figure Description

[0027] Figure 1 The diagram shown is a flowchart illustrating the method for detecting pin abnormalities according to the present invention.

[0028] Figure 2 The diagram shows the module structure of the system for detecting pin malfunctions according to the present invention.

[0029] Figure 3 The diagram shows a cross-sectional structure of the simulated ejector pin operation of the present invention;

[0030] Figure 4 The diagram shown is a top view of the distribution of ejector pin marks when the ejector pin is in normal operation according to the present invention.

[0031] Figure 5 The diagram shows a cross-sectional structure of another simulated ejector pin operation according to the present invention;

[0032] Figure 6 The diagram shown is a top view of the distribution of ejector pin marks when the ejector pin malfunctions according to the present invention. Detailed Implementation

[0033] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0034] Figure 1 This is a flowchart illustrating a method for detecting pin anomalies in one embodiment. The method for detecting pin anomalies includes:

[0035] Step 1: Provide wafer 102 and use a chuck to pick up wafer 102.

[0036] In some embodiments, in step one, the chuck includes a top chuck 101 or a bottom chuck.

[0037] Wafer 102 may include a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The active layer and bulk semiconductor typically comprise the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0038] Wafer 102 can contain various integrated circuit devices, such as complementary metal-oxide-semiconductor transistors, planar field-effect transistors, image sensors, or memory devices. The actuator can be an automated wafer handling system or a robotic arm, which transfers wafer 102 and places it on a chuck. The chuck is typically integrated into the process chamber of the wafer bonding equipment. The chuck can be of various types, including a vacuum chuck, an electrostatic chuck, or a mechanical chuck. A vacuum chuck achieves adsorption by creating a localized negative pressure region between the adsorption surface and the back of wafer 102. It has a simple structure and low cost, and is suitable for atmospheric pressure or low vacuum process environments. An electrostatic chuck, on the other hand, fixes wafer 102 by applying voltage to generate a Coulomb force on the dielectric layer. It can provide uniform and stable adsorption force in high vacuum environments while avoiding wafer edge stress damage or particle contamination that may occur with mechanical clamping.

[0039] In wafer bonding processes, chucks serve a dual purpose: fixing the substrate and controlling deformation. (Combined with...) Figure 3 and Figure 5 As shown, specifically, wafer bonding equipment typically includes a pair of opposing top chucks 101 and bottom chucks. The bottom chuck is primarily used to support and level the underlying substrate wafer, providing a solid support base. The top chuck 101 floats above the bottom chuck and is used to attract the upper wafer 102 from its back side, preparing it for alignment with its front side facing down. Taking the top chuck as an example, the top chuck 101 needs to work in conjunction with the ejector pin 103. The central area of ​​the top chuck 101 typically has a channel or opening allowing the ejector pin 103 to pass through. When the top chuck 101 maintains its attraction to the wafer 102 at the edge area, the ejector pin 103 extends downward from the center of the top chuck 101 and applies a mechanical thrust. By firmly securing the wafer 102 with the chucks, accidental slippage or deflection of the wafer 102 during simulation operations can be prevented, ensuring high accuracy of subsequently collected data.

[0040] Step 2: Repeat the simulated ejector pin operation on wafer 102 using ejector pin 103.

[0041] In some embodiments, in step two, the simulated ejector pin operation is repeatedly performed on the wafer 102 using the ejector pin 103 10 to 50 times. Figure 3 and Figure 5 As shown, the ejector pin 103 moves downward through the central opening of the top chuck 101. The ejector pin 103 can be a mechanical ejector pin used to trigger bonding waves in the silicon direct bonding process. The material of the ejector pin 103 can include stainless steel, ceramic, quartz, or a polymer with high hardness and wear resistance. The simulated ejector pin operation is driven by the equipment control system to execute the ejector pin mechanism, controlling the ejector pin 103 to contact the surface of the wafer 102 with a predetermined mechanical force and speed. By repeatedly simulating the ejector pin action, hidden defects such as mechanical fatigue, position drift, or uneven force application that may exist in the ejector pin mechanism during long-term operation can be effectively exposed, making it easier to capture abnormalities during the measurement stage and improving the sensitivity of process monitoring.

[0042] Step 3: Measure the pin marks on wafer 102 after performing the simulated pin operation.

[0043] Measurement operations can be performed by optical inspection equipment or defect review machines integrated into the production line. Such equipment can include bright-field microscopes, dark-field microscopes, scanning electron microscopes, or laser scattering-based measurement tools. When the probe 103 contacts the wafer 102, it leaves minute physical indentations, localized stress variation zones, or surface morphology changes at the contact point; these microscopic changes are collectively referred to as probe imprints. High-resolution optical systems are used to capture the coordinate data of these probe imprints, obtaining the position of each probe imprint in the wafer coordinate system.

[0044] Step 4: Determine whether there is any abnormality in the thimble 103 based on the location and distribution of the thimble imprints.

[0045] In some embodiments, step four, determining whether there is an abnormality in the ejector pin 103 based on the positional distribution of the ejector pin marks, includes determining whether all the ejector pin marks are located within a preset central area.

[0046] Figure 4 and Figure 6 This is a top-view structural diagram of the distribution of thimble markings. (Combined with...) Figure 4 and Figure 6 As shown, in some embodiments, the preset center region is a circular region with a diameter of 1 mm centered on the center of wafer 102. The center coordinates of wafer 102 are precisely calculated by a measurement device or wafer alignment system based on the wafer edge profile and alignment marks.

[0047] In some embodiments, in step four, if all pin marks are located within the preset central area, the pin 103 is determined to be normal; if there are pin marks located outside the preset central area, the pin 103 is determined to be abnormal.

[0048] The decision-making process can be executed by the processor of the process monitoring system or a controller with logical judgment function.

[0049] Combination Figure 4 As shown, when all the pin marks fall within the preset center area, the marks in the figure are highly overlapping and concentrated in the center, indicating that the position of the pin mechanism applying force each time is consistent and well aligned, without mechanical loosening or positioning deviation, and the pin 103 is judged to be normal.

[0050] Combination Figure 6 As shown, once a pin mark is found that deviates from the preset center area, multiple scattered mark points are shown in the figure, indicating that the position of the pin 103 is significantly different each time it is applied or has deviated from the center, indicating that the pin 103 has malfunctioned.

[0051] In some embodiments, in step four, determining that the ejector pin 103 is abnormal is used to indicate the risk of abnormal bonding wave diffusion during the wafer bonding process.

[0052] In some embodiments, abnormal bonding wave diffusion can cause the lithography overlay error distribution map obtained in subsequent lithography processes to exhibit an asymmetrical morphology.

[0053] In wafer bonding during semiconductor manufacturing, a normal bonding wave diffuses uniformly outward, resulting in a concentric circle distribution of photolithography overlay errors centered on the wafer center. However, when the ejector pin 103 malfunctions, the force applied by the ejector pin 103 is not always at the wafer center, or the application position varies each time. This causes the bonding wave diffusion to lose its uniformity, leading to non-concentric circle distortions in the die pattern after wafer bonding, or inconsistent distortion distributions each time. This monitoring method directly and independently detects the ejector pin status during the bonding process, replacing the delayed feedback mechanism that typically only notifies the bonding station after the wafer reaches the photolithography stage. This allows for timely detection of ejector pin malfunctions, preventing the generation of a large number of abnormal wafers with pattern distortions, reducing wafer scrap, lowering semiconductor manufacturing costs, and improving overall process yield.

[0054] Figure 2 This is a block diagram of the module structure of a system for detecting pin abnormalities in one embodiment.

[0055] A system for detecting pin anomalies includes:

[0056] Adsorption module, used to adsorb wafer 102 using a chuck.

[0057] In some embodiments, the chuck includes a top chuck 101 or a bottom chuck. The adsorption module can correspond to a base assembly or wafer stage within the bonding equipment chamber. The top chuck 101 can be mounted on the top of the chamber for adsorbing the wafer 102 prepared for downward bonding; the bottom chuck can be mounted on the bottom of the chamber for supporting the substrate wafer. Specifically, the chuck can be an electrostatic chuck or a vacuum chuck as described above, and can also be combined with internal thermal control components to regulate the wafer temperature.

[0058] The simulation module is used to repeatedly perform simulated pin operations on wafer 102 using pin 103.

[0059] The simulation module may include hardware components such as a robotic arm with ejector pins, servo motors, and pneumatic actuators. A programmable logic controller (PLC) sends control commands to the hardware to control the ejector pin 103 to continuously touch the wafer 102.

[0060] The measurement module is used to measure the pin marks on wafer 102 after performing a simulated pin operation.

[0061] The measurement module may include an optical image sensor, a light source emitter, and image signal processing circuitry. A high-resolution optical sensor scans the wafer surface to extract the edge features and coordinate data of the pin markings.

[0062] The judgment module is used to determine whether there is an abnormality in the ejector pin 103 based on the positional distribution of the ejector pin marks.

[0063] In some embodiments, the judgment module includes: a region comparison unit, used to determine whether all pin marks are located within a preset central region; and a logic judgment unit, used to determine that the pin 103 is normal when all pin marks are located within the preset central region; and to determine that the pin 103 is abnormal when there are pin marks located outside the preset central region.

[0064] The judgment module, area comparison unit, and logic judgment unit can be implemented using a microprocessor, application-specific integrated circuit (ASIC), or field-programmable gate array (FPGA). The control unit integrates a coordinate comparison algorithm that mathematically compares the received imprint coordinates with the preset area boundaries. Through hardware-level logic operations, the system can trigger equipment alarms or shutdown commands upon detecting an anomaly, preventing the continuation of non-conforming processes.

[0065] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0066] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for detecting pin abnormalities, characterized in that, At least including: Step 1: Provide a wafer and use a chuck to pick up the wafer; Step 2: Repeat the simulated ejector pin operation on the wafer using ejector pins; Step 3: Measure the pin marks on the wafer after performing the simulated pin operation; Step 4: Determine whether the ejector pin is abnormal based on the location and distribution of the ejector pin marks.

2. The method for detecting pin abnormalities according to claim 1, characterized in that: In step one, the chuck includes a top chuck or a bottom chuck.

3. The method for detecting pin abnormalities according to claim 1, characterized in that: In step two, the simulated pin operation is repeated 10 to 50 times on the wafer using the pin.

4. The method for detecting pin abnormalities according to claim 1, characterized in that: In step four, determining whether the pin is abnormal based on the positional distribution of the pin marks includes: determining whether all the pin marks are located within a preset central area.

5. The method for detecting pin abnormalities according to claim 4, characterized in that: In step four, if all the pin marks are located within the preset center area, the pin is determined to be normal; if there are pin marks located outside the preset center area, the pin is determined to be abnormal.

6. The method for detecting pin abnormalities according to claim 5, characterized in that: In step four, determining that the ejector pin is abnormal is used to indicate the risk of abnormal bonding wave diffusion during the wafer bonding process.

7. The method for detecting pin abnormalities according to claim 6, characterized in that: The abnormal diffusion of the bonding wave will cause the lithography overlay error distribution map obtained in the subsequent lithography process to exhibit an asymmetrical morphology.

8. A system for detecting pin malfunctions, characterized in that, include: The adsorption module is used to adsorb wafers using a chuck; The simulation module is used to repeatedly perform simulated pin operations on the wafer using pins; The measurement module is used to measure the pin marks on the wafer after the simulated pin operation is performed; The judgment module is used to determine whether there is any abnormality in the ejector pin based on the positional distribution of the ejector pin imprint.

9. The method for detecting pin abnormalities according to claim 8, characterized in that: The chuck may be a top chuck or a bottom chuck.

10. The method for detecting pin abnormalities according to claim 8, characterized in that: The judgment module includes: a region comparison unit, used to determine whether all the pin marks are located within a preset central region; and a logic judgment unit, used to determine that the pin is normal when all the pin marks are located within the preset central region; and to determine that the pin is abnormal when there are pin marks located outside the preset central region.

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