A power semiconductor device electrical characteristic aging test power transfer device
Patent Information
- Application Number
- CN202611332855.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-31
- Publication Date
- 2026-09-25
AI Technical Summary
它的杂感极限往往卡在20-30nH左右，而碳化硅（SiC）模块由于更高的开关速度，要求更低的杂感，传统叠层式铜排难以满足碳化硅（SiC）模块较低杂感的测试需求
1.利用PCB工艺实现相邻转接铜排的极窄层间距与相邻转接铜排反向电流设计，使相邻转接铜排产生的磁场高效抵消，将杂散电感降至9.5nH左右，提升了测试精度；
Smart Images
Figure CN122814958A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the technical field of power semiconductor test adapters, and proposes a power adapter for aging test of the electrical characteristics of power semiconductor devices. Background Technology
[0002] Currently, when testing traditional power semiconductor modules, such as medium-power IGBT (Insulated Gate Bipolar Transistor) packaged modules or HPD (High Power Density) packaged modules, a stacked copper busbar is typically used. The two ends of the busbar are connected to the power terminals of the power semiconductor module and the external testing equipment via screws or other clamps. For some high-power-density semiconductor modules, modular, solderless power terminals, such as multi-pin parallel connection of special pins (e.g., "eagle eye" pins), are generally used to replace the traditional power terminals of the power semiconductor module. This design is particularly useful in some three-level topologies, as it reduces internal inductance and facilitates disassembly and replacement of the power module.
[0003] However, the principle behind reducing stray inductance in traditional multilayer copper busbars is to bring the positive and negative copper busbars as close as possible, so that the current directions of adjacent layers of copper busbars are opposite, and the magnetic fields generated partially cancel each other out. However, due to the limitations of the copper busbar thickness and the thickness of the insulating paper between adjacent copper busbars, the distance between adjacent copper busbars and the thickness of a single copper busbar in traditional two- or three-layer multilayer copper busbars are usually on the order of millimeters. Its stray inductance limit is often limited to around 20-30 nH. However, silicon carbide (SiC) modules, due to their higher switching speeds, require even lower stray inductance, and traditional multilayer copper busbars cannot meet the testing requirements for the lower stray inductance of SiC modules. Summary of the Invention
[0004] To reduce the inductance of multilayer copper busbars, this application provides a power switching device for aging test of the electrical characteristics of power semiconductor devices.
[0005] The power conversion device for aging test of electrical characteristics of power semiconductor devices provided in this application adopts the following technical solution: A power switching device for aging testing the electrical characteristics of power semiconductor devices, applied to power modules with separate solderless terminals, comprising: The adapter copper busbar is stacked in at least three layers along the thickness direction. A PCB substrate is provided between adjacent adapter copper busbars. The first side of the adapter copper busbar is provided with a plug hole, and the second side away from the first side is provided with a power terminal. The plug hole is used for the pins of the power module to be plugged in and out, and the power terminal is used to connect to the test device. The PCB structure is formed by pressing multiple copper busbars and multiple PCB substrates together. The power terminals of two adjacent copper busbars are configured to be connected to the potential terminals of different potentials of the test device so that the current directions of the two adjacent copper busbars are opposite when the test is powered on.
[0006] By adopting the above technical solution, the current directions of two adjacent transition copper busbars are opposite under test power-on conditions. According to Ampere's law, the magnetic fields generated by the currents of the two adjacent transition copper busbars are in opposite directions, which can partially cancel each other out, reducing stray inductance and electromagnetic interference during the test, and improving test accuracy and signal integrity. The transition device designed through PCB process technology allows the distance between adjacent transition copper busbars to be closer, and the opposite current of adjacent transition copper busbars has a better effect on reducing stray inductance. Simulation tests show that the stray inductance of two adjacent transition copper busbars is reduced to about 9.5nH. The thinner transition copper busbars make the PCB structure less rigid than traditional multilayer copper busbars. In high-temperature aging tests, the PCB structure can absorb and buffer the stress caused by thermal expansion, reducing the mechanical damage rate of the semiconductor power module pins during testing.
[0007] Optionally, the multiple transition copper busbars are a positive potential copper busbar, a negative potential copper busbar, and a neutral point potential copper busbar; the neutral point potential copper busbar is located between the positive potential copper busbar and the negative potential copper busbar, and the positive potential copper busbar is located between the two neutral point potential copper busbars or the negative potential copper busbar is located between the two neutral point potential copper busbars; the two neutral point potential copper busbars are connected in parallel.
[0008] By adopting the above technical solution, since the current corresponding to the neutral point potential copper busbar is approximately twice that of the positive or negative potential copper busbar, the thermal stress of the neutral point potential copper busbar is approximately twice that of the positive or negative potential copper busbar, resulting in uneven thermal stress in the transfer device. Designing the number of neutral point potential copper busbar layers to be twice that of the positive or negative potential copper busbars allows the neutral point potential current to be split between the two neutral point potential copper busbars, ensuring that the current in each neutral point potential copper busbar is approximately the same as the current in the positive and negative potential copper busbars, thus achieving more uniform thermal stress.
[0009] Optionally, the positive potential copper busbar includes a first positive potential copper busbar and a second positive potential copper busbar connected in parallel; the neutral point potential copper busbar includes a first neutral point potential copper busbar, a second neutral point potential copper busbar, a third neutral point potential copper busbar and a fourth neutral point potential copper busbar connected in parallel; and the negative potential copper busbar includes a first negative potential copper busbar and a second negative potential copper busbar connected in parallel. The first positive potential copper busbar, the first neutral point potential copper busbar, the first negative potential copper busbar, the second neutral point potential copper busbar, the second positive potential copper busbar, the third neutral point potential copper busbar, the second negative potential copper busbar and the fourth neutral point potential copper busbar are arranged in a sequentially stacked manner.
[0010] By adopting the above technical solution, the eight layers of transition copper busbars are arranged in a specific order to ensure that the current direction of any two adjacent layers of transition copper busbars is opposite, which increases the magnetic field cancellation effect across the entire cross-section of the transition device and further reduces stray inductance. The positive potential copper busbar, negative potential copper busbar, and neutral point potential copper busbar are all set to be connected in parallel with multiple electrical polarities, which improves the current carrying capacity.
[0011] Optionally, the insertion holes of the positive potential copper busbar, the insertion holes of the negative potential copper busbar, and the insertion holes of the neutral point potential copper busbar are staggered vertically.
[0012] By adopting the above technical solution, the staggered arrangement of the plug holes of different adapter copper busbars ensures that when pins of different potentials are pressed into the plug holes, they only establish an electrical connection with their corresponding adapter copper busbars, eliminating the need for additional insulation structures and simplifying the structure of the adapter device. The staggered plug holes have a natural anti-misinsertion function, as pins of different potentials do not interfere with each other in physical position, reducing the risk of misoperation.
[0013] Optionally, the power terminals of the positive potential copper busbar, the negative potential copper busbar, and the neutral point potential copper busbar are staggered vertically.
[0014] By adopting the above technical solution, the power terminals of different adapter copper busbars are staggered vertically, spatially separating power terminals of different potentials. This facilitates the connection of test device cables to the corresponding power terminals, simplifying wiring operations. The staggered distribution increases the creepage distance and clearance between power terminals of different potentials, reducing the risk of breakdown under high voltage / high current testing conditions and improving safety. The staggered distribution also allows for gaps between power terminals of different potentials, promoting airflow and heat dissipation, and reducing heat concentration caused by densely packed power terminals of different potentials.
[0015] Optionally, it also includes a pin sleeve, which includes a plug portion and a connecting portion connected to the plug portion. The plug portion is disposed in a plug hole, and the connecting portion has an inner hole for the power module pins to be plugged in and out.
[0016] By adopting the above technical solution, the thermal expansion coefficients of the pins, PCB substrate, and adapter copper busbar differ under the high-temperature environment of the aging test. Compared with the pins of the semiconductor power module, the insertion part of the pin sleeve is better able to adapt to the gaps caused by the different hole diameters of the insertion holes at high temperatures, reducing contact resistance fluctuations. The connecting part of the pin sleeve is located outside the insertion hole and connects to the pins of the semiconductor power module, allowing the heat generated by the pins of the semiconductor power module and the connecting part to be released into the air, reducing the accumulation of heat in the adapter copper busbar and PCB substrate.
[0017] Optionally, the PCB substrate is provided with a first through hole communicating with the plug hole, and the hole wall of the first through hole is provided with a first conductive layer electrically connected to the corresponding adapter copper busbar, and the first conductive layer abuts against the plug part.
[0018] By adopting the above technical solution, the first conductive layer on the wall of the first through hole increases the contact area between the PCB substrate and the copper busbar, reduces the contact resistance, and reduces the heat generation at the contact point when energized.
[0019] Optionally, the PCB substrate thickness is 0.1-0.5mm, and the transition copper bus thickness is 35-140um.
[0020] By adopting the above technical solution, a PCB substrate thickness of 0.1-0.5mm allows for controllable overall thickness of the adapter after multilayer lamination, facilitating matching with the pin length of the semiconductor power module and ensuring that the pins can be inserted into the corresponding adapter copper busbar. An adapter copper busbar thickness of 35-140um ensures current carrying capacity while also considering the manufacturability of the PCB lamination process.
[0021] Optionally, the power terminal is provided with a connection hole, and the PCB substrate is provided with a second through hole corresponding to the connection hole. The inner wall of the connection hole and the second through hole is provided with a second conductive layer.
[0022] By adopting the above technical solution, the connecting hole penetrates the power terminal area, forming a longitudinal heat conduction channel, which accelerates the transfer of heat from the inner layer of the transfer copper busbar to the outside and reduces the temperature rise of the power terminal area during high-current testing. The second conductive layer on the inner wall of the connecting hole and the second through hole increases the conductive cross-sectional area between the transfer copper busbar and the test device, reducing the contact resistance.
[0023] Optionally, the adapter copper busbar is embedded in the corresponding PCB substrate so that the surface of the adapter copper busbar is flush with the surface of the PCB substrate.
[0024] By adopting the above technical solution, after the adapter copper busbar is embedded into the PCB substrate, the surfaces of the areas with and without copper busbars on the PCB substrate are basically flush, and the interlayer thickness tends to be consistent. This avoids the warping and deformation of the PCB substrate caused by thickness differences when multiple adapter copper busbars are pressed onto multiple PCB substrates. After pressing, a tight mechanical bond is formed between the adapter copper busbar and the PCB substrate, enhancing interlayer adhesion and reducing delamination during high and low temperature thermal cycling tests.
[0025] In summary, this application includes at least one of the following beneficial technical effects: 1. By utilizing PCB technology to achieve extremely narrow layer spacing between adjacent transition copper busbars and reverse current design between adjacent transition copper busbars, the magnetic fields generated by adjacent transition copper busbars are efficiently canceled, stray inductance is reduced to about 9.5nH, and test accuracy is improved. 2. By electrically connecting multiple neutral point copper busbars in parallel, equivalent current shunting is achieved, ensuring that the current in each transition copper busbar is the same, thus reducing deformation caused by uneven local thermal stress. Attached Figure Description
[0026] Figure 1 This is a three-level topology circuit diagram of a power module suitable for a power conversion device for aging test of the electrical characteristics of a power semiconductor device according to an embodiment of this application. Figure 2This is a schematic diagram of the structure of a power switching device for aging test of the electrical characteristics of a power semiconductor device according to an embodiment of this application; Figure 3 This is a schematic diagram of the stacked copper busbar and PCB substrate of a power conversion device for aging test of electrical characteristics of power semiconductor devices according to an embodiment of this application. Figure 4 This is an exploded schematic diagram of a power switching device for aging test of the electrical characteristics of a power semiconductor device according to an embodiment of this application; Figure 5 This is an exploded view of the copper busbar and PCB substrate of a power switching device for aging test of the electrical characteristics of a power semiconductor device according to an embodiment of this application. Figure 6 yes Figure 5 Enlarged view of area A in the middle; Figure 7 This is an exploded view of the copper busbar of the power transfer device for aging test of electrical characteristics of a power semiconductor device and the PCB substrate from another angle, according to an embodiment of this application.
[0027] Explanation of reference numerals in the attached drawings: 100, adapter copper busbar; 110, plug-in hole; 120, power terminal; 121, connection hole; 130, positive potential copper busbar; 131, first positive potential copper busbar; 132, second positive potential copper busbar; 140, negative potential copper busbar; 141, first negative potential copper busbar; 142, second negative potential copper busbar; 150, neutral point potential copper busbar; 151, first neutral point potential copper busbar; 152, second neutral point potential copper busbar; 153, third neutral point potential copper busbar; 154, fourth neutral point potential copper busbar; 200, PCB substrate; 210, first through hole; 220, second through hole; 300, pin sleeve; 310, plug-in part; 320, connection part; 400, power module; 410, pin. Detailed Implementation
[0028] The following combination Figures 1-7 This application will be described in further detail.
[0029] This application discloses a power switching device for aging test of the electrical characteristics of power semiconductor devices.
[0030] Reference Figure 1The power conversion device for aging testing the electrical characteristics of power semiconductor devices is applied to a power module 400 with separate solderless terminals. The internal circuit of the power module 400 adopts a three-level ANPC (Active Neutral Point Clamp) topology, which includes six power switches T1, T2, T3, T4, T5, and T6, and two voltage divider capacitors C1 and C2. Power switches T1 and T4 are connected to the positive terminal DC+ and the negative terminal DC-, respectively. Power switches T2 and T3 are connected in series between power switches T1 and T4. Power switch T5 is connected between the neutral point terminal N and power switches T1 and T2, and power switch T6 is connected between the neutral point terminal N and power switches T3 and T4. Voltage divider capacitor C1 is connected between the positive terminal DC+ and the neutral point terminal N, and voltage divider capacitor C2 is connected between the neutral point terminal N and the negative terminal DC-. The power module 400 has multiple pins 410 corresponding to the positive terminal DC+, the negative terminal DC-, and the neutral terminal N, respectively, to facilitate the removal and replacement of the power module 400.
[0031] In the above three-level topology circuit, viewed from the external power side of the transition copper busbar 100, there are four types of current loops under different switching states or switching cycles: The first current direction in the positive current loop: The current of the test device flows into the power terminal 120 of the neutral point potential copper busbar 150, then into the power module 400 through the neutral point potential copper busbar 150 and the neutral point potential terminal N of the power module 400, and then into the positive potential copper busbar 130 from the positive potential terminal DC+ of the power module 400. Finally, it flows into the test device from the power terminal 120 of the positive potential copper busbar 130. At this time, T1 and T5 are open, and T2, T3, T4 and T6 are closed.
[0032] The second current direction in the positive current loop: The current of the test device flows into the power terminal 120 of the positive potential copper busbar 130, then into the power module 400 via the positive potential copper busbar 130 and the positive potential terminal DC+ of the power module 400, and then into the neutral point potential copper busbar 150 from the neutral point potential terminal N of the power module 400. Finally, it flows into the test device from the power terminal 120 of the neutral point potential copper busbar 150. At this time, T1 and T5 are open, and T2, T3, T4 and T6 are closed.
[0033] The first current direction in the negative current loop: The current of the test device flows into the power terminal 120 of the negative potential copper busbar 140, then into the power module 400 via the negative potential copper busbar 140 and the negative potential terminal DC- of the power module 400, then into the neutral point potential copper busbar 150 from the neutral point potential terminal N of the power module 400, and finally into the test device via the power terminal 120 of the neutral point potential copper busbar 150. At this time, T4 and T6 are open, and T1, T2, T3 and T5 are closed.
[0034] The second current direction in the negative current loop: The current of the test device flows into the power terminal 120 of the neutral point potential copper busbar 150, then into the power module 400 through the neutral point potential copper busbar 150 and the neutral point potential terminal N of the power module 400, and then into the negative potential copper busbar 140 from the negative potential terminal DC- of the power module 400. Finally, it flows into the test device from the power terminal 120 of the negative potential copper busbar 140. At this time, T4 and T6 are open, and T1, T2, T3 and T5 are closed.
[0035] Reference Figure 2 and Figure 3 The power switching device for aging testing the electrical characteristics of power semiconductor devices includes a switching copper busbar 100 and a PCB substrate 200. The switching copper busbar 100 is stacked in at least three layers along its thickness direction, and is generally made of copper or oxygen-free copper to ensure good electrical and thermal conductivity. The PCB substrate 200 is disposed between adjacent switching copper busbars 100, and is generally made of FR4 (glass fiber reinforced epoxy resin) material, which has good insulation properties and mechanical strength.
[0036] In this embodiment, each layer of transition copper busbar 100 is manufactured using an embedding process. Specifically, each layer of transition copper busbar 100 is not simply laid flat on the surface of the PCB substrate 200, but is pre-embedded into the corresponding PCB substrate 200, so that the surface of the transition copper busbar 100 of the same layer is basically flush with the surface of the PCB substrate 200 in the area without copper busbars, eliminating thickness steps. Then, the layers are stacked and cured to form an integral PCB structure. This PCB structure significantly reduces the distance between adjacent transition copper busbars 100 compared to traditional stacked copper busbars.
[0037] Reference Figure 3 The power terminals 120 of two adjacent transition copper busbars 100 are configured to be connected to potential terminals of different potentials in the test device, so that the current directions of the two adjacent transition copper busbars 100 are opposite when the test is energized. By making the currents flowing in opposite directions through the two adjacent layers of transition copper busbars 100, the magnetic fields generated by the two layers of copper busbars partially cancel each other out at a very close distance, thereby reducing the stray inductance of the circuit.
[0038] The PCB substrate 200 has a thickness of 0.1-0.5 mm, preferably 0.3 mm, and the transition copper busbar 100 has a thickness of 35-140 μm, preferably 70 μm. The transition copper busbar 100 and the PCB substrate 200 are integrally press-fitted using PCB technology. The spacing between adjacent transition copper busbars 100 is only the thickness of the PCB substrate 200, far smaller than the millimeter-level spacing of the insulating paper in traditional multilayer copper busbars. Simulation tests show that the stray inductance between adjacent transition copper busbars in this application can be reduced to approximately 9.5 nH, which meets the low stray inductance testing requirements of silicon carbide modules.
[0039] To verify the low parasitic inductance effect of the PCB structure in this embodiment, a three-dimensional electromagnetic field full-wave solution tool, such as Ansys Q3D Extractor, was used to conduct a parasitic parameter extraction simulation experiment. The specific simulation conditions and process are as follows: First, a three-dimensional equivalent model of the adapter is established, wherein the material of the adapter copper busbar 100 is set to have an electrical conductivity of 5.8 × 10⁻⁶. 7 The copper is S / m pure copper with a thickness of 70um; the PCB substrate 200 between adjacent copper busbars 100 is made of FR4 (glass fiber reinforced epoxy resin) with a relative permittivity of 4.4 and a thickness of 0.3mm.
[0040] Secondly, based on the power module 400, such as a silicon carbide (SiC) three-level module, the excitation source and load terminals are configured according to the actual current path. For example, a current input terminal is set at the power terminal 120 of the positive potential copper busbar 130 connected to the external test device, and a current output terminal is set at the corresponding power terminal 120 of the neutral point potential copper busbar 150. The current forms opposite current loops with very close distances in the positive potential copper busbar 130 and the neutral point potential copper busbar 150.
[0041] Furthermore, considering the extremely high switching speeds of silicon carbide devices, dv / dt and di / dt, the AC frequency scanning range in the simulation experiment was set to 100kHz to 30MHz.
[0042] This simulation experiment also established a set of comparative models of traditional stacked copper busbars. Traditional stacked copper busbars use relatively thick copper busbars stacked together, with insulating paper placed between adjacent layers for insulation. The thickness of traditional stacked copper busbars is typically 1-5 mm, and the thickness of the insulating paper is typically 0.5-2 mm. In this comparative model, the thickness of the copper busbars is set to 3 mm, and the spacing of the insulating paper between adjacent copper busbars is set to 1 mm. The formula for calculating the equivalent stray inductance is: The simulation results are shown in Table 1 below: Table 1 Single-layer copper busbar thickness 3mm 70um Interlayer insulation medium of adjacent transition copper busbars Insulating paper FR4 Spacing between adjacent copper busbar layers 1mm 0.3mm Test frequency points 30MHz 30MHz <![CDATA[Positive current loop: self-inductance of positive copper busbar (L 11 )]]> 17.65nH 11.74nH <![CDATA[Positive current loop: self-inductance of neutral potential copper bar (L 12 )]]> 17.43nH 11.58nH Positive current loop: Interlayer mutual inductance (M) -3.54nH -7.01nH <![CDATA[Equivalent stray inductance of positive copper bar and neutral potential copper bar (L loop )]]> 28.00nH 9.30nH <![CDATA[Negative current loop: self-inductance of negative copper bar (L 11 )]]> 17.65nH 11.24nH <![CDATA[Negative current loop: self-inductance of neutral point potential copper bar (L 12 )]]> 17.43nH 11.47nH Negative current loop: Interlayer mutual inductance (M) -3.54nH -6.53nH <![CDATA[Equivalent stray inductance of negative copper bar and neutral point potential copper bar (L loop )]]> 28.00nH 9.66nH Referring to Table 1, simulation results show that at a test frequency of 30MHz, the equivalent AC stray inductance of the positive current loop in the comparative model (traditional multilayer copper busbar) is approximately 28nH, and the equivalent AC stray inductance of the negative current loop is approximately 28nH. In the adapter model of this application, the equivalent loop AC stray inductance of the positive current loop is reduced to approximately 9.3nH, and the stray inductance of the negative current loop is reduced to 9.66nH. Compared to traditional multilayer copper busbars with spacing of millimeters or more, where the stray inductance between adjacent copper busbars is typically above 20-30nH, the adapter of this application can reduce the stray inductance between adjacent adapter copper busbars by approximately 40-70%.
[0043] Reference Figure 2 and Figure 4 The power module 400 has multiple pins 410 at its bottom. These pins 410 typically use modular, solderless power terminals such as eagle-eye pins to facilitate connection between the power module 400 and the adapter. The first side of the adapter copper busbar 100 has a insertion hole 110 for inserting and removing the pins 410 of the power module 400, enabling a detachable electrical connection between the power module 400 and the adapter. The second side of the adapter copper busbar 100, away from the first side, has a power terminal 120 for connecting a testing device. A pin sleeve 300 is installed inside the insertion hole 110, which can be soldered into the insertion hole 110. The pin sleeve 300 includes an insertion part 310 and a connecting part 320 that connects to the insertion part 310. The insertion part 310 is located inside the insertion hole 110 and fits tightly within it. The connecting part 320 has an inner hole for inserting and removing the pins 410 of the power module 400. The PCB substrate 200 has a first through hole 210 communicating with the insertion hole 110. The wall of the first through hole 210 has a first conductive layer electrically connected to the corresponding adapter copper busbar 100. The first conductive layer is generally an electroplated gold layer, typically 35µm thick, and can be formed through a hole metallization process in PCB manufacturing. The first conductive layer abuts against the insertion part 310 of the pin sleeve 300, allowing the pin sleeve 300 to establish a reliable electrical connection with the corresponding adapter copper busbar 100 through the first conductive layer. The power terminal 120 has a connecting hole 121, and the PCB substrate 200 has a second through hole 220 corresponding to the connecting hole 121. The inner walls of the connecting hole 121 and the second through hole 220 have a second conductive layer, also typically an electroplated gold layer, typically 35µm thick. The second conductive layer increases the conductive cross-sectional area of the power terminal 120 region, reducing the contact resistance when the power terminal 120 is connected to the test device.
[0044] Reference Figure 3 and Figure 5The multiple transition copper busbars 100 are designated as positive potential copper busbar 130, negative potential copper busbar 140, and neutral point potential copper busbar 150. The neutral point potential copper busbar 150 is located between the positive potential copper busbar 130 and the negative potential copper busbar 140, and either the positive potential copper busbar 130 is located between the two neutral point potential copper busbars 150, or the negative potential copper busbar 140 is located between the two neutral point potential copper busbars 150. The two neutral point potential copper busbars 150 are connected in parallel.
[0045] Reference Figure 1 and Figure 5 In a three-level ANPC (Active Neutral Point Clamp) topology, the neutral point N serves as the common return point for both the upper and lower half-bridges. During operation, the current flowing through neutral point N is approximately twice the current flowing through either the positive (DC+) or negative (DC-) terminal. Therefore, the current corresponding to the neutral point copper busbar 150 is approximately twice the current corresponding to either the positive (DC+) or negative (DC-) copper busbar 130. If only one layer of neutral point copper busbar 150 is used, its thermal stress is approximately twice that of either the positive (DC+) or negative (DC-) copper busbar 130, causing deformation of the adapter due to uneven thermal stress. The number of layers of the neutral point potential copper busbar 150 is designed to be twice that of the positive potential copper busbar 130 or the negative potential copper busbar 140. The current at the neutral point potential terminal of the power module 400 is shunt through the two electrically parallel neutral point potential copper busbars 150, so that the current of each neutral point potential copper busbar 150 is approximately the same as that of the positive potential copper busbar 130 or the negative potential copper busbar 140, resulting in more uniform thermal stress.
[0046] Reference Figure 5 The positive potential copper busbar 130 includes a first positive potential copper busbar 131 and a second positive potential copper busbar 132 connected in parallel. The neutral point potential copper busbar 150 includes a first neutral point potential copper busbar 151, a second neutral point potential copper busbar 152, a third neutral point potential copper busbar 153, and a fourth neutral point potential copper busbar 154 connected in parallel. The negative potential copper busbar 140 includes a first negative potential copper busbar 141 and a second negative potential copper busbar 142 connected in parallel. The first positive potential copper busbar 131, the first neutral point potential copper busbar 151, the first negative potential copper busbar 141, the second neutral point potential copper busbar 152, the second positive potential copper busbar 132, the third neutral point potential copper busbar 153, the second negative potential copper busbar 142, and the fourth neutral point potential copper busbar 154 are stacked sequentially along the thickness direction. This stacked arrangement allows multiple copper busbars 130, 140, and 150 to be connected in parallel, thus improving the current carrying capacity.
[0047] Reference Figure 5 and Figure 6The insertion holes 110 of the positive potential copper busbar 130, the negative potential copper busbar 140, and the neutral point potential copper busbar 150 are staggered vertically in the stacking direction, meaning that the insertion holes 110 on the transition copper busbars 100 of different potentials do not coincide in the stacking direction. This staggered distribution ensures that the insertion holes 110 of different potentials correspond to the pins 410 of different potentials at the bottom of the power module 400.
[0048] Reference Figure 7 The power terminals 120 of the positive potential copper busbar 130, the negative potential copper busbar 140, and the neutral point potential copper busbar 150 are staggered vertically in the stacking direction. This staggered distribution allows the power terminals 120 of the different potential transfer copper busbars 100 to be offset from each other in the stacking direction, facilitating the connection of the power terminals 120 of different potentials to the corresponding potential terminals of the testing device.
[0049] The implementation principle of the power conversion device for electrical characteristic aging testing of power semiconductor devices according to an embodiment of this application is as follows: In use, the power module 400 is placed on top of the conversion device, and the multiple pins 410 on the bottom of the power module 400 are aligned with the corresponding insertion holes 110 on the conversion copper busbar 100. The pins 410 are inserted and removed through the inner hole of the connecting part 320 of the pin sleeve 300 to achieve a reliable electrical connection between the power module 400 and the conversion device. The power terminal 120 on the second side of the conversion copper busbar 100 is bolted to the external busbar capacitor and other equipment of the testing device through the connecting hole 121. Under test power-on conditions, the positive potential copper busbar 130 is connected to the positive potential terminal DC+ of the power module 400, the negative potential copper busbar 140 is connected to the negative potential terminal DC- of the power module 400, and the neutral point potential copper busbar 150 is connected to the neutral point potential terminal N of the power module 400. Currents flowing in opposite directions through adjacent transition copper busbars 100 generate magnetic fields that partially cancel each other out at very close distances, effectively reducing stray inductance in the circuit. The transition device, designed using PCB press-fit technology, allows for a closer distance between adjacent transition copper busbars 100 compared to traditional multilayer copper busbars, resulting in better stray inductance reduction.
[0050] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.
Claims
1. A power adapter for aging test of electrical characteristics of power semiconductor devices, applied to a power module (400) with separate solderless terminals, characterized in that, include: A copper busbar (100) is stacked in at least three layers along the thickness direction. A PCB substrate (200) is provided between adjacent copper busbars (100). A plug hole (110) is provided on the first side of the copper busbar (100), and a power terminal (120) is provided on the second side away from the first side. The plug hole (110) is used for the pins (410) of the power module (400) to be plugged in and unplugged. The power terminal (120) is used to connect to the test device. The multiple adapter copper busbars (100) and multiple PCB substrates (200) are pressed together to form a PCB structure. The power terminals (120) of two adjacent adapter copper busbars (100) are configured to be connected to potential terminals of different potentials of the test device, so that the current directions of the two adjacent adapter copper busbars (100) are opposite when the test is powered on.
2. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 1, characterized in that, The plurality of the transfer copper busbars (100) are respectively a positive potential copper busbar (130), a negative potential copper busbar (140) and a neutral point potential copper busbar (150); the neutral point potential copper busbar (150) is located between the positive potential copper busbar (130) and the negative potential copper busbar (140), and the positive potential copper busbar (130) is located between two neutral point potential copper busbars (150) or the negative potential copper busbar (140) is located between two neutral point potential copper busbars (150); the two neutral point potential copper busbars (150) are electrically connected in parallel.
3. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 2, characterized in that, The positive potential copper busbar (130) includes a first positive potential copper busbar (131) and a second positive potential copper busbar (132) connected in parallel. The neutral point potential copper busbar (150) includes a first neutral point potential copper busbar (151), a second neutral point potential copper busbar (152), a third neutral point potential copper busbar (153), and a fourth neutral point potential copper busbar (154) connected in parallel. The negative potential copper busbar (140) includes a first negative potential copper busbar (141) and a second negative potential copper busbar (142) connected in parallel. The first positive potential copper busbar (131), the first neutral point potential copper busbar (151), the first negative potential copper busbar (141), the second neutral point potential copper busbar (152), the second positive potential copper busbar (132), the third neutral point potential copper busbar (153), the second negative potential copper busbar (142), and the fourth neutral point potential copper busbar (154) are arranged in a stacked manner.
4. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 2, characterized in that, The insertion holes (110) of the positive potential copper busbar (130), the insertion holes (110) of the negative potential copper busbar (140), and the insertion holes (110) of the neutral point potential copper busbar (150) are staggered vertically.
5. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 2, characterized in that, The power terminals (120) of the positive potential copper busbar (130), the power terminals (120) of the negative potential copper busbar (140), and the power terminals (120) of the neutral point potential copper busbar (150) are staggered vertically.
6. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 1, characterized in that, It also includes a needle sleeve (300), which includes a plug portion (310) and a connecting portion (320) connected to the plug portion (310). The plug portion (310) is disposed in the plug hole (110), and the connecting portion (320) is provided with an inner hole for the pins (410) of the power module (400) to be plugged in and out.
7. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 6, characterized in that, The PCB substrate (200) is provided with a first through hole (210) communicating with the plug hole (110). The hole wall of the first through hole (210) is provided with a first conductive layer electrically connected to the corresponding adapter copper bus (100). The first conductive layer abuts against the plug part (310).
8. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 1, characterized in that, The PCB substrate (200) has a thickness of 0.1-0.5 mm, and the adapter copper busbar (100) has a thickness of 35-140 μm.
9. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 1, characterized in that, The power terminal (120) has a connection hole (121), and the PCB substrate (200) has a second through hole (220) corresponding to the connection hole (121). The inner walls of the connection hole (121) and the second through hole (220) are provided with a second conductive layer.
10. The power conversion device for aging test of electrical characteristics of power semiconductor devices according to claim 1, characterized in that, The adapter copper busbar (100) is embedded in the corresponding PCB substrate (200) so that the surface of the adapter copper busbar (100) is flush with the surface of the PCB substrate (200).