A dynamic zero point compensation method and circuit for open loop hall current sensors

Abstract

The application discloses a kind of dynamic zero point compensation method and circuit of open loop hall current sensor, belong to hall current sensor technical field, by temperature compensation branch and reference current branch hall element power supply, adjust temperature compensation resistance to make positive temperature coefficient relationship and the negative temperature coefficient of hall element match, carry out first-order forward compensation to hall element, the sensing voltage signal of real-time acquisition reference feedback node at reference feedback node, generate compensation voltage by analog operation circuit, carry out mixed operation in operational amplifier with compensation voltage and hall differential signal, output compensated single-ended current sensing voltage signal.The application changes in real time by compensation voltage following temperature and the change of power supply, carries out dynamic compensation to sensor, and zero point temperature drift coefficient is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of Hall current sensor technology, and relates to a dynamic zero-point compensation method and circuit for an open-loop Hall current sensor. Background Technology

[0002] With the rapid development of new energy vehicles, industrial automation, rail transit, and energy storage systems, power electronic equipment often needs to operate reliably for extended periods in extreme temperature environments ranging from -40℃ to 105℃. Among these, frequency converters and energy storage inverters, as core components for motor drive and power conversion, require high-precision real-time sampling of internal current using open-loop Hall current sensors to ensure system control accuracy, operational efficiency, and equipment safety. However, the core sensing elements of open-loop Hall current sensors, such as Hall chips and magnetic cores, exhibit significant temperature dependence, resulting in inherent zero-point and sensitivity drift. This becomes a major bottleneck restricting their ability to achieve high-precision measurements over a wide temperature range.

[0003] Current mainstream solutions mostly employ fixed bias zero-adjustment circuits such as potentiometer zeroing or fixed compensation at the constant current source, which are static compensations. They can only be calibrated once at a specific temperature point (usually room temperature of 25°C). Once the equipment is actually running, the internal temperature changes drastically with the load and environment. For example, from a cold start at -40°C to full-load operation, the internal temperature rises to 105°C. The sensor's operating temperature is far from the calibration point, while the compensation signal remains unchanged. This causes the compensation amount to fail to track the actual drift curve, resulting in severe undercompensation or overcompensation. This severely degrades the sensor's output accuracy at high or low temperatures, with a typical zero-point temperature drift coefficient exceeding 100 ppm / °C.

[0004] Furthermore, temperature drift coupled with electromagnetic interference (EMI) can trigger unpredictable failure modes. The high-frequency switching (typically 20kHz to 50kHz) of IGBTs and MOSFETs inside frequency converters and energy storage inverters generates extremely strong common-mode noise and EMI. This interference not only couples directly into the Hall signal chain but also couples with temperature drift, interfering with the stability of the sensor's static operating point (bias point). Existing static zero-adjustment circuits cannot handle this "temperature drift-interference coupling" effect, making it impossible to guarantee the long-term stability and reliability of the sensor in complex electromagnetic environments, easily leading to misjudgments in the control system or malfunctions in protection functions. To improve performance, some high-performance solutions use dedicated compensation chips or digital processing systems for dynamic compensation, but these are costly and complex, making them unsuitable for the extremely cost-sensitive industrial market. Summary of the Invention

[0005] To address the aforementioned problems, this invention proposes a dynamic zero-point compensation method and circuit for an open-loop Hall current sensor, which effectively solves the problems in the prior art.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0007] A dynamic zero-point compensation method for an open-loop Hall current sensor includes:

[0008] S1. A temperature compensation branch is formed through the PNP type regulating transistor and the temperature compensation resistor. The current in the temperature compensation branch and the reference current branch formed by the reference chip Vz1, the NPN type regulating transistor and the sampling resistor converge to form a total current with a positive temperature coefficient relationship. Total current Power the Hall element and adjust the temperature compensation resistor to match the positive temperature coefficient with the negative temperature coefficient of the Hall element, and perform first-order forward compensation on the Hall element.

[0009] S2. Using the reference pin REF connected to the reference chip Vz1 as the reference feedback node, the reference pin REF is also connected to the connection node between the emitter of the NPN type regulating transistor and the sampling resistor, and the sensed voltage signal of the reference feedback node is acquired in real time. ;

[0010] S3, Sensing voltage signal Input to analog computing circuit, according to preset scaling factor Perform addition and subtraction operations to generate compensation voltage. ;

[0011] S4, adjust the compensation voltage The Hall differential signal, amplified by a two-stage operational amplifier, is subjected to real-time analog differential addition and subtraction mixing operations in the second-stage operational amplifier to output a compensated single-ended current-sensing voltage signal. .

[0012] Optionally, S4 includes:

[0013] S41. The two channels U1.1 and U1.2 of the dual operational amplifier U1 are both in-phase amplification branches, which amplify and condition the differential signals output by the dual Hall elements in in-phase.

[0014] S42. Through the differential operational structure formed by the operational amplification unit U2.1 in the dual operational amplifier U2, the inverting input terminal of U2.1 receives the output from U1.2, and the non-inverting input terminal of U2.1 receives the output from U1.1, while a compensation voltage is injected. Output compensated single-ended current sensing voltage signal .

[0015] Optionally, the first Hall in-phase signal amplified by U1.1 is injected into the in-phase terminal of U2.1 via a parallel signal transmission path formed by resistors R6 and R12 connected in parallel, and the second Hall in-phase signal amplified by U2.1 is injected into the inverting terminal of U2.1 via resistor R8. The scaling factor... for:

[0016]

[0017] in, This is the parallel value of R12 and R6.

[0018] Optionally, an adjustable resistor VR1 connected in series is connected to the inverting input of U2.1, and the adjustment terminal of the adjustable resistor VR1 is connected to the channel of resistor R23. The two ends of the adjustable resistor VR1 are respectively connected to sense voltage signals. The nodes at the same potential and the ground form Provides a static bias adjustment channel, the proportional coefficient for:

[0019]

[0020] in, The resistance value is the series resistance of R23 and the adjustable resistor VR1.

[0021] A circuit, comprising the circuit of the dynamic zero-point compensation method for an open-loop Hall current sensor as described in any of the preceding claims, comprising:

[0022] The positive temperature coefficient constant current source module includes a parallel reference chip Vz1, a PNP type regulating transistor TR1, an NPN type regulating transistor TR2, a sampling resistor R13, and a bias resistor network R16, R17, R14, and R15. Resistors R17 and R16 are temperature compensation resistors connected in series with the emitter of the PNP type regulating transistor TR1. The reference pin REF of the parallel reference chip Vz1 is connected to the emitter of the NPN type regulating transistor TR2. The connection node between the sampling resistor R13 and the reference feedback node is the reference feedback node.

[0023] The Hall module includes a first Hall element H1 and a second Hall element H2, and the Hall module is connected to the positive temperature coefficient constant current source module;

[0024] The differential amplifier module includes a dual operational amplifier U1, which includes non-inverting operational amplifier units U1.1 and U1.2. The first Hall element H1 and the second Hall element H2 are respectively connected to input resistor networks R19, R20 and input resistor networks R21, R22. The input resistor networks R19, R20 and R21, R22 provide differential voltage signals to U1.1 and U1.2 respectively.

[0025] The dynamic compensation and output module includes a dual operational amplifier U2, which includes an operational amplification unit U2.1 and a precision resistor network R6, R8, and R12. The output signal of U1.1 is input to the non-inverting input of U2.1 after passing through the parallel resistors R6 and R12, and the output signal of U1.2 is input to the inverting input of U2.1 after passing through R8.

[0026] The reference feedback node is connected to the inverting input of U2.1. After generating a compensation voltage, it performs a real-time analog differential operation with the output signals of U1.1 and U1.2. U2.1 outputs a compensated single-ended voltage signal.

[0027] Optionally, the output terminal of the operational amplifier unit U2.1 is connected to a built-in RC low-pass filter, which includes a filter resistor R10 and a filter capacitor C15.

[0028] Optionally, a wideband decoupling network is connected in parallel to the reference feedback node, and the wideband decoupling network includes capacitors C18, C1, and C2 connected in parallel between the constant current input point of the Hall module and GND.

[0029] Optionally, the resistors R19, R20, R21, and R22 have equal resistance values ​​and a matching accuracy of not less than ±0.1%.

[0030] Optionally, it also includes a static zero-point coarse adjustment network, which includes a resistor R23 connected in series with the inverting input of U2.1 and an adjustable resistor VR1. The resistor R23 is connected to the adjustment terminal of the adjustable resistor VR1. The first terminal of the adjustable resistor VR1 is connected in series with the resistor R1, which is connected to the anode of the reference chip Vz1. The second terminal is connected to the resistor R11, which is grounded.

[0031] Compared with the prior art, the present invention has the following beneficial effects:

[0032] 1. A constant current source is connected in series with a temperature compensation resistor, and a reference feedback node is established at the output of the constant current source for voltage sampling. After passing through an operational amplifier, a compensation voltage is generated. The potential change of the reference feedback node reflects the constant current source adjustment information caused by changes in ambient temperature and constant current source adjustment information caused by fluctuations in power supply voltage. Compared with the traditional static compensation scheme, the zero-point temperature drift coefficient is significantly reduced.

[0033] 2. The compensation signal tracks the changes in temperature and power supply in real time, and can actively offset the slow changes in zero point caused by temperature cycling, component aging, and power fluctuations. This solves the fundamental problem of compensation failure in traditional solutions under dynamic temperature conditions and greatly improves the long-term stability of the sensor under hot and cold cycling conditions.

[0034] 3. By combining the temperature compensation resistor and the sampling resistor, the output current of the constant current source increases with the temperature, thereby achieving dynamic compensation. This eliminates the need for expensive dedicated compensation chips or digital processing systems, reducing the cost of use.

[0035] 4. By using built-in filtering and a wideband reference decoupling network, the filter resistor is located after the op-amp output stage rather than within the feedback loop. The filter cutoff frequency and circuit gain G are independently adjustable, avoiding signal attenuation and load effects caused by traditional front-end RC filtering. This decouples the filter cutoff frequency from the circuit gain, suppressing common-mode noise without sacrificing bandwidth. This ensures that the current sampling signal remains pure and reliable even in harsh electrical environments such as IGBT high-frequency switching noise.

[0036] 5. By cascading two operational amplifiers to condition the signal, a two-stage cascaded architecture of "dual-channel parallel differential amplification - single-channel convergence compensation" is formed. The first-stage operational amplifier allows the signals of the two Hall elements to enter two independent operational amplifier channels through two amplification branches, suppressing crosstalk and common-mode noise between channels. Combined with the dual intermediate signals of the first-stage operational amplifier, real-time differential mixing operation is performed in the second stage to achieve cascaded coordination between the first-stage in-phase amplification and the second-stage dynamic compensation.

[0037] 6. The static zero-point coarse adjustment network of the static bias adjustment circuit is also retained for initial calibration, forming a two-level compensation architecture of "coarse adjustment + fine adjustment". The static coarse adjustment ensures accurate alignment of the room temperature point, while the dynamic fine adjustment ensures real-time tracking across the entire temperature range. The two work together to minimize the zero-point error of the system across the entire temperature range. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the overall circuit structure of an embodiment of the present invention;

[0039] Figure 2 This is a schematic diagram of the positive temperature coefficient constant current source module circuit according to an embodiment of the present invention;

[0040] Figure 3 This is a schematic diagram of the Hall module circuit according to an embodiment of the present invention;

[0041] Figure 4 This is a schematic diagram of the differential amplifier module circuit according to an embodiment of the present invention;

[0042] Figure 5 This is a schematic diagram of the dynamic compensation and output module according to an embodiment of the present invention;

[0043] Figure 6 This is a schematic diagram of the static zero-point coarse adjustment network circuit according to an embodiment of the present invention;

[0044] Figure 7 This is a schematic diagram of the built-in filter in an embodiment of the present invention;

[0045] Figure 8 This is a record of the zero-point amplitude temperature drift of a 1000A product under the traditional static compensation scheme.

[0046] Figure 9 This is a record of the zero-point amplitude temperature drift of a 1000A product under the compensation scheme of this invention embodiment;

[0047] Figure 10 This is a comparison curve of the zero-point output of the present invention and the traditional static compensation scheme in the temperature range of -40℃ to 105℃. Detailed Implementation

[0048] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0049] Please see Figures 1 to 5 The present invention discloses a dynamic zero-point compensation method for an open-loop Hall current sensor, comprising:

[0050] S1. A temperature compensation branch is formed by the PNP type regulating transistor and the temperature compensation resistor. A reference current branch is formed by the reference chip Vz1, the NPN type regulating transistor, and the sampling resistor. The collector and base of the NPN type regulating transistor are connected to the base and collector of the PNP type regulating transistor, respectively. The two branches merge to form a total current with a positive temperature coefficient relationship. Power the Hall element and adjust the temperature compensation resistor to match the positive temperature coefficient with the negative temperature coefficient of the Hall element, and perform first-order forward compensation on the Hall element.

[0051] S2. Using the reference pin REF connected to the reference chip Vz1 as the reference feedback node, the reference pin REF is also connected to the connection node between the emitter of the NPN type regulating transistor and the sampling resistor, and the sensed voltage signal of the reference feedback node is acquired in real time. ;

[0052] S3, Sensing voltage signal Input to analog computing circuit, according to preset scaling factor Perform addition and subtraction operations to generate compensation voltage. ;

[0053] S4, adjust the compensation voltage The Hall differential signal, amplified by a two-stage operational amplifier, is then subjected to real-time analog differential addition and subtraction mixing operations in the second-stage operational amplifier to output a compensated single-ended current-sensing voltage signal. .

[0054] Specifically, a closed-loop negative feedback constant current system is formed by the PNP type regulating transistor and the reference current branch. The reference chip operates in its linear regulation region. When the voltage at the REF pin is lower than the internal reference voltage, the cathode absorbs current, causing the base potential of the NPN type regulating transistor to drop. Consequently, the collector current of the NPN type regulating transistor increases, which in turn causes the base current of the PNP type regulating transistor to be shunted and increased, enhancing conduction. This, in turn, increases the current flowing through the sampling resistor, and the voltage drop across the sampling resistor increases, causing the voltage at the REF pin to rise again.

[0055] Thus, when the connection node between the reference pin REF of the reference chip Vz1 and the emitter of the NPN regulating transistor and the sampling resistor is used as the reference feedback node, it simultaneously carries information about both temperature and power supply disturbances. Total current The positive temperature coefficient is carried by the sampling resistor branch, which is connected between the Vz1 reference pin REF and the anode. The voltage drop across the sampling resistor is clamped to a constant value by the internal reference of Vz1. The current in the sampling resistor branch is determined by the reference voltage drop and the resistance value of the sampling resistor. When the temperature changes, the resistance value of the sampling resistor changes, causing a corresponding change in the current in the sampling resistor branch. The Vz1 negative feedback loop adjusts the conduction level of the PNP and NPN regulating transistors. The collector current of the PNP regulating transistor compensates for the current change, and the total current output from the constant current source to the Hall constant current input node... It exhibits a positive temperature coefficient of variation with temperature. The temperature compensation resistor is connected in series in the emitter path of the PNP type regulating transistor. The slope of the temperature coefficient plays an auxiliary regulating role. Therefore, the constant current source It increases with increasing temperature, exhibiting a positive temperature coefficient, and this positive temperature coefficient is bidirectionally symmetrical across the entire temperature range of -40℃ to 105℃. When the temperature decreases... The slight decrease automatically cancels out the increase in Hall sensitivity at low temperatures. Node voltage The synchronous changes accurately reflect the constant current source adjustment information caused by changes in ambient temperature. Simultaneously, when the power supply VCC experiences ripple fluctuations due to load changes or IGBT switching, the voltage at this node synchronously reflects the power supply disturbance information through the negative feedback of the parallel reference chip.

[0056] The reference feedback node serves as the compensation signal source, requiring no additional temperature sensing element. This minimizes the delay in the compensation path, and the compensation path inherently includes a contribution to suppressing power supply voltage disturbances. Specifically, when VCC fluctuations cause a change in the voltage at the Hall element's constant current input node, the closed-loop negative feedback of the constant current source automatically adjusts the operating points of the PNP and NPN regulating transistors to ensure the total current output from the constant current source to the Hall element's constant current input node is optimal. While maintaining approximately constant, the reference feedback node voltage... The change is introduced into the final output voltage signal In this process, the direction of change is opposite to the direction of zero-point drift caused by VCC fluctuations, thereby achieving synchronous suppression of power supply disturbances.

[0057] Sensing voltage signal at the reference feedback node Data is collected, and the compensation voltage is processed through an analog computing circuit. The calculation is performed. The Hall differential signal from the Hall element, processed by two stages of operational amplifiers, undergoes real-time analog differential addition and subtraction mixing operations within the operational amplifiers, resulting in a compensated single-ended current-sensing voltage signal as the output. .

[0058] In this way, the compensation voltage changes in real time with the temperature and power supply, dynamically compensating the sensor. Compared with the traditional static compensation scheme, the zero-point temperature drift coefficient is significantly reduced. Furthermore, it can actively offset the slow zero-point changes caused by temperature cycling, component aging, and power supply fluctuations, solving the fundamental problem of compensation failure under dynamic temperature conditions in traditional schemes and greatly improving the long-term stability of the sensor under thermal cycling conditions.

[0059] Meanwhile, the constant current source output current increases with temperature by the combined action of the temperature compensation resistor and the sampling resistor, thus achieving dynamic compensation. This eliminates the need for expensive dedicated compensation chips or digital processing systems, reducing the cost of use.

[0060] As a specific implementation of the dynamic zero-point compensation method for an open-loop Hall current sensor provided in this application, please refer to... Figure 4 S4 includes:

[0061] S41. The two channels U1.1 and U1.2 of the dual operational amplifier U1 are both in-phase amplification branches, which amplify and condition the differential signals output by the dual Hall elements in in-phase.

[0062] S42. Through the differential operational structure formed by the operational amplification unit U2.1 in the dual operational amplifier U2, the inverting input terminal of U2.1 receives the output from U1.2, and the non-inverting input terminal of U2.1 receives the output from U1.1, while a compensation voltage is injected. Output compensated single-ended current sensing voltage signal .

[0063] It should be understood that by setting the signals of the two Hall elements to enter the two in-phase amplification branches respectively, crosstalk between channels is avoided, and crosstalk and common-mode noise are suppressed. U1.1 and U1.2 each generate independent signal outputs, providing a well-separated signal source for the second-stage multi-input mixed operation.

[0064] Furthermore, the first Hall in-phase signal amplified by U1.1 is injected into the in-phase input of U2.1 via a parallel signal transmission path formed by resistors R6 and R12 connected in parallel, while the second Hall in-phase signal amplified by U2.1 is injected into the inverting input of U2.1 via resistor R8. The scaling factor... for:

[0065]

[0066] in, This is the parallel value of R12 and R6.

[0067] It should be understood that the differential addition and subtraction circuit composed of R12, R6, and R8 converts the signal from the reference feedback node into a signal. Convert to compensation voltage and the dual output signals from U1.1 and U1.2 are combined with Real-time differential mixing is performed in U2.1, achieving cascaded coordination between the first-stage in-phase amplification and the second-stage dynamic compensation. By selecting different values ​​for R6 and R12, the required relative injection ratio of the U1.1 and U1.2 signals can be precisely set, indirectly controlling... Common-mode suppression effect after injection. By precisely matching the resistance values ​​of resistors R12, R6, and R8, it can be achieved... The zero-point drift curve of the sensor is optimally fitted in the full temperature range of -40℃ to 105℃, achieving a dynamic cancellation effect with equal magnitude and opposite direction.

[0068] Further, please refer to Figure 6 Connect the adjustable resistor VR1 (connected in series) to the inverting input of U2.1 and the channel of resistor R23. Connect the two ends of the adjustable resistor VR1 to sense voltage signals. The nodes at the same potential and the ground form Provides a static bias adjustment channel, the proportional coefficient for:

[0069]

[0070] in, The resistance value is the series resistance of R23 and the adjustable resistor VR1.

[0071] It should be understood that by adding an adjustable resistor VR1, a static zero-point coarse adjustment circuit is formed, constituting... Static bias adjustment channel, simultaneously for The value produces an additional modulation effect. The static zero-point coarse adjustment circuit and... The dynamic compensation generated by real-time sampling forms a two-level compensation architecture of "coarse adjustment + fine adjustment". Static coarse adjustment ensures accurate alignment of the room temperature point, while dynamic fine adjustment ensures real-time tracking across the entire temperature range. The two work together to minimize the zero-point error of the system across the entire temperature range.

[0072] For a better understanding and implementation of this method, please refer to [link / reference]. Figures 1 to 5 This application also discloses a circuit, including:

[0073] For the positive temperature coefficient constant current source module, please refer to [link / reference]. Figure 2 It includes a parallel reference chip Vz1, a PNP type regulating transistor TR1, an NPN type regulating transistor TR2, a sampling resistor R13, and a bias resistor network R16, R17, R14, and R15. Resistors R17 and R16 are temperature compensation resistors connected in series with the emitter of the PNP type regulating transistor TR1. The reference pin REF of the parallel reference chip Vz1 is connected to the emitter of the NPN type regulating transistor TR2. The connection node between the sampling resistor R13 and the reference feedback node is the reference feedback node.

[0074] Hall effect module, please refer to Figure 3 It includes a first Hall element H1 and a second Hall element H2, and the Hall module is connected to a positive temperature coefficient constant current source module;

[0075] Differential amplifier module, please refer to Figure 4 It includes a dual operational amplifier U1, which includes non-inverting operational amplifier units U1.1 and U1.2. The first Hall element H1 and the second Hall element H2 are respectively connected to input resistor networks R19, R20 and input resistor networks R21, R22. The input resistor networks R19, R20 and R21, R22 provide differential voltage signals for U1.1 and U1.2 respectively.

[0076] For the dynamic compensation and output module, please refer to [link / reference]. Figure 5 It includes a dual operational amplifier U2, which includes an operational amplifier unit U2.1 and a precision resistor network R6, R8, and R12. The output signal of U1.1 is input to the non-inverting input of U2.1 after passing through the parallel resistors R6 and R12, and the output signal of U1.2 is input to the inverting input of U2.1 after passing through R8.

[0077] The reference feedback node is connected to the inverting input of U2.1. After generating a compensation voltage, it performs a real-time analog differential operation with the output signals of U1.1 and U1.2. U2.1 outputs a compensated single-ended voltage signal.

[0078] Specifically, in the positive temperature coefficient constant current source module, the system power supply +VCC is connected in series with temperature compensation resistors R16 and R17 to the emitter of TR1. The resistance values ​​of R16 and R17 change with temperature. By setting the resistance values ​​of R16 and R17, the positive temperature coefficient slope of the constant current source output current is adjusted. The collector of TR2 is connected to the base of TR1, and the base of TR2 is connected to the collector of TR1. The collector of TR2 is connected in series with +VCC through resistor R15. R15 forms the pull-up bias path at the junction of the base of TR1 and the collector of TR2. Resistor R14 is connected between +VCC and the base of R2. R14 forms the bias path for the base of TR2. R14 and R15 ensure that TR1 and TR2 operate at a suitable quiescent operating point throughout the entire temperature range. The sampling resistor R13 is connected to the emitter of TR2, and the REF pin of the reference chip Vz1 is connected to the emitter of TR2. This connection point is the reference feedback node. The sampling resistor R13 and the collector of TR1 power the Hall module. The R13 sampling resistor branch provides a constant reference current clamped by the internal reference of Vz1, and the TR1 collector branch provides a compensation current dynamically adjusted by the negative feedback loop. After the two paths are combined... It exhibits a positive temperature coefficient relationship, and performs first-order forward compensation for the negative temperature coefficient of the Hall sensor unit's sensitivity.

[0079] In the cascaded structure of a PNP-type regulating transistor TR1 and an NPN-type regulating transistor TR2, the emitter of TR1 is connected to VCC via R17 and R16, and the collector is connected to the power supply terminal of the Hall element via the lower end of R13. This structure is naturally suitable for high-side constant current source applications. By adjusting the positive temperature coefficient slope of the constant current source through R17 and R16, the problem of the output potential being lower than the two Vbe voltage drops below VCC in a single NPN scheme is avoided, thus improving the effective supply voltage range. TR2, as a pre-control stage, amplifies the low-power control signal of Vz1 to drive the base of TR1, achieving decoupling between the control loop and the main current loop, improving the stability and load-carrying capacity of the constant current, and sensing the voltage signal. The sampling point is located at the emitter of TR2 (low current side) rather than the collector of TR1 (high current side), resulting in a higher signal-to-noise ratio for the sampled signal and it is not affected by the Hall load current.

[0080] Specifically, in the Hall module, the first Hall element H1 and the second Hall element H2 are connected in parallel to jointly carry the magnetic field generated by the conductor passing through the magnetic core and convert it into a differential voltage signal output. The power supply terminals of H1 and H2 are connected in parallel to form a common power supply node, simultaneously receiving the constant current output from the collector of the PNP regulating transistor TR1 and the current drawn in by the sampling resistor R13, i.e., the total current. Pin 3 (negative terminal of constant current input) of both H1 and H2 is grounded. Pin 2 (first output terminal) of H1 is connected to the non-inverting input terminal of U1.2 through resistor R20. Pin 2 (first output terminal) of H2 is connected to the non-inverting input terminal of U1.2 through resistor R19. Pin 4 (second output terminal) of H1 is connected to the non-inverting input terminal of U1.1 through resistor R21. Pin 4 (second output terminal) of H2 is also connected to the non-inverting input terminal of U1.1 through resistor R22. The parallel averaging structure of the two Hall elements can reduce the discreteness and self-noise of individual devices and improve the signal-to-noise ratio.

[0081] Specifically, the differential amplifier module includes two non-inverting amplifier branches, U1.1 and U1.2. U1.1 is responsible for processing the pin 4 signals of the two Hall elements. After receiving the signals, the two signals are superimposed at the non-inverting input of U1.1. The inverting input of U1.1 is connected to its own output through a feedback resistor R4. A capacitor C6 is connected in parallel across R4 for phase compensation to limit high-frequency gain and prevent self-oscillation. C6 and R4 in parallel form an independent non-inverting amplification closed loop for this channel of U1.1. The signals from pin 2 of the two Hall elements are superimposed on the non-inverting input of U1.2. The inverting input of U1.2 is connected to the upper end of the adjustable resistor VR2 through the coupling resistor R18. The lower end of VR2 is connected to the inverting input of U1.1 through the resistor R3. VR2 adjusts the gain balance of the two non-inverting amplification branches. The output of U1.2 is connected to the inverting input through the feedback resistor R7, forming an independent non-inverting amplification closed loop for this channel. The capacitor C9 is connected in parallel across R7 for phase compensation to limit high-frequency gain and prevent self-oscillation.

[0082] The two outputs maintain the phase relationship of the Hall differential signals, while simultaneously achieving preliminary amplification and noise suppression of the dual Hall signals. In some feasible configurations, the four Hall input resistors R19, R20, R21, and R22 are configured with consistent matching values, i.e., equal resistance values, ensuring that the equivalent input impedances of the non-inverting terminals of the two branches U1.1 and U1.2 are identical. VR2 is connected across the series resistors R3 and R18 at both ends of the amplitude modulation path, working in conjunction with VR2 itself to determine the amplitude modulation ratio of the inverting terminals of the two channels—the symmetrical value of R3=R18 ensures that the gains of the two branches U1.1 and U1.2 are symmetrical when the VR2 tap is at the physical midpoint, ensuring balanced impedance of the dual Hall signal path and consistent gain of the dual operational amplifier channels. The degree of freedom in characteristic matching is borne by the subsequent differential operational network and the static zero-point coarse adjustment network.

[0083] Specifically, the dynamic compensation and output module adopts a differential operational amplifier structure. The output of U1.1 is connected to the non-inverting input of U2.1 through parallel resistors R6 and R12. The left ends of R6 and R12 are both connected to the output of U1.1, and the right ends are both connected to the non-inverting input of U2.1. The non-inverting input of U2.1 is also pulled down to ground through resistor R5. Capacitor C8 is connected in parallel across R5 to form a filter network. The output of U1.2 is connected to the inverting input of U2.1 through resistor R8. Please refer to [link to relevant documentation]. Figure 1 , Figure 5 and Figure 6 Sensing voltage signals The voltage is divided by VR1 and injected into the inverting input of U2.1 after passing through resistor R23. When a static zero-point fine-tuning function is required, VR1 is an adjustable resistor. The upper end of VR1 is connected to the anode of Vz1 via resistor R1, and the lower end of VR1 is grounded via resistor R11. The adjustment terminal of VR1 is injected into the inverting input of U2.1 via R23. Adjustment of VR1 allows for... A voltage divider is used to extract the center tap and inject it into the inverting input of U2.1 to provide a fixed zero-point bias voltage during initial calibration. This enables the coordinated operation of static coarse adjustment and dynamic compensation.

[0084] U2.1 also includes two parallel feedback paths that work together to determine its frequency response characteristics. The feedback capacitor C11 is connected between the output terminal and the inverting input terminal (pin 2) of U2.1, forming an AC negative feedback path. At low frequencies, C11 has extremely high impedance and very weak negative feedback, allowing U2.1 to operate with high gain in the DC, low-frequency range. The current-limiting resistor R10 isolates the output terminal of U2.1 from the output terminal OUT in series. The output filter capacitor C15 is connected in parallel between the OUT terminal and ground. The OUT node, after passing through the auxiliary feedback resistor R9 and the auxiliary feedback capacitor C12 in parallel, is connected to the inverting input terminal of U2.1, forming an auxiliary feedback path. R9 and C12, connected in parallel, form an impedance network. R9 provides strong proportional feedback in the low-frequency range to ensure stable operation of U2.1, while C12 bypasses R9 in the high-frequency range to maintain phase margin and suppress high-frequency self-oscillation. Among them, C12 has the same resistance value as the non-inverting filter capacitor C8 to maintain the symmetry of the two filter networks, and R9 has the same resistance value as the non-inverting bias resistor R5 to maintain the symmetry of the two bias networks.

[0085] Please see Figure 7 U2.1 output terminal The current-limiting resistor R10 is connected to the output terminal OUT. The output filter capacitor C15 is connected in parallel between the OUT terminal and ground, forming a built-in RC low-pass filter, which constitutes a first-order RC low-pass filter. The OUT node is also connected back to the inverting input of U2.1 through an auxiliary feedback network. The positional relationship between R10, R9, and C12 determines that R10 only affects the output filtering characteristics and does not affect the closed-loop gain of U2.1, thus aligning the output cutoff frequency with the circuit gain. They are independently adjustable. The cutoff frequency of the built-in RC low-pass filter is...

[0086] .

[0087] U2.1 constitutes a differential operational amplifier, i.e., an analog operational circuit, whose output signal... satisfy:

[0088]

[0089] in, The voltage at the non-inverting input terminal is output from U1.1 and connected to R12. The voltage divider effect is determined by the parallel connection of R6. Resistor R12 is positioned between the intermediate signal output terminal of U1.1 and the non-inverting input terminal of U2.1. R6 and R12, connected in parallel, are both connected to the non-inverting input. Connect to U2.1 via the compensation input resistor R6; The feedback impedance is determined by the feedback capacitor C11, and is relevant for DC signals. ; The equivalent input impedance of the inverting input is determined by R8 and the static zero-point coarse adjustment network, namely R23 and VR1. The output source impedance of U1.1 is the internal resistance of the non-inverting amplifier branch of U1.1 when it drives U2.1 as a voltage source. This refers to the output voltage of U1.2; It is 0 when there is no static zero coarse adjustment network, which is the fixed bias voltage applied to the inverting input of U2.1 during initial calibration.

[0090] After simplification based on the maximum impedance of the feedback capacitor C11:

[0091]

[0092]

[0093] in, For differential gain, The compensation coefficient, also known as the proportional coefficient. .

[0094] In some feasible approaches, a wideband decoupling network is connected in parallel to the reference feedback node. This network includes capacitors C18, C1, and C2 connected in parallel between the Hall module's constant current input point and GND. Of these three capacitors, the low-value capacitor filters low-frequency power supply ripple, the medium-value capacitor filters intermediate-frequency switching noise, and the high-value capacitor filters high-frequency electromagnetic interference. The equivalent impedance of the three capacitors connected in parallel remains low across a wide frequency band of 10Hz to 100MHz, covering a broad spectrum from low-frequency power supply ripple to high-frequency electromagnetic interference. This ensures the stability of the Hall constant current input node potential and prevents noise from entering the inverting terminal of U2.1 via the VR1-R23 path.

[0095] In some feasible configurations, the +VCC power input terminal is equipped with a positive power surge absorption module, including capacitors C10 and C14 connected in parallel to ground to bypass high-frequency and low-frequency surge currents on the power line, and a bidirectional transient suppression diode D1 connected between +VCC and GND to absorb transient overvoltage spikes on VCC, forming triple protection against surge voltages on the positive power line. The GND power input terminal is equipped with a negative power surge absorption module, including capacitors C5 and C7 connected in parallel to ground to bypass high-frequency and low-frequency noise on the ground loop, and a bidirectional Zener diode D2 connected between GND and a reference low potential to clamp negative transients, forming symmetrical protection against transient interference on the ground loop. A rectifier diode D3 is connected in series in the power input circuit. When the power is reverse-connected, D3 is reverse-biased and cuts off the power circuit, protecting the entire circuit board from reverse connection damage.

[0096] Experimental Example

[0097] Please see Figures 8 to 10 In the full temperature range of -40℃ to 105℃ high and low temperature cycling test, the sensor using the dynamic zero-point compensation method and circuit of the applied open-loop Hall current sensor was compared with the traditional static compensation scheme. The traditional static compensation scheme only uses VR1 for zeroing with a fixed potentiometer. The comparison results are shown in Table 1:

[0098] Table 1: Comparison of zero-point output changes with temperature (based on output = 4.00V at 25℃)

[0099] -40℃ 4.017 (+17 mV) 4.008 (+8mV) 9mV -20℃ 4.012 (+12mV) 4.006 (+6mV) 6mV 0℃ 4.009 (+9mV) 4.006 (+6mV) 3mV 25℃ 4.008 (Base) 4.005 (Base) — 45℃ 3.997 (-3mV) 3.999 (-1mV) 2mV 65℃ 3.989 (-11mV) 3.994 (-6mV) 5mV 85℃ 3.979 (-21mV) 3.994 (-6mV) 15mV 105℃ 3.972 (-28mV) 3.993 (-7mV) 21mV

[0100] From Table 1 above (based on Figure 8 / Figure 9 / Figure 10 (Based on actual screenshots and measured data) it can be seen that the peak-to-peak value of the zero-point deviation of the traditional solution reaches 16mV across the entire temperature range. Figure 10 (Note: ±10mV) The peak-to-peak zero-point deviation of this application solution is only 7mV across the entire temperature range. Figure 10(Note: ±3mV), dynamic compensation improves zero-point temperature drift by approximately 70% compared to static compensation. Combined with... Figure 8 and Figure 9 Regarding the amplitude data, the proposed solution narrows the peak-to-peak amplitude deviation across the entire temperature range from 45mV in the traditional solution to 15mV, representing an amplitude improvement of approximately 67%. In summary, the proposed solution significantly outperforms the traditional solution in both the zero-point and amplitude dimensions, verifying the dynamic compensation mechanism's ability to comprehensively track the temperature characteristics of analog signal links.

[0101] Please see Figure 8 Traditional solutions exhibit significant unidirectional temperature drift at the zero point output across the entire temperature range: the maximum zero-point deviation reaches +10mV (positive) at -40℃ and -6mV (negative) at +105℃, with a peak-to-peak zero-point deviation of 16mV across the entire temperature range. The entire zero-point curve shows an approximately linear and monotonically decreasing trend with increasing temperature, indicating that the compensation amount of the traditional static compensation scheme remains constant and cannot track the direction and magnitude of the zero-point drift caused by temperature changes, resulting in continuous unidirectional insufficient compensation across the entire temperature range.

[0102] After calibration at 25℃, the actual output amplitude of the traditional scheme exhibits an approximately linear and monotonically decreasing trend with temperature: the actual value reaches 4.017V at -40℃ (+17mV relative to the 4.000V calibrated at 25℃), and drops to 3.972V at +105℃ (-28mV), with a peak-to-peak amplitude deviation of 45mV across the entire temperature range. The entire amplitude curve decays approximately linearly with increasing temperature, indicating that the sensitivity of the Hall element and the temperature coefficient of the analog signal link in the traditional scheme are not effectively compensated, resulting in significant gain deviations at the two ends of the temperature range deviating from the 25℃ calibration point. Here, amplitude refers to the true output voltage after deducting the zero-point offset, i.e., the actual value, and peak-to-peak value is the difference between the maximum and minimum values ​​across the entire temperature range.

[0103] Please see Figure 9 The present invention significantly narrows the zero-point output deviation across the entire temperature range: the zero-point deviation is only +4mV (positive) at -40℃ and only -3mV (positive) at +105℃, with a peak-to-peak zero-point deviation of only 7mV across the entire temperature range. The entire zero-point curve remains essentially horizontal across the entire temperature range, without exhibiting a significant monotonic divergence trend. This indicates that the compensation voltage generated after simulation calculation based on the real-time temperature and power supply disturbance information collected by the reference feedback node can effectively track the zero-point drift direction and achieve dynamic cancellation across the entire temperature range.

[0104] After calibration at 25℃, the actual output amplitude deviation of this invention is significantly narrowed across the entire temperature range: the actual value is only 4.008V at -40℃ (+8mV relative to the 4.000V calibrated at 25℃), and only 3.993V at +105℃ (-7mV), with a peak-to-peak amplitude deviation of only 15mV across the entire temperature range. The entire amplitude curve changes smoothly across the entire temperature range without significant monotonic decay. This indicates that the dynamic compensation mechanism in this invention effectively tracks the gain temperature coefficient of the analog signal link while offsetting zero-point drift, thus maintaining stable amplitude output across the entire temperature range.

[0105] Please see Figure 10 Table 2 shows a comparison of the zero-point output curves as a function of temperature between the traditional static compensation scheme and the dynamic compensation scheme of this invention. The traditional scheme exhibits a zero-point drift range of ±10mV across the entire temperature range of -40℃ to +105℃, while the scheme of this invention shows a zero-point drift range of only ±3mV within the same temperature range. The dynamic compensation improves the zero-point drift by approximately 70% compared to the static compensation. Specifically, the traditional scheme has a steep curve slope, with the zero point diverging approximately linearly with temperature; the scheme of this invention has a significantly flatter curve, with a substantial reduction in zero-point drift. The improvement is most significant at the two extreme temperature ranges (-40℃ and +105℃), indicating that the dynamic compensation effect is stronger the further the temperature deviates from the 25℃ calibration point.

[0106] Table 2 Comparison of Results

[0107] Peak-to-peak value of zero-point deviation (-40℃~+105℃) 16mV 7mV Narrowed by approximately 56% Zero-point temperature drift range (rounded) ±10mV ±3mV Approximately 70% Figure 10 (Note) Peak-to-peak amplitude deviation (-40℃~+105℃) 45mV 15mV Narrowed by approximately 67% Overall performance Both the zero-point and amplitude indicators show approximately linear divergence. Both the zero-point and amplitude indicators are trending towards flattening. The dynamic compensation effect is significant.

[0108] Anti-interference tests were also conducted. In a strong EMI environment test with an IGBT switching frequency of 20kHz in the analog inverter, the peak-to-peak noise of the output signal of the built-in filtering scheme of this application was 15mVpp, while that of the traditional front-end RC filtering scheme was 38mVpp, resulting in a noise reduction of about 60%.

[0109] When the measured current range or sensor sensitivity differs, the compensation coefficient can be adjusted. Adjusting the value of the compensation input resistor R6 or R12 allows for rematching of the compensation curve. The calculation basis for R6 is: measured at 25℃. Rate of change with temperature and the drift rate when the sensor zero point is not compensated. ,make This allows the compensation curve and drift curve to achieve optimal matching in the linear segment. For nonlinear drift components, higher-order compensation can be achieved by further refining the resistance ratio (introducing an additional correction branch), further reducing the zero-point temperature drift coefficient to below 25 ppm / ℃. Specifically, a temperature-sensitive feedback element can be introduced into the U2.1 feedback loop—replacing the feedback capacitor C11 of U2.1 with an NTC capacitor or connecting a temperature-sensitive compensation branch consisting of R11-C11 in series in parallel across C11. This utilizes the feedback impedance... Temperature sensitivity directly alters the closed-loop gain of U2.1. The temperature drift characteristics, thus affecting The temperature drift rate of the item is dynamically fine-tuned, and... The synergistic effect of the temperature drift rate of the items enables temperature-sequential compensation for nonlinear drift.

[0110] When the measured current increases, causing the power consumption of the Hall element to increase, the output current of the constant current source can be increased by reducing the resistance value of the sampling resistor R13. At the same time, the resistance ratios of resistors R16, R17, R14, and R15 should be adjusted accordingly to keep the operating point of the parallel reference chip Vz1 unchanged and ensure that the dynamic compensation characteristics are not affected.

[0111] When it is necessary to adjust the gain of the first-stage in-phase amplifier, it can be achieved by modifying the resistance ratio of the feedback resistors R7 and R9 of U1.1 and U1.2 and the input resistors R18~R22.

[0112] Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A dynamic zero-point compensation method for an open-loop Hall current sensor, characterized in that, include: S1. A temperature compensation branch is formed through the PNP type regulating transistor and the temperature compensation resistor. The current in the temperature compensation branch and the reference current branch formed by the reference chip Vz1, the NPN type regulating transistor and the sampling resistor converge to form a total current with a positive temperature coefficient relationship. Total current Power the Hall element and adjust the temperature compensation resistor to match the positive temperature coefficient with the negative temperature coefficient of the Hall element, and perform first-order forward compensation on the Hall element. S2. Using the reference pin REF connected to the reference chip Vz1 as the reference feedback node, the reference pin REF is also connected to the connection node between the emitter of the NPN type regulating transistor and the sampling resistor, and the sensed voltage signal of the reference feedback node is acquired in real time. ; S3, Sensing voltage signal Input to analog computing circuit, according to preset scaling factor Perform addition and subtraction operations to generate compensation voltage. ; S4, adjust the compensation voltage The Hall differential signal, amplified by a two-stage operational amplifier, is subjected to real-time analog differential addition and subtraction mixing operations in the second-stage operational amplifier to output a compensated single-ended current-sensing voltage signal. .

2. The dynamic zero-point compensation method for an open-loop Hall current sensor according to claim 1, characterized in that: S4 includes: S41. The two channels U1.1 and U1.2 of the dual operational amplifier U1 are both in-phase amplification branches, which amplify and condition the differential signals output by the dual Hall elements in in-phase. S42. Through the differential operational structure formed by the operational amplification unit U2.1 in the dual operational amplifier U2, the inverting input terminal of U2.1 receives the output from U1.2, and the non-inverting input terminal of U2.1 receives the output from U1.1, while a compensation voltage is injected. Output compensated single-ended current sensing voltage signal .

3. The dynamic zero-point compensation method for an open-loop Hall current sensor according to claim 2, characterized in that: The first Hall in-phase signal amplified by U1.1 is injected into the in-phase input of U2.1 via a parallel signal transmission path formed by resistors R6 and R12 connected in parallel. The second Hall in-phase signal amplified by U2.1 is injected into the inverting input of U2.1 via resistor R8. The scaling factor... for: in, This is the parallel value of R12 and R6.

4. The dynamic zero-point compensation method for an open-loop Hall current sensor according to claim 3, characterized in that: Connect the adjustable resistor VR1 (connected in series) to the inverting input of U2.1 and the channel of resistor R23. Connect the two ends of the adjustable resistor VR1 to sense voltage signals. The nodes at the same potential and the ground form Provides a static bias adjustment channel, the proportional coefficient for: in, The resistance value is the series resistance of R23 and the adjustable resistor VR1.

5. A circuit, wherein the circuit is the circuit of a dynamic zero-point compensation method for an open-loop Hall current sensor according to any one of claims 1-4, characterized in that, include: The positive temperature coefficient constant current source module includes a parallel reference chip Vz1, a PNP type regulating transistor TR1, an NPN type regulating transistor TR2, a sampling resistor R13, and a bias resistor network R16, R17, R14, and R15. Resistors R17 and R16 are temperature compensation resistors connected in series with the emitter of the PNP type regulating transistor TR1. The reference pin REF of the parallel reference chip Vz1 is connected to the emitter of the NPN type regulating transistor TR2. The connection node between the sampling resistor R13 and the reference feedback node is the reference feedback node. The Hall module includes a first Hall element H1 and a second Hall element H2, and the Hall module is connected to the positive temperature coefficient constant current source module; The differential amplifier module includes a dual operational amplifier U1, which includes non-inverting operational amplifier units U1.1 and U1.

2. The first Hall element H1 and the second Hall element H2 are respectively connected to input resistor networks R19, R20 and input resistor networks R21, R22. The input resistor networks R19, R20 and R21, R22 provide differential voltage signals to U1.1 and U1.2 respectively. The dynamic compensation and output module includes a dual operational amplifier U2, which includes an operational amplification unit U2.1 and a precision resistor network R6, R8, and R12. The output signal of U1.1 is input to the non-inverting input of U2.1 after passing through the parallel resistors R6 and R12, and the output signal of U1.2 is input to the inverting input of U2.1 after passing through R8. The reference feedback node is connected to the inverting input of U2.

1. After generating a compensation voltage, it performs a real-time analog differential operation with the output signals of U1.1 and U1.

2. U2.1 outputs a compensated single-ended voltage signal.

6. The circuit according to claim 5, characterized in that: The output of the operational amplifier unit U2.1 is connected to a built-in RC low-pass filter, which includes a filter resistor R10 and a filter capacitor C15.

7. The circuit according to claim 5, characterized in that: A wideband decoupling network is connected in parallel to the reference feedback node. The wideband decoupling network includes capacitors C18, C1, and C2 connected in parallel between the constant current input point of the Hall module and GND.

8. The circuit according to claim 5, characterized in that: The resistors R19, R20, R21, and R22 have equal resistance values ​​and a matching accuracy of not less than ±0.1%.

9. A circuit according to claim 5, characterized in that: It also includes a static zero-point coarse adjustment network, which includes a resistor R23 connected in series with the inverting input of U2.1 and an adjustable resistor VR1. The resistor R23 is connected to the adjustment terminal of the adjustable resistor VR1. The first terminal of the adjustable resistor VR1 is connected in series with the resistor R1, which is connected to the anode of the reference chip Vz1. The second terminal is connected to the resistor R11, which is grounded.

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