Probe card manufacturing method and probe card

Abstract

The application discloses a probe card manufacturing method and a probe card, and comprises the following steps: providing a multilayer ceramic substrate with a polished surface, etching the polished surface, and forming a circuit pattern groove on the polished surface according to a preset circuit layout; filling the circuit pattern groove with conductive metal, removing the excess conductive metal on the polished surface, and forming an embedded conductive circuit; preparing a metal pad at the end position of the conductive circuit on the polished surface, so that the metal pad is electrically connected with the conductive circuit; growing a metal bump on the metal pad; performing an insulating film treatment on the plane where the polished surface of the multilayer ceramic substrate is located and the metal bump as a whole, and removing the insulating film at the top end of the metal bump; and fixing and electrically connecting the bottom end of the probe beam with the top end of the metal bump. The application can reduce the accumulation of metal particles such as tin slag, and further reduce the risk of short circuit caused by the lapping of the conductive structure of the metal particles under the narrow needle spacing working condition.

Description

Technical Field

[0001] This application relates to the field of chip test device manufacturing technology, and in particular to a method for preparing a probe card and the probe card itself. Background Technology

[0002] As semiconductor chip manufacturing processes become increasingly refined, the density of chip electrode pads continues to increase, making wafer testing increasingly demanding in terms of reducing probe card pin pitch. A probe card mainly consists of probes, a space conversion substrate, and a printed circuit board. The space conversion substrate facilitates pin pitch conversion and signal conduction, and the printed circuit board then aggregates the signals for connection to testing equipment.

[0003] Currently, conventional probe card fabrication often employs surface-level wiring structures, which are ill-suited for high-density wiring requirements. Furthermore, during the solder paste reflow soldering process for pin assembly, impurities such as solder balls, solder dross, and process dust particles are easily generated, and even after cleaning, small amounts remain. These impurities continue to accumulate during subsequent production testing and actual use. The continuously shrinking pin pitch design makes these impurities prone to causing short circuits and other electrical faults between adjacent pins, severely impacting the stability and accuracy of wafer testing operations. Summary of the Invention

[0004] This application aims to provide a method for preparing a probe card and a probe card in order to solve the technical problem that adjacent pins of the probe card are prone to electrical short circuits.

[0005] In a first aspect, this application proposes a method for preparing a probe card, comprising the following steps: A multilayer ceramic substrate with a polished surface is provided. The polished surface is etched to form a circuit pattern groove on the polished surface according to a preset circuit layout. Conductive metal is filled into the circuit pattern groove, and excess conductive metal on the polished surface is removed to form an embedded conductive line. Metal pads are prepared at the ends of the conductive lines on the polished surface to electrically connect the metal pads to the conductive lines. Metal bumps are grown on the metal pads. An insulating film is applied to the plane of the polished surface of the multilayer ceramic substrate and the entire metal bump, and the insulating film at the top of the metal bump is removed. The bottom end of the probe beam is fixed and electrically connected to the top end of the metal bump.

[0006] In some embodiments, before providing a multilayer ceramic substrate with a polished surface, the method further includes: polishing the surface of the multilayer ceramic substrate using a chemical mechanical polishing process, and cleaning the multilayer ceramic substrate to form a polished surface; wherein the roughness of the polished surface is less than 3 μm and the flatness is less than 10 μm.

[0007] In some embodiments, etching is performed on the polished surface to form a circuit pattern groove on the polished surface according to a preset circuit layout, including: coating photoresist on the polished surface and performing soft baking; exposing and developing the photoresist to form a photoresist pattern; performing hard baking reinforcement on the photoresist pattern; etching the polished surface based on the photoresist pattern to form a circuit pattern groove; and removing residual photoresist on the polished surface.

[0008] In some embodiments, filling the circuit pattern groove with conductive metal and removing excess conductive metal from the polished surface includes: electroplating the polished surface to fill the circuit pattern groove with conductive metal and forming a metal layer on the polished surface as a whole; and chemically and mechanically polishing the polished surface to remove the metal layer on the surface of the polished surface, so that the upper surface of the conductive metal in the circuit pattern groove is flush with the polished surface, forming an embedded conductive circuit.

[0009] In some embodiments, a metal pad is prepared at the end position of the conductive line corresponding to the polished surface, including: depositing a metal thin film on the polished surface of a multilayer ceramic substrate by electroplating; and patterning the metal thin film by etching to form a metal pad of a preset shape.

[0010] In some embodiments, growing metal bumps on a metal pad includes: electroplating metal bumps on the surface of the metal pad; wherein the metal bumps include at least a first layer of bumps and a second layer of bumps, the first layer of bumps and the second layer of bumps being stacked sequentially to form a stepped structure.

[0011] In some embodiments, covering the polished surface of the multilayer ceramic substrate and the entire metal bump with an insulating film, and removing the insulating film at the top of the metal bump, includes: depositing an insulating film on the polished surface and the outer surface of the metal bump using a chemical vapor deposition process; spin-coating photoresist on the polished surface, controlling the upper surface of the photoresist to be lower than the top of the metal bump, so that the top of the metal bump is exposed; etching the insulating film at the exposed position of the metal bump top to remove the insulating film at the exposed position; and peeling off the entire photoresist on the polished surface.

[0012] In some embodiments, controlling the upper surface of the photoresist to be lower than the top of the metal bump, so that the top of the metal bump is exposed, includes: controlling the upper surface of the photoresist to be 20 μm to 30 μm lower than the top of the metal bump, so that the top of the metal bump is exposed.

[0013] In some embodiments, fixing and electrically connecting the bottom end of the probe beam to the top end of the metal bump includes: using a reflow soldering process to solder and fix the bottom of the probe beam to the exposed top end of the metal bump with solder paste, so that the probe beam is assembled and connected to the multilayer ceramic substrate and achieves electrical connection.

[0014] Secondly, this application also proposes a probe card, prepared using the probe card preparation method of any embodiment of the first aspect described above. The probe card includes a multilayer ceramic substrate, metal pads, metal bumps, an insulating film, and a probe beam. The multilayer ceramic substrate has a polished surface with embedded conductive lines. The metal pads are disposed on the polished surface and electrically connected to the conductive lines. The metal bumps are disposed on the metal pads. The insulating film covers a portion of the polished surface and the surface of the metal bumps, with the tops of the metal bumps exposed. The bottom of the probe beam is fixed to and electrically connected to the top of the metal bumps.

[0015] The advantages of this application, which differ from existing technologies, are: In the embodiments of this application, a circuit pattern groove is first formed by polishing and etching the multilayer ceramic substrate, and then filled with conductive metal to flatten it, resulting in an embedded conductive circuit. This replaces the traditional exposed surface wiring, optimizes the surface flatness of the multilayer ceramic substrate, reduces the step structure at the interface between the conductive circuit and the multilayer ceramic substrate, and reduces the accumulation of metal particles such as solder dross. This reduces the risk of short circuits caused by metal particles bridging the conductive structure under narrow pin pitch conditions. Based on this, metal pads are prepared at the ends of the embedded conductive circuit to stabilize the electrical connection between the probe beam and the embedded conductive circuit, reduce contact impedance fluctuations, and improve the stability of test signal transmission. Metal bumps are prepared on the metal pads, and the polished surface of the multilayer ceramic substrate and the metal bumps are completely covered with an insulating film, with only the top of the metal bumps exposed. This isolates adjacent conductive structures, reduces electrical interference under narrow pin pitch arrangements, and improves the overall insulation reliability of the probe card. Finally, the probe beam is soldered to the exposed metal bump tops. The insulating film isolates the solder, reduces solder bridging defects, and maintains the stability of the conductive path. In summary, this application adopts an embedded wiring structure, which improves the defects of traditional narrow-pitch probe cards, such as the accumulation of metal particles causing short circuits and the easy damage to conductive structures, thereby optimizing the stability and detection accuracy of wafer testing operations using narrow-pitch probe cards.

[0016] Additional aspects and advantages of the embodiments of this application will be described or shown in part in the following description, or illustrated by practice of the embodiments of this application. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference to the accompanying drawings, which are not intended to limit the embodiments, and elements having the same reference numerals in the drawings are designated as similar elements.

[0018] Figure 1 The flowchart shows a method for preparing probe cards according to some embodiments of this application; Figure 2 This is a step-by-step structural diagram of the fabrication of embedded conductive lines on a multilayer ceramic substrate according to some embodiments of this application; Figure 3This is a three-dimensional schematic diagram of the overall assembly structure of the probe card according to some embodiments of this application; Figure 4 This is a schematic diagram of the step structure of some embodiments of this application, in which metal bumps are covered with an insulating film and the top ends are exposed.

[0019] Explanation of reference numerals in the attached figures: 10. Multilayer ceramic substrate; 11. Circuit pattern groove; 20. Photoresist; 21. Photoresist pattern; 30. Conductive metal; 31. Conductive circuit; 40. Metal bumps; 41. First layer bumps; 42. Second layer bumps; 50. Insulating film; 60. Probe beam; 70. Solder paste. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of this application, but not all embodiments. In this application, the term "embodiment" means that a particular feature, structure, or characteristic commonly described with respect to that embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. In the explanation of the embodiments of this application, technical terms such as "first" and "second" are used to distinguish different objects and should not be construed as indicating or implying relative importance, nor do they mean that the specified technical features have a specific meaning in terms of quantity, specific order, or primary and secondary relationship. In the explanation of the embodiments of this application, "multiple" refers to two or more, unless otherwise explicitly and specifically defined.

[0021] In the description of the embodiments of this application, the term "and / or" is used to describe the relationship between related objects, which can reflect three types of relationships. For example, A and / or B can present the following three situations: only A exists, A and B exist simultaneously, and only B exists. In addition, the character " / " in this document usually means that the related objects before and after are in an "or" relationship; " / " can also represent a proportional relationship; when " / " appears in a table, it can also indicate that the corresponding substance and parameter do not exist, and its specific meaning needs to be determined according to the actual scenario. The technical features described in the different embodiments of this application below can be combined with each other as long as they do not conflict with each other.

[0022] Wafer testing typically relies on probe cards to transmit signals between the test equipment and the wafer chip electrodes. As chip manufacturing processes continue to shrink, the density of chip electrode pads increases, leading to a shrinking gap between adjacent probes on the probe card and a growing demand for narrow-pitch probe cards. Most existing probe cards use multi-level ceramic (MLC) substrates for spatial conversion, with the MLC itself being an integral ceramic insulating substrate. Traditional processing methods typically involve directly fabricating exposed metal lines on the surface of the MLC substrate, resulting in noticeable steps and uneven structures at the interface between the metal lines and the ceramic insulating substrate. When assembling probes, a solder paste reflow soldering process is generally used to solder the probes to the pads on the MLC substrate. This soldering process generates solder dross, solder balls, and other metal particles. Even after cleaning, some particles remain and continue to accumulate during subsequent testing and use. For narrow-pitch structures, these metal particles trapped in the uneven circuitry can easily overlap with adjacent conductive structures, potentially causing short circuits and other malfunctions in the probe card.

[0023] To mitigate the aforementioned problems, firstly, this application proposes a method for preparing a probe card, please refer to... Figure 1 The preparation method includes the following steps: S1: Provide a multilayer ceramic substrate 10 with a polished surface, etch the polished surface, and form a circuit pattern groove 11 on the polished surface according to a preset circuit layout.

[0024] A multilayer ceramic substrate 10 can be used as the space conversion substrate for the probe card. The multilayer ceramic substrate 10 possesses excellent insulation properties and thermal stability, making it a commonly used substrate for narrow-pitch probe cards. The surface of the multilayer ceramic substrate 10 to be processed can be polished using a chemical mechanical polishing (CMP) process. After polishing, a cleaning process is followed to remove dust, grinding debris, and other impurities from the surface of the multilayer ceramic substrate 10, resulting in a highly smooth polished surface. Specifically, the surface roughness is less than 3μm and the flatness is less than 10μm. A smooth and flat polished surface is beneficial for improving the processing accuracy of subsequent etching processes.

[0025] Specifically, the polished surface is etched to form a circuit pattern groove 11 on the polished surface according to a preset circuit layout; this includes: S11: Please refer to Figure 2In step (B), after polishing and cleaning the multilayer ceramic substrate 10, photoresist 20 can be uniformly coated on the polished surface of the multilayer ceramic substrate 10 and then subjected to soft baking. The soft baking operation can improve the bonding strength between the photoresist 20 and the polished surface of the multilayer ceramic substrate 10, reducing the problem of photoresist 20 peeling off during subsequent exposure and development processes. This step optimizes the adhesion of the photoresist 20 through the soft baking process, improves the uniformity and adhesion of the photoresist 20 film layer, and provides a basic condition for high-precision photolithography pattern formation.

[0026] S12: Please refer to Figure 2 In steps (C) and (D), the coated photoresist 20 is sequentially exposed and developed, for example, by using ultraviolet (UV) light to complete the exposure according to the preset circuit layout. Figure 2 (C) indicates the direction of ultraviolet light irradiation. The multilayer ceramic substrate 10 is then immersed in a developing solution for development, peeling off the photoresist 20 corresponding to the circuit pattern area. A photoresist 20 pattern is formed on the polished surface of the multilayer ceramic substrate 10, simultaneously exposing the substrate to be etched. This process replicates the preset circuit layout through exposure and development operations, forming a photoresist 20 mask pattern with clear boundaries, precisely etching the area to be etched, and improving the alignment accuracy of subsequent groove patterns.

[0027] S13: The photoresist 20 pattern remaining after development undergoes hard baking reinforcement treatment. High-temperature baking enhances the hardness and etching resistance of the photoresist 20 pattern, reducing mask damage during subsequent etching processes and improving the integrity of the circuit pattern outline. This process improves the corrosion resistance of the photoresist 20 through high-temperature hard baking, optimizes the structural stability of the photoresist 20, reduces the probability of damage during etching, and ensures the integrity of the circuit pattern outline.

[0028] S14: Please refer to Figure 2 In steps (E) and (F), the reinforced photoresist 20 pattern is used as a mask to etch the polished surface of the multilayer ceramic substrate 10. Areas on the polished surface of the multilayer ceramic substrate 10 not covered by the photoresist 20 are etched, ultimately forming a circuit pattern groove 11 on the polished surface of the multilayer ceramic substrate 10 that matches the preset circuit layout. This process relies on a stable photolithographic mask for point etching, accurately replicating the preset circuit trajectory and forming a circuit pattern groove 11 with uniform size and regular contour, providing an effective cavity structure for the subsequent uniform filling of conductive metal 30.

[0029] S15: After all etching is completed, the residual photoresist 20 on the polished surface of the multilayer ceramic substrate 10 is removed, resulting in a multilayer ceramic substrate 10 with circuit pattern grooves 11. This provides a groove for the next process of filling the circuit pattern grooves 11 with conductive metal 30. This process effectively removes residual photoresist 20 impurities from the surface, optimizes the cleanliness of the substrate surface, reduces the interference of residual adhesive layers on subsequent metal filling processes, and improves the forming quality of subsequent conductive lines 31.

[0030] In step S1 above, circuit pattern grooves 11 for wiring are pre-fabricated inside the multilayer ceramic substrate 10. This differs from the traditional processing method of directly fabricating exposed metal lines on the surface of the multilayer ceramic substrate 10, which can reduce the uneven structure such as steps formed by exposed traces. At the same time, relying on high-precision polishing combined with a complete photolithography etching process, the formed circuit pattern grooves are regular in size and uniform in outline, providing a good foundation for the uniform filling of conductive metal 30 in the subsequent process.

[0031] S2: Fill the circuit pattern groove 11 with conductive metal 30 and remove excess conductive metal 30 from the polished surface to form an embedded conductive line 31. By preparing the conductive line within the circuit pattern groove 11 formed in the multilayer ceramic substrate 10, compared to the traditional exposed surface wiring structure, the conductive line 31 is completely embedded inside the multilayer ceramic substrate 10, keeping the polished surface of the multilayer ceramic substrate 10 intact and flat, reducing the uneven structure caused by the line, thereby reducing the accumulation of metal particles such as tin dross and short circuits, while improving the dimensional accuracy of the conductive line 31.

[0032] Specifically, filling the circuit pattern groove 11 with conductive metal 30 and removing excess conductive metal 30 from the polished surface includes: S21: Please refer to Figure 2 In step (G), the polished surface of the multilayer ceramic substrate 10 is electroplated. The conductive metal 30 can be made of metals with excellent conductivity, such as copper or gold. During the electroplating process, the conductive metal 30 is continuously deposited, completely filling the circuit pattern grooves 11 on the polished surface of the multilayer ceramic substrate 10, and forming a continuous and complete metal layer on the entire polished surface of the multilayer ceramic substrate 10, ensuring that the conductive metal 30 inside the circuit pattern grooves 11 is fully filled without gaps. This process can use electroplating deposition to achieve full filling of the grooves, improve the fullness of the metal filling inside the grooves, reduce forming defects such as voids and material shortages, and ensure the continuity of the conductive path.

[0033] It is understood that filling the circuit pattern groove 11 with conductive metal 30 can be done by means of electroplating, physical vapor deposition, chemical plating, metal paste pressing and sintering and other metallization filling processes. The appropriate solution can be flexibly selected according to the material of the conductive metal 30 and the size and specifications of the groove.

[0034] S22: Please refer to Figure 2 In step (H), the polished surface of the multilayer ceramic substrate 10 is treated with a chemical mechanical polishing process to remove all excess metal layers from the surface of the polished surface of the multilayer ceramic substrate 10 until the upper surface of the conductive metal 30 inside the circuit pattern groove 11 is flush with the polished surface of the multilayer ceramic substrate 10. Finally, a fully embedded conductive line 31 is formed inside the multilayer ceramic substrate 10. This process removes redundant surface metal through a leveling process, achieving flushness between the circuit surface and the substrate surface, optimizing the overall flatness of the multilayer ceramic substrate 10, and reducing the risk of metal particle accumulation such as tin dross in subsequent processes.

[0035] In step S2 above, the conductive line 31 is completely housed inside the circuit pattern groove 11 of the multilayer ceramic substrate 10. Unlike traditional exposed metal wiring processes, the polished surface of the multilayer ceramic substrate 10 after leveling is smooth and flat, without any steps or uneven structures formed by metal lines. This reduces the accumulation of metal particles such as slag generated during soldering, and lowers the risk of short circuits caused by particle overlap conductive structures under narrow pin pitch conditions. At the same time, the circuit pattern groove 11 formed in the previous step S1 has regular boundaries, and the conductive metal 30 is deposited evenly during electroplating. Combined with chemical mechanical polishing and leveling, it can reduce surface protrusions and other processing defects, and improve the overall processing accuracy and yield of the probe card.

[0036] S3: Prepare metal pads at the ends of the conductive lines 31 on the polished surface to electrically connect the metal pads to the conductive lines 31. By preparing metal pads at the ends of each embedded conductive line 31 on the polished surface of the multilayer ceramic substrate 10 with embedded conductive lines 31, an electrical connection port between the conductive lines 31 and the external test probes is formed, achieving stable and reliable electrical connection between the two. This reduces the problem of slag and other metal particles accumulating under narrow-pitch, dense-line conditions, and ensures the stability of electrical signal transmission during subsequent wafer testing of the probe card.

[0037] Specifically, a metal pad is prepared at the end position of the conductive line 31 corresponding to the polished surface, so that the metal pad is electrically connected to the conductive line 31, including: S31: A metal thin film is deposited integrally on the polished surface of the multilayer ceramic substrate 10 by electroplating. The metal thin film has excellent conductivity and solderability, and it is tightly bonded to the end of the embedded conductive line 31 below, achieving preliminary electrical connection. This process can deposit a metal thin film over the entire surface, ensuring complete metal layer coverage at the end of the line, increasing the contact area between the pad and the conductive line 31, reducing contact resistance, and optimizing electrical conductivity. The metal thin film can be made of at least one of copper, nickel, gold, etc.

[0038] S32: After photolithographic patterning of the deposited metal film, the metal film is precisely processed by etching to remove excess metal film in non-pad areas, retaining the metal structure of the preset area at the end of the conductive line 31, and patterning it into a metal pad of a preset shape. This process achieves independent pad forming through patterned etching, standardizes the pad boundaries and dimensions, reduces excess metal residue, and weakens electrical interference between adjacent conductive structures.

[0039] In step S3 above, metal pads are prepared by first electroplating to form a film and then etching to create a pattern. The formed metal pads are regularly sized and make full contact with the ends of the embedded conductive lines 31, effectively reducing contact impedance and ensuring stable transmission of test signals. Simultaneously, the independent distribution of each metal pad strictly limits the diffusion range of solder dross and other metal particles during the soldering process, reducing the risk of short circuits between adjacent pads under narrow pin pitch conditions. Combined with the overall flat surface structure of the multilayer ceramic substrate 10, this effectively reduces the accumulation of solder dross and metal particles, further improving the test yield of narrow pin pitch probe cards.

[0040] S4: Grow metal bumps 40 on the metal pads. By preparing metal bumps 40 on the surface of the metal pads, a contact conductive medium is built between the probe card and the wafer chip under test, realizing stable electrical conduction between the chip and the embedded conductive lines 31.

[0041] Specifically, growing metal bumps 40 on the metal pads includes: S41: Please refer to Figure 3 Electroplating is performed on the surface of the metal pad to deposit the first layer of bumps 41. The first layer of bumps 41 covers the upper surface of the metal pad and fits tightly with the metal pad to achieve electrical connection. This process increases the contact area with the pad by depositing bumps to cover the entire surface, optimizes the stability of the conductive path, and reduces the possibility of poor local contact.

[0042] S42: Continuing with the electroplating process, a second layer of bumps 42 is deposited over the central area of ​​the first layer of bumps 41. The lateral dimension of the second layer of bumps 42 can be set to be smaller than that of the first layer of bumps 41. The two layers are stacked sequentially to form a stepped metal bump structure 40. This process creates a stepped structure that is smaller at the top and larger at the bottom, which optimizes the alignment accuracy of subsequent probes, disperses the pressure stress, and reduces the degree of localized pressure deformation of the substrate and pads.

[0043] In step S4 above, stepped metal bumps 40 are prepared using a layered electroplating method. The lower first layer bumps 41 increase the contact area with the metal pads, reduce contact resistance, and ensure stable conductive paths. The upper second layer bumps 42 reduce the contact end face, which can accurately correspond to the chip electrode points and improve alignment accuracy. The layered stepped structure can disperse the pressure during bonding, buffer the assembly pressure, and effectively reduce pressure damage to the metal pads and embedded conductive lines 31.

[0044] S5: Cover the polished surface of the multilayer ceramic substrate 10 and the entire metal bump 40 with an insulating film 50, and remove the insulating film 50 at the top of the metal bump 40. By completely covering the polished surface of the multilayer ceramic substrate 10, the metal pads, and the sidewalls of the metal bump 40 with an insulating film 50, insulation isolation between adjacent conductive structures is achieved, reducing short circuits between adjacent lines under narrow-pitch dense arrangement; at the same time, only the insulating film 50 at the top of the metal bump 40 is removed, retaining the conductive contact surface at the top of the bump, which ensures the insulation protection effect without affecting the electrical contact between the metal bump 40 and the electrode of the chip under test.

[0045] Specifically, the polished surface of the multilayer ceramic substrate 10 and the entire metal bump 40 are covered with an insulating film 50, and the insulating film 50 at the top of the metal bump 40 is removed. S51: Please refer to Figure 4 In step (b), a chemical vapor deposition process can be used to uniformly deposit an insulating film 50 on the polished surface of the multilayer ceramic substrate 10, the metal pads, and all the outer surfaces of the metal bumps 40, completely covering the sidewalls of all metal conductive structures and the substrate plane. This process can form a continuous insulating protective layer on the surface of all conductive structures, improving the overall insulation performance of the substrate and the metal structure, and reducing the risk of leakage between adjacent conductors.

[0046] The insulating film 50 can be made of dielectric materials with excellent insulating properties, such as silicon dioxide, silicon nitride, or polyimide. For example, a silicon nitride film can be used, which has a dense structure, low water vapor permeability, and good insulation withstand voltage. It can stably coat the multilayer ceramic substrate 10 and the surface of the metal structure, reducing oxidation and water vapor erosion problems during long-term use, and further improving the insulation stability and service life of the narrow-pitch probe card.

[0047] S52: Please refer to Figure 4 In step (c), photoresist 20 is spin-coated onto the polished surface of the multilayer ceramic substrate 10. The coating thickness of the photoresist 20 is precisely controlled, ensuring that the upper surface of the photoresist 20 is 20μm to 30μm below the top of the metal bump 40, thus guaranteeing that the top of the metal bump 40 is completely exposed above the photoresist 20. This process, through the precise height control of the photoresist 20, limits the range of subsequent etching areas, reducing the possibility of accidental etching of the insulating film 50 on the sidewalls of the bumps.

[0048] S53: Please refer to Figure 4In step (d), the insulating film 50 exposed at the top of the metal bump 40 is etched, removing only the insulating film 50 at the top of the metal bump 40, while the insulating film 50 on the sidewalls of the metal bump 40 and the polished surface of the substrate is completely preserved. This process only removes the insulating layer at the contact location, retaining the insulating structure between the sidewalls and the substrate, thus maintaining the overall insulation protection capability while ensuring conductive contact.

[0049] S54: Please refer to Figure 4 In step (e), all photoresist 20 on the polished surface of the multilayer ceramic substrate 10 is peeled off, leaving the insulating film 50 covering the sidewalls and the substrate plane, exposing the tops of the conductive metal bumps 40. This process removes the temporary mask layer, resulting in a well-structured insulating and conductive composite structure with clear functional partitions, improving the product's appearance and process consistency.

[0050] In step S5 above, the entire area is covered by an insulating film 50 and etched with a limiting photoresist 20. The polished surface and the sidewalls of the metal bumps 40 are isolated by the insulating film 50, which can block the leakage path between adjacent conductive structures and improve the insulation reliability under narrow-pitch probe card testing conditions. The photoresist 20 is precisely controlled at a height of 20μm to 30μm to precisely define the etching area, exposing only the contact area at the top of the metal bumps 40. The insulation boundary is regular and controllable, reducing the defects of over-etching of the insulating film 50 and excessive exposure of the sidewall metal. At the same time, the complete insulating film 50 can also isolate air and moisture, slow down the oxidation and corrosion of metal lines and pads, extend the service life of the probe card in cycle testing, and the flat substrate combined with the integrated insulating layer makes it less prone to short circuit failures during long-term use.

[0051] S6: Fix and electrically connect the bottom end of the probe beam 60 to the top end of the metal bump 40. This completes the assembly and fixation of the probe beam 60 and the multilayer ceramic substrate 10, thereby achieving stable electrical conduction between the two and establishing a complete test conductive path.

[0052] Specifically, fixing and electrically connecting the bottom end of the probe beam 60 to the top end of the metal protrusion 40 includes: S61: Please refer to Figure 3 A reflow soldering process can be used. Solder paste 70 is applied to the exposed top of the metal bump 40. The bottom of the probe beam 60 is then aligned and attached to the top of the metal bump 40. The solder paste 70 is melted and solidified by high-temperature reflow, and the probe beam 60 is soldered and fixed to the top of the metal bump 40, completing the assembly and connection of the probe beam 60 with the multilayer ceramic substrate 10 and achieving electrical connection. This process achieves both mechanical fixation and electrical conduction through reflow soldering, improving the assembly firmness of the probe beam 60, reducing contact impedance fluctuations, and maintaining the continuity of signal transmission.

[0053] In step S6 above, the probe beam 60 and the metal bump 40 are connected by reflow soldering. After the solder paste 70 melts, it fills the gaps on the contact surface, resulting in high mechanical bonding strength. It can withstand multiple pressing tests and is not easy to fall off. The metal bump 40 has only its top exposed and its sidewalls are covered with an insulating film 50, which can reduce the occurrence of solder bridging and short circuits between adjacent probe beams 60. It is suitable for the assembly requirements of narrow-pitch high-density probe cards and ensures the stability of wafer testing during long-term operation.

[0054] In the embodiments of this application, a circuit pattern groove is first formed by polishing and etching the multilayer ceramic substrate 10, and then filled with conductive metal 30 to flatten it, resulting in an embedded conductive line 31. This replaces the traditional exposed wiring on the surface, which optimizes the surface flatness of the multilayer ceramic substrate 10, reduces the step structure at the junction of the conductive line 31 and the multilayer ceramic substrate 10, reduces the accumulation of metal particles such as solder dross, and thus reduces the risk of short circuits caused by metal particles overlapping the conductive structure under narrow pin pitch conditions. On this basis, an independent metal pad is prepared at the end of the embedded conductive line 31 to stabilize the electrical connection between the probe beam 60 and the embedded conductive line 31, reduce contact impedance fluctuations, and improve the stability of test signal transmission. Metal bumps 40 are prepared on the metal pads, and the polished surface of the multilayer ceramic substrate 10 and the metal bumps 40 are completely covered with an insulating film 50, with only the top of the metal bumps 40 exposed. This isolates adjacent conductive structures, reduces electrical interference under narrow pin pitch arrangement, and improves the overall insulation reliability of the probe card. Finally, the probe beam 60 is soldered to the top of the exposed metal bump 40. The insulating film 50 isolates the solder, reducing solder bridging defects and maintaining a stable conductive path. In summary, this application adopts an embedded wiring structure, which improves upon the defects of traditional narrow-pitch probe cards, such as the accumulation of metal particles causing short circuits and the susceptibility of conductive structures to damage. This optimizes the stability and testing accuracy of wafer testing operations using narrow-pitch probe cards.

[0055] Secondly, this application also proposes a probe card, which is prepared by the probe card preparation method of any of the embodiments of the first aspect described above. The probe card includes a multilayer ceramic substrate 10, metal pads, metal bumps 40, an insulating film 50, and a probe beam 60.

[0056] The multilayer ceramic substrate 10 serves as the insulating carrier of this probe card. The multilayer ceramic substrate 10 has a smooth, polished surface, within which embedded conductive lines 31 are embedded. The conductive lines 31 are entirely housed within the multilayer ceramic substrate 10, and the polished surface lacks any metal protrusions, reducing the accumulation of dross and other metal particles. Metal pads are formed on the polished surface of the multilayer ceramic substrate 10, and are electrically connected to the ends of the embedded conductive lines 31, serving as transitional connection ports for signal transmission from the conductive lines 31. Metal bumps 40 can be stacked in layers on the metal pads, forming a stepped structure. This increases the contact area with the metal pads and also accommodates the assembly pressing height of the probe beam 60, buffering the mechanical stress generated during pressing. An insulating film 50 completely covers the polished surface of the multilayer ceramic substrate 10 and the sidewalls of the metal bumps 40, leaving only the top areas of the metal bumps 40 exposed. The insulating film 50 provides isolation and protection for adjacent conductive structures, reducing the probability of leakage and particle bridging short circuits under narrow pin spacing. The bottom end of the probe beam 60 is welded and fixed to the exposed top end of the metal bump 40, forming a stable electrical connection between the two, thereby establishing a complete signal transmission path between the wafer under test and the embedded conductive line 31.

[0057] The probe card in this embodiment optimizes the surface flatness of the multilayer ceramic substrate 10 by relying on the embedded conductive line 31 structure, and achieves multiple insulation protection with the insulating film 50. Combined with the stepped metal bumps 40 to disperse assembly stress, it can reduce the probability of short circuit faults under narrow pin pitch conditions, and improve signal transmission stability and product long-term service life.

[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of this application as described above, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for preparing a probe card, characterized in that, Includes the following steps: A multilayer ceramic substrate with a polished surface is provided, the polished surface is etched, and a circuit pattern groove is formed on the polished surface according to a preset circuit layout. The circuit pattern groove is filled with conductive metal, and the excess conductive metal on the polished surface is removed to form an embedded conductive circuit. A metal pad is prepared at the end position of the polished surface corresponding to the conductive line, so that the metal pad is electrically connected to the conductive line; Metal bumps are grown on the metal pads; An insulating film is applied to the polished surface of the multilayer ceramic substrate and the entire metal bump, and the insulating film at the top of the metal bump is removed. The bottom end of the probe beam is fixed and electrically connected to the top end of the metal protrusion.

2. The method for preparing the probe card according to claim 1, characterized in that, Before providing a multilayer ceramic substrate with a polished surface, the method further includes: The surface of the multilayer ceramic substrate is polished using a chemical mechanical polishing process, and the multilayer ceramic substrate is then cleaned to form the polished surface; wherein the roughness of the polished surface is less than 3 μm and the flatness is less than 10 μm.

3. The method for preparing the probe card according to claim 1, characterized in that, The etching process on the polished surface, forming circuit pattern grooves on the polished surface according to a preset circuit layout, includes: Photoresist is applied to the polished surface and then subjected to a soft baking process. The photoresist is exposed and developed to form a photoresist pattern; The photoresist pattern is subjected to hard baking for reinforcement. The polished surface is etched based on the photoresist pattern to form the circuit pattern groove; Remove any residual photoresist from the polished surface.

4. The method for preparing the probe card according to claim 1, characterized in that, The step of filling the grooves of the circuit pattern with conductive metal and removing excess conductive metal from the polished surface includes: The polished surface is electroplated so that the conductive metal fills the grooves of the circuit pattern and forms a metal layer on the entire polished surface; The polished surface is subjected to chemical mechanical polishing to remove the metal layer on the surface of the polished surface, so that the upper surface of the conductive metal in the circuit pattern groove is flush with the polished surface, forming an embedded conductive circuit.

5. The method for preparing the probe card according to claim 1, characterized in that, The step of preparing a metal pad at the end position of the polished surface corresponding to the conductive line includes: A metal thin film is deposited on the polished surface of the multilayer ceramic substrate by electroplating. The metal film is patterned by etching to form the metal pad of a preset shape.

6. The method for preparing the probe card according to claim 1, characterized in that, The process of growing metal bumps on the metal pads includes: Metal bumps are electroplated and grown on the surface of the metal pads; wherein the metal bumps include at least a first layer of bumps and a second layer of bumps, and the first layer of bumps and the second layer of bumps are stacked in sequence to form a stepped structure.

7. The method for preparing the probe card according to claim 1, characterized in that, The process of covering the polished surface of the multilayer ceramic substrate and the entire metal bump with an insulating film, and removing the insulating film from the top of the metal bump, includes: An insulating film is deposited on the polished surface and the outer surface of the metal bumps using a chemical vapor deposition process. Photoresist is spin-coated onto the polished surface, and the upper surface of the photoresist is controlled to be lower than the top of the metal bump, so that the top of the metal bump is exposed. The insulating film at the exposed position of the metal bump tip is etched to remove the insulating film at the exposed position; The photoresist on the polished surface is completely peeled off and removed.

8. The method for preparing the probe card according to claim 7, characterized in that, Controlling the upper surface of the photoresist to be lower than the top of the metal bump, so that the top of the metal bump is exposed, includes: The upper surface of the photoresist is controlled to be 20 μm to 30 μm lower than the top of the metal bump, so that the top of the metal bump is exposed.

9. The method for preparing a probe card according to claim 1, characterized in that, The step of fixing and electrically connecting the bottom end of the probe beam to the top end of the metal protrusion includes: A reflow soldering process is used to solder the bottom of the probe beam to the exposed top of the metal bump using solder paste, so that the probe beam is assembled and connected to the multilayer ceramic substrate and achieves electrical connection.

10. A probe card, characterized in that, The probe card is prepared by the method described in any one of claims 1 to 9, and the probe card comprises: A multilayer ceramic substrate has a polished surface, on which conductive lines are embedded. Metal pads are disposed on the polished surface and electrically connected to the conductive lines; Metal bumps are provided on the metal pads; An insulating film covers a portion of the polished surface and the metal bumps, with the tips of the metal bumps exposed. The probe beam is fixed and electrically connected at its bottom to the top of the metal protrusion.

Images