A current effective value sampling method and system suitable for servo driver PWM control

Abstract

The application belongs to the technical field of servo drive control, and particularly discloses a current effective value sampling method and system suitable for PWM control of a servo driver, which comprises the following steps: sampling and modulating a motor current signal to obtain a single-bit stream; performing cross-clock domain processing on the single-bit stream; performing dynamic sliding window Sinc filtering on the single-bit stream after the cross-clock domain processing; sliding the sliding window on the single-bit stream after the cross-clock domain processing, and performing Sinc filtering operation on the single-bit data in the sliding window at each position to obtain a first intermediate digital signal; performing sliding window averaging on the first intermediate digital signal to obtain a second intermediate digital signal; and obtaining the current effective value based on the second intermediate digital signal in each PWM control period. The application can output high-precision current effective value in each PWM control period, and has low data delay, strong anti-overflow capability and remarkable noise suppression effect.

Description

Technical Field

[0001] This invention belongs to the field of servo drive control technology, and more specifically, relates to a current effective value sampling method and system suitable for servo driver PWM control. Background Technology

[0002] As a core component of motor control, the servo drive's control performance directly determines the motor's motion accuracy, response speed, and operational stability. Current sampling is the foundation of servo drive closed-loop control, and the accuracy, real-time performance, and completeness of the sampled signal are crucial prerequisites for achieving high-precision motor control and rapid dynamic response.

[0003] Currently, current sampling schemes for servo drives generally employ instantaneous value sampling or use traditional fixed-decimation Sinc filters to process the bitstream output from the Sigma-Delta ADC modulator. Instantaneous value sampling cannot reflect the true equivalent value of the current throughout the entire PWM cycle; it can only reflect the current state at a certain moment and cannot characterize the true equivalent characteristics of the current over a control cycle. Traditional fixed-decimation Sinc filters only output a valid value once at the decimation moment, resulting in data updates lagging by at least one decimation cycle. Under conditions such as motor start-up, rapid acceleration, and sudden load changes, current peaks can easily cause intermediate variable overflow in the filter. Furthermore, insufficient sampling frequency can easily lead to signal aliasing and distortion, making it difficult to capture dynamic changes in current; limited sampling accuracy can lead to the accumulation of control errors. These problems collectively mean that traditional sampling methods are no longer sufficient to meet the high-performance control requirements of high-end servo systems. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the prior art, the present invention provides a current effective value sampling method and system suitable for servo driver PWM control, the purpose of which is to improve the accuracy of current effective value sampling.

[0005] To achieve the above objectives, according to a first aspect of the present invention, a current RMS value sampling method suitable for servo driver PWM control is proposed, comprising the following steps: The motor current signal is sampled and modulated to obtain a single bit stream; Perform cross-clock domain processing on a single bit stream; Dynamic sliding window Sinc filtering is performed on the single bit stream after cross-clock domain processing: a sliding window is used to slide on the single bit stream after cross-clock domain processing, and Sinc filtering is performed on the single bit data in the sliding window at each position to obtain the first intermediate digital signal. The first intermediate digital signal is averaged using a sliding window to obtain the second intermediate digital signal; Within each PWM control cycle, the effective value of the current is obtained based on the second intermediate digital signal.

[0006] As a further preferred option, when performing Sinc filtering on single-bit data within the sliding window, a third-order Sinc filter is specifically used.

[0007] As a further preferred option, when performing third-order Sinc filtering, the intermediate variables and the final output bit width are increased by at least 2 bits compared to the theoretical minimum bit width.

[0008] As a further preferred option, the motor current signal is oversampled and modulated using a Sigma-Delta ADC modulator to obtain a single bit stream.

[0009] As a further preferred option, cross-clock domain processing of the single bit stream includes: using an asynchronous FIFO combined with a Gray code pointer synchronization mechanism to transmit the single bit stream from the modulator clock domain to the digital controller clock domain through a cross-clock domain circuit.

[0010] As a further preferred embodiment, within each PWM control cycle, the effective value of the current is obtained based on the second intermediate digital signal, including: squaring the second intermediate digital signal, averaging the squared second intermediate digital signal using a sliding window, and then taking the square root of the averaging result to obtain the effective value of the current.

[0011] As a further preferred embodiment, when the effective value of the current is obtained based on the second intermediate digital signal, the effective value of the current is updated in real time each time the sliding window slides, and latched output is performed at the boundary of the PWM control cycle.

[0012] As a further preferred embodiment, when performing sliding window averaging on the first intermediate digital signal and on the second intermediate digital signal after square processing, the length of the sliding window is equal to the number of sampling points corresponding to one PWM control cycle.

[0013] According to a second aspect of the present invention, a current RMS value sampling system suitable for servo driver PWM control is provided, comprising a processor for executing the above-described current RMS value sampling method suitable for servo driver PWM control.

[0014] According to a third aspect of the present invention, a servo driver PWM control method is provided, wherein the servo driver realizes motor closed-loop control based on the effective current value obtained by the above-described current effective value sampling method applicable to servo driver PWM control.

[0015] In summary, compared with the prior art, the above-described technical solutions conceived by this invention mainly possess the following technical advantages: 1. This invention utilizes cross-clock domain data transmission processing to effectively improve the frequency of current sampling, and achieves higher-precision oversampling through dynamic Sinc filtering and sliding window averaging. This effectively reduces the noise of current sampling, realizes high-precision current acquisition, and fully meets the technical requirements of high-end servo systems for sampling the effective value of current under PWM control.

[0016] 2. The novel dynamic Sinc filter designed in this invention has the real-time performance of dynamic window. By utilizing the sliding window mechanism, the filter always processes continuously updated data, resulting in low data latency. This avoids the data lag problem of traditional static filtering and can improve the accuracy of current RMS sampling.

[0017] 3. The third-order Sinc filter used in this invention has a strong ability to suppress high-frequency noise; and further, it reserves two redundant bits in its output bit width, which not only ensures that the intermediate accuracy is not lost during the filtering process, but also can cope with current peak working scenarios such as motor start-up and load change, avoid data overflow, and has better long-term stability than traditional 16-bit ADC solutions.

[0018] 4. This invention, through high-precision oversampling processing and subsequent sliding window averaging algorithm, can further reduce the amplitude of residual quantization noise that has not been thoroughly processed by the filter, and can also eliminate the influence of occasional data anomalies at individual sampling points on the sampling of the overall current effective value, further avoiding control errors caused by a single anomaly.

[0019] 5. This invention employs cross-clock domain processing, which avoids the instability that may occur when low-speed ADC data is processed in the high-speed FPGA domain, leading to data errors and system crashes. By utilizing the asynchronous FIFO's read / write dual-ended RAM separation mechanism, the low-speed domain data is temporarily stored and then read at the required rate by the FPGA's high-speed domain. This allows the system to adapt to rapid current changes, preventing data overflow or loss. Attached Figure Description

[0020] Figure 1 This is a flowchart of a current effective value sampling method applicable to servo driver PWM control according to an embodiment of the present invention.

[0021] Figure 2 This is a flowchart illustrating the cross-clock domain processing logic of an embodiment of the present invention.

[0022] Figure 3 This is a schematic diagram of the dynamic sliding window averaging process in an embodiment of the present invention. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0024] This invention provides a current RMS sampling method suitable for servo driver PWM control, such as... Figure 1 As shown, it includes the following steps: (1) The motor current signal is oversampled using a Sigma-Delta ADC modulator to obtain a single bit stream.

[0025] Specifically, an analog signal representing the phase current of the motor is obtained through a current sampling circuit, and then oversampled and noise shaped by a Sigma-DeltaADC modulator to obtain a single-bit data stream.

[0026] (2) Perform cross-clock domain processing on single bit streams.

[0027] Specifically, since the Sigma-Delta modulator typically operates in the modulator clock domain and the FPGA control module operates in another clock domain, when processing across clock domains, the single bit stream is transmitted from the modulator clock domain to the digital controller clock domain through a cross-clock domain circuit.

[0028] Furthermore, cross-clock domain processing employs an asynchronous FIFO combined with a Gray code pointer synchronization mechanism to safely and efficiently transmit low-speed ADC data to the high-speed domain of the FPGA, avoiding metastability issues caused by simultaneous transitions of multiple bits.

[0029] (3) Perform dynamic sliding window Sinc filtering on the single bit stream after cross-clock domain processing to obtain the first intermediate digital signal.

[0030] Specifically, the dynamic sliding window Sinc filtering method works as follows: a sliding window slides across the single-bit stream processed across clock domains; each time a new single-bit data is input, it is added to the sliding window, and the oldest historical data in the window is removed. Then, a complete Sinc filtering operation is performed on the single-bit data in the window. Compared with the traditional method of block decimation according to the decimation rate and outputting only once at the decimation time, the filter of this invention updates and outputs the result once for each input.

[0031] The window length of the dynamic sliding window Sinc filter is the number of single-bit sampling points corresponding to the Sinc filter decimation rate M. M is determined based on the oversampling rate of the Sigma-Delta ADC modulator and the target output sampling rate. In this embodiment, M=128.

[0032] Furthermore, the Sinc filter specifically employs a third-order Sinc filter, which, compared to a first-order Sinc filter, offers stronger high-frequency noise suppression, higher output current resolution, and smoother filtered digital signals; making it more suitable for high-noise PWM environments such as motor current sampling. The third-order Sinc filter can filter out high-frequency quantization noise generated by Sigma-Delta modulation, converting high-speed single-bit streams into low-speed multi-bit digital signals, and improving current measurement resolution through window accumulation.

[0033] Furthermore, the intermediate variables and final output bit width of the third-order Sinc filter are increased by at least 2 bits compared to the theoretical minimum bit width, reserving 2 bits of redundancy to prevent overflow caused by instantaneous peak values ​​during motor startup or sudden load changes.

[0034] (4) Perform a sliding window average on the first intermediate digital signal to obtain the second intermediate digital signal.

[0035] Specifically, the first intermediate digital signal still exhibits PWM switching ripple, residual quantization noise, sampling jitter, local spikes, and small fluctuations between control cycles. Therefore, a second intermediate digital signal, which is a more stable current sampling sequence, is obtained by further smoothing through a sliding window. Each time a new first intermediate digital signal sample value is obtained, this new sample value is added to the sliding window, and the oldest sample value within the window is discarded. The average result of the sample values ​​within the window is updated recursively to obtain the second intermediate digital signal.

[0036] (5) In each PWM control cycle, the effective value of the current is obtained based on the second intermediate digital signal.

[0037] Specifically, the effective value of the current is the root mean square (RMS) value. Therefore, during the PWM control cycle, the second intermediate digital signal is squared, and the squared signal is then averaged using a sliding window. Finally, the square root of the average result is taken to obtain the effective current value. The effective current value is updated in real time with each sliding window update and latched at the boundary of the PWM control cycle. This latched value serves as the effective current value output for the corresponding PWM cycle.

[0038] Furthermore, when performing sliding window averaging in steps (4) and (5), the window length is the number of sampling points corresponding to one PWM control cycle, specifically the number of sampling points of the digital signal after Sinc filtering.

[0039] The present invention provides a servo driver PWM control method, comprising: obtaining the current effective value of the current in the current PWM cycle by using the above-mentioned current effective value sampling method, and using the current effective value to realize motor closed-loop control of the servo driver.

[0040] The following are specific examples: This embodiment uses a Sigma-Delta ADC with a built-in clock frequency of 20MHz, which is divided into a Sigma sampling integration stage, a Delta comparison quantization stage, and a 1-bit DAC feedback modulation stage. Through oversampling and noise shaping, the PWM analog voltage signal obtained by the three-phase current of the motor through the sampling resistor is converted into a high-resolution single-bit pulse sequence, i.e., Sigma-Delta modulation code.

[0041] In CDC cross-clock domain processing, mechanisms such as asynchronous FIFO double-ended RAM buffering, Gray code pointer synchronization, and empty / full state detection are utilized, for example... Figure 2 As shown, the dual-port RAM has two independent ports, completely isolating read and write operations. The write port is driven by a 20MHz clock. Each clock edge triggers a single-bit modulation code output by the ADC, which is written to a designated address in the RAM. Simultaneously, the write pointer increments synchronously and is converted via a binary-to-Gray code module. To prevent FIFO overflow, the "full state detection module" determines whether the RAM is full based on the synchronized write pointer Gray code. If full, it disables the "write enable control," pausing data writing. The read port is driven by a 125MHz clock. The read pointer Gray code is transmitted to the FPGA-side "empty state detection module" via a "write clock domain two-stage synchronizer." Based on the synchronized read pointer Gray code, it determines whether the dual-port RAM is empty. If not empty, it enables the "read enable control," allowing data to be read from the RAM's read port, thus achieving secure data transfer from the 20MHz clock domain to the 125MHz clock domain.

[0042] The dynamic sliding window Sinc filter removes the oldest data entry in the window and adds the newest data entry each time it extracts data. The extracted data must match the ADC oversampling rate; therefore, a sampling rate of 128 is selected. The Sinc filter order is 3, and the filter input bit width is 1 bit. The minimum bit width of the intermediate variable in the sinc3 filter is calculated using the following formula:

[0043] Where Bout is the output variable bit width (theoretical minimum bit width), N is the Sinc filter order, M is the Sinc filter decimation rate, and Bin is the filter input bit width.

[0044] 125 can be obtained in each sampling period A total of 128 22-bit high-resolution, low-rate, high-precision digital signals were extracted. Here, the scheme of this invention reserves a 24-bit redundancy design to prevent data overflow.

[0045] like Figure 3 As shown, in order to further suppress random noise in current sampling, a high-precision oversampling process is designed to reduce the PWM period to 125. The data was evenly divided into 256 parts, and a sliding window update strategy was adopted. Each time the oldest original sample data in the window was removed, the latest data was added, and the data was continuously averaged.

[0046] Applying the above method to a practical servo driver, high-precision real-time output of the effective current value was achieved within each PWM control cycle.

[0047] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for sampling the effective value of current suitable for PWM control of a servo driver, characterized in that, Includes the following steps: The motor current signal is sampled and modulated to obtain a single bit stream; Perform cross-clock domain processing on a single bit stream; Dynamic sliding window Sinc filtering is performed on the single bit stream after cross-clock domain processing: a sliding window is used to slide on the single bit stream after cross-clock domain processing, and Sinc filtering is performed on the single bit data in the sliding window at each position to obtain the first intermediate digital signal. The first intermediate digital signal is averaged using a sliding window to obtain the second intermediate digital signal; Within each PWM control cycle, the effective value of the current is obtained based on the second intermediate digital signal.

2. The current RMS sampling method for servo driver PWM control as described in claim 1, characterized in that, When performing Sinc filtering on single-bit data within a sliding window, a third-order Sinc filter is specifically used.

3. The current RMS sampling method for servo driver PWM control as described in claim 2, characterized in that, When performing a third-order Sinc filter operation, the intermediate variables and the final output bit width are increased by at least 2 bits compared to the theoretical minimum bit width.

4. The current RMS sampling method for servo driver PWM control as described in claim 1, characterized in that, The motor current signal was oversampled and modulated using a Sigma-Delta ADC modulator to obtain a single bit stream.

5. The current RMS sampling method for servo driver PWM control as described in claim 1, characterized in that, Cross-clock domain processing of single bit streams includes: using an asynchronous FIFO combined with a Gray code pointer synchronization mechanism to transmit the single bit stream from the modulator clock domain to the digital controller clock domain through a cross-clock domain circuit.

6. The current RMS sampling method for servo driver PWM control as described in any one of claims 1-5, characterized in that, Within each PWM control cycle, the effective value of the current is obtained based on the second intermediate digital signal, including: squaring the second intermediate digital signal, averaging the squared second intermediate digital signal using a sliding window, and then taking the square root of the averaging result to obtain the effective value of the current.

7. The current RMS sampling method for servo driver PWM control as described in claim 6, characterized in that, When the effective value of the current is obtained based on the second intermediate digital signal, the effective value of the current is updated in real time each time the sliding window slides, and latched and output at the boundary of the PWM control cycle.

8. The current RMS sampling method for servo driver PWM control as described in claim 6, characterized in that, When performing a sliding window average on the first intermediate digital signal and on the second intermediate digital signal after square processing, the length of the sliding window is equal to the number of sampling points corresponding to one PWM control cycle.

9. A current RMS sampling system suitable for servo driver PWM control, characterized in that, Includes a processor for executing the current RMS sampling method for servo driver PWM control as described in any one of claims 1-8.

10. A servo driver PWM control method, characterized in that, The servo driver uses the effective current value obtained by the current effective value sampling method applicable to servo driver PWM control as described in any one of claims 1-8 to achieve closed-loop control of the motor.

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