DDR dynamic current test method, system, and storage medium

Abstract

The application discloses a DDR dynamic current test method, system and storage medium. The method comprises the following steps: collecting differential voltage and extracting a state vector by using an active interference suppression circuit, adjusting a digital controllable resistance-capacitance network physical noise elimination and outputting an analog baseband voltage signal; establishing a step code set based on a background current distribution, compressing and packaging sampling data by binary short code mapping, and issuing; decompression recovers discrete sampling points, substitutes into the physical differential residual equation based on the parasitic parameters of the power distribution network, and analyzes and optimizes to reconstruct the continuous state time analytical function and generate the test current value; monitoring the optimization characteristic vector, calculating the dynamic fluctuation fingerprint based on the multi-dimensional space moving track oscillation characteristics and the steady-state baseline dynamic confidence interval width, and determining the probe abnormality and intercepting the test value and triggering the re-pressing if the dynamic fluctuation fingerprint exceeds the standard; if there is no abnormality, the reverse solution is performed in the chip internal physical leakage propagation topology adjacency matrix to locate the leakage position.

Description

Technical Field

[0001] This application belongs to the field of semiconductor integrated circuit chip testing and failure analysis technology, specifically relating to a DDR dynamic current testing method, system and storage medium. Background Technology

[0002] During the testing and failure analysis of high-speed double-data-rate synchronous dynamic random access memory (DDR SDRAM), the chip generates drastic transient dynamic currents when switching between different instruction modes at high speeds. Accurately capturing the peaks and evolution characteristics of these dynamic currents is a key means to evaluate the chip's power consumption barrier and locate internal physical leakage faults.

[0003] However, existing DDR dynamic current testing systems have the following problems in actual mass production and yield analysis: Limited testing accuracy and lack of traceability: In high-speed testing environments, the power distribution network (PDN) formed between the chip, package, and test load board has complex parasitic parameter effects, which cause severe passivation and distortion of the signals acquired by the external analog-to-digital converter (ADC). Traditional testing methods cannot reverse the actual transient current inside the chip, nor can they directly convert the external current waveform into the physical failure traceability of the specific layout location inside the chip.

[0004] Data stream quality and transmission are mutually restrictive: High-frequency continuous acquisition generates massive amounts of test data, causing the internal transmission bus of the test system to face a significant bandwidth throughput bottleneck. At the same time, dynamic contact anomalies caused by probe mechanical stress or oxide layer during test operation can easily lead to numerical distortion during reconstruction. However, existing technologies lack self-diagnostic interception mechanisms during operation, resulting in false failure data severely polluting the chip yield analysis chain.

[0005] Therefore, how to reduce bus transmission bandwidth pressure, eliminate PDN parasitic network interference, and achieve operational self-diagnosis of probe contact status, thereby transforming pure leakage characteristics into accurate tracing of internal physical failures, is a technical challenge that urgently needs to be solved in the current semiconductor packaging and testing field. Summary of the Invention

[0006] To achieve the above-mentioned objective, this application provides a DDR dynamic current testing method. The method utilizes the measurement path of an external testing machine, which includes a shunt resistor, an active interference suppression circuit, and an analog-to-digital converter connected in sequence. The method includes the following steps: The differential voltage signal across the shunt resistor is acquired using the active interference suppression circuit, and the state vector is extracted. Based on this, the digitally controllable RC network in the active interference suppression circuit is adjusted to physically cancel the test noise and output an analog baseband voltage signal. The physical distribution law of the standby background current is used to establish the exponent set and determine the steady-state baseline current value. The floating-point sampling data of the analog baseband voltage signal converted by the analog-to-digital converter is compressed, packaged into a compressed data packet, and then sent down through the data bus. The compressed data packet is decompressed to recover the discrete sampling points, which are then used as boundary conditions in the physical differential residual equation constructed based on the parasitic parameters of the power supply distribution network for analytical optimization, so as to reconstruct the continuous-state time analytical function and generate the test current value. The optimization feature vector of the parameters during the analysis optimization process is monitored. Based on the oscillation characteristics of the movement trajectory of the optimization feature vector in the multi-dimensional space, combined with the dynamic confidence interval width of the steady-state baseline current value, a dynamic fluctuation fingerprint characterizing the physical contact quality is calculated. When the dynamic fluctuation fingerprint exceeds the preset interception threshold, it is determined that the probe contact is abnormal, so as to intercept the generated test current value and trigger a hardware interrupt instruction to drive the external test machine to re-press. If the probe contact is not determined to be abnormal, the steady-state baseline current value is subtracted from the test current value of the chip under test in multiple test modes to construct a differential leakage feature vector. This vector is then injected into a preset chip internal physical leakage propagation topology adjacency matrix for reverse weight allocation iteration to determine the physical leakage location inside the chip. Based on the physical leakage location, the external mechanical sorting machine is driven to perform physical compartmenting.

[0007] In some preferred embodiments, adjusting the digitally controllable RC network in the active interference suppression circuit accordingly includes: The differential voltage signal is acquired and a fast Fourier transform is performed to obtain the frequency domain amplitude distribution vector; The frequency domain amplitude distribution vector is converted into a state probability vector as the state vector through multi-layer matrix multiplication; The state vector is mapped to a target impedance adjustment parameter using a preset mapping matrix, and the target impedance adjustment parameter is configured as an impedance tuning parameter for the digitally controllable RC network to perform the adjustment.

[0008] In some preferred embodiments, establishing the exponent set includes: using the pre-calculated standard deviation of the standby background current samples, and based on a preset interval coverage target value, integrating the normal distribution probability density function of the standby background current to output multiple consecutive exponent values ​​that can cover the preset sample probability boundary as the exponent set.

[0009] In some preferred embodiments, compressing the floating-point sampled data of the analog baseband voltage signal after conversion by the analog-to-digital converter includes: The floating-point sampled data is divided into a sign bit, an octet exponent segment, and a significant digit segment by binary short code mapping. If the exponent value of the floating-point sampled data belongs to the exponent set, then the eight-bit exponent segment is replaced with a binary short code of a preset number of bits, wherein the code length of the preset number of bits is less than eight bits. If the exponent value of the floating-point sampled data does not belong to the exponent set, an escape identifier is assigned and the original eight-bit exponent segment is then completely concatenated to form an outlier bypass.

[0010] In some preferred embodiments, the parasitic parameters in the physical differential residual equation constructed based on the parasitic parameters of the power distribution network include the equivalent parasitic inductance, equivalent series resistance, and decoupling capacitor of the test load board; the physical differential residual equation is a second-order linear differential equation established based on Kirchhoff's voltage and current laws, reflecting the instantaneous current consumption inside the chip and the external node voltage collected by the analog-to-digital converter.

[0011] In some preferred embodiments, the step of substituting the result into the physical differential residual equation constructed based on the parasitic parameters of the power supply distribution network for analytical optimization to reconstruct the continuous-state time analytical function and generate the test current value includes: By calculating the mean square error term of the physical differential residual equation at each of the discrete sampling points, a mean square error residual scalar function is generated as the residual objective function. With the direction of finding the extreme value of the residual objective function as the optimization guide, the parameters to be optimized are updated during the numerical iteration process until the residual objective function is less than the preset engineering tolerance threshold. Based on the updated parameters to be optimized, the continuous-state time analytical function is reconstructed. By differentiating the continuous-state time-analytical function, points where the derivative is zero and the second derivative is negative are extracted as transient current spikes to generate the test current value.

[0012] In some preferred embodiments, calculating the dynamic fluctuation fingerprint based on the optimized feature vector includes: Calculate the spatial geometric rotation angle of the optimization feature vector between two adjacent numerical iteration steps, as the oscillation feature of the movement trajectory; Obtain the confidence interval that characterizes the fluctuation of the steady-state baseline current value based on the time series covariance, and extract the width of the confidence interval as the width of the dynamic confidence interval; The product of the spatial geometric rotation angle and the width of the confidence interval is used as the dynamic fluctuation fingerprint.

[0013] In some preferred embodiments, the preset chip internal physical leakage current propagation topology adjacency matrix is ​​based on the physical layout design of the chip under test. Independent functional hardware units that consume current inside the chip are defined as topology nodes, and the physical connections of charge transfer when switching different test instructions are defined as directed edges with a clear physical flow direction to establish the adjacency matrix.

[0014] To achieve the above-mentioned objectives, this application also provides a DDR dynamic current testing system, the system comprising: The front-end purification module is used to acquire the differential voltage signal across the shunt resistor through an active interference suppression circuit connected in series between the shunt resistor and the analog-to-digital converter, extract the state vector, and adjust the impedance parameters of the digitally controllable RC network accordingly to physically cancel the test noise and output the analog baseband voltage signal. The hardware compression module is used to determine the steady-state baseline current value based on the physical distribution law of the standby background current, and to compress the floating-point sampled data of the analog baseband voltage signal after it has been converted by the analog-to-digital converter, package it into a compressed data packet and send it down through the test bus. The differential reconstruction module is used to receive and decompress the compressed data packet to recover the discrete sampling points, and substitute them as boundary conditions into the physical differential residual equation constructed based on the parasitic parameters of the power supply distribution network for analytical optimization, so as to reconstruct the continuous-state time analytical function and generate the test current value. The feature interception module is used to monitor the parameter optimization feature vector in the parsing optimization process and calculate the dynamic fluctuation fingerprint. When the dynamic fluctuation fingerprint exceeds the preset interception threshold, it is determined that the probe contact is abnormal, so as to intercept the generated test current value. At the same time, a hardware interrupt command is sent to the external test equipment to drive the external test equipment to perform the probe re-pressing action. The failure tracing module is used to construct a differential leakage current feature vector based on the test current value under multiple test modes and the steady-state baseline current value when the probe contact is not determined to be abnormal. The vector is then injected into a preset chip internal physical leakage current propagation topology adjacency matrix for reverse weight allocation iteration to determine the physical leakage current location inside the chip. Based on the physical leakage current location, the module sends a compartment control command to the external mechanical sorting machine to drive the external mechanical sorting machine to perform physical compartmenting action.

[0015] To achieve the above-mentioned objectives, this application also provides a computer-readable storage medium storing a computer program thereon, characterized in that the computer program, when executed by a processor, implements the DDR dynamic current testing method described in any of the above claims. Attached Figure Description

[0016] To more clearly illustrate the solution of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a DDR dynamic current testing method provided in an embodiment of this application.

[0018] Figure 2 This is a block diagram of a DDR dynamic current testing system provided in one embodiment of this application. Detailed Implementation

[0019] The technical solutions in this application will be clearly and completely described below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0020] Before providing a detailed description of the method in this application, the hardware environment on which the method depends will be described first.

[0021] The method described in this application operates on an external testing machine. This external testing machine is an automated testing device widely used in semiconductor mass production testing, and it is internally configured with a measurement path for acquiring the dynamic current of the DDR chip. This measurement path consists of a shunt resistor, an active interference suppression circuit, and an analog-to-digital converter connected in series. Specifically, the shunt resistor is a high-precision resistor with micro-ohms, connected in series in the power supply circuit of the DDR chip under test. When the chip consumes current, a differential voltage signal proportional to the current is generated across the shunt resistor. This differential voltage is then fed into the active interference suppression circuit.

[0022] The active interference suppression circuit is a key component of the hardware platform of this application. This circuit is connected in series between the shunt resistor and the analog-to-digital converter, and internally integrates a sensing node, an operational amplifier circuit, and a digitally controllable RC network. The sensing node is used to acquire the weak differential voltage across the shunt resistor; the operational amplifier circuit generates a reverse compensation current to cancel test noise; the digitally controllable RC network includes a capacitor array with capacitance values ​​adjustable from 10 picofarads to 500 nanofarads and a switchable feedback resistor network, controlled by digital logic, capable of dynamically adjusting the resonant frequency and phase margin of the compensation circuit according to the test conditions. Through the synergistic effect of the above structures, the active interference suppression circuit can physically cancel the non-stationary high-frequency switching noise superimposed in the test environment in the analog domain, thereby outputting a clean analog baseband voltage signal to the subsequent stages.

[0023] As an optional hardware implementation example, the analog-to-digital converter (ADC) in this embodiment can employ a 16-bit high-precision device, with a sampling rate set, for example, to 100 million times per second. Those skilled in the art should understand that the specific quantization bit depth (e.g., 12-bit, 14-bit, 16-bit) and sampling rate of the ADC can be flexibly configured based on the actual clock frequency and testing accuracy of the DDR chip, and are not limited thereto. The input terminal of the ADC is electrically connected to the output terminal of the active interference suppression circuit, used to convert the analog baseband voltage signal into discrete floating-point sampled data, which is then fed into the subsequent field-programmable gate array (FPGA).

[0024] The field-programmable gate array (FPGA) is electrically connected to the output of the analog-to-digital converter (ADC). Internally configured with hardware compression logic, it enables real-time lossless compression of discrete data streams. The compressed data packets are transmitted to a host computer via a data bus. The host computer, electrically connected to the FPGA via the data bus, receives and decompresses the compressed data packets, then performs calculations such as transient spike reconstruction, probe contact anomaly detection, and failure physics root cause analysis. Furthermore, the host computer stores pre-defined prior data such as the chip's internal physical leakage current propagation topology adjacency matrix and the baseline current value of good chips.

[0025] The external testing equipment is also equipped with a testing equipment controller and test probes. The testing equipment controller is electrically connected to the host computer and can receive hardware interrupt commands sent by the host computer, and drive the test probes to perform mechanical actions according to the commands. The test probes are used to form physical electrical contact with the pads or bumps of the DDR chip under test. Driven by the controller, they can perform operations such as pressing down, lifting up, and re-pressing. At the same time, the current signal of the chip is introduced into the above measurement path through the traces on the test load board.

[0026] In addition, this application also relates to an external mechanical sorting machine. This mechanical sorting machine is not an external testing machine, but is electrically connected to a host computer via a communication interface to receive sorting control commands sent by the host computer, and accordingly drive the robotic arm to place the chips into the corresponding physical sorting trays.

[0027] It should be noted that the aforementioned shunt resistor, active interference suppression circuit, analog-to-digital converter, FPGA, host computer, test platform controller, and test probes together constitute the physical hardware resources required to execute the method of this application. The method of this application completes the testing process by calling these hardware resources. Specifically, the system of this application, namely the front-end purification module, hardware compression module, differential reconstruction module, feature interception module, and failure tracing module described below, is deployed on the aforementioned FPGA and host computer, and is a collection of logical functions running on the hardware platform. Those skilled in the art should understand that the physical deployment carrier of the above modules is not limited to this. In other alternative embodiments, each module can also be fully integrated into a single application-specific integrated circuit (ASIC), system-on-a-chip (SoC), or distributed cloud test server, which does not affect the implementation of its logical function combination. Figure 2 The system described in this application is within the dashed box. The external DDR testing equipment and external mechanical sorting machine are outside the dashed box.

[0028] Similarly, those skilled in the art should understand that the external test equipment can be an independent general-purpose test platform or integrated with the DDR dynamic current test system in the same physical cabinet or sorting station, which does not affect the scope of protection of this application.

[0029] The following provides a detailed description of each step of the method described in this application.

[0030] See Figure 1 , Figure 1 This is a flowchart illustrating a DDR dynamic current testing method according to an embodiment of this application. The method includes the following steps: S101: The front-end active interference suppression circuit acquires the differential voltage signal and extracts the state vector, adjusts the digital controllable resistor-capacitor network to physically cancel the noise, and outputs the analog baseband voltage signal.

[0031] The method of this application first uses an active interference suppression circuit connected in series between the shunt resistor and the analog-to-digital converter to acquire the differential voltage signal across the shunt resistor, extract the state vector, and adjust the digitally controllable RC network in the active interference suppression circuit accordingly to physically cancel the test noise and output an analog baseband voltage signal.

[0032] Specifically, a voltage-sensing active interference suppression circuit is connected in series between a micro-ohm high-precision shunt resistor and the input of a 16-bit high-precision analog-to-digital converter. This circuit includes a sensing node for acquiring the weak differential voltage across the shunt resistor, an operational amplifier circuit providing reverse compensation current, and a digitally logic-controlled RC network within the compensation circuit. This RC network comprises a digitally controllable injected capacitor array with capacitance values ​​adjustable from 10 picofarads to 500 nanofarads.

[0033] The controller acquires the interference voltage signal at the current test time step in real time and performs a fast Fourier transform on it to extract the frequency domain amplitude distribution vector. Through multi-layer matrix multiplication, the original high-dimensional frequency domain amplitude vector is mapped to a mean vector and a standard deviation vector, and a low-dimensional probability state space that strictly follows a normal distribution is reconstructed as the state vector.

[0034] Then, a discrete action space is established, including the switching of the digitally controllable injected capacitor array and the resistance switching of the operational amplifier loop feedback resistor. The controller calculates the joint mapping function between the current state and each selectable action, outputs a set of optimal discrete control quantities from the action space, and sends them to the active interference suppression circuit to change its low-frequency cutoff frequency and phase margin, thereby physically canceling the switching noise at the current frequency.

[0035] To enable those skilled in the art to fully reproduce the process of converting the frequency domain amplitude distribution vector into a state probability vector (i.e., the state vector) through multi-layer matrix multiplication, the following outlines the essential calculation steps of the core mapping algorithm in this embodiment: First, let the frequency domain amplitude distribution vector obtained by the aforementioned steps through Fast Fourier Transform (FFT) be the input vector X ∈ R. N×1 , where N is the dimension of the frequency domain features. The multi-layer matrix multiplication is implemented by constructing a two-layer feedforward mapping topology network.

[0036] First-level matrix multiplication (hidden layer mapping): The frequency domain amplitude distribution vector X is injected into a preset first-level weight matrix W1∈R. M×N Perform a linear transformation and accumulate the first-level bias vector B1∈R. M×1 Then, a nonlinear transformation is performed using an activation function σ(.) with nonlinear compact support properties to output the hidden layer feature vector H ∈ R. M×1 The calculation process satisfies the following formula (1): H = σ ( W1·X + B1 ).

[0037] Second-level matrix multiplication (probability space mapping): The hidden layer feature vector H is injected into a preset second-level weight matrix W2 ∈ R. 2K×MA second mapping is performed, and the second-level bias vector B2 ∈ R is accumulated. 2K×1 To output a low-dimensional parameterized vector Y ∈ R 2K×1 The calculation process satisfies the following formula (2): Y = W2 · H + B2 Wherein, the first K dimensions of the low-dimensional parameterized vector Y are defined as the mean feature vector μ ∈ R. K×1 The K-dimensional data is defined as the logarithm of the standard deviation eigenvector log(σ). 2 ) ∈ R K×1 .

[0038] Finally, the mean eigenvector μ and the logarithmic eigenvector log(σ) of the standard deviation are used to... 2 A low-dimensional probability state space that strictly follows a multivariate normal distribution is reconstructed, and the sampling boundary probability vector in this probability space is used as the state vector (state probability vector) S ∈ R. K×1 .

[0039] Furthermore, after obtaining the state vector S, the system calls a preset mapping matrix M ∈ R. L×K Through linear product operation: Z = M·S Calculate the target impedance adjustment parameter Z ∈ R L×1 The target impedance adjustment parameter Z comprises L sets of discrete hardware control words, which are directly configured as impedance tuning parameters for the digitally controllable RC network to drive the capacitor switching of the internal numerically controlled capacitor array to perform corresponding discrete actions, thereby physically canceling test noise in the analog domain. Through the explicit analytical solution of the above-mentioned multi-layer matrix multiplication, this application achieves a high-precision and robust mapping from macroscopic frequency domain noise to microscopic hardware impedance control parameters while ensuring the real-time performance of hardware tuning.

[0040] Within each control cycle, the controller uses the residual noise amplitude at the output of the active interference suppression circuit, read after issuing the action command and maintaining a predetermined physical stabilization time, as the evaluation criterion. The voltage value corresponding to one quantization step of the 16-bit high-precision analog-to-digital converter is used as the target threshold. If the current action suppresses the residual high-frequency noise amplitude below the quantization step voltage value, the logarithmic attenuation ratio before and after filtering is calculated and assigned as a positive utility value to the action; if the residual noise is still higher than the quantization step voltage value, a fixed negative constant is output as a penalty utility value.

[0041] To prevent the matrix optimization process from getting stuck in local deadlock, a random perturbation factor (such as a random exploration probability of 2.5%) is forcibly injected in the action instruction selection step, allowing the system to try non-optimal capacitor switching combinations in the early stages. Subsequently, the controller uses the difference between the utility values ​​of the current time step and the previous time step (i.e., the timing difference error) to update the weight parameters of the action utility function matrix using gradients. When the positive utility values ​​received by the system tend to stabilize and converge over multiple consecutive test instruction cycles, the current weight matrix and the digitally controllable injected capacitor settings are immediately locked.

[0042] Through the above steps, the method of this application, without relying on pre-set fixed low-pass filter parameters, can dynamically match a pure transmission channel with extremely high attenuation characteristics for the current parasitic noise frequency band and no phase shift for low-frequency real abrupt signals, using only millisecond-level calibration overhead, every time the test conditions are switched (such as changing the memory read / write frequency or changing the test temperature). At this time, the active interference suppression circuit outputs an analog baseband voltage signal to the subsequent 16-bit high-precision analog-to-digital converter, which has been freed from high-frequency non-stationary interference and retains only the real leakage current and transient waveforms.

[0043] S102: Establish an exponent set based on the physical distribution law of background current to determine the steady-state baseline current value, compress the floating-point sampling data after analog-to-digital converter conversion through binary short code mapping, and package it into a compressed data packet for distribution.

[0044] The method of this application then uses the physical distribution law of the standby background current to establish an exponent set and determine the steady-state baseline current value. The floating-point sampling data of the analog baseband voltage signal converted by the analog-to-digital converter is compressed, packaged into a compressed data packet, and then sent down through the data bus.

[0045] In mass production testing of memory chips, to accurately reproduce real nanosecond-level extreme current spikes in subsequent steps, the 16-bit analog-to-digital converter must always maintain a high-frequency limit operation of 100 MSps (100 million samples per second). Before the test program issues high-frequency burst read / write commands, the memory chip is in an active standby state or a pre-charge standby state. At this time, the base signal sampled across the shunt resistor only contains the chip's semiconductor static leakage current and the basic thermal noise of the test environment. Physical thermodynamics and the characteristics of semiconductor transistors determine that the fluctuation amplitude of this static background current strictly follows a normal distribution.

[0046] After receiving fixed-point data from a 16-bit analog-to-digital converter, the field-programmable gate array (FPGA) first converts it into a binary data structure conforming to the standard floating-point specification. This involves dividing the data at each sampling point into a sign bit, an eight-bit exponent segment, and a significant digit segment. Because the background current follows a normal distribution, it exhibits extreme exponent value concentration in the floating-point data structure. That is, the amplitude fluctuations of most background noise are only reflected in the flipping of the significant digit segment, while the value of the exponent segment is highly concentrated within a very few fixed values.

[0047] This application uses deterministic mathematical partial derivative calculations instead of dynamic histogram statistics. Since the data follows a normal distribution, the field-programmable gate array (FPGA) pre-calculates the sample standard deviation of the standby background current and directly integrates the normal distribution probability density function of the standby background current based on a preset interval coverage target value, outputting multiple consecutive exponent values ​​that can cover more than 97% of the sample probabilities as a high-frequency exponent set.

[0048] As data flows through the transmit pipeline of the field-programmable gate array (FPGA), parallel pure hardware bit operations are performed to complete compression. Hardware registers split the incoming 16-bit floating-point data, storing the sign bit and significant digits intact into a fixed-step contiguous storage area, ensuring complete losslessness of underlying physical noise and weak transient details. A hardware comparator judges the separated exponent segment: if the exponent value belongs to one of the seven locked high-frequency exponents, the original eight-bit exponent is mapped to a binary short code of a preset number of bits. The preset number of bits is strictly less than eight bits to achieve deterministic bit-width hard simplification at the underlying hardware structure; if the exponent value is not in the high-frequency set, bypass logic is triggered, assigning it a special escape flag (e.g., 000 indicating an anomaly), and then completely concatenating the original eight-bit exponent after the flag.

[0049] As a preferred and optimal implementation method, in this embodiment, the code length of the preset number of bits is specifically set to a three-bit binary short code (for example, using 000 to 110 to correspond to seven high-frequency order codes respectively). In this case, the method of this application transforms the originally large and irregular analog-to-digital converter output stream into an asymmetric structure code stream based on the physical rule of normal current distribution, which strictly constrains the code stream, thus forcibly reducing the volume of invalid order code redundancy by more than 31%.

[0050] Those skilled in the art should understand that the specific code length of the preset number of bits is not limited thereto. Depending on the test accuracy or the coverage of the normal distribution boundary, the preset number of bits can also be flexibly configured to four bits, five bits, or any other short code length as long as it is less than the original eight-bit width. As long as the short code width is less than the original eight bits, the data transmission bandwidth bottleneck between the high-speed analog-to-digital converter and the host computer can be eliminated by reducing the redundant volume of the invalid exponent, and all of these fall within the protection scope of this application.

[0051] S103: Receives and decompresses data packets to restore discrete sampling points, substitutes them into the physical differential residual equation based on the parasitic parameters of the power supply distribution network for analytical optimization, reconstructs the continuous-state time function and differentiates it to generate the test current value.

[0052] The method of this application then decompresses the compressed data packet to recover the discrete sampling points, substitutes them into the physical differential residual equation constructed based on the parasitic parameters of the power supply distribution network for analytical optimization, in order to reconstruct the continuous-state time analytical function and generate the test current value.

[0053] In burst read tests of memory chips, the physical duration of the real current spikes generated by the rapid charge transfer within the internal memory array is only two to three nanoseconds. However, the maximum sampling rate of a conventional 16-bit analog-to-digital converter on an automated test bench is typically limited to 100 million times per second (i.e., one sampling interval of ten nanoseconds). According to the Nyquist sampling theorem, such sparse, low-frequency discrete sampling will directly miss transient extrema.

[0054] In order to extract the true extrema without upgrading expensive hardware, the method in this application adopts a reverse reconstruction method based on physical equations.

[0055] First, in the host computer computing unit, based on the printed circuit board stack-up information and chip packaging specifications of the test load board, the exact equivalent parasitic inductance of the traces, equivalent series resistance, and decoupling capacitance between the test socket and the chip are extracted. Based on Kirchhoff's voltage and current laws, a second-order linear differential equation is established between the actual instantaneous current consumed inside the chip and the external node voltage acquired by the analog-to-digital converter, serving as the physical differential residual equation.

[0056] Secondly, to address the magnitude gradient difference of tens of thousands or even hundreds of thousands of times between the actual burst read / write peak current and the smooth standby background current, a step first derivative of a Gaussian wavelet function with tight support characteristics (i.e., only locally non-zero) is introduced as the basic mapping unit (i.e., basis function) for constructing the continuous current curve. This physical and mathematical property enables high-fidelity reconstruction within time intervals containing drastic local abrupt changes (i.e., nanosecond-level peaks) without introducing unnecessary high-frequency oscillation noise on the global time axis.

[0057] Then, by calculating the mean square error term of the physical differential residual equation at each discrete sampling point, a mean square error residual scalar function is generated as the residual objective function. The low sampling rate, noisy discrete digital voltage sampling points obtained after decompression are substituted into the residual objective function as strong boundary constraints. The method of this application abandons the inefficient computational graph chain-style automatic differentiation mechanism, and directly puts the pre-derived Gaussian wavelet analytical derivative formula into the host computer processor. With the direction of finding the extremum of the residual objective function as the optimization guide, a numerical iterative optimization algorithm is started (as a preferred option, a finite memory quasi-Newton numerical iterative algorithm is used in this embodiment; in other parallel embodiments, any one of the Gauss-Newton algorithm, Levenberg-Marquardt algorithm, or momentum-based gradient descent iterative algorithm can also be used), dynamically adjusting the scale scaling factor (directly determining the physical width of the reconstructed current peak) and the time axis translation factor (directly determining the exact nanosecond moment when the peak appears) of the Gaussian wavelet basis function. The iterative process continues to approach the direction of decreasing the residual objective function until the value of the residual objective function is less than the preset engineering tolerance threshold.

[0058] Once the residual objective function has converged, the host computer system outputs no longer a set of discrete data points and their smoothed connections, but a continuous-state time-dependent analytical function expression that strictly follows the physical dynamics of charge transfer in the circuit system. By performing differentiation on this continuous-state analytical function, points where the derivative is zero and the second derivative is negative (i.e., local maxima) are extracted as transient current spikes to generate test current values.

[0059] S104: Monitor the optimization feature vector of the parameters during the analytical optimization process, and based on the oscillation characteristics of the movement trajectory of the optimization feature vector in the multi-dimensional space, combined with the dynamic confidence interval width of the steady-state baseline current value, calculate the dynamic fluctuation fingerprint characterizing the physical contact quality, and determine whether the dynamic fluctuation fingerprint exceeds the preset interception threshold.

[0060] In large-scale automated testing of memory chips, the physical probes on the test fixtures are repeatedly pressed down mechanically at extremely high frequencies, inevitably resulting in tip wear, oxide layer accumulation, and microscopic mechanical bouncing. This poor physical contact can cause random charge injection in the test circuit, creating high-amplitude spurious voltage spikes in the sampled data of the analog-to-digital converter. If, during the residual equation reconstruction in the previous stage, the system blindly approximates all extreme points, this mechanical contact noise will be misinterpreted as genuine excessive leakage current within the chip, leading to the false rejection of many good chips.

[0061] To address this issue, the method in this application monitors parameter changes in real time during the iterative process of analytical optimization to extract the optimization feature vector. Specifically, in each iteration of the numerical iterative algorithm, the scaling factor and time axis translation factor of the wavelet basis function are recorded, and the parameter combinations of each iteration are arranged according to the iteration sequence to construct a multidimensional parameter optimization feature vector.

[0062] In a normal charge transfer process that conforms to the physical laws of power distribution networks, the movement path of the optimization feature vector in multidimensional space should exhibit a smooth characteristic with a clear convergence direction, meaning its trajectory oscillation characteristic is at an extremely low level. If the sudden spike is caused by the actual gate circuit flipping inside the chip, its electrical change is limited by the energy storage and release laws of the capacitors and inductors inside the chip, and the direction change of the parameter optimization feature vector in multidimensional space is gradual. As a specific quantitative manifestation of the trajectory oscillation characteristic, the spatial geometric rotation angle between adjacent iteration steps is extremely small at this time.

[0063] Conversely, if the spike is caused by electromagnetic radiation or a sudden change in contact resistance due to the instantaneous mechanical bounce of an external probe, it exhibits an infinite rate of change of current on the time axis, completely ignoring the current-limiting characteristics of the inductor. In this case, in order to force the fitting of the random non-physical abrupt signal with physical equations, the parameter optimization feature vector of the numerical algorithm will undergo violent oscillations and reversals in multidimensional space. That is, in the macroscopic form, it manifests as an abnormal surge in the oscillation characteristics of the movement trajectory, and in the microscopic mathematical solution, it is specifically manifested as an extremely abnormal deviation in the spatial geometric rotation angle between adjacent iteration steps.

[0064] Meanwhile, to eliminate the impact of temperature drift within the high and low temperature test chamber on the base current, a fixed static threshold cannot be used; the dynamic confidence interval width must be dynamically updated in real time. When continuously testing multiple chips, the host computer extracts the background current value of each chip in steady-state standby mode as the historical sequence input. A time-series covariance matrix update algorithm is used for statistical analysis, and the reference current confidence interval for dynamic drift at the current batch test temperature is calculated and output in real time. The physical span of this confidence interval is taken as the dynamic confidence interval width.

[0065] Finally, the method of this application calculates in real time the spatial geometric rotation angle between adjacent iteration steps (as the oscillation feature of the movement trajectory of the optimization feature vector in multidimensional space), and the product of the width of the dynamic baseline confidence interval calculated based on the temporal covariance (as the width of the dynamic confidence interval), and uses the product result as the dynamic fluctuation fingerprint characterizing the physical contact quality.

[0066] S105: If the above product exceeds the interception threshold, it is determined that the probe contact is abnormal, the generated test current value is intercepted, and a hardware interrupt instruction is triggered to drive the test machine to re-press.

[0067] Based on the actual yield and error tolerance of the production line (e.g., setting a maximum false positive probability parameter), a strict interception threshold is pre-calculated. The calculated dynamic fluctuation fingerprint is compared with this interception threshold: if it exceeds the threshold, the test program immediately triggers an adaptive rejection mechanism, discards the currently acquired extreme current data, and sends a hardware interrupt control command to the external test equipment on the lower-level computer, forcing the mechanical arm of the equipment to lift up and perform probe cleaning or re-execute the micron-level alignment mechanical pressing action on the current test chip, and then restarts data acquisition.

[0068] S106: If the above product does not exceed the interception threshold, the difference between the test current value and the steady-state baseline current value is used to generate a differential leakage current feature vector, which is then injected into the internal physical leakage current propagation topology adjacency matrix for reverse weight allocation iteration.

[0069] S107: Determine the topology node whose cumulative weight exceeds the preset threshold as the internal physical leakage location, and drive the mechanical sorting machine to perform physical compartmenting action based on this.

[0070] If the probe contact is not determined to be abnormal, the method of this application subtracts the steady-state baseline current value from the test current value of the chip under test in multiple test modes respectively to construct a differential leakage feature vector, injects it into the preset chip internal physical leakage propagation topology adjacency matrix for reverse weight allocation iteration, so as to determine the physical leakage location inside the chip, and drives the external mechanical sorting machine to perform physical compartmenting action based on the physical leakage location.

[0071] In traditional mass production testing of memory chips, when a dynamic or static current exceeds the limit, the automated testing equipment can only output a Boolean failure signal, rendering the chip unusable. However, a chip contains billions of transistors, and the equipment only indicates an excessive current, without being able to determine whether the leakage is occurring in the row address decoder, column sensitive amplifier, or core capacitor array. Traditional methods of locating the problem rely on destructive unpacking and time-consuming low-light microscopy scanning.

[0072] In this application, the method pre-establishes a structured physical leakage current propagation topology map in the host computer memory based on the physical layout design of the DDR chip under test. Independent functional hardware units that consume current within the chip are defined as topology nodes, including: address decoding buffer units, word line driver units, column sensitive amplifiers, core memory capacitor arrays, and data input / output driver units. The physical connections for charge transfer during different test instruction switching are defined as directed edges with a clear physical flow direction, and an adjacency matrix is ​​established.

[0073] During the execution of the automated test program, the testing equipment outputs a complete set of basic current test items according to the JEDEC international standard. The method in this application extracts the measured current values ​​of the currently failed chip under various standard test modes, such as standby current, activation backup current, burst read current, and automatic refresh current. These measured values ​​are subtracted from the standard baseline values ​​of good chips to obtain a multi-dimensional differential leakage current feature vector. This vector reflects the amount of abnormal charge that the chip draws from the external pins to the power network under different physical operating conditions.

[0074] Since the excessive external current is the result of leakage current superimposed from multiple internal hardware units, the method in this application uses the aforementioned differential leakage current feature vector as boundary input and performs inverse calculation on the topological adjacency matrix. Specifically, the input vector containing the leakage current difference of multiple modes is subjected to iterative matrix multiplication with the topological adjacency matrix representing the internal circuit connection relationship. During each matrix multiplication, the excessive current difference is weighted and redistributed according to the proportion of parasitic resistance of each node in the physical layout. After two to three predetermined matrix multiplication iterations, the abnormal current increment measured by the external pin will mathematically converge and accumulate in large quantities on one or two specific topological nodes. The method in this application calculates the accumulated leakage current distribution weight of each topological node at this time. The node with the largest absolute deviation of the weight value from the mean is the fundamental physical structural source of physical short circuit or gate breakdown.

[0075] The host computer system converts the calculated maximum weight node into an accurate engineering physical description output, such as directly generating a structured record in the test report. Based on this physical root-finding result, the method in this application then sends a sorting control command to the mechanical sorting machine on the lower-level computer via a universal serial bus. Instead of a simple binary sorting of good / defective products, it drives a robotic arm to place chips that have failed due to different failure types (such as decoder leakage, core array leakage, etc.) into the corresponding physical sorting trays.

[0076] This application also provides a DDR dynamic current testing system, see reference. Figure 2 ,include: The front-end purification module 10 is used to acquire the differential voltage signal across the shunt resistor through an active interference suppression circuit connected in series between the shunt resistor and the analog-to-digital converter, extract the state vector, and adjust the impedance parameters of the digitally controllable RC network accordingly to physically cancel the test noise and output the analog baseband voltage signal. The hardware compression module 20 is used to determine the steady-state baseline current value based on the physical distribution law of the standby background current, and to compress the floating-point sampled data of the analog baseband voltage signal after it has been converted by the analog-to-digital converter. Specifically, it performs lossless compression operations such as retaining the sign bit and replacing the eight-bit exponent segment belonging to the exponent set with a preset number of binary short codes with a code length of less than eight bits. After packaging and generating a compressed data packet, it is sent down through the test bus. The differential reconstruction module 30 is used to receive and decompress the compressed data packet to recover the discrete sampling points, and substitute them as boundary conditions into the physical differential residual equation constructed based on the parasitic parameters of the power supply distribution network for analytical optimization, so as to reconstruct the continuous-state time analytical function and generate the test current value. The feature interception module 40 is used to monitor the parameter optimization feature vector in the parsing optimization process and calculate the dynamic fluctuation fingerprint. When the dynamic fluctuation fingerprint exceeds the preset interception threshold, it is determined that the probe contact is abnormal, so as to intercept the generated test current value. At the same time, a hardware interrupt command is sent to the external test machine to drive the external test machine to perform the probe re-pressing action. The failure tracing module 50 is used to construct a differential leakage current feature vector based on the test current value under multiple test modes and the steady-state baseline current value when the probe contact is not determined to be abnormal. The vector is then injected into a preset chip internal physical leakage current propagation topology adjacency matrix for reverse weight allocation iteration to determine the physical leakage current location inside the chip. Based on the physical leakage current location, the module sends a compartment control command to the external mechanical sorting machine to drive the external mechanical sorting machine to perform physical compartmenting action.

[0077] The specific implementation methods of each of the above modules correspond one-to-one with the steps of the aforementioned method, and will not be repeated here.

[0078] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the DDR dynamic current testing method described in any of the preceding claims. The storage medium includes, but is not limited to, ROM, RAM, hard disk, solid-state drive, USB flash drive, optical disk, etc.

[0079] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of those different embodiments or examples.

[0080] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0081] In this application, unless otherwise stated, directional terms such as "up" and "down" are generally used in relation to the direction shown in the accompanying drawings, or in relation to the vertical, perpendicular, or gravitational direction; similarly, for ease of understanding and description, "left" and "right" are generally used in relation to the left and right shown in the accompanying drawings; "inner" and "outer" refer to the inner and outer contours of each component itself, but the above directional terms are not intended to limit this application.

[0082] The above description is merely an exemplary embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope described in this application, and these should all be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for testing dynamic current of DDR, characterized in that, The method utilizes the measurement path of an external testing machine for testing. The measurement path includes a shunt resistor, an active interference suppression circuit, and an analog-to-digital converter connected in sequence. The method includes: The differential voltage signal across the shunt resistor is acquired using the active interference suppression circuit, and the state vector is extracted. Based on this, the digitally controllable RC network in the active interference suppression circuit is adjusted to physically cancel the test noise and output an analog baseband voltage signal. The physical distribution law of the standby background current is used to establish the exponent set and determine the steady-state baseline current value. The floating-point sampling data of the analog baseband voltage signal converted by the analog-to-digital converter is compressed, packaged into a compressed data packet, and then sent down through the data bus. The compressed data packet is decompressed to recover the discrete sampling points, which are then substituted into the physical differential residual equation constructed based on the parasitic parameters of the power distribution network for analytical optimization in order to reconstruct the continuous-state time analytical function and generate the test current value. The optimization feature vector of the parameters during the analysis optimization process is monitored. Based on the oscillation characteristics of the movement trajectory of the optimization feature vector in the multi-dimensional space, combined with the dynamic confidence interval width of the steady-state baseline current value, a dynamic fluctuation fingerprint characterizing the physical contact quality is calculated. When the dynamic fluctuation fingerprint exceeds the preset interception threshold, it is determined that the probe contact is abnormal, so as to intercept the generated test current value and trigger a hardware interrupt instruction to drive the external test machine to re-press. If the probe contact is not determined to be abnormal, the steady-state baseline current value is subtracted from the test current value of the chip under test in multiple test modes to construct a differential leakage feature vector. This vector is then injected into a preset chip internal physical leakage propagation topology adjacency matrix for reverse weight allocation iteration to determine the physical leakage location inside the chip. Based on the physical leakage location, the external mechanical sorting machine is driven to perform physical compartmenting.

2. The method according to claim 1, characterized in that, The adjustment of the digitally controllable RC network in the active interference suppression circuit accordingly includes: The differential voltage signal is acquired and a fast Fourier transform is performed to obtain the frequency domain amplitude distribution vector; The frequency domain amplitude distribution vector is converted into a state probability vector as the state vector through multi-layer matrix multiplication; The state vector is mapped to a target impedance adjustment parameter using a preset mapping matrix, and the target impedance adjustment parameter is configured as an impedance tuning parameter for the digitally controllable RC network to perform the adjustment.

3. The method according to claim 1, characterized in that, The establishment of the exponent set includes: using the pre-calculated standard deviation of the standby background current samples, and based on a preset interval coverage target value, integrating the normal distribution probability density function of the standby background current to output multiple consecutive exponent values ​​that can cover the preset sample probability boundary as the exponent set.

4. The method according to claim 1, characterized in that, The compression of the floating-point sampled data of the analog baseband voltage signal after conversion by the analog-to-digital converter includes: The floating-point sampled data is divided into a sign bit, an octet exponent segment, and a significant digit segment by binary short code mapping. If the exponent value of the floating-point sampled data belongs to the exponent set, then the eight-bit exponent segment is replaced with a binary short code of a preset number of bits, wherein the code length of the preset number of bits is less than eight bits. If the exponent value of the floating-point sampled data does not belong to the exponent set, an escape identifier is assigned and the original eight-bit exponent segment is then completely concatenated to form an outlier bypass.

5. The method according to claim 1, characterized in that, In the physical differential residual equation constructed based on the parasitic parameters of the power distribution network, the parasitic parameters include the equivalent parasitic inductance, equivalent series resistance, and decoupling capacitor of the test load board; the physical differential residual equation is a second-order linear differential equation established based on Kirchhoff's voltage and current laws, reflecting the instantaneous current consumption inside the chip and the external node voltage collected by the analog-to-digital converter.

6. The method according to claim 5, characterized in that, The process of substituting the equation into the physical differential residual equation constructed based on the parasitic parameters of the power supply distribution network for analytical optimization, in order to reconstruct the continuous-state time analytical function and generate the test current value, includes: By calculating the mean square error term of the physical differential residual equation at each of the discrete sampling points, a mean square error residual scalar function is generated as the residual objective function. With the direction of finding the extreme value of the residual objective function as the optimization guide, the parameters to be optimized are updated during the numerical iteration process until the residual objective function is less than the preset engineering tolerance threshold. Based on the updated parameters to be optimized, the continuous-state time analytical function is reconstructed. By differentiating the continuous-state time-analytical function, points where the derivative is zero and the second derivative is negative are extracted as transient current spikes to generate the test current value.

7. The method according to claim 1, characterized in that, The dynamic fluctuation fingerprint characterizing the physical contact quality is calculated by combining the oscillation characteristics of the movement trajectory of the optimized feature vector in multidimensional space with the dynamic confidence interval width of the steady-state baseline current value, including: Calculate the spatial geometric rotation angle of the optimization feature vector between two adjacent numerical iteration steps, as the oscillation feature of the movement trajectory; Obtain the confidence interval that characterizes the fluctuation of the steady-state baseline current value based on the time series covariance, and extract the width of the confidence interval as the width of the dynamic confidence interval; The product of the spatial geometric rotation angle and the width of the confidence interval is used as the dynamic fluctuation fingerprint.

8. The method according to claim 1, characterized in that, The preset chip internal physical leakage current propagation topology adjacency matrix is ​​based on the physical layout design of the chip under test. Independent functional hardware units that consume current inside the chip are defined as topology nodes, and the physical connections of charge transfer when switching different test commands are defined as directed edges with a clear physical flow direction to establish the adjacency matrix.

9. A DDR dynamic current testing system, characterized in that, The system includes: The front-end purification module is used to acquire the differential voltage signal across the shunt resistor through an active interference suppression circuit connected in series between the shunt resistor and the analog-to-digital converter, extract the state vector, and adjust the impedance parameters of the digitally controllable RC network accordingly to physically cancel the test noise and output the analog baseband voltage signal. The hardware compression module is used to determine the steady-state baseline current value based on the physical distribution law of the standby background current, and to compress the floating-point sampled data of the analog baseband voltage signal after it has been converted by the analog-to-digital converter, package it into a compressed data packet and send it down through the test bus. The differential reconstruction module is used to receive and decompress the compressed data packet to recover the discrete sampling points, and substitute them as boundary conditions into the physical differential residual equation constructed based on the parasitic parameters of the power supply distribution network for analytical optimization, so as to reconstruct the continuous-state time analytical function and generate the test current value. The feature interception module is used to monitor the parameter optimization feature vector in the parsing optimization process and calculate the dynamic fluctuation fingerprint. When the dynamic fluctuation fingerprint exceeds the preset interception threshold, it is determined that the probe contact is abnormal, so as to intercept the generated test current value. At the same time, a hardware interrupt command is sent to the external test equipment to drive the external test equipment to perform the probe re-pressing action. The failure tracing module is used to construct a differential leakage current feature vector based on the test current value under multiple test modes and the steady-state baseline current value when the probe contact is not determined to be abnormal. The vector is then injected into a preset chip internal physical leakage current propagation topology adjacency matrix for reverse weight allocation iteration to determine the physical leakage current location inside the chip. Based on the physical leakage current location, the module sends a compartment control command to the external mechanical sorting machine to drive the external mechanical sorting machine to perform physical compartmenting action.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the DDR dynamic current testing method according to any one of claims 1 to 8.

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