A triple-redundant current signal acquisition device

Abstract

The application belongs to the technical field of signal processing, and particularly relates to a triple-redundant current signal acquisition device. The device comprises three input signal processing modules, three median taking comparators and a selection switch module. The three input signal processing modules respectively receive three redundant input signals, process the received input signals into three identical comparison signals, and input the comparison signals into the three median taking comparators. The three median taking comparators perform median operation and output the median of the received comparison signals to the selection switch module. The selection switch module is also connected to fault positions of the three median taking comparators, and outputs the signal input by the fault-free median taking comparator according to the fault condition of the median taking comparators. The embodiment of the application can realize independent acquisition and median voting of multiple signals, improve the reliability of signal acquisition, and avoid the influence of single-point fault on the output signal through triple-redundant design.

Description

Technical Field

[0001] This application belongs to the field of signal processing technology, specifically relating to a triple-redundant current signal acquisition device. Background Technology

[0002] In industrial applications with extremely high safety and reliability requirements, such as nuclear power plants, petrochemical plants, and power systems, automatic control systems typically collect process parameters, such as pressure, flow, or valve position transmitters, through field measuring devices and transmit the measured signals to the upper-level control unit for processing. After processing the collected signals, the control system outputs a 4-20mA standard current signal to continuously variable actuators, such as pneumatic control valves and frequency converters, to achieve precise regulation of the process. If the current signal in the control system output is abnormal due to interference, drift, short circuit, or module failure, it will directly cause the actuator to malfunction, triggering interlock protection or even emergency shutdown of the unit. In severe cases, it can cause reactor shutdown or production interruption, resulting in huge economic losses and safety hazards. By configuring redundant current signal acquisition and voting modules on the control command output side, the correct signal can be maintained by other normal channels when a single output is abnormal, thereby preventing the control valve from opening or closing erroneously, avoiding false triggering of interlocks, and effectively improving the overall safety and stability of the system.

[0003] With the increasing demands for reliability and continuous operation in industrial automation systems, redundant signal acquisition and processing technology has become a crucial means to ensure stable system operation. By acquiring and fusing data from multiple channels of the same physical quantity, the correctness of the output can be maintained even in the event of signal anomalies, interference, or localized faults, thereby significantly improving the system's fault tolerance and operational continuity. As industrial control systems evolve towards higher safety levels and long-term unattended operation, single signal links or single-module acquisition methods are no longer sufficient to meet stringent safety requirements, and the fault coverage capability under single-point-of-failure and dual-redundancy architectures is limited. Summary of the Invention

[0004] The purpose of this application is to provide a triple-redundant current signal acquisition device to solve the problems of single-point failure and limited fault coverage under dual-redundant architecture in traditional signal acquisition and processing. Through triple redundancy design, the system's fault tolerance and anti-interference performance under extreme operating conditions are improved.

[0005] The technical solution to achieve the purpose of this application is as follows: This application provides a triple-redundant current signal acquisition device, which includes: three input signal processing modules, three midpoint comparators, and a selection switch module; The three input signal processing modules respectively receive three redundant input signals, process the received input signals into three identical comparison signals, and input them into the three midpoint comparators respectively; The three median comparators perform median calculations and output the median value of the received comparison signals to the selection switch module; The selection switch module is also connected to the fault bits of the three center comparators, and outputs the input signal of the center comparator without fault according to the fault status of the center comparator.

[0006] Optionally, the selection switch module includes: a first trigger submodule, a second trigger submodule, a first selection switch, and a second selection switch; The first selection switch receives the signals output by two of the center comparators, and outputs the signal input by the fault-free center comparator to the second selection switch based on the fault signals of the two center comparators. The second selection switch also receives the signals output by the remaining center comparators and outputs the signals input by the fault-free center comparators based on the fault signals of the three center comparators.

[0007] Optionally, there are three input signal processing modules, including: a first input signal processing module, a second input signal processing module, and a third input signal processing module; three center-of-center comparators, including: a first center-of-center comparator, a second center-of-center comparator, and a third center-of-center comparator; a first trigger submodule, including: a first AND gate and a first RS flip-flop; and a second trigger submodule, including: a second AND gate, a third AND gate, a fourth AND gate, an OR gate, and a second RS flip-flop. The first input signal processing module receives the first input signal Vin1 and processes the first input signal Vin1 into three identical first comparison signals Vcom1, second comparison signals Vcom2 and third comparison signals Vcom3, which are then input to the first center comparator, the second center comparator and the third center comparator, respectively. The second input signal processing module receives the second input signal Vin2 and processes it into three identical fourth comparison signals Vcom4, fifth comparison signals Vcom5 and sixth comparison signals Vcom6, which are then input to the first center comparator, the second center comparator and the third center comparator, respectively. The third input signal processing module receives the third input signal Vin3 and processes it into three identical seventh comparison signals Vcom7, eighth comparison signals Vcom8 and ninth comparison signals Vcom9, which are then input to the first center comparator, the second center comparator and the third center comparator, respectively. The output terminals of the first and second center comparators are connected to the two input terminals of the first selection switch; the output terminals of the first and third center comparators are connected to the two input terminals of the second selection switch. The first fault signal Vd1 output by the first intermediate comparator is input to the S terminal of the first RS flip-flop and the first input terminal of the second AND gate. After being inverted, it is input to the first input terminal of the first AND gate and the first input terminal of the fourth AND gate. The output terminal of the first AND gate is connected to the R terminal of the first RS flip-flop, and the output terminal of the first RS flip-flop is connected to the control terminal of the first selection switch. The second fault signal Vd2 output by the second neutral comparator is input to the second input terminal of the first AND gate and the second input terminal of the second AND gate. After being inverted, it is input to the first input terminal of the third AND gate. The output terminal of the second AND gate is connected to the S terminal of the second RS flip-flop. The R terminal of the second RS flip-flop is connected to the output terminal of the OR gate, and the output terminal is connected to the control terminal of the second selection switch. The third fault signal Vd3 output by the third neutral comparator is input to the second input terminal of the third AND gate and the second input terminal of the fourth AND gate; the output terminals of the third AND gate and the fourth AND gate are connected to the two input terminals of the OR gate.

[0008] Optionally, the output of the first RS flip-flop is also connected to a first alarm indicator light; the output of the second RS flip-flop is also connected to a second alarm indicator light.

[0009] Optionally, the input signal processing module has a signal fault diagnosis function, which triggers a signal fault alarm when the received input signal is abnormal.

[0010] Optionally, the input signal processing module performs signal conditioning and filtering isolation on the received input signal.

[0011] Optionally, the signal conditioning and filtering isolation are implemented based on a common-mode choke and a voltage regulator circuit.

[0012] Optionally, the three input signal processing modules may have different grounding points.

[0013] Optionally, the three mean-finding comparators can communicate with a digital communication network via a joint logic bus.

[0014] Optionally, the logic bus adopts a ring cascade structure to connect the three centering comparators; the digital communication network adopts an RS485 bus and a custom communication protocol to realize the interaction of status information and coordinated control among the three centering comparators.

[0015] The beneficial technical effects of this application are as follows: This application provides a triple-redundant current signal acquisition device, comprising: three input signal processing modules, three median comparators, and a selection switch module. The three input signal processing modules receive three redundant input signals respectively, process the received input signals into three identical comparison signals, and input them to the three median comparators respectively. The three median comparators perform median calculations and output the median value of the received comparison signals to the selection switch module. The selection switch module is also connected to the fault bits of the three median comparators, and outputs the signal of the fault-free median comparator based on the fault status of the median comparator. This application achieves independent acquisition and median voting of multiple signals, improving the reliability of signal acquisition. Through triple redundancy design, it avoids the impact of single-point failures on the output signal, ensuring that the system can still operate normally when any signal is abnormal, and improving the system's fault tolerance and anti-interference performance under extreme conditions. Without increasing system complexity and power consumption, the three-channel independent acquisition and multi-level comparison mechanism ensures high reliability and stability of signal acquisition and transmission, meeting the stringent requirements of high-reliability signal processing for critical industrial systems such as nuclear power plants and chemical plants. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of a triple-redundant current signal acquisition device provided in an embodiment of this application. Detailed Implementation

[0017] To enable those skilled in the art to better understand this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described below are only a part of the embodiments of this application, and not all of them. Based on the embodiments described in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] To address the problems of existing technologies, this application provides a triple-redundant current signal acquisition device. By introducing three independent current signal acquisition channels to acquire the same signal, and utilizing a "middle of three" voting mechanism to compare and filter the three signals, it can still output stable and reliable results even when a single signal is abnormal, thereby significantly improving the system's anti-interference capability and fault tolerance performance. This device can not only effectively identify and eliminate fault signals, ensuring the continuity and accuracy of the final output, but also provide redundancy switching and alarm prompts in extreme cases. It is an important technical means to meet the safety requirements of critical industries such as nuclear power and chemical industry.

[0019] Based on the above, in order to clearly and in detail illustrate the advantages of this application, the specific embodiments of this application will be described below in conjunction with the accompanying drawings.

[0020] See Figure 1 The figure is a schematic diagram of the structure of a triple-redundant current signal acquisition device provided in an embodiment of this application.

[0021] This application provides a triple-redundant current signal acquisition device, comprising: three input signal processing modules, three midpoint comparators, and a selection switch module; The three input signal processing modules respectively receive three redundant input signals, process the received input signals into three identical comparison signals, and input them into the three midpoint comparators respectively; The three median comparators perform median calculations and output the median value of the received comparison signals to the selection switch module; The selection switch module is also connected to the fault bits of the three center comparators, and outputs the input signal of the center comparator without fault according to the fault status of the center comparator.

[0022] In this embodiment, the three redundant input signals can be redundant current signals, voltage signals, control signals, etc., and can be obtained by parallel acquisition of the same signal from three sensors; no limitation is made here. The three redundant input signals undergo redundant mean-taking processing through three mean-taking comparators. Based on the deviation of the actual current value, abnormal signals are filtered out by taking the mean value. This triple redundancy setting makes the signal output more reliable. The mean-taking comparators adopt a triple redundancy configuration, using the "three mean-taking" principle to achieve mean value selection and abnormal signal rejection, ensuring the accuracy and stability of the output signal.

[0023] It is understood that the output signal of the selection switch module is the output signal Vout after processing by the device. Through the redundancy of signal acquisition, signal centering comparison and control of the selection switch module, the fault tolerance of the device is significantly improved.

[0024] This application embodiment enhances the system's fault tolerance by increasing the number of acquisition channels. When a signal malfunctions or abnormal data occurs on one channel, the system can automatically identify and eliminate the erroneous signal, while another normal channel continues to provide accurate control signals. This not only effectively prevents actuator malfunctions and interlocking mis-triggering but also significantly improves the system's operational reliability and safety in nuclear power, chemical, and high-safety-level industrial scenarios. Furthermore, to meet the demands of modern industrial control systems for long-term unattended operation and high safety levels, the device incorporates self-checking, self-switching, and status indication functions, enabling the system to automatically switch and issue alarms in abnormal situations. This reduces manual intervention and maintenance workload, improving the stability and reliability of industrial control processes.

[0025] In one example, such as Figure 1 As shown, the selection switch module may include: a first trigger submodule, a second trigger submodule, a first selection switch 301, and a second selection switch 302; The first selection switch 301 receives the signals output by two of the center comparators, and outputs the signal input by the fault-free center comparator to the second selection switch 302 based on the fault signals of the two center comparators. The second selection switch 302 also receives the signals output by the remaining center comparators and outputs the signals input by the fault-free center comparators based on the fault signals of the three center comparators.

[0026] In some possible implementations of this application, the three input signal processing modules include: a first input signal processing module 101, a second input signal processing module 102, and a third input signal processing module 103; the three center comparators include: a first center comparator 201, a second center comparator 202, and a third center comparator 203; the first trigger submodule includes: a first AND gate 401 and a first RS flip-flop RS1; the second trigger submodule includes: a second AND gate 402, a third AND gate 403, a fourth AND gate 404, an OR gate 500, and a second RS flip-flop RS2; The first input signal processing module 101 receives the first input signal Vin1 and processes the first input signal Vin1 into three identical first comparison signals Vcom1, second comparison signals Vcom2 and third comparison signals Vcom3, which are respectively input to the first centering comparator 201, the second centering comparator 202 and the third centering comparator 203. The second input signal processing module 102 receives the second input signal Vin2 and processes it into three identical fourth comparison signals Vcom4, fifth comparison signals Vcom5 and sixth comparison signals Vcom6, which are then input to the first center comparator 201, the second center comparator 202 and the third center comparator 203, respectively. The third input signal processing module 103 receives the third input signal Vin3 and processes the third input signal Vin3 into three identical seventh comparison signal Vcom7, eighth comparison signal Vcom8 and ninth comparison signal Vcom9, which are respectively input to the first centering comparator 201, the second centering comparator 202 and the third centering comparator 203; The output terminals of the first centering comparator 201 and the second centering comparator 202 are connected to the two input terminals of the first selection switch 301; the output terminal of the first selection switch 301 and the output terminal of the third centering comparator 203 are connected to the two input terminals of the second selection switch 302. The first fault signal Vd1 output by the first midpoint comparator 201 is input to the S terminal of the first RS flip-flop RS1 and the first input terminal of the second AND gate 402. After being inverted, it is input to the first input terminal of the first AND gate 401 and the first input terminal of the fourth AND gate 404. The output terminal of the first AND gate 401 is connected to the R terminal of the first RS flip-flop RS1. The output terminal of the first RS flip-flop RS1 is connected to the control terminal of the first selection switch 301. The second fault signal Vd2 output by the second neutral comparator 202 is input to the second input terminal of the first AND gate 401 and the second input terminal of the second AND gate 402. After being inverted, it is input to the first input terminal of the third AND gate 403. The output terminal of the second AND gate 402 is connected to the S terminal of the second RS flip-flop RS2. The R terminal of the second RS flip-flop RS2 is connected to the output terminal of the OR gate 500, and the output terminal is connected to the control terminal of the second selection switch 302. The third fault signal Vd3 output by the third center comparator 203 is input to the second input terminal of the third AND gate 403 and the second input terminal of the fourth AND gate 404; the output terminals of the third AND gate 403 and the fourth AND gate 404 are connected to the two input terminals of the OR gate 500.

[0027] Understandably, the selection switch module contains logic circuits and RS flip-flops to achieve redundant switching control among the three neutral comparators. The fault bit signals of the three neutral comparators are input to the logic AND and OR gates, which control the selection switch via the RS flip-flops, enabling automatic switching between the outputs of the neutral comparators.

[0028] Specifically, when the first centering comparator 201 malfunctions and the second centering comparator 202 is not faulty, the first fault signal Vd1 is 1, the second fault signal Vd2 is 0, the first input terminal of the first AND gate 401 is 0, the second input terminal is 0, and the output is 0; the S terminal of the first RS flip-flop RS1 is 1, the R terminal is 0, and the output is 1; the first selection switch 301 is activated, outputting the signal input to the second centering comparator 202 to the second selection switch 302. The first input terminal of the second AND gate 402 is 1, the second input terminal is 0, and the output is 0; the S terminal of the second RS flip-flop RS2 is 0.

[0029] At this time, if the third center comparator 203 is fault-free, the third fault signal Vd3 is 0, the first input of the third AND gate 403 is 1, the second input is 0, and the output 0 is sent to the OR gate 500; the first input of the fourth AND gate 404 is 0, the second input is 0, and the output 0 is sent to the OR gate 500; the OR gate 500 input 0 is sent to the R terminal of the second RS flip-flop RS2. The S terminal of the second RS flip-flop RS2 is 0, the R terminal is 0, and the output is 0. The second selection switch 302 does not operate, and the signal input to the second center comparator 202 is output. If the third center comparator 203 is faulty, the third fault signal Vd3 is 1, the first input of the third AND gate 403 is 1, the second input is 1, and the output 1 is sent to the OR gate 500; the first input of the fourth AND gate 404 is 0, the second input is 1, and the output 1 is sent to the OR gate 500; the OR gate 500 input 1 is sent to the R terminal of the second RS flip-flop RS2. When the S terminal of the second RS flip-flop RS2 is 0 and the R terminal is 1, the output is 0. The second selection switch 302 does not operate, and the signal input to the second midpoint comparator 202 is output.

[0030] Similarly, when the first center comparator 201 is fault-free but the second center comparator 202 is faulty, the first fault signal Vd1 is 0, the second fault signal Vd2 is 1, the first input of the first AND gate 401 is 1, the second input is 1, and the output is 1; the S terminal of the first RS flip-flop RS1 is 0, the R terminal is 1, and the output is 0; the first selection switch 301 does not operate, and the signal input to the first center comparator 201 is output to the second selection switch 302. The first input of the second AND gate 402 is 0, the second input is 1, and the output is 0; the S terminal of the second RS flip-flop RS2 is 0.

[0031] At this time, if the third center comparator 203 is fault-free, the third fault signal Vd3 is 0, the first input of the third AND gate 403 is 0, the second input is 0, and the output 0 is sent to the OR gate 500; the first input of the fourth AND gate 404 is 1, the second input is 0, and the output 0 is sent to the OR gate 500; the OR gate 500 inputs 0 to the R terminal of the second RS flip-flop RS2. The S terminal of the second RS flip-flop RS2 is 0, the R terminal is 0, and the output is 0. The second selection switch 302 does not operate, and outputs the signal input to the first center comparator 201. If the third center comparator 203 is faulty, the third fault signal Vd3 is 1, the first input of the third AND gate 403 is 0, the second input is 1, and the output 0 is sent to the OR gate 500; the first input of the fourth AND gate 404 is 1, the second input is 1, and the output 1 is sent to the OR gate 500; the OR gate 500 inputs 1 to the R terminal of the second RS flip-flop RS2. When the S terminal of the second RS flip-flop RS2 is 0 and the R terminal is 1, the output is 0. The second selection switch 302 does not operate, and the signal input to the second midpoint comparator 202 is output.

[0032] Furthermore, when both the first center comparator 201 and the second center comparator 202 fail, the first fault signal Vd1 is 1, the second fault signal Vd2 is 1, the first input of the first AND gate 401 is 0, the second input is 1, and the output is 0. The S terminal of the first RS flip-flop RS1 is 0, the R terminal is 0, and the output is 0. The first selection switch 301 does not operate, and the signal input to the first center comparator 201 is output to the second selection switch 302. The first input of the second AND gate 402 is 1, the second input is 1, and the output is 1. The S terminal of the second RS flip-flop RS2 is 1.

[0033] At this time, if the third center comparator 203 is not faulty, the third fault signal Vd3 is 0, the first input of the third AND gate 403 is 0, the second input is 0, and the output is 0 to OR gate 500; the first input of the fourth AND gate 404 is 0, the second input is 0, and the output is 0 to OR gate 500; OR gate 500 inputs 0 to the R terminal of the second RS flip-flop RS2. The S terminal of the second RS flip-flop RS2 is 1, the R terminal is 0, and the output is 0. The second selection switch 302 is activated, outputting the signal input to the third center comparator 203. If the third center comparator 203 is also faulty, the third fault signal Vd3 is 1, the first input of the third AND gate 403 is 0, the second input is 1, and the output is 0 to OR gate 500; the first input of the fourth AND gate 404 is 0, the second input is 1, and the output is 0 to OR gate 500; OR gate 500 inputs 0 to the R terminal of the second RS flip-flop RS2. When the S terminal of the second RS flip-flop RS2 is 1 and the R terminal is 0, the output is 1. The second selection switch 302 is activated, and the signal input to the third midpoint comparator 203 is output.

[0034] In practical implementation, it can be flexibly configured as a dual-redundant (for example, without the second selector switch 302 working, the output of the first selector switch 301 can be directly used as Vout) or a triple-redundant structure according to actual needs. The standardized interface design facilitates integration with DCS, PLC and other systems, and is suitable for various industrial control occasions such as nuclear power plants and chemical plants, and has high engineering promotion value.

[0035] In one example, the output of the first RS flip-flop RS1 is also connected to the first alarm indicator light; the output of the second RS flip-flop RS2 is also connected to the second alarm indicator light.

[0036] It is understandable that when the output of the first RS flip-flop RS1 is 1, the first alarm indicator light can be triggered to issue a fault alarm. When the output of the second RS flip-flop RS2 is 1, the second alarm indicator light can be triggered to issue a fault alarm.

[0037] In another example, the input signal processing module has a signal fault diagnosis function, which triggers a signal fault alarm when the received input signal is abnormal.

[0038] In practical implementation, when the input signal is a certain current signal, if a certain current signal is less than 2.4mA or greater than 21.6mA, the corresponding input signal processing module can issue a light alarm for the corresponding channel and output fault information through the normally open dry contact of the relay, which facilitates the upper system and maintenance personnel to quickly locate the fault channel and reduce maintenance workload.

[0039] Understandably, the input signal processing module integrates fault detection and alarm output functions. When the input signal exceeds the limit, it automatically triggers the channel indicator light alarm and outputs a relay dry contact signal, which facilitates the upper system or maintenance personnel to quickly identify the faulty channel, shorten the troubleshooting time, and reduce the maintenance workload.

[0040] As an example, the input signal processing module can perform signal conditioning and filtering isolation on the received input signal. For instance, the signal conditioning and filtering isolation can be implemented based on a common-mode choke and a voltage regulator circuit. Any specific signal conditioning and filtering isolation technique can be used; no limitation is imposed here, nor will it be elaborated upon further.

[0041] In one possible implementation, the three input signal processing modules have different grounding points.

[0042] Understandably, the three input signal processing modules all adopt independent signal conditioning and filtering isolation designs. Combined with common-mode chokes, LDO voltage regulation, and grounding partitioning strategies, they can effectively suppress external electromagnetic interference and common-mode noise, ensure the accuracy of the sampled signal, and improve anti-interference and electrical isolation performance.

[0043] In some possible implementations of the embodiments of this application, the three mean-taking comparators can communicate with a digital communication network via a joint logic bus.

[0044] Understandably, when each center comparator passes its self-test and is in a normal state, the center comparators can communicate with the digital communication network through the joint logic bus.

[0045] In one example, the logic bus can be connected in a ring cascade structure to connect the three mean-taking comparators; the digital communication network can use an RS485 bus and a custom communication protocol to realize the interaction of status information and coordinated control among the three mean-taking comparators.

[0046] Understandably, by using a dual-channel handshake between the logic bus and the RS485 communication network, information exchange and state coordination between redundant comparators can be achieved, thereby improving the system's fault tolerance.

[0047] When a fault is detected in one of the center-of-point comparators on the logic bus, the next-level fault-free center-of-point comparator initiates an acknowledgment signal. If there is no response or failure to recover within a set time, the normal center-of-point comparator automatically takes over the output operation to maintain stable operation of the device. During normal operation, the device defaults to outputting the result from the first center-of-point comparator. When the first center-of-point comparator detects a fault, it automatically switches to the second center-of-point comparator for operation. If the second center-of-point comparator fails while the first center-of-point comparator recovers, it switches back to the first center-of-point comparator. When both the first and second center-of-point comparators fail simultaneously, the device switches to the third center-of-point comparator to continue operation. This multi-level switching mechanism ensures that the device maintains output continuity and stability even when some center-of-point comparators fail. The device features intelligent fault-tolerant switching functionality. The module incorporates logic judgment and RS flip-flop control circuitry, which can automatically switch signal channels based on comparator self-tests and fault states, ensuring output continuity and correctness, and achieving self-recovery and fault-tolerant operation in unattended conditions. The device also features indicator lights to alert users of input signals and comparator faults, and provides a relay dry contact alarm output interface so that external systems can obtain fault information in a timely manner.

[0048] This application implements independent acquisition and median voting of multiple signals, improving the reliability of signal acquisition. Through triple redundancy design, it avoids the impact of single-point failures on the output signal, ensuring the system can still operate normally even when any signal is abnormal, thus enhancing the system's fault tolerance and anti-interference performance under extreme conditions. Without increasing system complexity or power consumption, the three-channel independent acquisition and multi-level comparison mechanism ensure high reliability and stability of signal acquisition and transmission, meeting the stringent requirements of critical industrial systems such as nuclear power plants and chemical plants for high-reliability signal processing.

[0049] The following example, using the case where the first input signal Vin1, the second input signal Vin2, and the third input signal Vin3 are redundant current signals, illustrates in detail the triple-redundant current signal acquisition device provided in this application.

[0050] like Figure 1 As shown in the embodiment of this application, the first input signal Vin1 is input to the first input signal processing module 101 and processed into three identical first comparison signals Vcom1, second comparison signal Vcom2, and third comparison signal Vcom3, which are respectively input to the first centering comparator 201, the second centering comparator 202, and the third centering comparator 203; the second input signal Vin2 is input to the second input signal processing module 102 and processed into three identical fourth comparison signals Vcom4, fifth comparison signals Vcom5, and sixth comparison signals Vcom6, which are respectively input to the first centering comparator 201, the second centering comparator 202, and the third centering comparator 203; the third input signal Vin3 is input to the third input signal processing module 103 and processed into three identical seventh comparison signals Vcom7, eighth comparison signals Vcom8, and ninth comparison signals Vcom9, which are respectively input to the first centering comparator 201, the second centering comparator 202, and the third centering comparator 203. The output signals of the first center comparator 201 and the second center comparator 202 are both input to the first selection switch 301.

[0051] The fault signal Vd1 output by the first center comparator 201 is connected to the S terminal of the first RS flip-flop RS1 and the second AND gate 402. This fault signal is inverted and connected to the first AND gate 401 and the fourth AND gate 404. The second center comparator 202 outputs a second fault signal Vd2, which is connected to the first AND gate 401 and the second AND gate 402. This fault signal is inverted and connected to the third AND gate 402. The output signal of the first AND gate 401 is connected to the R terminal of the first RS flip-flop RS1. When the R terminal and S terminal of the first RS flip-flop RS1 are both 0, the output value is 0. At this time, the first selection switch 301 does not operate, and the output signal of the first center comparator 201 is output. When the first center comparator 201 malfunctions, the S terminal of the first RS flip-flop RS1 is 1, the R terminal is 0, and the output value is 1. At this time, the first selection switch 301 operates, and the output signal 24 of the second center comparator 202 is output.

[0052] The fault signal Vd3 output by the fault bit of the third neutral comparator 203 is connected to the third AND gate 402 and the fourth AND gate 404. The outputs of the third AND gate 402 and the fourth AND gate 404 are connected to the OR gate 500. The output signal of the OR gate 500 is connected to the R terminal of the second RS flip-flop RS2. The output signal of the second AND gate 402 is connected to the S terminal of the second RS flip-flop RS2.

[0053] When both the first and second center comparators 201 and 202 fail, the S-terminal of the second RS flip-flop RS2 is 0, and it is in a reset or hold state, with an output signal of 0. At this time, the second selection switch 302 does not operate, and the output signal of the selection switch A is output 31. When both the first and second center comparators 201 and 202 fail, the output signal of the second AND gate 402 is 1, and the output signal of the OR gate 500 is 0. That is, the S-terminal of the second RS flip-flop RS2 is 1, the R-terminal is 0, and the output value is 1. At this time, the second selection switch 302 operates, and the output signal 32 of the third center comparator 203 is output.

[0054] Based on the fundamental theory of signal redundancy acquisition and processing technology, this application proposes a practical and feasible method for designing a transmitter circuit, and verifies its feasibility and performance through experimental testing. At the same time, by combining Internet data and industry application cases, the design method is continuously optimized and improved, providing scientific and effective technical guidance for the engineering design of signal redundancy acquisition and transmission circuits.

[0055] The present application has been described in detail above with reference to the accompanying drawings and embodiments. However, the present application is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present application. All content not described in detail in this application can be derived from existing technology.

Claims

1. A triple-redundant current signal acquisition device, characterized in that, The device includes: three input signal processing modules, three center-of-point comparators, and a selection switch module; The three input signal processing modules respectively receive three redundant input signals, process the received input signals into three identical comparison signals, and input them into the three midpoint comparators respectively; The three median comparators perform median calculations and output the median value of the received comparison signals to the selection switch module; The selection switch module is also connected to the three fault bits of the center comparator, and outputs the input signal of the center comparator without fault according to the fault status of the center comparator.

2. The triple-redundant current signal acquisition device according to claim 1, characterized in that, The selection switch module includes: a first trigger submodule, a second trigger submodule, a first selection switch, and a second selection switch; The first selection switch receives the signals output by two of the center comparators, and outputs the signal input by the fault-free center comparator to the second selection switch based on the fault signals of the two center comparators. The second selection switch also receives the signals output by the remaining center comparators and outputs the signals input by the fault-free center comparators based on the fault signals of the three center comparators.

3. The triple-redundant current signal acquisition device according to claim 2, characterized in that, The system includes three input signal processing modules: a first input signal processing module, a second input signal processing module, and a third input signal processing module; three center-of-center comparators: a first center-of-center comparator, a second center-of-center comparator, and a third center-of-center comparator; a first trigger submodule: a first AND gate and a first RS flip-flop; and a second trigger submodule: a second AND gate, a third AND gate, a fourth AND gate, an OR gate, and a second RS flip-flop. The first input signal processing module receives the first input signal Vin1 and processes the first input signal Vin1 into three identical first comparison signals Vcom1, second comparison signals Vcom2 and third comparison signals Vcom3, which are then input to the first center comparator, the second center comparator and the third center comparator, respectively. The second input signal processing module receives the second input signal Vin2 and processes it into three identical fourth comparison signals Vcom4, fifth comparison signals Vcom5 and sixth comparison signals Vcom6, which are then input to the first center comparator, the second center comparator and the third center comparator, respectively. The third input signal processing module receives the third input signal Vin3 and processes it into three identical seventh comparison signals Vcom7, eighth comparison signals Vcom8 and ninth comparison signals Vcom9, which are then input to the first center comparator, the second center comparator and the third center comparator, respectively. The output terminals of the first and second center comparators are connected to the two input terminals of the first selection switch; the output terminals of the first and third center comparators are connected to the two input terminals of the second selection switch. The first fault signal Vd1 output by the first intermediate comparator is input to the S terminal of the first RS flip-flop and the first input terminal of the second AND gate. After being inverted, it is input to the first input terminal of the first AND gate and the first input terminal of the fourth AND gate. The output terminal of the first AND gate is connected to the R terminal of the first RS flip-flop, and the output terminal of the first RS flip-flop is connected to the control terminal of the first selection switch. The second fault signal Vd2 output by the second neutral comparator is input to the second input terminal of the first AND gate and the second input terminal of the second AND gate. After being inverted, it is input to the first input terminal of the third AND gate. The output terminal of the second AND gate is connected to the S terminal of the second RS flip-flop. The R terminal of the second RS flip-flop is connected to the output terminal of the OR gate, and the output terminal is connected to the control terminal of the second selection switch. The third fault signal Vd3 output by the third neutral comparator is input to the second input terminal of the third AND gate and the second input terminal of the fourth AND gate; the output terminals of the third AND gate and the fourth AND gate are connected to the two input terminals of the OR gate.

4. The triple-redundant current signal acquisition device according to claim 3, characterized in that, The output of the first RS flip-flop is also connected to the first alarm indicator light; the output of the second RS flip-flop is also connected to the second alarm indicator light.

5. The triple-redundant current signal acquisition device according to claim 1, characterized in that, The input signal processing module has a signal fault diagnosis function, which triggers a signal fault alarm when the received input signal is abnormal.

6. The triple-redundant current signal acquisition device according to claim 1, characterized in that, The input signal processing module performs signal conditioning, filtering, and isolation on the received input signal.

7. The triple-redundant current signal acquisition device according to claim 6, characterized in that, The signal conditioning and filtering isolation are implemented based on a common-mode choke and a voltage regulator circuit.

8. The triple-redundant current signal acquisition device according to claim 1, characterized in that, The three input signal processing modules have different grounding points.

9. The triple-redundant current signal acquisition device according to claim 1, characterized in that, The three centering comparators communicate with the digital communication network via a joint logic bus.

10. The triple-redundant current signal acquisition device according to claim 9, characterized in that, The logic bus uses a ring cascade structure to connect the three centering comparators; the digital communication network uses an RS485 bus and a custom communication protocol to realize the interaction of status information and coordinated control among the three centering comparators.

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