A multi-channel synchronous acquisition system for rail transit

Abstract

The present disclosure provides a kind of multi-channel synchronous acquisition system for rail transit, including main CPU board card, function subboard and backboard;Inter-board service bus and three-wire hardware synchronization bus are arranged on the backboard, and the three-wire hardware synchronization bus includes sampling time synchronization bus, system time synchronization bus and time synchronization enable bus;Main CPU board card is inserted in backboard, and is connected with function subboard by inter-board service bus and three-wire hardware synchronization bus, for gathering and processing sampling data, wherein, sampling time synchronization bus is used to transmit PPS second pulse to align sampling phase, system time synchronization bus is used to transmit IRIG-B code stream to distribute absolute time, and time synchronization enable bus is used to transmit trigger permission signal to control sampling start timing;Function subboard is inserted in backboard, and is used to acquire sampling data.The present disclosure separates physically by aligning sampling phase, distributing absolute time and controlling start timing, flexibly configures subboard according to train demand, and guarantees acquisition time synchronization.

Description

Technical Field

[0001] This disclosure relates to the field of intelligent monitoring technology for electrical circuits of rail trains, and more specifically to a multi-channel synchronous acquisition system for rail transit. Background Technology

[0002] The status monitoring of electrical circuits in rail transit trains places extremely high demands on the number of data acquisition channels, synchronization accuracy, and time consistency. In existing technologies, industrial data acquisition equipment boards only support 8-16 channels per board, and when multiple boards are cascaded, synchronization relies on software triggering, which is insufficient to meet the time consistency requirements of transient data analysis in electrical circuits. Furthermore, the fixed backplane architecture of existing acquisition systems prevents the mixing of different types of acquisition boards, such as analog sampling, contact monitoring, and environmental variable monitoring boards, within the same chassis, resulting in poor system scalability. Summary of the Invention

[0003] In view of the above problems, this disclosure provides a multi-channel synchronous acquisition system for rail transit that is applicable to the intelligent monitoring scenario of electrical circuits of rail trains, and supports the simultaneous transmission of steady-state data and transient data.

[0004] This disclosure provides a multi-channel synchronous data acquisition system for rail transit, including a main CPU board, functional daughter boards, and a backplane. The backplane is equipped with an inter-board service bus and a three-wire hardware synchronization bus, which includes a sampling time synchronization bus, a system time synchronization bus, and a time synchronization enable bus. The main CPU board, plugged into the backplane, is connected to the functional daughter boards via the inter-board service bus and the three-wire hardware synchronization bus. It is used to aggregate and process sampled data. The sampling time synchronization bus transmits PPS second pulses to align the sampling phase, the system time synchronization bus transmits IRIG-B code streams to distribute absolute time, and the time synchronization enable bus transmits trigger permission signals to control the sampling start timing. The functional daughter boards, plugged into the backplane, are used to acquire sampled data.

[0005] According to embodiments of this disclosure, the inter-board service bus includes an RS485 bus, an IIC bus, a high-speed SerDes bus, and an SPI bus; the RS485 bus and the IIC bus connect the main CPU board and the functional daughter board, and are used to send configuration parameters according to the functional type of the daughter board; the high-speed SerDes bus connects the main CPU board and the functional daughter board, and is used for uplink transmission of high-speed sampling data; the SPI bus connects the main CPU board and the functional daughter board, and is used for remotely updating the FPGA program of the daughter board.

[0006] According to an embodiment of this disclosure, the main CPU board includes a CPU, an FPGA, and a first DDR cache unit; the FPGA is connected to the CPU, the first DDR cache unit, the inter-board service bus, and the three-wire hardware synchronization bus, and is used to parse protocols, schedule data streams, and generate synchronization signals; the first DDR cache unit is used to cache sampled data; the CPU is connected to the FPGA through a PCIe interface and is used to process application layer logic and external communication.

[0007] According to embodiments of this disclosure, the main CPU board further includes an IRIG-B decoding interface, an NTP network interface, and a PPS input interface; the IRIG-B decoding interface connects to an external time source and the FPGA, and is used to decode the external IRIG-B code stream into parallel time data; the NTP network interface connects to an external NTP server and the CPU, and is used to obtain a backup clock source through the network time protocol to maintain system time continuity when the IRIG-B signal is missing; the PPS input interface connects to an external second pulse source and the FPGA, and is used to provide a phase reference; the FPGA integrates a digital phase-locked loop, the input of which is connected to the PPS input interface, and the output is connected to the sampling time synchronization bus, which is used to tame the local clock and output a low-jitter synchronization PPS.

[0008] According to embodiments of this disclosure, the functional daughterboard includes a 200kHz sampling board or a 1MHz sampling board; the 200kHz sampling board or the 1MHz sampling board includes a daughterboard FPGA, an ADC, and a second DDR cache unit; the daughterboard FPGA is connected to the ADC, the second DDR cache unit, and a three-wire hardware synchronization bus, respectively, for responding to the PPS second pulse to clear the sampling counter, controlling the ADC to perform synchronous sampling, and uploading sampling data to the main CPU board; the second DDR cache unit is connected to the daughterboard FPGA and is divided into 24 independent physical storage areas for caching transient data of 24 channels.

[0009] According to embodiments of this disclosure, the functional subboard includes a multi-channel isolation acquisition board; the multi-channel isolation acquisition board includes 8 independent signal acquisition channels.

[0010] According to embodiments of this disclosure, the functional sub-board includes a contact monitoring board; the contact monitoring board includes a high-voltage conditioning circuit and a status recognition FPGA; the high-voltage conditioning circuit is connected to an external circuit breaker contact and the status recognition FPGA, and is used to attenuate the high-voltage signal to the range that the status recognition FPGA can collect; the status recognition FPGA is connected to the high-voltage conditioning circuit and an RS485 bus, and is used to identify the opening and closing state of the contact and filter the closed state data, and upload it to the main CPU board.

[0011] According to embodiments of this disclosure, the functional sub-board includes an environmental variable monitoring board; the environmental variable monitoring board includes at least 8 RS485 physical interfaces and a protocol parsing FPGA; the RS485 physical interfaces are connected to remote environmental sensors and the protocol parsing FPGA for transmitting and receiving environmental sensor data; the protocol parsing FPGA is connected to the RS485 physical interfaces for parsing the environmental sensor protocol and performing mean filtering on the environmental sensor data before uploading it to the main CPU board.

[0012] According to embodiments of this disclosure, the backplane is provided with 7 standard daughterboard slots; the first slot is a dedicated slot for communication expansion boards, used to insert communication expansion boards to provide additional network ports, serial ports or CAN interfaces; the remaining slots are general-purpose slots, used to mix and match at least two of the following: 200KHz sampling boards, 1MHz sampling boards, multi-channel isolation acquisition boards, contact monitoring boards and environmental variable monitoring boards; the FPGA of the main CPU board integrates a slot identification circuit, which is connected to the detection pins of each slot to read the daughterboard ID and automatically load the corresponding configuration parameters.

[0013] According to embodiments of this disclosure, a power supply board is also included; the power supply board is plugged into the backplane and is used to convert the externally input DC power supply into multiple low-voltage power supplies required by each board; the power supply board adopts an architecture combining a low-noise switching power supply and a linear regulator to suppress power ripple and ensure the sampling accuracy of the functional sub-boards.

[0014] According to the multi-channel synchronous acquisition system for rail transit provided in this disclosure, the problem of sampling asynchrony between multiple boards and multiple channels is solved from the hardware level by physically separating sampling phase alignment, absolute time distribution and start-up timing control, thereby improving the stability of multi-channel sampling. Attached Figure Description

[0015] Figure 1 A schematic diagram of a multi-channel synchronous data acquisition system for rail transit according to an embodiment of the present disclosure is shown.

[0016] Figure 2 A data processing flowchart according to an embodiment of the present disclosure is illustrated schematically;

[0017] Figure 3 A flowchart illustrating an embodiment of the present disclosure is shown schematically.

[0018] Figure 4 A flowchart illustrating a high-precision time synchronization according to an embodiment of the present disclosure is shown schematically.

[0019] Figure 5 A schematic diagram of a system apparatus according to an embodiment of the present disclosure is shown. Detailed Implementation

[0020] The embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the present disclosure for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0021] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0022] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0023] When using expressions such as "at least one of A, B and C", they should generally be interpreted in accordance with the meaning that is commonly understood by those skilled in the art (e.g., "a system having at least one of A, B and C" should include, but is not limited to, a system having A alone, a system having B alone, a system having C alone, a system having A and B, a system having A and C, a system having B and C, and / or a system having A, B and C, etc.).

[0024] With the advancement of technology, rail transit is becoming increasingly dense, placing higher demands on the safety of rail trains. Real-time monitoring of the operating status of rail trains, equipment working status, and the track environment is therefore crucial. This system focuses on solving the problem of simultaneously detecting multiple states of rail trains. It supports up to 144 data channels and multiple sampling rates, including 200kHz and 1MHz. It also supports boards for environmental variable detection, communication expansion, and contact monitoring. The system is flexible and can be configured with the required data acquisition card types according to the train's needs.

[0025] In the process of implementing the embodiments of this disclosure, at least the following problems have been found in the related technology:

[0026] In practical applications, current data acquisition systems used in rail transit have a limited and unconfigurable sampling rate. They are not compatible with multi-channel systems that support multiple sampling rates and cannot be configured. Furthermore, there is currently no data acquisition system that supports a 1MHz sampling rate across all 144 channels.

[0027] In practical tasks, the multi-channel transient data currently used for intelligent monitoring of electrical circuits in rail trains rarely meets the requirement of storing data longer than 50ms. Even if it does, only a few channels can achieve transient data storage of more than 50ms.

[0028] In practical applications, current data acquisition systems for intelligent monitoring of electrical circuits in rail trains are rarely compatible with multiple board types working simultaneously. For example, systems that support data acquisition may not support communication expansion and environmental variable acquisition, while systems that support environmental variable acquisition may not support sensor data and contact monitoring. In the future, more sub-board types can be added, making them highly scalable.

[0029] In actual tasks, the multi-channel data collected for intelligent monitoring of electrical circuits in rail trains is rarely synchronized, which increases the difficulty of post-event data analysis and train troubleshooting.

[0030] This disclosure provides a multi-channel synchronous data acquisition system for rail transit, including a main CPU board, functional daughter boards, and a backplane. The backplane is equipped with an inter-board service bus and a three-wire hardware synchronization bus, which includes a sampling time synchronization bus, a system time synchronization bus, and a time synchronization enable bus. The main CPU board, plugged into the backplane, is connected to the functional daughter boards via the inter-board service bus and the three-wire hardware synchronization bus. It is used to aggregate and process sampled data. The sampling time synchronization bus transmits PPS second pulses to align the sampling phase, the system time synchronization bus transmits IRIG-B code streams to distribute absolute time, and the time synchronization enable bus transmits trigger permission signals to control the sampling start timing. The functional daughter boards, plugged into the backplane, are used to acquire sampled data.

[0031] Figure 1 A schematic diagram of a multi-channel synchronous data acquisition system for rail transit according to an embodiment of the present disclosure is shown, in conjunction with... Figure 1This disclosure provides an intelligent monitoring system for the electrical circuits of rail trains based on multiple types of daughter boards, a main CPU board, a power supply board, and a backplane. The daughter boards include a 200kHz@24-channel non-isolated voltage acquisition daughter board supporting selectable ±5V and ±500V ranges; a 1MHz@24-channel non-isolated voltage acquisition daughter board supporting selectable ±5V and ±500V ranges; a 200kHz@8-channel isolated voltage acquisition daughter board supporting selectable ±5V and ±500V ranges; an 8-channel contact board; and an 8-channel environmental variable monitoring board. More daughter board types can be added based on this system architecture in the future. The daughter boards and the main board are interconnected via RS485 bus, IIC data bus, high-speed SERDES data line, SPI data bus, sampling time synchronization bus, time synchronization enable bus, system time synchronization bus, and serial port. Parameter configuration data is configured via RS485 bus and IIC bus to ensure normal system operation. High-speed SERDES uses the transmission band protocol to transmit sampled data. The SPI data bus is used to update the FPGA (Field Programmable Gate Array) program on the daughter board. The sampling time synchronization line and time synchronization enable ensure the synchronization of sampling timestamps and sampled data across daughter boards. The system synchronization bus is mainly used to ensure system time synchronization between the motherboard CPU and each daughter board.

[0032] Based on the above embodiments, the inter-board service bus includes an RS485 bus, an IIC bus, a high-speed SerDes (serializer / deserializer) bus, and an SPI bus; the RS485 bus and IIC bus connect the main CPU board and the functional daughter board, and are used to send configuration parameters according to the function type of the daughter board; the high-speed SerDes bus connects the main CPU board and the functional daughter board, and is used for uplink transmission of high-speed sampling data; the SPI bus connects the main CPU board and the functional daughter board, and is used for remotely updating the FPGA program of the daughter board.

[0033] Through the embodiments of this disclosure, a heterogeneous bus design is adopted to achieve physical isolation between control flow and data flow. RS485 / IIC is responsible for low-bandwidth configuration distribution with strong anti-interference capability; high-speed SerDes is responsible for uplink transmission of large-volume sampling data, ensuring real-time performance at high sampling rates; the SPI bus supports remote firmware updates, greatly reducing on-site maintenance costs. Bus contention is avoided, improving the overall stability of the system.

[0034] Based on the above embodiments, the main CPU board includes a CPU, an FPGA, and a first DDR cache unit (Double Data Rate SDRAM); the FPGA is connected to the CPU, the first DDR cache unit, the inter-board service bus, and the three-wire hardware synchronization bus, and is used to parse protocols, schedule data streams, and generate synchronization signals; the first DDR cache unit is used to cache sampled data; the CPU is connected to the FPGA through a PCIe interface and is used to process application layer logic and external communication. The main CPU board also includes an IRIG-B (InterRange Instrumentation Group-B) decoding interface, an NTP (Network Time Protocol) network interface, and a PPS (pulses per second) input interface. The IRIG-B decoding interface connects to an external time source and the FPGA to decode the external IRIG-B code stream into parallel time data. The NTP network interface connects to an external NTP server and the CPU to obtain a backup clock source via the Network Time Protocol when the IRIG-B signal is missing, thus maintaining system time continuity. The PPS input interface connects to an external second pulse source and the FPGA to provide a phase reference. The FPGA integrates a digital phase-locked loop (PLL), whose input is connected to the PPS input interface and whose output is connected to the sampling time synchronization bus to tame the local clock and output a low-jitter synchronous PPS.

[0035] Based on the above embodiments, the functional daughterboard includes a 200kHz sampling board or a 1MHz sampling board; the 200kHz or 1MHz sampling board includes a daughterboard FPGA, an ADC, and a second DDR cache unit; the daughterboard FPGA is connected to the ADC, the second DDR cache unit, and a three-wire hardware synchronization bus, respectively, for responding to the PPS pulse-per-second reset sampling counter and controlling the ADC to perform synchronous sampling, uploading sampling data to the main CPU board; the second DDR cache unit, connected to the daughterboard FPGA, is divided into 24 independent physical storage areas for caching transient data from 24 channels. Dividing the DDR into 24 independent physical storage areas within the daughterboard FPGA, with each channel occupying its own cache area, combined with a configurable transient depth of 256 to 51200 points, allows a single channel to record up to 256ms of transient data at a 200kHz sampling rate.

[0036] In this embodiment, the 200kHz or 1MHz sampling board supports both steady-state and transient data types, which need to be distinguished using different protocol headers. The functional sub-board also includes a multi-channel isolation acquisition board; the multi-channel isolation acquisition board includes 8 independent signal acquisition channels. The functional sub-board also includes a contact monitoring board; the contact monitoring board includes a high-voltage conditioning circuit and a status recognition FPGA; the high-voltage conditioning circuit connects to the external circuit breaker contacts and the status recognition FPGA, used to attenuate the high-voltage signal to the range that the status recognition FPGA can acquire; the status recognition FPGA connects to the high-voltage conditioning circuit and the RS485 bus, used to identify the open / closed state of the contacts and filter the closed state data, and upload it to the main CPU board. The functional subboard also includes an environmental variable monitoring board; the environmental variable monitoring board includes at least 8 RS485 physical interfaces and a protocol parsing FPGA; the RS485 physical interfaces connect to remote environmental sensors and the protocol parsing FPGA for sending and receiving environmental sensor data; the protocol parsing FPGA connects to the RS485 physical interfaces for parsing the environmental sensor protocol and performing mean filtering on the environmental sensor data before uploading it to the main CPU board.

[0037] This system achieves high integration of multi-functional daughterboards. The FPGA handles low-level protocol parsing and high-speed data stream scheduling, freeing up CPU computing power. Combined with DDR cache, it effectively absorbs data surges from 144 channels at full sampling, eliminating packet loss. The main card integrates IRIG-B, NTP, and PPS multi-source time synchronization mechanisms, using a digital phase-locked loop to discipline the local clock, maintaining sampling synchronization even with external time synchronization interruptions. The high-sampling board divides DDR into 24 independent physical storage areas, supporting up to 250ms of full-channel transient data buffering at 1MHz. The multi-channel isolation acquisition board suppresses common-mode interference through physical isolation between channels, ensuring the accuracy of weak signals. The front-end daughterboard features edge intelligence: the contact monitoring board incorporates high-voltage conditioning and status recognition algorithms, automatically filtering out invalid interruption data and only reporting filtered contact resistance; the environmental variable monitoring board uses the FPGA for protocol parsing to perform mean filtering and extraction of multi-channel sensor data. These modules work together to achieve end-to-end optimization from high-precision acquisition and edge preprocessing to reliable transmission, significantly improving data validity while significantly reducing the computational load and bandwidth pressure on the back-end system.

[0038] Figure 2 A schematic diagram illustrating a data processing flowchart according to an embodiment of the present disclosure is shown, such as Figure 2As shown, the 200kHz@24-channel non-isolated voltage acquisition sub-board, the 1MHz@24-channel non-isolated voltage acquisition sub-board, and the 200kHz@8-channel isolated voltage acquisition sub-board all use the same processing method. The RS485 serial bus sends configuration parameters according to the board type and slot number. These three types of sub-boards support both steady-state and transient data. Steady-state data refers to steady-state sampled data. When steady-state data is enabled, the data is extracted according to the steady-state data sampling rate and continuously packaged into steady-state data message format across the 24 channels. This is then processed into a SERDES message format by the steady-state and transient data processing modules and sent to the main board via SERDES. Transient data refers to the data recorded before and after a signal change or exceeding a limit. This data length supports 256~51200 points, which translates to a maximum of 256ms data recording at a 200kHz sampling rate and 512ms at a 1MHz sampling rate. The system supports up to 24 channels for data recording on the daughterboard and up to 144 channels for the entire system. These parameters are currently unparalleled in the industry. Transient data needs to be recorded in relatively long amounts, and each daughterboard needs to record 24 channels, so DDR data caching is required. The FPGA is used to divide the DDR into 24 storage areas to store the 24 channels of data. The transient data cached by DDR is processed using the transient data protocol. During transient algorithm data processing, it is necessary not only to determine the point of signal transition, but also to accurately record the sampling time and system time of the signal transition for easy post-analysis. After being processed by the transient data protocol, the transient data is sent to the steady-state and transient data processing modules to be processed into SerDes transmission message format. When processing transient and steady-state data in the SerDes transmission message format, different protocol message headers are used to distinguish them. This way, the data sent to the main CPU board FPGA can distinguish between transient and steady-state data and send the steady-state and transient data to different storage areas via DMA.

[0039] Figure 2The sampling rate requirements for the contact monitoring board and the environmental monitoring board are relatively low. They also use RS485 serial bus to send configuration parameters according to the board type and slot number. After the contact detection board ADC collects data, it needs to process the data to distinguish between the open and closed states of the circuit breaker contacts. Data from the open and closed states is not useful and needs to be discarded. Data from the closed states needs to be filtered to ensure data stability and data extraction. Data can be sent up once every 1 second. Therefore, the data is processed through the backplane serial port according to the dedicated protocol for contact monitoring and environmental variables and then sent to the main CPU board. The FPGA on the main CPU board parses the data and sends it to the CPU through PCIe, and finally it is displayed on the host computer. The environmental variable monitoring board is different. It uses the RS485 protocol to input information such as temperature and humidity from the remote module. The environmental variable monitoring board parses the remote module's protocol, performs average filtering, and finally extracts data once per second. After being packaged according to the protocol, it is sent to the main CPU board through the backplane serial port. The FPGA on the main CPU board parses the data and sends it to the CPU through PCIe, and finally it is displayed on the host computer.

[0040] Figure 2 The CPU motherboard is the core of the entire system, controlling important functions such as daughterboard type identification, parameter configuration, data processing, and data transmission. After various daughterboard data are aggregated to the main CPU board, the FPGA on the main CPU board needs to identify the data. After accurate identification, the data is classified, and finally, different data are sent to different access areas via PCIe, realizing data stream splitting and parallel processing. The CPU is then notified, and the CPU sends the data to the host computer. After data processing, the host computer displays the data to the user. When the FPGA on the main CPU board processes data, it needs to support the surge of 144 channels of 1MHz sampling data, and the data types are inconsistent. Therefore, the FPGA also uses DDR for data caching, and it needs to accurately store different data in different areas according to different slots. For transient and steady-state data, after DDR caching, DMA is used to quickly upload the data to the CPU via PCIe. For small amounts of contact monitoring and environmental variable monitoring data, the data is parsed and processed and then mounted in the PCIe storage area under different slots. When the CPU is idle, it reads the data itself and finally sends it to the host computer for display to the user.

[0041] Figure 3 A flowchart illustrating an embodiment of the present disclosure is shown schematically, such as Figure 3 As shown, after power-on, the host computer detects the daughter card type and issues different daughter card system operation parameters according to the daughter card type. It can also read back the current daughter card's operating status and configuration parameters. Once all daughter board parameters are configured, data DMA is enabled, daughter card synchronization is enabled, and finally, daughter card operation is enabled. The daughter card then begins operation. Finally, it follows the... Figure 2After data processing, the data is uploaded. If power is lost, the process is repeated.

[0042] Figure 4 A flowchart illustrating a high-precision time synchronization process according to an embodiment of the present disclosure is shown, such as... Figure 4 As shown, this system supports IRIG-B, NTP, and PPS time synchronization. If the main CPU is connected to IRIG-B or PPS time synchronization, the system synchronization state will be locked, and it will discipline the motherboard clock according to IRIG-B or PPS time synchronization, generating the required clock synchronization PPS second pulse and subsystem time B code. When the system is connected to PPS time synchronization, the system time is generated using NTP time synchronization for the first time. If the system IRIG-B or PPS is lost, the subsystem clock synchronization PPS will rely on the disciplined clock to maintain high accuracy. When IRIG-B or PPS is not connected, the subsystem time B code depends on NTP time synchronization. If the main CPU detects the loss of PPS or IRIG-B, the CPU will automatically calibrate the subsystem time in the FPGA every minute. The FPGA will then generate the subsystem B code to synchronize the subcard time according to the subsystem time. The subsystem clock synchronization PPS does not depend on NTP time synchronization because NTP time synchronization has poor accuracy. Subsystem synchronization enablement ensures the consistency of subsystem synchronization sampling time information, thus ensuring the synchronization of the entire system.

[0043] Figure 4 The neutron system receives the subsystem time B code, parses the subsystem system time, samples it, and packages it into the protocol. Upon receiving the subsystem clock synchronization PPS, it also disciplines the subsystem clock based on the PPS, ensuring that the subsystem's synchronization sampling error remains within 20ns. The sampling control module generates the ADC sampling rate based on the disciplined sub-card clock and the configured sampling rate control word to control the ADC acquisition. Simultaneously, the synchronization sampling time control module can generate synchronization sampling time information, including year, month, day, hour, minute, second, millisecond, and microsecond. The difference between this time information and the system time information is that it is not affected by external synchronization. This information can be used to analyze the relationship between the data (steady-state data and transient data) collected by different sub-cards in the entire system. The time can be kept absolutely consistent with an error within 20ns. The synchronization sampling time information is also packaged into the protocol for data analysis.

[0044] Therefore, the coordinated time synchronization between the main CPU board and the functional daughterboard can be used to achieve system-wide sampling synchronization and timekeeping under time interruption, wherein:

[0045] The main CPU board supports three time synchronization modes: IRIG-B, NTP, and PPS. When an IRIG-B or PPS signal is received, the main CPU board locks the synchronization state, uses the signal to discipline the motherboard's local clock, and generates the clock synchronization PPS second pulse and subsystem time B code required by the subsystem. When only a PPS signal is received, the initial system time is obtained through NTP time synchronization upon initial power-on. When the IRIG-B or PPS signal is lost, the clock synchronization PPS second pulse is generated by the disciplined motherboard local clock to maintain high-precision output. At the same time, the main CPU automatically calibrates the subsystem time in the FPGA every minute, and the FPGA continuously generates the subsystem time B code based on the calibrated time.

[0046] The functional subboard receives the subsystem time B code and parses out the absolute time information. At the same time, it uses the clock synchronization PPS second pulse as a phase reference to discipline the local clock of the subboard. The sampling control module in the functional subboard drives the ADC to acquire data according to the disciplined subcard clock and sampling rate configuration word. The synchronous sampling time control module generates synchronous sampling time information containing year, month, day, hour, minute, second, millisecond, and microsecond. This time information is independent of the external time source's operating status and is packaged and uploaded along with the sampling data for spatiotemporal correlation analysis of cross-subboard data.

[0047] Figure 5The diagram schematically illustrates a system device according to an embodiment of this disclosure. The diagram includes one CPU motherboard and seven daughterboards, one of which is a fixed communication expansion board, expandable with Ethernet, USB, serial ports, etc. The other six boards can be arbitrarily plugged into: a 200kHz@24-channel non-isolated voltage acquisition daughterboard supporting selectable ±5V and ±500V ranges; a 1MHz@24-channel non-isolated voltage acquisition daughterboard supporting selectable ±5V and ±500V ranges; a 200kHz@8-channel isolated voltage acquisition daughterboard supporting selectable ±5V and ±500V ranges; an 8-channel contact board; an 8-channel environmental variable monitoring board, etc. The system features automatic identification, intelligent control, and automatic result analysis. Future expansion with other types of daughterboards, such as current-type acquisition cards, is also supported, demonstrating strong scalability. A low-noise power supply board is also included. This system supports wide-temperature operation from -40℃ to 70℃ and other type tests compliant with rail transit operation. Specifically, the backplane has seven standard daughterboard slots. The first slot is dedicated to communication expansion boards, used to insert communication expansion boards to provide additional network, serial, or CAN interfaces. The remaining slots are general-purpose slots, allowing for the mixed insertion of at least two of the following: 200kHz sampling boards, 1MHz sampling boards, multi-channel isolation acquisition boards, contact monitoring boards, and environmental variable monitoring boards. The FPGA of the main CPU board integrates a slot identification circuit, which connects to the detection pins of each slot to read the daughterboard ID and automatically load the corresponding configuration parameters. This design ensures that the communication expansion board's position is fixed (facilitating wiring) while providing six general-purpose slots to support mixed insertion. Combined with the slot identification circuit, the system automatically identifies the inserted daughterboard type and ID upon power-up and automatically loads configuration parameters, achieving true on-demand configuration and plug-and-play functionality, greatly enhancing the system's flexibility and scalability.

[0048] Based on the above embodiments, a power supply board is also included; the power supply board is plugged into the backplane and is used to convert the externally input DC power supply into multiple low-voltage power supplies required by each board; the power supply board adopts an architecture combining a low-noise switching power supply and a linear regulator to suppress power ripple and ensure the sampling accuracy of the functional sub-boards.

[0049] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this disclosure. In particular, the features described in the various embodiments and / or claims of this disclosure can be combined or combined in various ways without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0050] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. Although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A multi-channel synchronous data acquisition system for rail transit, characterized in that, Includes the main CPU board, functional daughterboards, and backplane; The backplane is equipped with an inter-board service bus and a three-wire hardware synchronization bus, which includes a sampling time synchronization bus, a system time synchronization bus, and a time synchronization enable bus. The main CPU board is plugged into the backplane and connected to the functional daughter board through the inter-board service bus and the three-wire hardware synchronization bus. It is used to aggregate and process sampled data. The sampling time synchronization bus is used to transmit PPS second pulses to align the sampling phase, the system time synchronization bus is used to transmit IRIG-B code streams to distribute absolute time, and the time synchronization enable bus is used to transmit trigger permission signals to control the sampling start timing. The functional subboard, including subboards of different functional types, is plugged into the backplane and used to collect sampling data.

2. The system according to claim 1, wherein, The inter-board service bus includes RS485 bus, IIC bus, high-speed SerDes bus and SPI bus; The RS485 bus and the IIC bus connect the main CPU board and the functional daughter board, and are used to send configuration parameters according to the functional type of the daughter board; The high-speed SerDes bus connects the main CPU board and the functional daughter board, and is used for uplink transmission of high-speed sampling data; The SPI bus connects the main CPU board and the functional daughter board, and is used to remotely update the FPGA program of the daughter board.

3. The system according to claim 1, wherein, The main CPU board includes a CPU, an FPGA, and a first DDR cache unit; The FPGA is connected to the CPU, the first DDR cache unit, the inter-board service bus and the three-wire hardware synchronization bus, respectively, and is used to parse the protocol, schedule the data stream and generate synchronization signals. The first DDR cache unit is used to cache sampled data; The CPU is connected to the FPGA via a PCIe interface and is used to process application layer logic and external communication.

4. The system according to claim 3, wherein, The main CPU board also includes an IRIG-B decoding interface, an NTP network interface, and a PPS input interface; The IRIG-B decoding interface is connected to an external time source and the FPGA, and is used to decode the external IRIG-B code stream into parallel time data. The NTP network interface connects to an external NTP server and the CPU, and is used to obtain a backup clock source through the Network Time Protocol when the IRIG-B signal is missing, so as to maintain the continuity of system time. The PPS input interface is connected to an external second pulse source and the FPGA to provide a phase reference; The FPGA integrates a digital phase-locked loop (PLL). The input of the PPS is connected to the PPS input interface, and the output is connected to the sampling time synchronization bus. This PPS is used to tame the local clock and output a low-jitter synchronization PPS.

5. The system according to claim 1, wherein, The functional sub-board includes a 200KHz sampling board or a 1MHz sampling board, and the 200KHz sampling board or the 1MHz sampling board includes a sub-board FPGA, ADC and a second DDR cache unit. The daughterboard FPGA is connected to the ADC, the second DDR cache unit and the three-wire hardware synchronization bus respectively, and is used to respond to the PPS second pulse zeroing sampling counter, control the ADC to perform synchronous sampling, and upload sampling data to the main CPU board; The second DDR cache unit, connected to the daughterboard FPGA, is divided into 24 independent physical storage areas for caching transient data from 24 channels.

6. The system according to claim 1, wherein, The functional subboard includes a multi-channel isolation acquisition board; the multi-channel isolation acquisition board includes 8 independent signal acquisition channels.

7. The system according to claim 1, wherein, The functional sub-board includes a contact monitoring board, which includes a high-voltage conditioning circuit and a status recognition FPGA. The high-voltage conditioning circuit is connected to the external circuit breaker contacts and the status recognition FPGA, and is used to attenuate the high-voltage signal to the range that the status recognition FPGA can collect. The status recognition FPGA is connected to the high-voltage conditioning circuit and the RS485 bus. It is used to identify the open and closed state of the contacts, filter the closed state data, and upload it to the main CPU board.

8. The system according to claim 1, wherein, The functional subboard includes an environmental variable monitoring board, which includes at least 8 RS485 physical interfaces and a protocol parsing FPGA. The RS485 physical interface connects the remote environmental sensor and the protocol parsing FPGA, and is used to send and receive environmental sensor data. The protocol parser FPGA is connected to the RS485 physical interface to parse the protocol of the environmental sensor, and performs mean filtering on the environmental sensor data before uploading it to the main CPU board.

9. The system according to claim 1, wherein, The back panel is provided with 7 standard daughterboard slots; The first slot is a dedicated slot for communication expansion cards, used to insert communication expansion cards to provide additional network ports, serial ports or CAN interfaces; The remaining slots are general-purpose slots, which can be used to mix and match at least two of the following: 200KHz sampling board, 1MHz sampling board, multi-channel isolation acquisition board, contact monitoring board, and environmental variable monitoring board; The FPGA of the main CPU board integrates a slot identification circuit, which is connected to the detection pins of each slot to read the daughter board ID and automatically load the corresponding configuration parameters.

10. The system according to claim 1, wherein, It also includes power supply boards; The power supply board is plugged into the backplane and is used to convert the externally input DC power supply into multiple low-voltage power supplies required by each board. The power supply board adopts an architecture that combines a low-noise switching power supply with a linear regulator to suppress power ripple and ensure the sampling accuracy of the functional sub-board.

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