ATE test system and chip test method based on SQPG and ALPG cooperative control

Abstract

The application discloses an ATE test system and chip test method based on SQPG and ALPG cooperative control, relates to the chip test technical field, and comprises an SQPG instruction initialization module, an ALPG instruction initialization module, an SQPG instruction processing unit and an ALPG instruction processing unit. The SQPG instruction initialization module is used for receiving and initializing the SQPG instruction. The ALPG instruction initialization module is used for receiving and initializing the ALPG instruction. The SQPG instruction processing unit is connected with the SQPG instruction initialization module and is used for running the SQPG instruction and generating a first test mode signal. The ALPG instruction processing unit is connected with the ALPG instruction initialization module and is used for running the ALPG instruction and generating a second test mode signal. The mutual connection relationship is established between the SQPG instruction processing unit and the ALPG instruction processing unit, the master-slave cooperative control mechanism is constructed, the flexible switching and ordered output of the two test mode signals are realized, the instruction conflict is avoided, and the overall execution efficiency of the ATE test system is significantly improved.

Description

Technical Field

[0001] This invention relates to the field of chip testing technology, and in particular to an ATE testing system and chip testing method based on the coordinated control of SQPG and ALPG. Background Technology

[0002] With the rapid development of semiconductor technology, the complexity of integrated circuits is increasing. Modern chips often integrate both logic processing and storage functions, which places higher demands on automated test equipment. In existing ATE (Automatic Test Equipment) systems, the pattern generator, as a core component, is responsible for generating test vectors. It mainly includes two types: Sequential Pattern Generator (SQPG) and Algorithmic Pattern Generator (ALPG). SQPG generates test patterns based on predefined instruction sequences, featuring high execution efficiency and deterministic timing, making it suitable for fixed-timing test scenarios of standard digital circuits. ALPG, on the other hand, dynamically generates test vectors based on algorithm descriptions, flexibly generating address, data, and control sequences, making it suitable for complex test scenarios such as March algorithm testing of memory and generation of irregular data patterns.

[0003] However, in practical testing applications, a single type of pattern generator often struggles to meet the comprehensive testing needs of complex chips. For mixed-signal chips that simultaneously contain logic circuits and memory cells, the testing process requires both the high throughput of the SQPG to ensure testing efficiency and the algorithmic flexibility of the ALPG to handle complex memory testing algorithms. In existing technologies, the SQPG and ALPG are typically configured as independent test resources in different test systems, or run in complete isolation within the same system. This design results in the test flow being fragmented into multiple independent stages when mixed testing is required, with each stage needing to load different test programs, significantly increasing test preparation time and the overall test cycle. Summary of the Invention

[0004] The purpose of this invention is to propose an ATE testing system based on the collaborative control of SQPG and ALPG to solve the above-mentioned technical problems.

[0005] Specifically, the present invention provides the following technical solution: an ATE test system based on SQPG and ALPG collaborative control, comprising: an SQPG instruction initialization module for receiving, sending, and initializing the SQPG instruction; an ALPG instruction initialization module for receiving, sending, and initializing the ALPG instruction; an SQPG instruction processing unit connected to the SQPG instruction initialization module for running the SQPG instruction and generating a first test mode signal; an ALPG instruction processing unit connected to the ALPG instruction initialization module for running the ALPG instruction and generating a second test mode signal; a MUX module connected to the SQPG instruction processing unit and the ALPG instruction processing unit for selectively receiving and sending the first test mode signal and the second test mode signal; and a test signal generation module connected to the MUX module for generating a test signal for testing the chip under test based on the selected test mode signal.

[0006] As a preferred embodiment of the ATE test system based on SQPG and ALPG collaborative control according to the present invention, the SQPG instruction processing unit and the ALPG instruction processing unit are interconnected. The SQPG instruction processing unit can run SQPG instructions as the main running unit, and during the running process, it can pause the current running and jump to the ALPG instruction processing unit according to the ALPG jump instruction. At this time, the ALPG instruction processing unit, as the slave running unit, runs ALPG instructions under the control of the SQPG instruction processing unit, and after the running is completed, it sends a return signal to the SQPG instruction processing unit, so that the SQPG instruction processing unit resumes running.

[0007] As a preferred embodiment of the ATE test system based on SQPG and ALPG collaborative control according to the present invention, the test signal generation module includes a To PDS module and a To TG module; wherein, the To PDS module is connected to the MUX module and is used to select a suitable test mode signal from the received test mode signals according to the pin configuration; the To TG module is connected to the To PDS module and is used to generate a test signal with precise timing relationship according to the selected test mode signal, and finally output it to the corresponding pin of the chip under test.

[0008] As a preferred embodiment of the ATE test system based on SQPG and ALPG collaborative control according to the present invention, it further includes a storage module and a cache module; wherein, the storage module is used to store SQPG instructions and ALPG instructions; the cache module is connected to the storage module, the SQPG instruction initialization module and the ALPG instruction initialization module, and is used to transfer the SQPG instructions and the ALPG instructions from the storage module to the corresponding SQPG instruction initialization module and the ALPG instruction initialization module.

[0009] As a preferred embodiment of the ATE test system based on SQPG and ALPG collaborative control according to the present invention, it further includes a host computer control unit; wherein the host computer control unit is connected to the storage module via a PCIE bus; the host computer control unit sends the SQPG command and the ALPG command to the storage module via the PCIE bus.

[0010] As a preferred embodiment of the ATE test system based on SQPG and ALPG collaborative control according to the present invention, the host computer control unit sends the SQPG instruction and the ALPG instruction to the storage module using the same instruction sending method.

[0011] As a preferred embodiment of the ATE test system based on SQPG and ALPG collaborative control according to the present invention, the ATE test system is configured with an SQPG independent mode, an ALPG independent mode, and an SQPG-ALPG collaborative mode; wherein, in the SQPG independent mode, only the SQPG instruction processing unit is enabled to execute the test of the chip under test; in the ALPG independent mode, only the ALPG instruction processing unit is enabled to execute the test of the chip under test; in the SQPG-ALPG collaborative mode, the SQPG instruction processing unit and the ALPG instruction processing unit collaboratively execute the test of the chip under test in a master-slave relationship.

[0012] Specifically, the present invention provides the following technical solution: a chip testing method, applied to the aforementioned ATE testing system, comprising the following steps: S1: The SQPG instruction initialization module and the ALPG instruction initialization module respectively initialize the SQPG instruction and the ALPG instruction; S2: After initialization is complete, start the SQPG instruction processing unit and / or ALPG instruction processing unit to generate the first test mode signal and / or the second test signal; S3: The MUX module selects the first test mode signal and / or the second test signal, and after timing shaping by the test signal generation module, outputs it to the chip under test.

[0013] As a preferred embodiment of the chip testing method of the present invention, in step S1, the SQPG instruction and ALPG instruction are both sent from the host computer control unit to the storage module, and then the SQPG instruction and / or ALPG instruction are transferred from the storage module to the corresponding SQPG instruction initialization module and / or ALPG instruction initialization module through the Cache module.

[0014] In a preferred embodiment of the chip testing method of the present invention, when the host computer control unit only issues an SQPG instruction in step S1, step S2 only activates the SQPG instruction processing unit to run the SQPG instruction to generate a first test mode signal; or, When the host computer control unit in step S1 only issues the ALPG command, step S2 only starts the ALPG command processing unit to run the ALPG command to generate the second test mode signal; or, When the host computer control unit mentioned in step S1 simultaneously issues SQPG and ALPG commands, step S2 includes the following sub-steps: S21: Start the SQPG instruction processing unit as the main execution unit to run the SQPG instruction; S22: When the ALPG jump instruction is reached, the SQPG instruction processing unit pauses its operation and jumps to start the ALPG instruction processing unit as a slave unit to run the ALPG instruction; S23: After the ALPG instruction processing unit finishes running, it sends a return signal to the SQPG instruction processing unit; S24: The SQPG instruction processing unit resumes operation according to the return signal.

[0015] The beneficial effects of this invention are as follows: by establishing an interconnection between the SQPG instruction processing unit and the ALPG instruction processing unit, a master-slave collaborative control mechanism is constructed to realize flexible switching and orderly output of signals for the two test modes, avoid instruction conflicts, and thus significantly improve the overall execution efficiency of the ATE test system. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1This is a diagram showing the operation of an ATE test system based on SQPG and ALPG collaborative control in SQPG independent mode according to an embodiment of the present invention. Figure 2 This is a diagram showing the operation of an ATE test system based on SQPG and ALPG collaborative control in ALPG independent mode according to an embodiment of the present invention. Figure 3 This is a diagram showing the operation of an ATE test system based on SQPG and ALPG collaborative control in the SQPG-ALPG collaborative mode according to an embodiment of the present invention. Figure 4 This is a flowchart of the chip testing method in one embodiment of the present invention; Figure 5 This is a flowchart of a sub-step in step S3 of a chip testing method according to an embodiment of the present invention. Detailed Implementation

[0018] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0019] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0020] Secondly, the term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single embodiment or an embodiment selectively excluded from other embodiments.

[0021] Furthermore, the present invention will be described in detail with reference to the schematic diagrams. When describing the embodiments of the present invention in detail, for ease of explanation, the cross-sectional views of the device structure will be partially enlarged without adhering to the general scale. Moreover, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention.

[0022] ATE: Automatic Test Equipment.

[0023] SQPG: Sequential Pattern Generator.

[0024] ALPG: Algorithmic Pattern Generator.

[0025] DDR: Double Data Rate.

[0026] MUX: multiplexer.

[0027] PDS: Pin Driver Selection.

[0028] TG: Timing Generator.

[0029] Cache: High-speed buffer memory PCIE: Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard.

[0030] Dut: Device Under Test (in this example, it refers to a semiconductor chip or electronic component that is being tested). Example 1 Reference Figures 1-3 In this embodiment, an ATE test system based on SQPG and ALPG collaborative control is proposed for chip testing, specifically for testing a chip under test that simultaneously has logic processing and storage functions. Further, the ATE test system includes an instruction initialization module group, an instruction processing unit group, a MUX module, and a test signal generation module.

[0031] Furthermore, the instruction initialization module group includes an SQPG instruction initialization module and an ALPG instruction initialization module.

[0032] Specifically, the SQPG instruction initialization module is used to send and receive the SQPG instruction and perform initialization operations on the SQPG instruction, such as completing instruction format parsing, parameter configuration, and runtime environment preparation.

[0033] Specifically, the ALPG instruction initialization module is used to send, receive, initialize, and perform initialization operations on the ALPG instruction. It is worth noting that the ALPG instruction initialization module performs initialization operations similar to those of the SQPG instruction initialization module.

[0034] It is worth noting that in this embodiment, the SQPG instruction initialization module and the ALPG instruction initialization module are set independently, so that the SQPG instruction and the ALPG instruction can be prepared in parallel, reducing the waiting time for instruction loading and thus improving the testing efficiency.

[0035] Furthermore, the instruction processing unit group includes an SQPG instruction processing unit connected to the SQPG instruction initialization module and an ALPG instruction processing unit connected to the ALPG instruction initialization module.

[0036] Specifically, the SQPG instruction processing unit is used to run the SQPG instruction and generate a first test mode signal.

[0037] Specifically, the ALPG instruction processing unit is used to run the ALPG instruction and generate a second test mode signal.

[0038] Furthermore, in this embodiment, the SQPG instruction processing unit and the ALPG instruction processing unit are interconnected to achieve collaborative control between them. In use, the SQPG instruction processing unit acts as the master unit, executing SQPG instructions and generating a first test mode signal. During operation, it pauses the current execution and jumps to the ALPG instruction processing unit based on an ALPG jump instruction. At this time, the ALPG instruction processing unit acts as the slave unit, executing ALPG instructions and generating a second test mode signal under the control of the SQPG instruction processing unit. After completion, it sends a return signal to the SQPG instruction processing unit, allowing the SQPG instruction processing unit to resume operation. Thus, through master-slave collaboration, the SQPG and ALPG instruction processing units achieve flexible switching and orderly output of the two test mode signals, avoiding instruction conflicts and improving the overall execution efficiency of the ATE test system described in this embodiment.

[0039] Furthermore, the MUX module is connected to the SQPG instruction processing unit and the ALPG instruction processing unit, and is used to selectively transmit and receive the first test mode signal and the second test mode signal. It is worth noting that in this embodiment, the selection control of the MUX module is automatically configured by the ATE test system according to the current operating mode. In the SQPG independent mode, the first test mode signal is selected; in the ALPG independent mode, the second test mode signal is selected; and in the SQPG-ALPG collaborative mode, the corresponding test mode signal is dynamically selected according to the master-slave switching sequence.

[0040] Furthermore, the test signal generation module is connected to the MUX module and is used to generate test signals for testing the chip under test based on the selected test mode signal.

[0041] Specifically, the test signal generation module includes a To PDS module and a To TG module. The To PDS module is connected to the MUX module and is used to select a suitable test mode signal from the received test mode signals based on the pin configuration. The To TG module is connected to the To PDS module and is used to generate a test signal with precise timing relationships based on the selected test mode signal, ultimately outputting it to the corresponding pin of the chip under test. This hierarchical signal processing architecture decouples test mode generation from pin timing control, improving the system's flexibility and configurability.

[0042] Furthermore, the ATE testing system described in this embodiment also includes a storage module and a cache module.

[0043] Specifically, such as Figure 1 As shown, the storage module is used to store SQPG and ALPG instructions. In this embodiment, the storage module includes a DDR memory, which has the characteristics of high bandwidth and large capacity, and can partition and store SQPG and ALPG instructions, as well as meet the high-speed access requirements for instruction data during ATE testing.

[0044] Specifically, such as Figure 1 As shown, the Cache module is connected to the storage module, the SQPG instruction initialization module, and the ALPG instruction initialization module. It is used to move the SQPG instructions and the ALPG instructions from the storage module to the corresponding SQPG instruction initialization modules and the ALPG instruction initialization modules, thereby reducing instruction reading latency, improving instruction loading speed, and ensuring the continuity and real-time performance of the test process.

[0045] It is worth noting that in this embodiment, a cache module is set up to handle the SQPG and ALPG instructions. During the handling process, the cache module pre-decodes and verifies the format of the instructions to ensure their integrity and correctness. By pre-decoding and verifying the format of the instructions, the time overhead of instruction parsing can be shifted from the runtime of the instruction processing unit to the initialization phase, avoiding impact on the real-time testing process and improving the continuity and stability of the test.

[0046] Furthermore, the ATE testing system described in this embodiment also includes a host computer control unit. Specifically, as shown... Figure 1As shown, the host computer control unit is connected to the storage module via a PCIe bus. In use, the host computer control unit sends the SQPG and ALPG instructions to the storage module via the PCIe bus. It is worth noting that the PCIe bus has high bandwidth; in this embodiment, using the PCIe bus to send instructions ensures the rapid transmission of a large number of test instructions, meeting the data transmission rate requirements of large-scale integrated circuit testing. Simultaneously, the PCIe bus also has low latency, significantly shortening the response time between instruction issuance and execution, thereby reducing test preparation time and improving the real-time performance and throughput of the test system.

[0047] In addition, the host computer control unit is also responsible for the scheduling management and anomaly monitoring of the instruction sequence, and dynamically verifies the integrity during instruction transmission to ensure that the SQPG instruction and the ALPG instruction are accurately loaded into the storage module and take effect synchronously.

[0048] It is worth noting that the host computer control unit uses the same instruction sending method to send the SQPG and ALPG instructions to the storage module, so as to simplify the host computer software architecture and facilitate unified management and scheduling, such as instruction storage management, instruction lifecycle management, configuration and status management, sending order scheduling, running mode scheduling, resource scheduling, etc.

[0049] Furthermore, the ATE test system described in this embodiment is configured with three operating modes: SQPG independent mode, ALPG independent mode, and SQPG-ALPG collaborative mode. In SQPG independent mode, only the SQPG instruction processing unit is activated to execute the test of the chip under test. In ALPG independent mode, only the ALPG instruction processing unit is activated to execute the test of the chip under test. In SQPG-ALPG collaborative mode, the SQPG instruction processing unit and the ALPG instruction processing unit collaboratively execute the test of the chip under test in a master-slave relationship.

[0050] In summary, this embodiment proposes an ATE test system based on the coordinated control of SQPG and ALPG, including a storage module, an instruction initialization module group, an instruction processing unit group, a MUX module, and a test signal generation module. The storage module uses DDR memory to implement partitioned storage of SQPG and ALPG instructions.

[0051] The instruction initialization module group is connected to the storage module and includes an SQPG instruction initialization module and an ALPG instruction initialization module, which are used to perform initialization operations on the SQPG instruction and the ALPG instruction, respectively. The SQPG instruction initialization module and the ALPG instruction initialization module are set independently, so that the two types of instructions can be prepared in parallel, thereby effectively reducing the instruction loading waiting time.

[0052] The instruction processing unit group includes an SQPG instruction processing unit and an ALPG instruction processing unit, respectively connected to the SQPG instruction initialization module and the ALPG instruction initialization module. The SQPG instruction processing unit executes SQPG instructions and generates a first test mode signal, while the ALPG instruction processing unit executes ALPG instructions and generates a second test mode signal. Furthermore, the SQPG and ALPG instruction processing units are interconnected, forming a unique master-slave collaborative control mechanism. Specifically, the SQPG instruction processing unit acts as the master unit, executing SQPG instructions and generating the first test mode signal. During execution, when an ALPG jump instruction is encountered, the current execution is paused, and the execution jumps to the ALPG instruction processing unit. At this time, the ALPG instruction processing unit acts as the slave unit, executing ALPG instructions and generating the second test mode signal under the control of the SQPG instruction processing unit. After completion, it sends a return signal to the SQPG instruction processing unit, allowing the SQPG instruction processing unit to resume execution. Through master-slave collaboration, flexible switching and orderly output of the two test mode signals are achieved, avoiding instruction conflicts and significantly improving the overall execution efficiency of the ATE test system.

[0053] The MUX module is connected to the instruction processing unit group, that is, to the SQPG instruction processing unit and the ALPG instruction processing unit, and is used to selectively send and receive the first test mode signal and the second test mode signal. In the SQPG independent mode, the first test mode signal is selected, and in the ALPG independent mode, the second test mode signal is selected. In the SQPG-ALPG collaborative mode, the corresponding test mode signal is dynamically selected according to the master-slave switching timing.

[0054] The test signal generation module includes a To PDS module and a To TG module. The To PDS module selects a suitable test mode signal from the received test mode signals according to the pin configuration. The To TG module generates a test signal with precise timing relationship according to the selected test mode signal and outputs it to the corresponding pin of the chip under test. In a hierarchical signal processing architecture, the generation of test mode signals and pin timing control are decoupled, thereby improving the flexibility and configurability of the ATE test system.

[0055] In addition, the system is equipped with a cache module and a host computer control unit. The cache module is connected to the storage module, the SQPG instruction initialization module, and the ALPG instruction initialization module. It is used to transfer SQPG and ALPG instructions from the storage module to the corresponding initialization modules to reduce instruction read latency, improve instruction loading speed, and ensure the continuity and real-time performance of the testing process. The host computer control unit is connected to the storage module via a PCIe bus and uses the same instruction distribution method to distribute SQPG and ALPG instructions to the storage module. This simplifies the host computer software architecture, facilitates unified management and scheduling, and is responsible for instruction sequence scheduling management and anomaly monitoring. It dynamically verifies the integrity of instructions during transmission to ensure that both types of instructions are accurately loaded into the storage module and take effect synchronously.

[0056] At this point, through the configuration of the aforementioned modules and units, the ATE test system can operate in three modes: SQPG independent mode, ALPG independent mode, and SQPG-ALPG collaborative mode. In SQPG independent mode, only the SQPG instruction processing unit is used to execute the test of the chip under test (DUT), fully leveraging SQPG's efficient generation capabilities in fixed timing modes. This is suitable for standard digital circuit testing scenarios where SQPG timing is the primary factor. In ALPG independent mode, only the ALPG instruction processing unit is used to execute the DUT test, suitable for memory chips or logic circuits requiring algorithmic generation of complex test vectors. In SQPG-ALPG collaborative mode, the two instruction processing units collaborate in a master-slave relationship to execute the DUT test, suitable for complex testing scenarios requiring a combination of sequential execution efficiency and algorithmic flexibility.

[0057] Example 2 This embodiment is used to specifically describe the workflow of the SQPG standalone mode.

[0058] Specifically, the SQPG independent mode is suitable for standard digital circuit testing scenarios where SQPG timing is the primary factor, and can fully leverage the efficient generation capabilities of SQPG in fixed timing modes. Its workflow is as follows: The host computer control unit sends the SQPG command to the storage module via the PCIE bus.

[0059] The Cache module moves the SQPG instruction from the storage module to the SQPG instruction initialization module to perform initialization operations, including configuring the working parameters of the SQPG instruction processing unit, setting the initial address pointer, and loading the loop counter.

[0060] After initialization is complete, the SQPG instruction processing unit is started, and the SQPG instruction processing unit generates a first test mode signal.

[0061] The first test mode signal is processed by the MUX module (which is configured to select the SQPG channel), the To PDS module, and the To TG module for timing shaping, and then output to the chip under test.

[0062] In summary, in the SQPG independent mode, the ALPG instruction processing unit is idle, the ALPG instruction initialization module does not load instructions, and the MUX module always selects the SQPG channel for output. Operating in single-channel mode allows the ATE test system to centrally allocate resources to SQPG processing, avoiding resource contention and timing synchronization issues caused by multi-module collaboration, and meeting the needs of scenarios with high test throughput requirements.

[0063] Example 3 This embodiment is used to specifically describe the workflow of the ALPG standalone mode.

[0064] Specifically, the ALPG independent mode is suitable for testing memory chips or logic circuits that require algorithms to generate complex test vectors, such as March algorithm testing of memory and generation of irregular data patterns. It can flexibly generate address, data, and control sequences. Its workflow is as follows: The host computer control unit sends ALPG instructions to the storage module via the PCIe bus. The ALPG instructions typically contain complex data structures such as algorithm descriptions, initial data, and address generation functions. Their data volume is often larger than that of the SQPG instructions, and therefore they rely more on the high bandwidth characteristics of the PCIe bus.

[0065] The Cache module moves the ALPG instruction from the storage module to the ALPG instruction initialization module for initialization.

[0066] It is worth noting that, in this embodiment, since the ALPG instruction involves algorithm parameter configuration, the Cache module needs to parse the algorithm description block and extract key parameters for use by the ALPG instruction initialization module during the process of handling the ALPG instruction. Therefore, the ALPG instruction initialization module configures the arithmetic unit, address generator, data generator, and other sub-modules of the ALPG instruction processing unit according to the algorithm type.

[0067] After initialization, the ALPG instruction processing unit is started, and the ALPG instruction processing unit generates a second test mode signal.

[0068] The second test mode signal is output to the chip under test via the selected MUX module (the MUX module is configured to select the ALPG channel at this time), the To PDS module, and the To TG module.

[0069] It is worth noting that in the ALPG independent mode, the host computer control unit adopts the same instruction issuance method and interface protocol as the SQPG independent mode. This unified software interface eliminates the need for test program developers to concern themselves with the specific operating modes of the underlying hardware; they only need to specify the mode parameters in the test program, significantly reducing the development difficulty and maintenance costs of the test program.

[0070] Example 4 This embodiment is used to specifically introduce the workflow of the SQPG-ALPG collaborative mode.

[0071] Specifically, the SQPG-ALPG collaborative mode is suitable for complex testing scenarios that require a combination of sequential execution efficiency and algorithmic flexibility, such as inserting specific algorithm-generated data segments during traversal testing, or embedding irregular test sequences within regular graphs. Its workflow is as follows: The host computer control unit simultaneously sends SQPG and ALPG instructions to the storage module via the PCIe bus. The simultaneous sending of the SQPG and ALPG instructions ensures that both types of instructions are ready in sync, laying the foundation for subsequent collaborative operation.

[0072] It is worth noting that in this embodiment, the SQPG and ALPG instructions are stored in partitions within the storage module, but the same instruction format and transmission protocol are used in the delivery process.

[0073] The cache initialization module moves the SQPG instruction from the storage module to the SQPG instruction initialization module and the ALPG instruction to the ALPG instruction initialization module, and performs initialization operations on the two types of instructions to shorten the preparation time of the ATE test system and improve test efficiency.

[0074] The SQPG instruction processing unit is started and begins running the SQPG instructions as the main running unit. It is worth noting that after the SQPG and ALPG instructions are initialized, both the SQPG and ALPG instruction processing units are in a standby state. However, at this time, only the SQPG instruction processing unit is started as the main running unit to run the SQPG instructions, while the ALPG instruction processing unit remains in standby mode.

[0075] When the ALPG jump instruction is executed, the master-slave switching mechanism is triggered, and the SQPG instruction processing unit suspends its current operation and jumps to the ALPG instruction processing unit.

[0076] The ALPG instruction processing unit receives a start signal to begin running the ALPG instruction from the running unit, while the SQPG instruction processing unit remains in a paused state, waiting for the return signal from the ALPG instruction processing unit.

[0077] It is worth noting that during master-slave switching, the MUX module switches the signal selection channel to the ALPG channel according to the system controller configuration, enabling the second test mode signal to be output to the chip under test via the To PDS and To TG modules. This dynamic channel switching mechanism achieves seamless connection between the two test mode signals, avoiding signal interruptions or glitches during the testing process.

[0078] After the ALPG instruction processing unit finishes its operation, it sends a return signal to the SQPG instruction processing unit.

[0079] Upon receiving the return signal, the SQPG instruction processing unit resumes the execution of the suspended SQPG instructions. It is worth noting that at this time, the MUX module switches the signal selection channel back to the SQPG channel, enabling the first test mode signal to be output to the chip under test again.

[0080] The first test mode signal and the second test mode signal generated by the SQPG instruction processing unit and the ALPG instruction processing unit are both provided to the MUX module. The appropriate test mode signal is selected by the To PDS module, and the test signal is generated by the To TG module and output to the chip under test.

[0081] In summary, the SQPG-ALPG collaborative mode adopts a master-slave collaborative operation approach, which can fully leverage the high throughput of SQPG and the flexibility of ALPG. This enables the ATE testing system to efficiently handle complex and ever-changing testing requirements in a single testing process, avoiding the time overhead caused by traditional testing solutions that require loading different test programs multiple times, and significantly improving the overall testing efficiency and resource utilization of the ATE testing system.

[0082] Example 5 Reference Figure 4 and Figure 5 In this embodiment, an ATE test system based on the collaborative control of SQPG and ALPG is proposed and applied to the ATE test systems described in Embodiments 1 to 4. Includes the following steps: S1: The SQPG instruction initialization module and the ALPG instruction initialization module perform initialization operations on the SQPG instruction and the ALPG instruction, respectively.

[0083] S2: After initialization is complete, start the SQPG instruction processing unit and / or ALPG instruction processing unit to generate the first test mode signal and / or the second test signal.

[0084] S3: The MUX module selects the first test mode signal and / or the second test signal, and after timing shaping by the test signal generation module, outputs it to the chip under test; specifically, the first test mode signal and / or the second test signal are sequentially timing shaped by the To PDS module and the To TG module.

[0085] It is worth noting that when the SQPG instruction processing unit is running, the MUX module selects the first test mode signal; when the ALPG instruction processing unit is running, the MUX module selects the second test mode signal.

[0086] It is worth noting that in step S1, the SQPG and ALPG instructions are both sent from the host computer control unit to the storage module, and then the SQPG and / or ALPG instructions are transferred from the storage module to the corresponding SQPG instruction initialization module and / or ALPG instruction initialization module through the Cache module.

[0087] In an optional embodiment, when the host computer control unit in step S1 only issues the SQPG instruction, step S2 only starts the SQPG instruction processing unit to run the SQPG instruction to generate the first test mode signal.

[0088] In an optional embodiment, when the host computer control unit in step S1 only issues the ALPG instruction, step S2 only starts the ALPG instruction processing unit to run the ALPG instruction to generate the second test mode signal.

[0089] In an optional embodiment, when the host computer control unit in step S1 simultaneously issues SQPG and ALPG commands, step S2 includes the following sub-steps: S21: Start the SQPG instruction processing unit as the main execution unit to run the SQPG instruction.

[0090] S22: When the ALPG jump instruction is reached, the SQPG instruction processing unit pauses its operation and jumps to start the ALPG instruction processing unit as a slave unit to run the ALPG instruction.

[0091] S23: After the ALPG instruction processing unit finishes running, it sends a return signal to the SQPG instruction processing unit.

[0092] S24: The SQPG instruction processing unit resumes operation according to the return signal.

[0093] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. An ATE test system based on the collaborative control of SQPG and ALPG, characterized in that, include, The SQPG instruction initialization module is used to send, receive, and initialize the SQPG instruction. An ALPG instruction initialization module is used to send, receive, and initialize the ALPG instruction. The SQPG instruction processing unit is connected to the SQPG instruction initialization module and is used to run the SQPG instruction and generate a first test mode signal. An ALPG instruction processing unit, connected to the ALPG instruction initialization module, is used to run the ALPG instruction and generate a second test mode signal. The MUX module is connected to the SQPG instruction processing unit and the ALPG instruction processing unit, and is used to selectively transmit and receive the first test mode signal and the second test mode signal. as well as, The test signal generation module, connected to the MUX module, is used to generate test signals for testing the chip under test based on the selected test mode signal.

2. The ATE testing system as described in claim 1, characterized in that, The SQPG instruction processing unit and the ALPG instruction processing unit are interconnected. The SQPG instruction processing unit can run SQPG instructions as the main running unit, and during the running process, it can pause the current running and jump to the ALPG instruction processing unit according to the ALPG jump instruction. At this time, the ALPG instruction processing unit, as the slave running unit, runs ALPG instructions under the control of the SQPG instruction processing unit, and sends a return signal to the SQPG instruction processing unit after the running is completed, so that the SQPG instruction processing unit can resume running.

3. The ATE testing system as described in claim 1, characterized in that, The test signal generation module includes a To PDS module and a To TG module; wherein, The To PDS module is connected to the MUX module and is used to select a suitable test mode signal from the received test mode signals according to the pin configuration. The To TG module is connected to the To PDS module and is used to generate a test signal with precise timing relationship based on the selected test mode signal, and finally output it to the corresponding pin of the chip under test.

4. The ATE testing system as described in claim 1, characterized in that, It also includes a storage module and a cache module; among which, The storage module is used to store SQPG and ALPG instructions; The Cache module is connected to the storage module, the SQPG instruction initialization module, and the ALPG instruction initialization module, and is used to transfer the SQPG instruction and the ALPG instruction from the storage module to the corresponding SQPG instruction initialization module and the ALPG instruction initialization module.

5. The ATE testing system as described in claim 4, characterized in that, It also includes a host computer control unit; among which, The host computer control unit is connected to the storage module via a PCIe bus; The host computer control unit sends the SQPG and ALPG instructions to the storage module via the PCIE bus.

6. The ATE testing system as described in claim 5, characterized in that, The host computer control unit sends the SQPG and ALPG commands to the storage module using the same command sending method.

7. The ATE testing system as described in claim 5, characterized in that, The ATE testing system is configured with SQPG independent mode, ALPG independent mode, and SQPG-ALPG collaborative mode; among which... In the SQPG standalone mode, only the SQPG instruction processing unit is enabled to perform the test of the chip under test; In the ALPG standalone mode, only the ALPG instruction processing unit is enabled to perform the test of the chip under test; In the SQPG-ALPG collaborative mode, the SQPG instruction processing unit and the ALPG instruction processing unit collaborate to perform the test of the chip under test in a master-slave relationship.

8. A chip testing method, applied to the ATE testing system as described in any one of claims 1 to 7, characterized in that, Includes the following steps: S1: The SQPG instruction initialization module and the ALPG instruction initialization module respectively initialize the SQPG instruction and the ALPG instruction; S2: After initialization is complete, start the SQPG instruction processing unit and / or ALPG instruction processing unit to generate the first test mode signal and / or the second test signal; S3: The MUX module selects the first test mode signal and / or the second test signal, and after timing shaping by the test signal generation module, outputs it to the chip under test.

9. The chip testing method as described in claim 8, characterized in that, In step S1, the SQPG and ALPG instructions are both sent from the host computer control unit to the storage module, and then the SQPG and / or ALPG instructions are transferred from the storage module to the corresponding SQPG instruction initialization module and / or ALPG instruction initialization module through the Cache module.

10. The chip testing method as described in claim 9, characterized in that, When the host computer control unit in step S1 only issues the SQPG command, step S2 only starts the SQPG command processing unit to run the SQPG command to generate the first test mode signal; or, When the host computer control unit in step S1 only issues the ALPG command, step S2 only starts the ALPG command processing unit to run the ALPG command to generate the second test mode signal; or, When the host computer control unit mentioned in step S1 simultaneously issues SQPG and ALPG commands, step S2 includes the following sub-steps: S21: Start the SQPG instruction processing unit as the main execution unit to run the SQPG instruction; S22: When the ALPG jump instruction is reached, the SQPG instruction processing unit pauses its operation and jumps to start the ALPG instruction processing unit as a slave unit to run the ALPG instruction; S23: After the ALPG instruction processing unit finishes running, it sends a return signal to the SQPG instruction processing unit; S24: The SQPG instruction processing unit resumes operation according to the return signal.

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