An interface pin testing device and an interface pin testing method

Abstract

The application discloses an interface pin testing device and method, and relates to the technical field of circuit testing.The device controls an excitation unit to generate an alternating current testing signal through a control unit, and applies the testing signal to the pins of an interface to be tested through a switching unit, collects a response signal of the pins to be tested under the excitation of the alternating current testing signal, calculates impedance parameters, and determines the impedance type of a testing circuit in which the pins to be tested are located according to the phase angle in the impedance parameters.The application solves the technical problems that a multimeter and other instruments can only roughly measure direct current resistance, cannot identify the states of capacitors and inductors in a circuit, cannot measure through direct-current isolation elements such as network transformers, and different interfaces need to be built in different testing environments, resulting in high testing costs.The application can accurately identify the types of resistance, capacitance and inductance in a circuit and quantitatively output the parameter values of elements, and achieves the technical effect of automatic polling testing of multiple interfaces by a single device.

Description

Technical Field

[0001] This application relates to the field of circuit testing technology, and in particular to an interface pin testing device and interface pin testing method. Background Technology

[0002] Computer boards typically have various connector interfaces for signal interconnection between boards and between boards and peripherals. During the research, development, verification, and production testing of computer boards, electrical tests are often required on these connector interfaces to confirm the soldering quality of each interface pin, the continuity of the circuit, and the correct installation of related peripheral components. As the integration of computer boards continues to increase and the types of interfaces become more diverse, the pin definitions, electrical characteristics, and peripheral circuit topologies of different interfaces vary, placing higher demands on testing work.

[0003] Currently, testing of computer board connector interfaces mainly employs two methods: functional testing and static impedance testing. Functional testing involves setting up a real-world application environment that matches the interface under test, connecting actual compatible boards or peripherals, and observing whether the interface functions correctly. However, this method requires corresponding test boards and fixtures for different interfaces, and the test environment setup is complex and costly. Furthermore, the test environment reusability between different board models is poor, leading to a sharp increase in testing costs as the number of interface types increases. Static impedance testing involves using instruments such as multimeters to measure the DC resistance of the pins of the interface under test. While this method is relatively simple to operate, it is limited by the DC testing principle. When DC blocking capacitors or network transformers are present in the circuit, the DC signal is blocked, making it impossible to measure the actual connection status at the transformer or capacitor's end. This means that such interfaces can only be tested in a real-world environment and cannot be quickly verified on the production line or during the R&D stage. Summary of the Invention

[0004] This application provides an interface pin testing device and interface pin testing method to at least solve the problems that traditional multimeters can only measure DC resistance and cannot identify the capacitive / inductive state in the circuit and cannot penetrate DC blocking components for measurement, as well as the high testing cost caused by the need to build different test environments for different interfaces.

[0005] This application provides an interface pin testing device, comprising: a control unit, an excitation unit, a switching unit, a signal acquisition unit, and a calculation unit; the control unit is electrically connected to the excitation unit, the switching unit, the signal acquisition unit, and the calculation unit respectively; the output terminal of the excitation unit is connected to the input terminal of the switching unit, the output terminal of the switching unit is used to connect to the interface under test, the acquisition signal output terminal of the switching unit is connected to the input terminal of the signal acquisition unit, and the output terminal of the signal acquisition unit is connected to the input terminal of the calculation unit; the excitation unit is configured to generate an AC test signal under the control of the control unit; the switching unit is configured to time-division switching the AC test signal to each pin of the interface under test; the signal acquisition unit is configured to acquire the response signal of the pin under test of the interface under test under the excitation of the AC test signal, and convert the response signal into a digital signal and send it to the calculation unit; the calculation unit is configured to calculate the impedance parameter of the pin under test based on the digital signal, the impedance parameter including a phase angle; the control unit is configured to determine the impedance type of the test circuit where the pin under test is located based on the phase angle; the impedance type includes resistive, capacitive, and inductive.

[0006] This application also provides an interface pin testing method, characterized by comprising: the control unit receiving a test command issued by a host computer, and controlling the switching unit to switch the output terminal of the excitation unit to the pin under test of the interface under test; the excitation unit generating an AC test signal under the control of the control unit, and the AC test signal being output to the pin under test via the switching unit; the signal acquisition unit acquiring the response signal of the pin under test under the excitation of the AC test signal, and converting the response signal into a digital signal and sending it to the calculation unit; the calculation unit calculating the impedance parameters of the test circuit where the pin under test is located based on the digital signal, the impedance parameters including a phase angle; the control unit further determining the impedance type of the test circuit where the pin under test is located based on the phase angle, the impedance type including resistive, capacitive, and inductive; the switching unit switching to the next pin, repeating the above steps until the pin testing of the interface under test is completed.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described interface pin testing methods when executing the computer program.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described interface pin testing methods.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described interface pin testing methods.

[0010] In summary, by applying an AC test signal to the pin under test and acquiring the response signal, the test signal can penetrate DC blocking components such as network transformers and DC blocking capacitors, obtaining complete impedance information of the test circuit where the pin is located. Furthermore, by calculating the phase angle of the response signal and classifying the test circuit into resistive, capacitive, or inductive based on the sign and magnitude of the phase angle, the system can clearly distinguish whether components such as capacitors and inductors exist in the circuit or whether their parameters are correct. This solves the problem that traditional multimeters can only measure DC resistance and cannot identify capacitive / inductive states, and that DC blocking components cannot measure such interfaces. At the same time, by using a switching unit to time-division switch the AC test signal of a single excitation source to each pin of the interface under test, multi-pin polling tests can be automatically completed without replacing the test board, solving the problem of high testing costs caused by the need to build different test environments for different interfaces. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A schematic diagram of an interface pin testing device in the prior art; Figure 2 This is a structural block diagram of an interface pin testing device according to some embodiments; Figure 3 This is a schematic diagram of an interface pin testing apparatus according to some embodiments; Figure 4 This is a schematic diagram of a calibration unit provided according to some embodiments; Figure 5 This is a schematic diagram of another interface pin testing apparatus provided according to some embodiments; Figure 6 This is a flowchart illustrating an interface pin testing method according to some embodiments; Figure 7 This is a schematic diagram of the calibration process for an interface pin testing method provided according to some embodiments.

[0013] The components include: 1. Control unit; 2. Excitation unit; 3. Switching unit; 4. Signal acquisition unit; 5. Calculation unit; 6. Calibration unit; 100. Interface pin testing device; 110. Communication interface; 120. Host computer. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0015] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The specific application environment architecture or specific hardware architecture on which the interface pin test device depends for execution is described here.

[0018] In the field of interface testing for computer boards, since the types, number, and pin definitions of interfaces on different models of computer boards vary, traditional testing methods usually require a corresponding test board or functional test fixture for each type of board under test.

[0019] like Figure 1 As shown, a complete test environment often requires the combination of CPU daughter cards, memory modules, motherboards and multiple dedicated interface daughter cards to simulate the actual working state of the interface.

[0020] First, different models of circuit boards require different test boards and fixtures, making them unusable across different models. As the number of circuit board models increases, the investment in testing equipment grows linearly, leading to a sharp rise in costs. Furthermore, the setup and debugging of the test environment is complex, requiring professional technicians and resulting in long test preparation times, making it difficult to meet the efficiency requirements of mass production testing. In addition, the test boards themselves are also subject to damage and aging risks, requiring regular maintenance and calibration, which further increases testing costs.

[0021] In addition to the functional testing methods mentioned above, some scenarios also use instruments such as multimeters to test DC impedance; however, this method also has many limitations.

[0022] On the one hand, multimeter testing requires manual contact with each pin to be tested, which is cumbersome and inefficient. When faced with interfaces with a large number of pins, it is easy to miss tests or make false tests due to poor contact. On the other hand, as mentioned above, multimeters are based on the principle of DC testing and cannot penetrate components such as DC blocking capacitors or network transformers that may exist in the interface circuit. Therefore, they cannot effectively verify the actual connection status of such interface pins.

[0023] Based on this, this application provides an interface pin testing device, which connects to different models of computer boards through a unified standard interface, such as... Figure 2 As shown, for different models of computer boards under test, only an adapter cable that matches the interface form under test needs to be connected to this device. There is no need to equip each board with a dedicated test board or functional test fixture. The specific device is as follows.

[0024] Figure 3 The present invention is a schematic diagram of an interface pin testing device according to some embodiments. The interface pin testing device 100 includes: a control unit 1, an excitation unit 2, a switching unit 3, a signal acquisition unit 4, and a calculation unit 5.

[0025] The control unit 1 is electrically connected to the excitation unit 2, the switching unit 3, the signal acquisition unit 4, and the calculation unit 5 respectively. The output terminal of the excitation unit 2 is connected to the input terminal of the switching unit 3. The output terminal of the switching unit 3 is used to connect to the interface under test. The acquisition signal output terminal of the switching unit 3 is connected to the input terminal of the signal acquisition unit 4. The output terminal of the signal acquisition unit 4 is connected to the input terminal of the calculation unit 5.

[0026] Excitation unit 2 is configured to generate an AC test signal under the control of control unit 1; switching unit 3 is configured to time-division switching the AC test signal to each pin of the interface under test; signal acquisition unit 4 is configured to acquire the response signal of the pin under test of the interface under test under the excitation of the AC test signal, and convert the response signal into a digital signal and send it to calculation unit 5; calculation unit 5 is configured to calculate the impedance parameters of the pin under test based on the digital signal, the impedance parameters including the phase angle.

[0027] Control unit 1 is configured to determine the impedance type of the test circuit where the pin under test is located based on the phase angle; the impedance type includes resistive, capacitive and inductive.

[0028] The impedance type in this application does not refer to the resistive, capacitive, or inductive properties of the pin under test alone, but rather to the overall impedance characteristics exhibited by the pin under test and the entire test circuit connected to its back end, including but not limited to pin traces, pull-up resistors, pull-down resistors, series matching resistors, filter capacitors, common-mode inductors, network transformers, and the input impedance of the back-end chip, under AC excitation.

[0029] First, under the control of the control unit 1, the excitation unit 2 generates an AC test signal. This AC test signal is applied to the pin of the interface under test via the switching unit 3. Since an AC test signal is used instead of a DC signal, the AC test signal can penetrate the DC blocking capacitor and network transformer and other DC blocking components in the back-end circuit of the pin under test. This allows the signal acquisition unit 4 to acquire a response signal containing complete circuit information of the pin's back end, thus solving the problem that traditional multimeters cannot measure this type of interface because the DC signal is blocked by the DC blocking components.

[0030] Based on this, the calculation unit 5 calculates the impedance parameters of the test circuit where the pin under test is located according to the collected response signal. The impedance parameters include at least the phase angle. The control unit 1 determines the impedance type of the test circuit as resistive, capacitive or inductive based on the phase angle.

[0031] In this way, the interface pin test device 100 can not only determine the continuity of the pin line, but also clearly distinguish the impedance type in the line. For example, when a matching capacitor that should exist in the line is missing, the phase angle will not show the expected capacitive characteristics, thus it can be accurately identified as an anomaly. This solves the problem that traditional multimeters can only roughly measure the resistance value and cannot identify the state of capacitance and inductance in the line.

[0032] Furthermore, in the interface pin testing device 100, the switching unit 3 switches the AC test signal generated by the single excitation unit 2 to each pin of the interface under test in a time-division manner, realizing automated polling test of multiple pins by a single excitation source. Compared with the existing method that requires different test boards for different interfaces, this device can complete the test of all pins one by one without replacing any hardware, which greatly reduces the cost of the test equipment and improves the efficiency of batch testing on the production line.

[0033] In summary, the interface pin testing device 100 is scheduled as a whole by the control unit 1, the excitation unit 2 provides AC test signals, the switching unit 3 realizes channel multiplexing and pin rotation testing, the signal acquisition unit 4 completes the digital acquisition of response signals, and the calculation unit 5 undertakes the calculation of impedance parameters. The functional units work together to achieve automated and accurate impedance testing of computer board interface pins.

[0034] In some embodiments, the control unit 1 determines the impedance type of the pin under test based on the phase angle, specifically including: When the absolute value of the phase angle is less than or equal to the preset threshold, the test circuit where the pin under test is located is determined to be in a pure resistance state.

[0035] When the phase angle is less than the negative preset threshold, the test circuit where the pin under test is located is determined to be in a capacitive state.

[0036] When the phase angle is greater than the positive preset threshold, the test circuit where the pin under test is located is determined to be in an inductive state.

[0037] The preset threshold in this application refers to a pre-set phase angle critical value used to determine the impedance type. This threshold can be set according to the actual test accuracy requirements. For example, if it is set to 5 degrees, when the absolute value of the phase angle is less than or equal to the preset threshold, it indicates that the voltage and current of the test circuit are basically in phase, and the resistance component dominates. Therefore, it is determined to be a pure resistance state.

[0038] The negative preset threshold is the opposite of the preset threshold, i.e., the negative phase angle critical value. When the phase angle is less than the negative preset threshold, it indicates that the current phase leads the voltage phase, and the capacitive load dominates in the test circuit, so it is judged as a capacitive state.

[0039] The positive preset threshold is the preset threshold itself; when the phase angle is greater than the positive preset threshold, it indicates that the voltage phase leads the current phase, and the inductive load dominates in the test circuit, so it is determined to be inductive.

[0040] Based on the above criteria, this application divides the continuous range of phase angle values ​​into three non-overlapping sub-ranges, corresponding to the pure resistive state, capacitive state, and inductive state, respectively, thereby realizing the classification of the impedance type of the test circuit.

[0041] First, by setting a preset threshold, taking 5 degrees as an example, when the absolute value of the phase angle calculated by the calculation unit 5 is less than or equal to 5 degrees, the control unit 1 determines that the test circuit is in a purely resistive state. This criterion actually reflects that the voltage and current of the test circuit are basically in phase. At this time, the capacitive and inductive components in the test circuit are weak, and the resistive component is absolutely dominant. Based on this, if the circuit design of the test circuit is expected to have a matching capacitor, but the actual measurement result shows a purely resistive state, it indicates that the matching capacitor may not be installed correctly or has failed, thus it can be accurately identified and an anomaly can be reported.

[0042] Meanwhile, when the phase angle is less than the negative preset threshold, i.e. less than -5 degrees, the current phase leads the voltage phase, indicating that the capacitive component dominates in the test circuit, and it is determined to be a capacitive state.

[0043] Similarly, when the phase angle is greater than the positive preset threshold, i.e., greater than +5 degrees, the voltage phase leads the current phase, indicating that the inductive component dominates in the test circuit, and it is determined to be inductive.

[0044] For example, the control unit controls the switching unit to connect at least two sets of precision resistors with different resistance values, acquires the sampling data corresponding to each precision resistor, and calculates the calibration gain value. The calibration gain satisfies the following relationship: Gain = ;in, and This calibration step, which measures the nominal value of the precision resistor on the measuring device, eliminates systematic errors caused by hardware paths and excitation sources.

[0045] After calibration, the testing phase begins. Under the control of the control unit 1, the excitation unit 2 generates a sinusoidal AC test signal. This sinusoidal AC test signal is applied to the current target pin of the interface under test via the switching unit 3. The signal acquisition unit 4 acquires the response signal of the current pin under the excitation of the sinusoidal AC test signal, converts the response signal into a digital signal, and sends it to the calculation unit 5. The calculation unit 5 performs discrete Fourier transform calculation on the acquired signal, extracts the sine and cosine components corresponding to the excitation frequency, and obtains the real part R and the imaginary part I of the impedance of the test circuit where the current pin is located, i.e.: Z = R + jX, where R is the real part of the impedance and X is the imaginary part of the impedance.

[0046] Calculation unit 5 also calculates the phase angle φ based on the real and imaginary parts mentioned above. The calculation method is: φ = arctan(X / R), meaning the phase angle is determined by the ratio of the imaginary part to the real part of the impedance. Simultaneously, the calculation unit calculates the impedance amplitude |Z| based on the calibration gain Gain, the real part R of the impedance, and the imaginary part I of the impedance: |Z| = R is the real part of the value obtained by the device, and I is the imaginary part; if it is a capacitor, |Z|= C is the capacitance value of the device being tested, and f is the operating frequency of the device; if it is an inductor, L, where L is the inductance value in this test.

[0047] After acquiring the phase angle, the control unit determines the impedance type of the test circuit where the current pin is located according to the relationship between the phase angle and the preset threshold, based on the following rules (the preset threshold is ±5 degrees in this embodiment): In the first scenario: when the absolute value of the phase angle is less than or equal to 5 degrees, control unit 1 determines that the test circuit containing the current pin is in a purely resistive state. In this case, calculation unit 5 outputs the impedance amplitude |Z| as the resistance value. For example, setting the gain Gain = 10... -6 With an excitation frequency f = 10 kHz, and the real part of the impedance R = 5000 and the imaginary part I = 10 obtained by calculation unit 5, the phase angle φ ≈ 0°6′, and its absolute value is approximately 0°, falling within the threshold range of ±5°. Control unit 1 determines that the test circuit is in a purely resistive state, and the impedance amplitude |Z| = 1 / (10 -6 ×√(5000²+10²))≈200Ω, and the calculation unit 5 outputs this value as the resistance value of the pin.

[0048] The second scenario: When the phase angle is less than the negative preset threshold, i.e., less than -5 degrees, the control unit 1 determines that the test circuit where the current pin is located is in a capacitive state. At this time, the calculation unit 5 calculates and outputs the capacitance value based on the impedance amplitude |Z| and the current excitation frequency f. The capacitance value is calculated as: C=1 / (2πf|Z|).

[0049] Where C is the capacitance of the test circuit, f is the current operating excitation frequency of the device, and |Z| is the impedance amplitude. For example, setting the gain Gain=10... -6 With an excitation frequency f=1kHz, the real part of the impedance R=100 and the imaginary part of the impedance I=-3183 obtained by the calculation unit 5, the phase angle φ≈-88°, which is less than the threshold of -5°. The control unit 1 determines that the test circuit is in a capacitive state; the impedance amplitude |Z|≈31830Ω, the calculation unit 5 calculates the capacitance value C=1 / (2π×1000×31830)≈5nF according to the formula, and outputs the capacitance value.

[0050] The third case: When the phase angle is greater than the positive preset threshold, that is, greater than +5 degrees, the control unit 1 determines that the test circuit where the current pin is located is in an inductive state; at this time, the calculation unit 5 calculates the inductance value according to the impedance amplitude |Z| and the current excitation frequency f and outputs it. The inductance value is calculated as: L=|Z| / (2πf).

[0051] Where L is the inductance of the test circuit, f is the current excitation frequency of the device, and |Z| is the impedance amplitude; for example, setting the gain Gain=10-6 With an excitation frequency f=1kHz, the real part of the impedance R=50 and the imaginary part of the impedance I=3140 obtained by the calculation unit 5, the phase angle φ≈89°, which is greater than the threshold of +5°. The control unit 1 determines that the test circuit is inductive. The impedance amplitude |Z|≈3140Ω. The calculation unit 5 calculates the inductance value L=3140 / (2π×1000)≈0.5H according to the formula and outputs the inductance value.

[0052] After completing the test of the current pin, the control unit controls the switching unit to switch to the next pin to be tested, repeating the above process of excitation, acquisition, calculation and judgment until all pins of the interface under test have been tested. In this way, the device realizes the automatic classification and identification of the impedance type of the test circuit where each pin of the computer board interface is located and the quantitative output of component parameter values.

[0053] In some embodiments, the calculation unit 5 is further configured to calculate the impedance amplitude of the test circuit where the pin under test is located based on the real part and the imaginary part of the impedance.

[0054] When the control unit 1 determines that the test circuit where the pin under test is located is in a purely resistive state, the calculation unit 5 is configured to output the impedance amplitude as the resistance value of the test circuit.

[0055] When the control unit 1 determines that the test circuit where the pin under test is located is in a capacitive state, the calculation unit 5 is configured to calculate and output the capacitance value of the test circuit based on the impedance amplitude and the frequency of the AC test signal.

[0056] When the control unit 1 determines that the test circuit where the pin under test is located is in an inductive state, the calculation unit 5 is configured to calculate and output the inductance value of the test circuit based on the impedance amplitude and the frequency of the AC test signal.

[0057] The impedance magnitude mentioned above refers to the impedance magnitude of the test circuit under AC excitation, that is, the magnitude of the complex impedance Z=R+jX, which is the ratio of the voltage magnitude to the current magnitude, and characterizes the total degree of obstruction of the test circuit to the AC signal.

[0058] After the control unit 1 determines the impedance type of the test circuit according to the above three-segment criterion, the calculation unit 5 further calculates the impedance amplitude based on the real part and the imaginary part of the impedance, and then calculates the corresponding component parameter values ​​according to different impedance types (refer to the above embodiment).

[0059] When the test circuit is determined to be in a purely resistive state, since both capacitive and inductive components can be ignored, the impedance amplitude is equal to the equivalent resistance value of the test circuit. At this time, no additional conversion is required, and the impedance amplitude can be directly output as the resistance value.

[0060] When the test circuit is determined to be in a capacitive state, the capacitive component in the test circuit dominates. The calculation unit 5 calculates the equivalent capacitance value of the test circuit based on the impedance amplitude and the current excitation frequency.

[0061] When the test circuit is determined to be in an inductive state, the inductive component in the test circuit dominates. The calculation unit 5 calculates the equivalent inductance value of the test circuit based on the impedance amplitude and the current excitation frequency.

[0062] Through the above method, this embodiment further achieves precise quantification of resistance, capacitance and inductance values, enabling testers to not only know what type of impedance the test circuit where the pin is located presents, but also to obtain the corresponding specific parameter values, which are easy to compare with the design values, thereby accurately identifying abnormalities such as incorrect component parts and parameter deviations.

[0063] Through the coordinated operation of the aforementioned calculation unit 5 and control unit 1, this device not only achieves qualitative determination of impedance type, but also further realizes quantitative output of component parameters, providing a more comprehensive and accurate detection method for production line testing.

[0064] like Figure 4 As shown, in some embodiments, the interface pin testing device 100 further includes a calibration unit 6.

[0065] The input terminal of calibration unit 6 is connected to the signal output terminal of switching unit 3; calibration unit 6 includes multiple precision resistors, which are configured to be connected to the test circuit in calibration state.

[0066] The switching unit 3 is also configured to selectively apply an AC test signal to the calibration unit 6 or the pin of the interface under test.

[0067] In this application, calibration unit 6 refers to a functional module used to calibrate the systematic error of the device. Its function is to eliminate measurement errors, thereby ensuring the accuracy and consistency of test results.

[0068] The calibration state refers to a working mode that the device periodically enters before or during formal testing. In this mode, the switching unit 3 switches the AC test signal output by the excitation unit 2 from the pin of the interface under test to the calibration unit 6, so that the AC test signal is applied to the precision resistor in the calibration unit 6.

[0069] Precision resistors are standard resistors with known resistance values ​​and high precision. Their resistance deviations are precisely calibrated at the factory and can be used as a reference for calculating and correcting device gain.

[0070] Selectively applying AC test signals to the calibration unit 6 or the pins of the interface under test means that the switching unit 3, under the control of the control unit 1, can switch between two connection paths: when the switching unit 3 selects the calibration unit 6, the AC test signal flows into the precision resistor, and the device enters the calibration state; when the switching unit 3 selects the interface under test, the AC test signal flows into the pin under test, and the device enters the test state. Through this setting, the calibration unit 6 and the interface under test share the same excitation source and the same signal acquisition channel, eliminating the need for additional independent calibration instruments to complete system self-calibration, simplifying the device structure and reducing hardware costs.

[0071] First, since the excitation unit 2 in this device may have nonlinear deviations in output gain during actual operation, and the response characteristics of the signal acquisition unit 4 may also differ at different frequency points, if the above-mentioned system errors are not calibrated, the impedance parameters calculated by the calculation unit 5 based on the response signal will deviate from the true value, thereby affecting the accuracy of the control unit 1 in determining the impedance type.

[0072] To address the aforementioned issues, this embodiment includes a calibration unit 6 containing multiple precision resistors. The switching unit 3 is configured to selectively apply an AC test signal to either the calibration unit 6 or the pins of the interface under test. In this manner, the calibration unit 6 and the interface under test share the same excitation source and the same signal acquisition link. Without the need for additional calibration instruments or disconnection of the interface under test, the calibration state can be switched at any time before or during the test.

[0073] Meanwhile, the calibration unit 6 contains multiple precision resistors with different resistance values. The nominal resistance value of each precision resistor is known, and it can cover different impedance measurement ranges. When the device enters the calibration state, the switching unit 3 applies the AC test signal to each of the different precision resistors one by one. The signal acquisition unit 4 acquires the response signal of each precision resistor under the excitation of the AC test signal. The calculation unit 5 calculates the measured impedance value of each precision resistor based on the response signal. The control unit 1 compares the measured impedance value with the nominal resistance value of each precision resistor to calculate the calibration parameters such as system gain deviation and phase offset under the current operating conditions. Based on the calibration parameters, when the pin under test is tested subsequently, the calculation unit 5 can compensate and correct the measurement results, thereby eliminating measurement errors and significantly improving the accuracy of impedance parameter measurement.

[0074] For example, the calibration unit 6 includes at least two sets of precision resistors with different resistance values, which are switched by the switching unit 3 and connected to the test circuit in stages to obtain calibration values, thus preventing miscalibration caused by a single resistor verification failure.

[0075] During the calibration phase, control unit 1 connects precision resistors with different resistance values ​​to the test circuit through switching unit 3, obtains the sampling data corresponding to each precision resistor, and establishes a system correction model based on the nominal value and the corresponding measured value of each precision resistor. This calibration method can effectively eliminate the gain deviation caused by the parasitic parameters of the analog-to-digital conversion front end and the circuit, ensure the consistency and accuracy of the device in long-cycle production line testing, and also provide an accurate benchmark for the subsequent impedance parameter calculation of the pin under test.

[0076] like Figure 4 As shown, in some embodiments, the control unit 1 connects precision resistors with different resistance values ​​to the test circuit through the switching unit 3 in the calibration state, obtains the sampling data corresponding to each precision resistor, and establishes a system correction model based on the nominal value and the corresponding measured value of each precision resistor; the calculation unit 5 is also configured to correct the impedance parameters according to the system correction model.

[0077] The system correction model in this application refers to the mathematical correction relationship established during the calibration phase based on the correspondence between the nominal value of the precision resistor and the measured value of the device, which is used to eliminate system errors.

[0078] Due to the combined effects of factors such as the output gain deviation of excitation unit 2, the response difference of signal acquisition unit 4 at different frequencies, the contact resistance of the internal path of switching unit 3, and the parasitic parameters of transmission cable, the measured impedance value calculated by calculation unit 5 based on the response signal often deviates from the true value of the object under test, and the degree of deviation may show different patterns at different frequency points and different impedance ranges.

[0079] Therefore, in this embodiment, the control unit 1 connects precision resistors with different resistance values ​​to the test circuit through the switching unit 3 in the calibration state, obtains the measured value corresponding to each precision resistor, and then establishes a system correction model based on the difference between the nominal value and the corresponding measured value of each precision resistor.

[0080] The nominal value refers to the standard resistance value marked when the precision resistor leaves the factory, which serves as the reference value in this calibration process.

[0081] The measured value refers to the impedance measurement value obtained by this device when the precision resistor is actually measured under calibrated conditions.

[0082] The correction model can be expressed in various forms such as gain correction coefficient, phase offset compensation value or frequency response correction curve, so that when the pin under test is tested, the calculation unit 5 can compensate and correct the measurement results according to the model, so that the corrected impedance parameter is close to the true value.

[0083] First, the control unit 1 connects precision resistors with different resistance values ​​to the test circuit one by one through the switching unit 3, obtains the sampling data corresponding to each precision resistor, and establishes a system correction model based on the nominal value and the corresponding measured value of each precision resistor. By using multiple precision resistors with different resistance values ​​to perform tests in stages and establishing a system correction model, different impedance ranges can be covered, so that the correction model has a good correction effect in the entire range.

[0084] Meanwhile, when the calculation unit 5 tests the pin under test in the future, it corrects the impedance parameters according to the system correction model. After the calculation unit 5 calculates the initial impedance parameters of the test circuit where the pin under test is located based on the response signal, it does not directly output the initial value as the final result. Instead, it compensates and corrects the initial impedance parameters according to the corresponding relationship in the system correction model to eliminate the influence of system error and obtain the corrected impedance parameters that are closer to the true value.

[0085] like Figure 5 As shown, in some embodiments, the communication terminal of the control unit 1 is bidirectionally connected to the communication terminal of the host computer 120 through the communication interface 110. The control unit 1 receives the excitation frequency and test parameters from the host computer 120 through the communication interface 110 and uploads the test results to the host computer 120 through the communication interface 110.

[0086] In some embodiments, the control unit 1 is also connected to the host computer 120 via a USB interface (communication interface 110) to output control signals and test data to the host computer 120 via the USB interface.

[0087] In this application, the host computer 120 refers to an external control device independent of the interface pin testing device 100, such as a personal computer, industrial control computer, server, or testing machine, which is used to send control commands to this device and receive test data.

[0088] The communication interface 110 refers to the physical and protocol interface for data interaction between this device and the host computer 120, which can be implemented in the form of a general serial bus interface, a network interface, or a serial communication interface 110.

[0089] Two-way communication connection means that data can be transmitted bidirectionally between the host computer 120 and this device. That is, the host computer 120 can send instructions and parameters downward, and this device can send test results and data back to the host computer 120.

[0090] Excitation frequency refers to the parameter obtained by control unit 1 from host computer 120 according to test requirements, which is used to set the frequency of AC test signal output by excitation unit 2. Different types of interfaces under test or pin lines with different characteristics may require different test frequencies to obtain the best measurement sensitivity.

[0091] Test parameters refer to other configurable operating parameters besides the excitation frequency. The control unit 1 communicates bidirectionally with the host computer 120 through the communication interface 110. It can receive control information from the host computer 120 and output test result data to the host computer 120 through the communication interface 110, thereby realizing human-computer interaction and centralized management of test data.

[0092] First, the communication terminal of the control unit 1 is bidirectionally connected to the communication terminal of the host computer 120 through the communication interface 110. With the above configuration, the host computer 120 can send test parameters including excitation frequency and gain level to this device according to different types of computer boards under test or different test requirements, without having to manually DIP switches or hardware jumpers set the device before each test.

[0093] After receiving the test parameters through the communication interface 110, the control unit 1 configures the output frequency and gain of the excitation unit 2 accordingly, thereby enabling the device to flexibly adapt to different interface types, different pin characteristics and different test specifications, thus improving the versatility and ease of use of the device.

[0094] Furthermore, the host computer 120 can automatically determine the pass / fail status based on the received test data. For example, it can compare the measured capacitance value with the design nominal value. If the deviation exceeds the allowable range, it is determined to be unqualified. Testers do not need to manually interpret the measurement data of each pin. The entire test process does not require manual intervention, which significantly improves the production line testing efficiency.

[0095] In some embodiments, the excitation unit 2 is a sinusoidal excitation source group; the output terminal of the sinusoidal excitation source group is connected to the input terminal of the switching unit 3; the sinusoidal excitation source group is configured to generate a sinusoidal AC test signal under the control of the control unit 1.

[0096] The sinusoidal excitation source group in this application refers to the specific implementation of the excitation unit 2 that can generate a sinusoidal AC test signal under the control of the control unit 1; so that when the sinusoidal AC test signal is applied to the test circuit where the pin under test is located, the response signal acquired by the signal acquisition unit 4 also has the same frequency components as the excitation signal, only the amplitude and phase change.

[0097] The calculation unit 5 can accurately extract the amplitude and phase information of the response signal by performing DFT analysis on the specific frequency. At the same time, since the amplitude and phase of the sinusoidal signal will change regularly with frequency when passing through energy storage elements such as capacitors and inductors, the sinusoidal AC test signal is most suitable for impedance measurement and determination of RC inductance type.

[0098] First, the sinusoidal excitation source group generates a sinusoidal AC test signal under the control of the control unit 1, enabling the signal acquisition unit 4 to acquire the response signal containing complete circuit information of the pin back end. The use of a sinusoidal signal as the excitation source in impedance measurement is based on the frequency domain uniformity of the sinusoidal signal. The linear characteristics of the test circuit ensure that the response signal has the same frequency as the excitation signal, with only the amplitude and phase changing. This allows the calculation unit 5 to accurately extract the amplitude and phase information of the response signal at a single frequency point through the DFT algorithm, avoiding spectral leakage and measurement errors caused by harmonic components.

[0099] In some embodiments, the signal acquisition unit 4 is an analog-to-digital converter chipset; the input terminal of the analog-to-digital converter chipset is connected to the acquisition signal output terminal of the switching unit 3, and the output terminal of the analog-to-digital converter chipset is connected to the input terminal of the calculation unit 5.

[0100] The analog-to-digital converter chipset in this application refers to an electronic device or device group that can convert analog signals into digital signals. The input end receives the analog response signal transmitted from the acquisition signal output end of the switching unit 3, and the output end sends the converted digital signal to the computing unit 5 for subsequent processing.

[0101] The acquisition signal output terminal is a port of the switching unit 3, which is used to extract the response signal acquired from the pin under test and transmit it to the signal acquisition unit 4. During the test, the AC test signal generated by the excitation unit 2 is applied to the pin under test through the switching unit 3. The signal flows through the test circuit where the pin under test is located and generates a response signal. The response signal is sent to the input terminal of the analog-to-digital converter chip group through the acquisition signal output terminal of the switching unit 3.

[0102] The input terminal of the analog-to-digital converter chip is connected to the acquisition signal output terminal of the switching unit 3, so that the analog response signal returned from the test circuit where the pin under test is located can be directly sent to the analog-to-digital converter chip for digital acquisition via the switching unit 3. Unlike traditional multimeters, this device realizes automatic acquisition and digital conversion of response signals through the analog-to-digital converter chip. During the process of the switching unit 3 polling each pin one by one, the response signal corresponding to each pin is automatically acquired by the analog-to-digital converter chip, without the need for manual point-by-point operation. The whole process is continuous and efficient.

[0103] In some embodiments, the calculation unit 5 is a digital signal processing chipset; the digital signal processing chipset is configured to calculate the real part of the impedance, the imaginary part of the impedance, and the phase angle of the test circuit where the pin under test is located based on the digital signal.

[0104] The digital signal processing chipset in this application refers to a microprocessor or chipset specifically designed for digital signal processing operations, capable of performing a large number of complex number operations in a very short time.

[0105] In this application, the digital signal processing chipset is used as a specific implementation of the computing unit 5. The input is the digital signal output by the analog-to-digital converter chipset, and the output is the calculated impedance parameters such as the real part of the impedance, the imaginary part of the impedance, and the phase angle.

[0106] Digital signals refer to discrete digital sequences obtained by sampling the analog response signals of the pins under test at equal intervals under AC test signal excitation by an analog-to-digital converter chip.

[0107] The real part and imaginary part of impedance refer to R and X in the complex impedance Z=R+jX of the test circuit, where the real part R represents the resistive component in the test circuit and the imaginary part X represents the reactive component (capacitive reactance or inductive reactance).

[0108] The phase angle refers to the phase offset of the response signal relative to the excitation signal. It satisfies the following relationship with the real and imaginary parts of the impedance: the tangent of the phase angle is equal to the ratio of the imaginary part to the real part of the impedance (when the real part is not zero); the sign of the phase angle directly reflects the impedance type of the test circuit. When the imaginary part is zero or negligible, it exhibits resistive characteristics; when the imaginary part is negative, it exhibits capacitive characteristics; and when the imaginary part is positive, it exhibits inductive characteristics.

[0109] First, after the analog-to-digital converter chipset converts the analog response signal into a digital signal, complex number operations need to be performed on the digital signal to extract impedance information.

[0110] Based on this, this embodiment uses a digital signal processing chipset as the computing unit 5. Utilizing its hardware architecture optimized for digital signal processing algorithms, it can complete complex number operations such as Fourier transform in a very short time. After receiving a large amount of sampled data from the analog-to-digital converter chipset, the digital signal processing chipset quickly calculates the real and imaginary parts of the impedance. After obtaining the real and imaginary parts of the impedance, the digital signal processing chipset further calculates the phase angle without the need for additional analog circuitry, thus avoiding additional errors introduced by the temperature drift and noise of analog devices.

[0111] Then, the digital signal processing chipset transmits the calculated real part of the impedance, imaginary part of the impedance, and phase angle to the control unit 1, which then determines the impedance type. Since the digital signal processing chipset is responsible for processing the large amount of data transmitted by the analog-to-digital conversion chipset and quickly calculating the real part of the impedance, imaginary part of the impedance, and phase angle of the sampled data, the control unit 1 only needs to perform logical judgments and data packaging and uploading based on the calculation results of the digital signal processing chipset.

[0112] Through the division of labor and cooperation between the control unit 1 and the digital signal processing chipset, the control unit 1 focuses on logical judgment, while the digital signal processing chipset focuses on complex number operations on the sampled data, thus achieving parallel processing. This ensures both the speed and accuracy of impedance parameter calculation and the real-time response capability of the device in production line batch testing scenarios.

[0113] Figure 6 This is a flowchart illustrating an interface pin testing method according to some embodiments. The method includes: S1. Control unit 1 receives the test command issued by host computer 120 and controls switching unit 3 to switch the output of excitation unit 2 to the pin under test of the interface under test.

[0114] Switching connection refers to the switching unit 3, under the control of the control unit 1, switching its internal path from the current state to the target state, so that the output of the excitation unit 2 is electrically connected to the current pin under test of the interface under test. Before the test starts, the switching unit 3 may be in an idle state or have completed the test of the previous pin. After receiving the test command from the host computer 120, the control unit 1 first sends a gating control signal to the switching unit 3 to connect the output of the excitation unit 2 to the first pin under test of the interface under test.

[0115] The pin under test refers to the pin currently being tested in the interface under test. During the test, the switching unit 3 selects each pin in a preset order, selecting only one pin at a time to form a complete test circuit, while the other pins are in the off state.

[0116] In step S1, the control unit 1 receives the test command issued by the host computer 120 and controls the switching unit 3 to switch the output of the excitation unit 2 to the current pin under test of the interface under test. Through the above steps, the host computer 120 only needs to issue a test command once to trigger the start of the entire test process. Under the control of the control unit 1, the switching unit 3 automatically completes the selection connection between the output of the excitation unit 2 and the pin under test, eliminating the need for manual wiring point by point, realizing the automated start of the test process, and avoiding wiring errors and time consumption caused by manual operation.

[0117] S2, under the control of the control unit 1, the excitation unit 2 generates an AC test signal, and the AC test signal is output to the pin under test through the switching unit 3.

[0118] In step S2, the excitation unit 2 generates an AC test signal under the control of the control unit 1. This AC test signal is output to the pin under test via the switching unit 3. Since this method uses an AC test signal instead of a DC signal, the AC test signal can penetrate the DC blocking capacitor and network transformer in the back-end circuit of the pin under test, so that the signal acquisition unit 4 can acquire the response signal containing complete circuit information of the pin's back end. The frequency and gain of the AC test signal are configured by the control unit 1 according to the test parameters issued by the host computer 120. The most suitable excitation parameters can be selected for different test scenarios to ensure the sensitivity and accuracy of the measurement.

[0119] S3, Signal acquisition unit 4 acquires the response signal of the pin under test under AC test signal excitation, and converts the response signal into a digital signal and sends it to the calculation unit 5.

[0120] In step S3, the signal acquisition unit 4 acquires the response signal of the pin under test under AC test signal excitation, converts the response signal into a digital signal and sends it to the calculation unit 5. Through the above steps, the analog response signal of the pin under test under AC excitation is automatically acquired and converted into a digital signal, providing a data basis for the subsequent digital domain processing of the calculation unit 5. The entire acquisition and conversion process is automatically completed by the device without the need for manual reading or recording.

[0121] S4, Calculation Unit 5 calculates the impedance parameters of the test circuit where the pin under test is located based on the digital signal. The impedance parameters include the phase angle.

[0122] In step S4, the calculation unit 5 calculates the impedance parameters of the test circuit where the pin under test is located based on the digital signal. The impedance parameters include at least the phase angle. Through the above steps, the calculation unit 5 performs calculation processing on the acquired digital signal and extracts the phase angle parameter used to determine the impedance type from the response signal.

[0123] S5, Control Unit 1 also determines the impedance type of the test circuit where the pin under test is located based on the phase angle.

[0124] Among them, impedance types include resistive, capacitive and inductive.

[0125] In step S5, the control unit 1 determines the impedance type of the test circuit where the pin under test is located based on the calculated phase angle. The impedance type includes resistive, capacitive, and inductive. The control unit 1 determines the impedance type based on the phase angle value, for example, if the phase angle is within ±5°, it is determined to be purely resistive; if the phase angle is negative, it is determined to be capacitive; and if the phase angle is positive, it is determined to be inductive. Thus, the impedance characteristics are identified through the phase response under AC signal, which solves the problem that traditional tests cannot identify the state of capacitance and inductance.

[0126] S6. Switching unit 3 switches to the next pin and repeats the above steps until the pin test of the interface under test is completed.

[0127] Switching to the next pin means that after completing the test of the current pin, the switching unit 3 disconnects the excitation unit 2 from the current pin, selects the next pin to be tested, and makes the output of the excitation unit 2 electrically connected to the newly selected pin.

[0128] "Until the pins of the interface under test are tested" means that the cycle of steps S1-S5 above continues until all the pins of the interface under test that need to be tested have completed the above test process.

[0129] In step S6, the switching unit 3 switches to the next pin and repeats the above steps until all pins of the interface under test are tested. Through the above polling control, after the current pin is tested, the switching unit 3 automatically disconnects the current pin and selects the next pin to be tested. There is no need to manually rewire or move the test probe. The test of all pins is completed automatically, which can further improve the efficiency of batch testing on the production line.

[0130] In summary, this method, through the complete process of steps S1 to S6, achieves a fully automated test cycle from test triggering, pin selection, AC excitation application, response signal acquisition, impedance parameter calculation to impedance type determination. The entire process does not require manual point-by-point operation, nor does it require changing the test board or test fixture for different interface types. It can complete the automated, efficient, and accurate impedance type identification of all pins of the interface under test, and is suitable for mass production line testing scenarios.

[0131] Before the control unit 1 receives the test command from the host computer 120 and the control switching unit 3 switches the output of the excitation unit 2 to the pin under test of the interface under test, a calibration stage is also included: S101, the control unit 1 receives the calibration command issued by the host computer 120, and the control switching unit 3 switches the output of the excitation unit 2 to the calibration unit 6.

[0132] S102, the control unit 1 controls the switching unit to connect precision resistors of different resistance values ​​to the test circuit, and controls the excitation unit 2 to generate an AC test signal to be applied to the currently connected precision resistor.

[0133] S103, Signal Acquisition Unit 4 acquires the response signals of each precision resistor under AC test signal excitation, and converts the response signals into digital signals before sending them to Calculation Unit 5.

[0134] S104, Calculation unit 5 calculates the measured value of each precision resistor based on the digital signal corresponding to each precision resistor.

[0135] S105, Control Unit 1 or Calculation Unit 5 establishes a system correction model based on the nominal value and corresponding measured value of each precision resistor, and completes the calibration.

[0136] The calibration method provided in this application controls the switching unit to switch the output of the excitation unit to the calibration unit during the calibration stage, and connects multiple precision resistors with different resistance values ​​to the test circuit. After obtaining the nominal and measured values ​​of each precision resistor, a system correction model is established. This enables the system error calibration to be completed using precision resistors without the need for external standard instruments or disconnection of the interface under test. It effectively eliminates the influence of factors such as excitation source output deviation, signal acquisition path gain drift, and parasitic parameters of transmission cables and internal paths of the switching unit on the measurement results. This allows the calculation unit to compensate and correct the impedance parameters based on the system correction model when the pin under test is subsequently tested.

[0137] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above-described interface pin testing method embodiments.

[0138] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described interface pin testing method embodiments at runtime.

[0139] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0140] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described interface pin testing method embodiments.

[0141] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described interface pin testing method embodiments.

[0142] Any of the components, modules, units, parts, methods, and operations described herein can be implemented using software, firmware, hardware (e.g., fixed logic circuitry), manual processing, or any combination thereof. Alternatively or additionally, any functionality described herein can be executed at least in part by one or more hardware logic components, such as, but not limited to, a central processing unit (CPU), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), an application-specific standard product (ASSP), a system-on-a-chip (SoC), a complex programmable logic device (CPLD), a microprocessor (MCU), etc. The terms "system," "computing device," or "apparatus" as used herein encompass various means, devices, and machines for processing data, including, for example, one or more programmable processors, computers, SoCs, or combinations thereof. The apparatus may also include code that creates an execution environment for the computer program in question, such as code constituting processor firmware, a protocol stack, a database management system, an operating system, a cross-platform runtime environment, a virtual machine, or one or more combinations thereof. The aforementioned computer program (also known as a program, software, software application, app, script, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages, and can be deployed in any form, including as a standalone program or as a module, component, subroutine, object, or other unit suitable for a computing environment.

[0143] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0144] The interface pin testing device and method provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. An interface pin testing device, characterized in that, include: Control unit, excitation unit, switching unit, signal acquisition unit, and computing unit; The control unit is electrically connected to the excitation unit, the switching unit, the signal acquisition unit, and the calculation unit, respectively; the output terminal of the excitation unit is connected to the input terminal of the switching unit, the output terminal of the switching unit is used to connect to the interface under test, the acquisition signal output terminal of the switching unit is connected to the input terminal of the signal acquisition unit, and the output terminal of the signal acquisition unit is connected to the input terminal of the calculation unit. The excitation unit is configured to generate an AC test signal under the control of the control unit; the switching unit is configured to time-division switching the AC test signal to each pin of the interface under test; the signal acquisition unit is configured to acquire the response signal of the pin under test of the interface under test under the excitation of the AC test signal, and convert the response signal into a digital signal and send it to the calculation unit; the calculation unit is configured to calculate the impedance parameter of the pin under test based on the digital signal, the impedance parameter including the phase angle; The control unit is configured to determine the impedance type of the test circuit in which the pin under test is located based on the phase angle; the impedance type includes resistive, capacitive and inductive.

2. The interface pin testing device according to claim 1, characterized in that, The control unit determines the impedance type of the pin under test based on the phase angle, specifically including: When the absolute value of the phase angle is less than or equal to a preset threshold, the test circuit where the pin under test is located is determined to be in a pure resistance state. When the phase angle is less than the negative preset threshold, the test circuit where the pin under test is located is determined to be in a capacitive state. When the phase angle is greater than the positive preset threshold, the test circuit where the pin under test is located is determined to be in an inductive state.

3. The interface pin testing device according to claim 2, characterized in that, The calculation unit is also used to calculate the impedance amplitude of the test circuit where the pin under test is located based on the real part and the imaginary part of the impedance; When the control unit determines that the test circuit where the pin under test is located is in the pure resistance state, the calculation unit is configured to output the impedance amplitude as the resistance value of the test circuit; When the control unit determines that the test circuit where the pin under test is located is in the capacitive state, the calculation unit is configured to calculate and output the capacitance value of the test circuit based on the impedance amplitude and the frequency of the AC test signal. When the control unit determines that the test circuit where the pin under test is located is in the inductive state, the calculation unit is configured to calculate and output the inductance value of the test circuit based on the impedance amplitude and the frequency of the AC test signal.

4. The interface pin testing device according to claim 1, characterized in that, It also includes a calibration unit; The input terminal of the calibration unit is connected to the signal output terminal of the switching unit; the calibration unit includes multiple precision resistors, which are configured to be connected to the test circuit in the calibration state. The switching unit is also configured to selectively apply the AC test signal to the pins of the calibration unit or the interface under test.

5. The interface pin testing device according to claim 4, characterized in that, In calibration mode, the control unit connects precision resistors with different resistance values ​​to the test circuit through the switching unit, obtains the sampling data corresponding to each precision resistor, and establishes a system correction model based on the nominal value and the corresponding measured value of each precision resistor. The calculation unit is also configured to correct the impedance parameters according to the system correction model.

6. The interface pin testing device according to claim 1, characterized in that, The communication terminal of the control unit is bidirectionally connected to the communication terminal of the host computer through a communication interface. The control unit receives the excitation frequency and test parameters from the host computer through the communication interface and uploads the test results to the host computer through the communication interface.

7. The interface pin testing device according to claim 1, characterized in that, The excitation unit is a sinusoidal excitation source group; The output terminal of the sinusoidal excitation source group is connected to the input terminal of the switching unit; The sinusoidal excitation source group is configured to generate a sinusoidal AC test signal under the control of the control unit.

8. The interface pin testing device according to claim 1, characterized in that, The signal acquisition unit is an analog-to-digital converter chipset; The input terminal of the analog-to-digital converter chip is connected to the acquisition signal output terminal of the switching unit, and the output terminal of the analog-to-digital converter chip is connected to the input terminal of the computing unit.

9. The interface pin testing device according to claim 1, characterized in that, The computing unit is a digital signal processing chipset; The digital signal processing chipset is configured to calculate the real part of the impedance, the imaginary part of the impedance, and the phase angle of the test circuit where the pin under test is located, based on the digital signal.

10. A method for testing interface pins, characterized in that, An interface pin testing apparatus as described in any one of claims 1-9; comprising: The control unit receives the test command issued by the host computer and controls the switching unit to switch the output of the excitation unit to the pin under test of the interface under test. The excitation unit generates an AC test signal under the control of the control unit, and the AC test signal is output to the pin under test via the switching unit. The signal acquisition unit acquires the response signal of the pin under test under the excitation of the AC test signal, and converts the response signal into a digital signal and sends it to the computing unit. The calculation unit calculates the impedance parameters of the test circuit where the pin under test is located based on the digital signal, and the impedance parameters include the phase angle; The control unit also determines the impedance type of the test circuit where the pin under test is located based on the phase angle. The impedance type includes resistive, capacitive and inductive. The switching unit switches to the next pin and repeats the above steps until the pin test of the interface under test is completed.

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