A millimeter wave full-time domain sounding radiometer receiver and noise suppression method

Abstract

The application provides a millimeter wave full-time domain detection radiometer receiver and a noise suppression method, and belongs to the technical field of millimeter wave detection. The receiver adopts a double-path parallel symmetric link, and through input complementary switch switching networks and output complementary switch switching networks, the antenna signal and the reference signal are alternately and uninterruptedly input into two receiving branches under the control of complementary clocks, so that 100% full duty cycle continuous integration is realized; then, in combination with a differential adder, a time-sharing integrator and a synthetic adder, relevant double-sampling noise statistical cancellation is completed in the charge domain, low-frequency noise, DC offset and gain fluctuation are suppressed. Under the same observation time, the effective integration time is increased to 100%, the output noise variance is reduced, the signal-to-noise ratio is theoretically improved times, and the sensitivity limit of the traditional architecture is broken, and the millimeter wave passive imaging system is suitable for security and safety, industrial nondestructive testing and non-ionizing radiation medical diagnosis.

Description

Technical Field

[0001] This application relates to the field of millimeter-wave detection technology, and in particular to a millimeter-wave full-time-domain radiometer receiver and a noise suppression method. Background Technology

[0002] Compared to infrared imaging, millimeter-wave passive imaging offers significant advantages such as strong penetration, no need for active signal transmission, and high concealment, making it highly valuable for applications in security inspection, industrial non-destructive testing, and radiation-free medical diagnostics. One of the core technologies of a high-precision passive imaging detection system is the millimeter-wave passive imaging receiver integrated circuit, whose key performance indicator is the noise equivalent temperature difference (NETD), which theoretically satisfies… Currently, millimeter-wave detector receivers are mainly integrated using silicon-based processes to meet the demands for miniaturization and low cost. The D-band (110-170 GHz) combines moderate atmospheric attenuation with the high performance achievable using current mature silicon-based CMOS processes, and is widely recognized as the golden frequency band for applications such as high-resolution passive imaging.

[0003] In existing technologies, the Dicke switching architecture is commonly used to suppress baseline shift caused by system gain fluctuations. This architecture uses a single-pole double-throw (SPDT) switch at the RF front end, periodically switching between the antenna signal and the reference reference, and using back-end subtraction operations to offset system instability. Currently, the internationally leading sensitivity (NETD=0.13 K) is approaching the theoretical limit of the traditional Dicke architecture, but deep sub-Kelvin level (NETD<0.1 K) detection chips are still lacking.

[0004] However, traditional Dicke receivers have the following defects and shortcomings: ① For example Figure 1 As shown in (a), in a traditional Dicke receiver, the mechanical switching of the SPDT switch introduces a 50% duty cycle hold time, forcing the effective integration time of the antenna signal to be reduced to 50% of the total time. According to the physical formula for sensitivity, halving the effective integration time directly leads to an increase in the theoretical sensitivity coefficient to half of its original value. The temperature difference resolution value increases by a factor of two, resulting in a decrease in detection capability. Simultaneously, since the thermal noise of the antenna path and the reference path are uncorrelated, the subtraction operation makes the total noise variance the sum of the two paths, causing the NETD value to deteriorate by a factor of two compared to the ideal 100% full duty cycle continuous integral state, thus significantly reducing the actual detection capability.

[0005] ② Under mature CMOS technology, severe 1 / f Noise and the small gain wave Δ caused by ambient temperature drift and power supply ripple GDynamic fluctuations remain prominent in the D band. The high-gain characteristics of low-noise amplifiers (LNAs) amplify minute low-frequency disturbances dramatically, resulting in significant baseline drift. Furthermore, due to the inherent random mismatch limitations of CMOS processes, traditional analog cancellation techniques are insufficient in precision to achieve significant cancellation of dynamic fluctuations.

[0006] ③ Domestically, the individual performance indicators of millimeter-wave CMOS LNAs, such as gain, noise, and area, have approached international advanced levels. However, existing research mainly focuses on the performance optimization of key components, and there are still significant shortcomings at the system architecture level. This field faces severe challenges in domestic production, with core receiver chips relying heavily on imports for a long time, and the architectural design of millimeter-wave deep sub-Kelvin level detector chips remains a blank. Summary of the Invention

[0007] The main objective of this application is to propose a millimeter-wave full-time-domain radiometer receiver and a noise suppression method to solve the problems of low effective integration time efficiency, difficulty in suppressing low-frequency noise and gain fluctuations, and inability to achieve deep sub-Kelvin level detection sensitivity in the traditional Dicke architecture.

[0008] To achieve the above objectives, one aspect of this application provides a millimeter-wave full-time-domain sounding radiometer receiver, comprising: A first receiving branch and a second receiving branch, wherein the first receiving branch includes a first low-noise amplifier and a first power detector connected in sequence, and the second receiving branch includes a second low-noise amplifier and a second power detector connected in sequence. The input complementary switch switching network includes first to fourth switches, which are used to alternately and continuously input the target signal and reference reference signal received by the antenna to the input terminals of the first low noise amplifier and the second low noise amplifier, respectively, under the control of a complementary clock signal. The output complementary switching network includes a fifth to an eighth switch, which, under the control of the complementary clock signal, alternately outputs the output signals of the first power detector and the second power detector to the differential adder. A differential adder is used to perform differential operations on the two signals provided by the output complementary switching network. An end-to-end switching switch is used to alternately distribute the differential signal output by the differential adder to the first integrator and the second integrator under the control of the complementary clock signal. The first integrator and the second integrator are used to perform charge integration on the allocated differential signal, respectively. A synthesizing adder is used to add the output voltages of the first integrator and the second integrator to output a stable level signal that is proportional to the temperature difference between the target signal and the reference signal. A complementary clock generation unit is used to generate the complementary clock signal.

[0009] In some embodiments, in the input complementary switch switching network: One end of the first switch and the third switch are connected to the antenna, and one end of the second switch and the fourth switch are connected to the reference reference. The other ends of the first and fourth switches are connected to the input of the first low-noise amplifier, and the other ends of the second and third switches are connected to the input of the second low-noise amplifier. The first and second switches are controlled by a first clock signal in a complementary clock signal, and the third and fourth switches are controlled by a second clock signal in a complementary clock signal, wherein the second clock signal is out of phase with the first clock signal.

[0010] In some embodiments, in the output complementary switching network: One end of the fifth switch and one end of the seventh switch are connected to the output terminal of the first power detector, and one end of the sixth switch and one end of the eighth switch are connected to the output terminal of the second power detector. The other ends of the fifth and eighth switches are connected to the non-inverting input of the differential adder, and the other ends of the sixth and seventh switches are connected to the inverting input of the differential adder. The fifth and sixth switches are controlled by the first clock signal, and the seventh and eighth switches are controlled by the second clock signal.

[0011] In some embodiments, the complementary clock signal causes: In the first half of the cycle, the input complementary switch switching network sends the target signal into the first receiving branch and the reference signal into the second receiving branch. At the same time, the output complementary switch switching network connects the output of the first receiving branch to the in-phase terminal of the differential unit and the output of the second receiving branch to the inverting terminal of the differential unit to generate a first differential signal. The end switch then sends the first differential signal into the first integrator. In the second half of the cycle, the input complementary switch switching network sends the target signal to the second receiving branch and the reference signal to the first receiving branch. At the same time, the output complementary switch switching network connects the output of the second receiving branch to the in-phase terminal of the differential unit and the output of the first receiving branch to the in-phase terminal of the differential unit to generate a second differential signal. The end switch then sends the second differential signal to the second integrator. The first half-cycle and the second half-cycle are continuous and without time gaps, achieving 100% full duty cycle integration.

[0012] In some embodiments, the low-noise amplifiers in the first and second receiving branches adopt the same circuit topology and follow the centroid symmetry principle in layout, so that the average gain, system noise temperature and group delay parameters of the two branches are statistically highly matched.

[0013] In some embodiments, the input terminal of the end switch is connected to the output terminal of the differential adder, its first output terminal is connected to the input terminal of the first integrator, and its second output terminal is connected to the input terminal of the second integrator; the end switch is controlled by the complementary clock signal, wherein when the first clock signal is valid, the output signal of the differential adder is sent to the first integrator, and when the second clock signal is valid, the output signal of the differential adder is sent to the second integrator.

[0014] In some embodiments, both the first integrator and the second integrator employ a current-mode integrator structure. Each integrator includes a transconductance operational amplifier and an integrating capacitor. The inverting input of the transconductance operational amplifier receives a current signal from the end switch, the non-inverting input is connected to analog ground, and the integrating capacitor is connected between the inverting input and the output of the transconductance operational amplifier.

[0015] In some embodiments, the first low-noise amplifier and the second low-noise amplifier have the same circuit topology and are arranged in a centroidally symmetrical layout; the first low-noise amplifier and the second low-noise amplifier operate in a frequency band of 110 GHz to 160 GHz and have a gain of 28 dB to 30 dB.

[0016] In some embodiments, the first to eighth switches are all NMOS transmission transistors with a channel length using the minimum feature size, a total width of 15μm to 25μm for a single transistor, and a deep N-well process.

[0017] To achieve the above objectives, another aspect of this application proposes a noise suppression method based on the millimeter-wave full-time-domain radiometer receiver described above, comprising the following steps: Complementary first and second clock signals are generated by a complementary clock generation unit. During the first half of the clock cycle, the control input complementary switch switching network causes the antenna signal to be input into the first receiving branch and the reference signal to be input into the second receiving branch. At the same time, the control output complementary switch switching network causes the output signals of the first receiving branch and the second receiving branch to be subtracted by the differential adder and then sent to the first integrator for integration by the end switch. In the second half of the clock cycle, the control input complementary switch switching network causes the antenna signal to be input into the second receiving branch and the reference reference signal to be input into the first receiving branch. At the same time, the control output complementary switch switching network causes the output signals of the first receiving branch and the second receiving branch to be subtracted by the differential adder and then sent to the second integrator for integration by the end switch. The integration results of the first integrator and the second integrator are added together by a synthesizer to output a stable level signal that is proportional to the temperature difference between the antenna signal and the reference signal.

[0018] In some embodiments, the noise suppression method further includes: through the coordinated switching of the input complementary switching network and the output complementary switching network, the antenna signal and the reference reference signal experience the same total gain path during the total integration time, thereby canceling the gain mismatch of the two receiving branches.

[0019] In some embodiments, the noise suppression method further includes: utilizing the differential operation of the differential adder and the integral accumulation of the first integrator and the second integrator to achieve statistical noise cancellation based on charge domain correlation double sampling, so as to suppress the 1 / f Noise, DC offset, and gain fluctuations.

[0020] In some embodiments, the modulation period is set to The half-cycle integration time is Total time , If the number of cycles is given, then after the total integration time, the receiver's output voltage is... Approximately:

[0021] in, Let be the response coefficient of the power detector. The system average gain. The equivalent temperature of the target signal. Using the reference equivalent temperature, statistical cancellation of low-frequency noise and gain fluctuations is achieved.

[0022] Compared with the prior art, this application has the following advantages: (1) This application eliminates the traditional single-pole double-throw Dicke switch at the receiver front end, and instead uses a dual-path highly symmetrical receiving link composed of two sets of complementary switching networks (SW1~SW4, SW5~SW8). Under the control of complementary clocks CLK and CLKB, the target signal received by the antenna... S Equivalent voltage to on-chip 50Ω reference R Always enters two equal receiving branches in parallel. G 1 and G2. This ensures that both receiving branches are operational throughout the entire process and always operate simultaneously, thus eliminating the 50% duty cycle hold-up time introduced by traditional Dicke switches. It achieves continuous signal integration across the entire time domain at the physical level, increasing the actual detection time to 100% full duty cycle. In the FTCC architecture, Effective integration time This is equal to the actual observation time. Therefore, the effective signal integration time efficiency of the FTCC architecture is increased from 50% to 100% compared to the traditional Dicke architecture. In terms of integration time alone, this architecture can improve the signal-to-noise ratio by approximately [missing information - likely a percentage] compared to the traditional architecture. times.

[0023] (2) This application utilizes a complementary switching network (SW1-SW8) in conjunction with an end-to-end synthesizer adder. S and R In two highly symmetrical receiving branches ( G 1. G 2) The signal is transmitted alternately and, after subtraction, enters two integrators via the end switch SW9. Finally, an adder performs real-time correlation calculations in the charge domain. Because... S and R Each will pass through two receiving branches. G 1 and G 2. The asymmetry of the two-path gain is canceled out during the summation and averaging. The system output no longer depends on the perfect matching of the two receiving branches. This advantage enables extremely high measurement accuracy even with the large discreteness of CMOS processes, significantly reducing the chip's dependence on the consistency of the fabrication process.

[0024] (3) Through the coordinated operation of the two sets of complementary switching networks (SW1-SW8) and combined with the relevant double sampling (CDS) logic, this application can extract and cancel the offset voltage of the preceding circuit and the 1 / ... f Noise. Modulation frequency f m =1 / T m When the frequency is increased to a level far above the noise inflection point, the system can minimize zero-point drift over long integration times through physical-level correlation cancellation, enabling the system to achieve stable detection at times of 30ms (common integration time) and above. This significantly suppresses zero-point drift over long integration times, ensuring extremely high stability of the detection baseline.

[0025] (4) Based on correlation double sampling, the noise statistical cancellation process, with the charge storage of the capacitor and the current conversion of the transconductance as the core, effectively avoids the nonlinear distortion and saturation that voltage domain operational amplifiers are prone to when processing weak signals, thus ensuring... V outThe system boasts an ultra-high dynamic range. Furthermore, through complementary path design in the charge domain, the system achieves autonomous compensation for gain mismatch between the two receiving branches, significantly reducing the calibration burden on the back-end digital processing. Attached Figure Description

[0026] Figure 1 This is a comparison diagram between the present application and existing technical architectures; in which, Figure 1 (a) shows a typical D-band traditional Dicke receiver architecture. Figure 1 (b) shows the full-time domain detection receiver architecture proposed in the embodiments of this application.

[0027] Figure 2 This is a comparison chart of the effective integration time utilization between the traditional Dicke architecture and the full-time-domain probing architecture (FTCC) of this application in the embodiments of this application.

[0028] Figure 3 This is a schematic diagram illustrating the multidimensional noise suppression principle of the full-time-domain detection architecture in this application embodiment. Detailed Implementation

[0029] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. The step numbers in the following embodiments are set only for ease of explanation, and there is no limitation on the order between the steps. The execution order of each step in the embodiments can be adaptively adjusted according to the understanding of those skilled in the art.

[0030] In the description of this application, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0031] In the description of this application, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0032] In the description of this application, unless otherwise expressly defined, terms such as "setup," "installation," and "connection" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this application in conjunction with the specific content of the technical solution.

[0033] To address the shortcomings and deficiencies of existing technologies, this application provides a dual-path parallel full-time complementary correlated (FTCC) detection architecture, such as... Figure 1 As shown in (b). Unlike the traditional Dicke receiver architecture, this architecture eliminates the single-pole double-throw (SPDT) switch in the RF front end, employing two complementary switching networks consisting of eight SPDT switches SW1-SW4 and SW5-SW8. In the dual-path highly symmetrical receive link, the antenna signal... S (corresponding temperature) T sig and reference signal R (corresponding temperature) T ref Under the control of complementary clocks (CLK / CLKB), alternating and uninterrupted entry into two completely symmetrical receive links is achieved: the first half-cycle f 1: S Enter the first receiving branch G 1, R Entering the second receiving branch G 2; Second half of the cycle f 2: S Entering the second receiving branch G 2, R Enter the first receiving branch G 1. This seamless switching ensures that both receiving branches are operational throughout the entire process and always work simultaneously, eliminating the 50% idle waiting time of traditional architectures and achieving 100% full duty cycle observation time for signal integration. In the FTCC architecture, Effective integration time This is equal to the actual observation time. Therefore, the FTCC architecture achieves 100% effective signal integration time, and theoretically, the signal-to-noise ratio can be improved compared to the traditional Dicke architecture. times.

[0034] Based on this architecture, this application further proposes a noise statistical cancellation method based on charge domain correlated double sampling (CDS), utilizing 1 / f The statistical characteristics of noise and gain fluctuations are used to achieve real-time suppression and statistical cancellation in the charge domain. This is due to the antenna signal... S and reference signalR After passing through two equal receiving branches alternately and performing subtraction operations, the signal enters two integrators via the terminal SW9, and finally passes through a synthesizer to achieve real-time correlation operations in the charge domain. S and R All will pass through G 1 and G 2. This ensures that the gain asymmetry is summed and averaged. By introducing a highly symmetrical charge integral and transconductance summing network at the back end of the FTCC architecture, real-time correlation calculation of the signal in the charge domain is achieved, suppressing noise in multiple dimensions, thereby significantly canceling the offset voltage and low-frequency drift of the preamplifier. When the integration time... At the end, V out The output reaches the temperature difference of the scene ( T sig T ref A stable level proportional to the input voltage (V / V). This current-mode integral readout method avoids the additional noise and mismatch error introduced by traditional voltage-domain adders, thereby improving system stability. The architecture and noise cancellation method proposed in this application systematically solve the technical challenge of simultaneously achieving high sensitivity, stability, and observation efficiency.

[0035] This application proposes a noise statistical cancellation method based on correlated double sampling. The significant cancellation capability of this mechanism for preamplifier offset voltage and low-frequency drift can be demonstrated through formula derivation. A multidimensional mapping model is established between the noise equivalent temperature difference (NETD) and key parameters such as the dual-path common-mode rejection ratio (CMRR), thus intuitively and concretely presenting the multidimensional noise suppression process. The specific process is as follows: (1) Noise model construction This embodiment uses an input reference equivalent noise model. Let the instantaneous RF voltage output by the receiver front-end LNA be... V rf ( t After passing through a PD (square-law detector), the output baseband voltage is... V det ( t The input noise power is proportional to the average power of the input signal. In the millimeter-wave band, according to the Rayleigh-Jeans approximation of Planck's law, the input noise power is proportional to the equivalent noise temperature. T Linear relationship:

[0036] Define the instantaneous gain of the dual-path parallel link as G ( t )= G +Δ G ( t ), PD response coefficient isK d . G The system average gain is given by Δ, which is a gain fluctuation that varies slowly over time. G(t) Due to the gain fluctuation coefficient Δ G / G The value is much less than 1 and the noise term is small, so the second-order cross term Δ can be ignored. G ( t ) ·n i ( t ).

[0037] For D-band high-gain silicon-based receivers, this embodiment decomposes the total system noise contribution into three statistical models: 1) System background noise power ( T rx ): This is expressed as the statistical average of the input equivalent noise temperature. T rx It enters the link along with the signal.

[0038] 2) Low-frequency random processes ( n i ( t ): Covering amplifier offset, power supply jitter noise, and environmental thermal drift 1 / f Noise and drift, after detection, are equivalent to baseband additional voltage noise. n i ( t The amplitude of this noise term is much smaller than that of the signal term, and its correlation time scale is much larger than the modulation period. After being detected by the power detector (PD), this noise term manifests as additional baseband voltage noise.

[0039] 3) Instantaneous thermal expansion and contraction ( i ( t The term ) represents uncorrelated Gaussian white noise determined by thermodynamic statistical properties. This term represents the instantaneous, minute jumps in thermal noise in the power domain, and is statistically uncorrelated because the two physical entities are independent.

[0040] In the FTCC receiver proposed in this application embodiment: the signal path is always connected to the antenna, receiving the equivalent voltage of the target signal in the scene. S (corresponding temperature) T sig The reference circuit is always connected to the on-chip 50Ω reference, and its equivalent voltage... R (corresponding temperature) T ref ).

[0041] This invention uses a face-to-face symmetrical layout to ensure the average system gain of the two branches. G Maintain high consistency and minimize dual-path baseband noise.n 1( t )and n 2( t It has extremely high spatial correlation.

[0042] Therefore, the single-channel output model of the system is defined as:

[0043]

[0044] (2) Noise cancellation analysis based on statistical characteristics Assuming modulation period T m , T m =2 t The half-cycle integration time is t , N The number of periods, the total integration time = N*T m It resets once after each cycle, and because the reset time is very short (1~5 seconds)... μs ), T cycle ≈ T m . Figure 2 A schematic diagram showing the effective integration time utilization of the traditional Dicke architecture and the full-time-domain probing architecture (FTCC) of this application is presented.

[0045] First half of the cycle f 1, 0~ : Receive the antenna signal connected to branch 1 ( S ), receive the reference signal connected to branch 2 ( R The output difference is:

[0046]

[0047]

[0048] Second half of the cycle f 2, ~ : Through on-chip complementary logic switching, the receiving branch 2 is connected to the antenna signal ( S ), receive branch 1 connection reference signal ( R The output difference is:

[0049]

[0050]

[0051] Total charge in a single period :

[0052] like Figure 3 As shown, after the total integration time back, V out= Q cycle / C int After differential integration and averaging over multiple periods, the system output is:

[0053]

[0054] Figure 3 This demonstrates the multidimensional noise suppression process of the FTCC architecture: 1) Integration time Average gain fluctuation within, After multiple averagings, the effect is negligible.

[0055] 2) Receiver system equivalent noise power ( T rx In differential operations, the receiver's own equivalent noise temperature... T rx As a common-mode component, it is directly canceled out. This means that by T rx The DC output bias caused by absolute value changes is effectively suppressed, thereby significantly reducing the drift of the output baseline.

[0056] 3) For two paths 1 / f Periodic averaging of the noise difference. From a signal processing perspective, this process is equivalent to implementing a discrete-time comb filter in the charge domain, whose transfer function | H ( f )| 2 =4sin 2 ( πf · T m / 2) Exhibits significant second-order high-pass rejection characteristics in the low-frequency range, accurately capturing and eliminating low-frequency 1 / f Noise components. Modulation frequency. f m =1 / T mWhen the frequency is increased to a level much higher than the noise inflection point, the system can reduce the zero-point drift under long integration time to a minimum through physical-level correlation cancellation, which can support the system to achieve stable detection at the order of 30ms (common integration time) and above.

[0057] 4) total ( t The ) represents the residual uncorrelated thermal fluctuations. According to the radiometer equation, the root mean square value of this residual term varies with the integration time. t int The increase and according to Proportional decay.

[0058] Therefore, when the integration time At the end, V out The output reaches the temperature difference of the scene ( T sig T ref A stable level proportional to the input voltage. This current-modulus integration readout method avoids the additional noise and mismatch error introduced by traditional voltage-domain adders, thereby improving system stability.

[0059] The solutions of the embodiments of this application will be described in detail and explained below with reference to specific application examples.

[0060] See Figure 1 In embodiment (b), this application proposes a dual-path parallel full-time-domain sounding radiometer receiver, which adopts a fully symmetrical dual-branch architecture and includes the following components: First receiving branch G 1. Target signal from antenna S It consists of an input complementary switch switching network, a complementary clock generation unit, a first low-noise amplifier LNA1 and a first power detector PD1, an output complementary switch switching network, a first differential adder Diff-Adder, an end switch SW9, a first integrator Integrator1, and a synthesis adder Sum-Adder.

[0061] Second receiving branch G 2. From the reference signal R It consists of an input complementary switch switching network, a complementary clock generation unit, a second low-noise amplifier LNA2 and a second power detector PD2, an output complementary switch switching network, a first differential adder Diff-Adder, an end switch SW9, a second integrator Integrator2, and a synthesis adder Sum-Adder.

[0062] The input complementary switch network consists of four NMOS transmission transistors, SW1 to SW4. To balance insertion loss and turn-off isolation, the total width of each transistor in this embodiment is selected to be between 15μm and 25μm. The channel length adopts the minimum feature size of the process node, and a deep N-well process is used to isolate substrate noise. The control is driven by a complementary clock unit (CLK / CLKB). One end of SW1 and SW3 is connected to the antenna, and one end of SW2 and SW4 is connected to an on-chip 50Ω reference. The other ends of SW1 and SW4 are connected to the input of LNA1, and the other ends of SW2 and SW3 are connected to the input of LNA2. The switch group is used to change the antenna signal under clock drive. S Reference Background R The transmission path is described. Although the cross-switching switch groups SW1-SW4 are located before the inputs of LNA1 and LNA2, both LNA1 and LNA2 possess high transconductance and low noise figures. By optimizing the input matching networks of LNA1 and LNA2, the slight insertion loss introduced by the front-end switches is compensated. Simultaneously, relying on the high gain (approximately 28~30dB) provided by LNA1 and LNA2 respectively, the additional noise from the switch groups (SW5-SW8) located after the power detectors in the subsequent two branches is effectively suppressed, ensuring the system-level sensitivity of the full-time-domain detection architecture.

[0063] LNA1 in the first amplification branch and LNA2 in the second amplification branch use the exact same circuit topology. In the actual chip implementation, LNA1 and LNA2 follow the centroid symmetry principle in their layout, aiming to maximize the average system gain of the two amplification branches. G System noise and temperature T sys The parameters, such as group delay, are statistically highly matched, thus providing a symmetrical physical environment for the complementary correlation operations in the backend. LNA1 and LNA2 possess an ultra-wide operating frequency band covering 110GHz to 160GHz, providing ample 50GHz of effective bandwidth for full-time domain integration. B This further optimized the NETD metric.

[0064] The LNA1 and LNA2 are configured as high-gain, high-transconductance amplifiers, whose gain values ​​can significantly offset the noise contribution of the front-end complementary switching network group and the subsequent power detectors PD1 and PD2, ensuring that the noise figure of the system front-end is determined by the first-stage LNA.

[0065] The uses of LNA1 and LNA2: First half of the cycle f 1. LNA1 is responsible for amplifying the target signal. S LNA2 is responsible for amplifying the reference signal. R The second half of the cycle f2. Through on-chip complementary logic switching and path reconstruction of the switching networks SW1-SW4, LNA1 amplifies the reference signal. R The LNA2 then amplifies the target signal. S Even if there is a difference in gain between LNA1 and LNA2 due to CMOS process variations, this alternating operation ensures the target signal... S and reference signal R The total gain experienced during the total observation time is ( After being summed and averaged by the synthesizer at the end, the mismatch effect of the two branches is eliminated in the first order. This physical gain balance eliminates the zero-point offset and baseline drift caused by amplifier mismatch at its source.

[0066] The input terminal of the first power detector PD1 is connected to the output terminal of LNA1 to convert power into current, which is then transmitted via SW9 according to the first half of the clock cycle. f 1 is injected into the first integrator, Integrator1.

[0067] The input of the second power detector PD2 is connected to the output of LNA2 to convert power into current, which is then transmitted via SW9 according to the second half of the clock cycle. f 2 is injected into the second integrator, Integrator2.

[0068] The output complementary switching network includes switches five through eight (SW5, SW6, SW7, SW8), all of which are single-pole single-throw MOS transistors. One end of SW5 and SW7 is connected to the output of PD1, and one end of SW6 and SW8 is connected to the output of PD2. The other end of SW5 and SW8 is connected to the non-inverting input of the first differential adder (Diff-Adder), and the other end of SW6 and SW7 is connected to the inverting input of the first differential adder (Diff-Adder). This switch group is used to change the antenna signal under clock drive. S With reference signal R The transmission path.

[0069] The output of the first differential adder (Diff-Adder) is directly connected to the input of the end-switch SW9 to perform real-time differential operations in both half-cycles and suppress common-mode interference. (First half-cycle) f In step 1, two receiving branches are obtained. G 1 and G 2 differential subtraction signal The second half of the cycle f In step 2, two receiving branches are obtained. G 1 and G 2 differential subtraction signal .

[0070] The complementary clock generation unit generates two complementary clock signals, CLK and CLKB, which are respectively connected to the control terminals of the aforementioned switches to control the on / off states of the input complementary switch switching network, the output complementary switch switching network, and SW9.

[0071] The system includes a symmetrically arranged first integrator1 and second integrator2. Each integrator employs a current-mode integration structure, consisting of a transconductance operational amplifier and a high-linearity integrating capacitor. The inverting input of the operational amplifier receives the detector current signal output from the power detector, while the non-inverting input is connected to analog ground. The integrating capacitor is used as the physical integrator, and is used for the first half-cycle... f 1 and the second half of the cycle f The signal charge of 2 is stored. Simultaneously, during this process, the integrating capacitor not only contains the signal but also includes 1 / 2 ohms generated by the preceding amplification branches LNA1 and LNA2. f Noise and DC offset. Due to the extremely fast switching speed, much higher than 1 / f The frequency of noise variation is used to ensure the smooth operation of the first and second half-cycles. f 1 and f The stored noise floor remains largely consistent, providing a precise physical reference for subsequent correlation double sampling via the Sum-Adder synthesizer, thereby offsetting the low-frequency drift of the system.

[0072] The end-switch SW9 is connected between the output of the first differential adder (Diff-Adder) and the inputs of the two integrators, used to alternately and continuously feed the output signal of the first differential adder (Diff-Adder) into the subsequent first integrator (Integrator1) and second integrator (Integrator2). In the first half-cycle, the output of the first differential adder (Diff-Adder) in the first branch is... SW9 will output a signal The signal is sent to the first integrator, Integrator1; in the second half of the cycle, the output of the first differential adder, Diff-Adder, in the second branch is... SW9 will output a signal The signal is sent to the second integrator, Integrator2. The end-to-end switching switch SW9 is controlled by the synchronous complementary clock CLK / CLKB, and its switching frequency is synchronized with the front-end input-side complementary switching network. This ensures that the useful charge after differential processing is always distributed to the corresponding integration branch with a constant polarity, thereby achieving lossless accumulation of the target signal energy in the charge domain.

[0073] The Sum-Adder adds the output voltage signals of the two integrators, forcing the antenna signal to merge in the physical topology. S With reference signal R Sharing the same total gain path, the energy after dual-path integration is finally superimposed, and the gain of the two receiving branches is aligned, thus completely eliminating branch mismatch caused by process discreteness. Furthermore, after multi-dimensional noise suppression (such as...), Figure 3 As shown), the final output should be related to the scene temperature difference. Proportional stable level signal .

[0074] In summary, the full-time-domain detection architecture and its noise suppression method proposed in this application overcome the bottlenecks of traditional Dicke receivers in terms of effective integration efficiency and low-frequency noise and gain fluctuation suppression at the system architecture level. Through the specific circuit implementation described above, a high-sensitivity millimeter-wave radiometer receiver with deep sub-Kelvin levels can be realized on mature silicon-based CMOS technology.

[0075] In the foregoing description of this specification, references to terms such as "one embodiment," "another embodiment," or "some embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0076] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0077] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A millimeter-wave full-time-domain radiometer receiver, characterized in that, include: A first receiving branch and a second receiving branch, wherein the first receiving branch includes a first low-noise amplifier (LNA1) and a first power detector (PD1) connected in sequence, and the second receiving branch includes a second low-noise amplifier (LNA2) and a second power detector (PD2) connected in sequence. The input complementary switch switching network includes first to fourth switches (SW1, SW2, SW3, SW4), which, under the control of a complementary clock signal, alternately and continuously input the target signal and reference reference signal received by the antenna to the input terminals of the first low noise amplifier and the second low noise amplifier, respectively. The output complementary switching network includes fifth to eighth switches (SW5, SW6, SW7, SW8) for alternately outputting the output signals of the first power detector and the second power detector to the differential adder under the control of the complementary clock signal. A differential adder is used to perform differential operations on the two signals provided by the output complementary switching network. An end-to-end switching switch (SW9) is used to alternately distribute the differential signal output by the differential adder to the first integrator and the second integrator under the control of the complementary clock signal. The first integrator and the second integrator are used to perform charge integration on the allocated differential signal, respectively. A synthesizing adder is used to add the output voltages of the first integrator and the second integrator to output a stable level signal that is proportional to the temperature difference between the target signal and the reference signal. A complementary clock generation unit is used to generate the complementary clock signal.

2. The millimeter-wave full-time-domain radiometer receiver according to claim 1, characterized in that, In the input complementary switch switching network: One end of the first switch (SW1) and the third switch (SW3) are connected to the antenna, and one end of the second switch (SW2) and the fourth switch (SW4) are connected to the reference reference. The other ends of the first switch (SW1) and the fourth switch (SW4) are connected to the input of the first low noise amplifier (LNA1), and the other ends of the second switch (SW2) and the third switch (SW3) are connected to the input of the second low noise amplifier (LNA2). The first switch (SW1) and the second switch (SW2) are controlled by the first clock signal (CLK) in the complementary clock signal, and the third switch (SW3) and the fourth switch (SW4) are controlled by the second clock signal (CLKB) in the complementary clock signal, wherein the second clock signal is out of phase with the first clock signal.

3. The millimeter-wave full-time-domain radiometer receiver according to claim 1, characterized in that, In the output complementary switching network: One end of the fifth switch (SW5) and the seventh switch (SW7) are connected to the output of the first power detector (PD1), and one end of the sixth switch (SW6) and the eighth switch (SW8) are connected to the output of the second power detector (PD2). The other ends of the fifth switch (SW5) and the eighth switch (SW8) are connected to the non-inverting input of the differential adder, and the other ends of the sixth switch (SW6) and the seventh switch (SW7) are connected to the inverting input of the differential adder. The fifth switch (SW5) and the sixth switch (SW6) are controlled by the first clock signal (CLK), and the seventh switch (SW7) and the eighth switch (SW8) are controlled by the second clock signal (CLKB).

4. The millimeter-wave full-time-domain radiometer receiver according to claim 1, characterized in that, The input terminal of the end switch (SW9) is connected to the output terminal of the differential adder, its first output terminal is connected to the input terminal of the first integrator, and its second output terminal is connected to the input terminal of the second integrator. The end switch (SW9) is controlled by the complementary clock signal, wherein when the first clock signal (CLK) is valid, the output signal of the differential adder is sent to the first integrator, and when the second clock signal (CLKB) is valid, the output signal of the differential adder is sent to the second integrator.

5. The millimeter-wave full-time-domain radiometer receiver according to claim 1, characterized in that, Both the first and second integrators adopt a current-mode integrator structure. Each integrator includes a transconductance operational amplifier and an integrating capacitor. The inverting input of the transconductance operational amplifier receives a current signal from the end switch (SW9), and the non-inverting input is connected to analog ground. The integrating capacitor is connected between the inverting input and the output of the transconductance operational amplifier.

6. The millimeter-wave full-time-domain radiometer receiver according to claim 1, characterized in that, The first low-noise amplifier (LNA1) and the second low-noise amplifier (LNA2) have the same circuit topology and are arranged in a centroid-symmetrical layout. The first low-noise amplifier and the second low-noise amplifier operate in a frequency band of 110 GHz to 160 GHz and have a gain of 28 dB to 30 dB. The first to eighth switches (SW1-SW8) are all NMOS transmission transistors with a channel length using the minimum feature size, a total width of 15μm to 25μm per transistor, and are manufactured using deep N-well technology.

7. A noise suppression method based on the millimeter-wave full-time-domain sounding radiometer receiver according to any one of claims 1 to 6, characterized in that, Includes the following steps: Complementary first and second clock signals are generated by a complementary clock generation unit. During the first half of the clock cycle, the control input complementary switch switching network causes the antenna signal to be input into the first receiving branch and the reference signal to be input into the second receiving branch. At the same time, the control output complementary switch switching network causes the output signals of the first receiving branch and the second receiving branch to be subtracted by the differential adder and then sent to the first integrator for integration by the end switch. In the second half of the clock cycle, the control input complementary switch switching network causes the antenna signal to be input into the second receiving branch and the reference reference signal to be input into the first receiving branch. At the same time, the control output complementary switch switching network causes the output signals of the first receiving branch and the second receiving branch to be subtracted by the differential adder and then sent to the second integrator for integration by the end switch. The integration results of the first integrator and the second integrator are added together by a synthesizer to output a stable level signal that is proportional to the temperature difference between the antenna signal and the reference signal.

8. The method according to claim 7, characterized in that, Also includes: By coordinating the switching of the input complementary switching network and the output complementary switching network, the antenna signal and the reference reference signal experience the same total gain path during the total integration time, thereby canceling the gain mismatch of the two receiving branches.

9. The method according to claim 7, characterized in that, It also includes: utilizing the differential operation of the differential adder and the integral accumulation of the first integrator and the second integrator to achieve noise statistical cancellation based on charge domain correlation double sampling, so as to suppress the 1 / f Noise, DC offset, and gain fluctuations.

10. The method according to claim 9, characterized in that, Let the modulation period be The half-cycle integration time is Total time , If the number of cycles is given, then after the total integration time, the receiver's output voltage is... Approximately: in, Let be the response coefficient of the power detector. The system average gain. The equivalent temperature of the target signal. Using the reference equivalent temperature, statistical cancellation of low-frequency noise and gain fluctuations is achieved.

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