A MIPI-based laser radar and millimeter wave radar aging device

Abstract

The application provides a MIPI-based laser radar and millimeter wave radar aging device, and relates to the technical field of radar testing.The technical scheme provided by the application provides a plurality of power supply voltage independently adjustable power supply output ports through a power supply and detection module, cooperates with a serialization and deserialization module to be compatible with a plurality of serialization protocols and uniformly output, so that the same set of device can simultaneously access different types of laser radars and millimeter wave radars, and there is no need to replace the equipment due to protocol differences or different power supply specifications.FPGA master control module concurrently receives a plurality of data, and the data checking unit executes ECC checking, CRC checking and error frame flag identification for each channel.The continuous frame data processed by the data checking unit is spliced into combined frame data by means of a cache module, and is transmitted to the upper computer together with the electrical parameters through a high-speed transmission module, thereby supporting parallel aging test on a large number of different types of radars, and improving the aging test efficiency of the laser radar and the millimeter wave radar.

Description

Technical Field

[0001] This application relates to the field of radar testing technology, specifically to an aging device for MIPI-based lidar and millimeter-wave radar. Background Technology

[0002] With the rapid development of advanced driver assistance systems (ADAS), automotive radar, as a core sensing device, is widely installed in mass-produced vehicles. This includes both lidar for long-range detection and millimeter-wave radar for medium- and short-range sensing. During radar mass production, pre-shipment radar products typically undergo aging screening tests. This involves placing the radar under test in a high- and low-temperature test chamber and allowing it to operate continuously for several to tens of hours under a specified temperature stress curve to induce and expose potential early failure defects. As the demand for radar installation from OEMs continues to grow, the number of lidar and millimeter-wave radars requiring aging tests per batch on the production line is increasing dramatically, placing higher demands on the efficiency of aging tests.

[0003] A common practice in related technologies is to configure dedicated aging test equipment for specific radar models. This equipment provides power to the radar under test and collects its operational status data. However, in practical applications, due to the differences in the serialization protocols used by lidar and millimeter-wave radar on their high-speed serial output interfaces (for example, some radars use the GMSL protocol while others use the APHY protocol), existing aging test equipment is usually designed with deserialization and receiving hardware only for one serialization protocol. When the production line needs to alternately or simultaneously perform aging tests on lidar and millimeter-wave radar using different serialization protocols, it is impossible to flexibly adapt to the same set of equipment. Instead, it is necessary to configure independent aging test equipment for each type of radar protocol, or to modify the equipment hardware when switching the type of radar under test, resulting in low efficiency in aging tests for lidar and millimeter-wave radar. Summary of the Invention

[0004] This application provides a MIPI-based aging device for lidar and millimeter-wave radar, which can improve the aging test efficiency of lidar and millimeter-wave radar.

[0005] Specifically, this application provides a MIPI-based aging device for lidar and millimeter-wave radar. The aging device includes a power supply and detection module, a serialization / deserialization module, an FPGA main control module, a cache module, and a high-speed transmission module, wherein: The power supply and detection module has multiple independent power supply output ports suitable for connecting to the radar under test. The power supply voltage of each power supply output port is independently adjustable. The power supply and detection module also includes an electrical parameter acquisition circuit, which is set up corresponding to each power supply output port. The serialization-to-serialization module has an input port suitable for receiving high-speed serial signals output by the radar under test, and the output terminal of the serialization-to-serialization module outputs MIPI DPHY data signals. The FPGA main control module is connected to the output terminals of the electrical parameter acquisition circuit and the serialization and deserialization module respectively. The FPGA main control module is equipped with a data receiving circuit and a data verification unit. The data receiving circuit receives multiple MIPI DPHY data signals concurrently, and the data verification unit performs ECC verification, CRC verification and error frame flag identification on each MIPI DPHY data signal. The high-speed cache module is connected to the FPGA main control module. The high-speed cache module provides concurrent cache space for the FPGA main control module. The FPGA main control module splices multiple consecutive frame data processed by the data verification unit into combined frame data in time sequence. The high-speed transmission module is connected to both the FPGA main control module and the host computer. The high-speed transmission module transmits the combined frame data and the electrical parameters output by the electrical parameter acquisition circuit to the host computer.

[0006] The beneficial effects of the technical solution in this application include: The power supply and detection module provides multiple independently adjustable power output ports. Combined with a serialization / deserialization module, it is compatible with various serialization protocols and outputs a unified MIPI DPHY data signal. This allows the same device to simultaneously connect to different types of LiDAR and millimeter-wave radar without requiring equipment replacement due to protocol differences or power supply specifications. The FPGA main control module concurrently receives multiple data streams through a data receiving circuit. A data verification unit performs ECC, CRC, and error frame flag identification on each stream. Combined with electrical parameters output from the electrical parameter acquisition circuit, synchronous monitoring at both the power supply and data levels is achieved. The continuous frame data processed by the data verification unit is concatenated into combined frame data using a high-speed cache module and transmitted to the host computer along with the electrical parameters via a high-speed transmission module. This supports parallel aging tests on large batches of different types of radar, improving the efficiency of aging tests for both LiDAR and millimeter-wave radar. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the structure of a MIPI-based lidar and millimeter-wave radar aging device according to an embodiment of this application; Figure 2 This is a schematic diagram of the system architecture of a MIPI-based lidar and millimeter-wave radar aging device according to an embodiment of this application. Detailed Implementation

[0008] To enable those skilled in the art to better understand the technical solutions in this specification, the technical solutions in the embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0009] In the description of the embodiments of this application, words such as "illustrative," "for example," or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "illustrative," "for example," or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of words such as "illustrative," "for example," or "for example" is intended to present the relevant concepts in a specific manner.

[0010] First, a brief introduction to the specific application scenario of this application: During the mass production of radar products, multiple radars under test need to be placed in a high and low temperature test chamber for long-term aging tests to verify the reliability and consistency of the products under extreme temperature environments. The test device is located outside the chamber and is responsible for powering and configuring each radar under test inside the chamber, and receiving its output sensing data in real time to determine whether its working status is normal. Currently, more and more automotive radar products are using the MIPICSI-2 / DPHY high-speed serial interface as the data output link.

[0011] In this scenario, due to the high signal rate of MIPI DPHY and the strict timing requirements of differential signals, the signal quality is easily degraded after being led out through the test box cable. Furthermore, mass production aging requires simultaneous testing of multiple radars. Existing test solutions are difficult to achieve stable reception, parsing, and status monitoring of multiple MIPI high-speed data streams while ensuring signal integrity.

[0012] The above problems can be solved through the following technical solutions, please refer to [link / reference]. Figure 1 , Figure 1 This application provides a schematic diagram of the structure of an aging device for MIPI-based lidar and millimeter-wave radar. Figure 1 The MIPI-based LiDAR and millimeter-wave radar aging device includes a power supply and detection module, a serialization and deserialization module, an FPGA main control module, a cache module, and a high-speed transmission module. The power supply and detection module has multiple independent power supply output ports suitable for connecting to the radar under test. The power supply voltage of each power supply output port is independently adjustable. The power supply and detection module also includes an electrical parameter acquisition circuit, which is set up corresponding to each power supply output port. The serialization-to-serialization module has an input port suitable for receiving high-speed serial signals output by the radar under test, and the output terminal of the serialization-to-serialization module outputs MIPI DPHY data signals. The FPGA main control module is connected to the output terminals of the electrical parameter acquisition circuit and the serialization and deserialization module respectively. The FPGA main control module is equipped with a data receiving circuit and a data verification unit. The data receiving circuit receives multiple MIPI DPHY data signals concurrently, and the data verification unit performs ECC verification, CRC verification and error frame flag identification on each MIPI DPHY data signal. The high-speed cache module is connected to the FPGA main control module. The high-speed cache module provides concurrent cache space for the FPGA main control module. The FPGA main control module splices multiple consecutive frame data processed by the data verification unit into combined frame data in time sequence. The high-speed transmission module is connected to both the FPGA main control module and the host computer. The high-speed transmission module transmits the combined frame data and the electrical parameters output by the electrical parameter acquisition circuit to the host computer.

[0013] The aging device provided in this embodiment includes a power supply and detection module, a serialization and deserialization module, an FPGA main control module, a high-speed cache module, and a high-speed transmission module in its overall architecture. Each module works in coordination according to the signal flow to jointly complete the functions of parallel power supply, data reception, quality verification, and uploading for multiple radars under test.

[0014] In mass production aging tests, multiple radars under test are simultaneously placed in high and low temperature test chambers. Due to component discreteness or batch differences, the operating voltage requirements of different radars may vary slightly, and testers often need to examine the stability of the radar's operation under different voltage conditions. Therefore, the power supply and detection module is equipped with multiple independent power supply output ports. Each power supply output port is connected to one radar under test in the test chamber via a cable, and the power supply voltage of each power supply output port is independently adjustable. This allows testers to set the power supply voltage for each radar under test according to test needs, without mutual interference caused by sharing a power supply. At the same time, simply providing power without monitoring the power supply status is insufficient. Radars may experience abnormally increased power consumption, short circuits, or loose connections during prolonged operation at extreme temperatures. Failure to detect these faults in time will lead to invalid test results or even damage to the equipment. Therefore, the power supply and detection module also includes an electrical parameter acquisition circuit corresponding to each power supply output port. This circuit collects the voltage and current values ​​of each power supply output port in real time, enabling the device to continuously monitor the power supply health status of each radar under test, providing basic data for subsequent comprehensive judgment by the host computer.

[0015] The sensing data output by the radar under test needs to be led out through the test chamber wall to the test device outside the chamber. Since the MIPIDPHY signal is a high-speed differential signal, its typical data rate can reach several Gbps. After transmission through the test chamber's wall-penetrating cable, the signal eye diagram will be significantly degraded due to factors such as cable length, impedance discontinuities, and connector insertion loss. Directly receiving the MIPIDPHY signal at a long distance outside the chamber carries a significant risk of bit errors. To solve this problem, this embodiment includes a serialization / deserialization module on the radar under test side. The input port of the serialization / deserialization module is adapted to receive the high-speed serial signal output by the radar under test. This high-speed serial signal, for example, is a signal serialized by a SerDes chip. After long-distance cable transmission, it is equalized, restored, and deserialized by the receiving end of the serialization / deserialization module. The output end of the serialization / deserialization module then re-outputs the standard MIPIDPHY data signal. In this way, the signal that was originally degraded due to long-distance transmission is regenerated at the serialization and deserialization module, thereby ensuring that the MIPI DPHY data signal sent to the subsequent FPGA main control module has good signal quality and effectively reducing the bit error rate caused by excessively long transmission links.

[0016] The FPGA main control module is the core processing unit of the entire aging device, connected to the outputs of the electrical parameter acquisition circuit and the serialization / deserialization module. The FPGA was chosen as the main control device because mass production aging tests require the simultaneous parallel reception of data streams from multiple radars. Each data stream is independent and has different timing sequences. The FPGA's rich programmable logic resources and hard-core transceiver naturally support multi-channel concurrent processing, and its deterministic timing behavior ensures that the reception of each data stream does not interfere with each other. The FPGA main control module is internally configured with a data receiving circuit and a data verification unit. The data receiving circuit utilizes the FPGA's internal MIPI DPHY hard-core interface or soft-core controller to concurrently receive multiple MIPI DPHY data signals output from the serialization / deserialization module. It performs lane alignment, byte concatenation, and header parsing operations on each signal to extract the original frame data. The data verification unit follows the data receiving circuit, performing ECC verification, CRC verification, and error frame flag identification on each MIPI DPHY data signal. The three verification mechanisms are as follows: ECC verification checks the error correction code field in the MIPI CSI-2 header to detect whether bit flipping occurs during transmission; CRC verification verifies the integrity of the payload data in each long packet to determine if the frame data is complete and error-free; and error frame flag identification detects whether there are protocol-level anomalies between the frame start and end markers. Through these three verification mechanisms, the FPGA main control module can perform fine-grained frame-by-frame and packet-by-packet evaluations of the transmission quality of each data stream. Once a data stream experiences bit errors or frame loss, the anomaly can be immediately marked, providing direct evidence for the host computer to determine whether the tested radar stream is faulty.

[0017] During concurrent reception of multi-channel data, the frame output times of each radar channel are not completely synchronized, and the data volume of a single frame for each channel is large. If the FPGA main control module relies solely on its limited on-chip Block RAM resources for caching, it will be difficult to simultaneously accommodate the concurrent write and read requirements of multiple channels of data, easily leading to buffer overflow and data loss. Therefore, this embodiment sets up a high-speed cache module connected to the FPGA main control module. The high-speed cache module, for example, uses a large-capacity DDR4 memory to provide concurrent cache space for the FPGA main control module. The FPGA main control module allocates an independent cache area for each channel of data within the high-speed cache module, writing the frame data of each channel, processed by the data verification unit, into the corresponding cache area. Based on this, the FPGA main control module concatenates multiple consecutive frame data into a combined frame data according to the timing sequence. Specifically, the FPGA main control module arranges several consecutive frames from the same channel sequentially in the high-speed cache module according to their frame sequence numbers, adds auxiliary information such as frame header identifiers, channel numbers, timestamps, and verification status, and then encapsulates them to form combined frame data. By combining frame data, the originally scattered frame-by-frame data can be integrated into larger data blocks, thereby reducing the protocol overhead and scheduling frequency of subsequent transmission links and improving data throughput efficiency.

[0018] The high-speed transmission module connects to both the FPGA main control module and the host computer, responsible for transmitting the combined frame data output from the FPGA main control module and the electrical parameters output from the electrical parameter acquisition circuit to the host computer. The high-speed transmission module uses high-bandwidth interfaces such as USB 3.0, Gigabit Ethernet, or PCIe to meet the total bandwidth requirements when multiple radar data streams are transmitted simultaneously. After receiving the combined frame data, the host computer can separate and reconstruct the data streams based on the channel number and timestamp, and determine the validity of each frame by combining the verification status information. Simultaneously, upon receiving the electrical parameters, the host computer can correlate the voltage and current trends of each tested radar with the data link status, thereby comprehensively evaluating the performance of each tested radar during the aging process.

[0019] Through the above scheme, the aging device in this embodiment can realize independent adjustable power supply for multiple radars under test, real-time monitoring of power supply status, multi-channel concurrent reception and signal regeneration of high-speed MIPI data, frame-by-frame multi-dimensional data verification, and efficient aggregation and uploading within the same system. Thus, while ensuring signal integrity and data reliability, it meets the requirements of mass production aging test for parallel test scale and test efficiency.

[0020] The following will combine Figure 2 For a detailed description of the specific architecture of the MIPI-based lidar and millimeter-wave radar aging device provided in the embodiments of this application, please refer to [link to relevant documentation]. Figure 2 , Figure 2This is a schematic diagram of the system architecture of a MIPI-based lidar and millimeter-wave radar aging device provided in an embodiment of this application.

[0021] like Figure 2 As shown, the aging device in this embodiment is generally composed of multiple FPGA main control boards and a host computer. For example, four FPGA main control boards are deployed in the system. The FPGA main control module on each FPGA main control board is, for example, an AU15P FPGA device. Each FPGA main control board is connected to multiple radars under test. For example, each board is connected to eight radars under test. Thus, the four boards can connect to, for example, thirty-two lidars or millimeter-wave radars in parallel to meet the needs of large-scale parallel testing in mass production aging tests.

[0022] In terms of power supply architecture, a main power module is set at the top level of the system. For example, the number of main power modules corresponds to the number of FPGA main control boards, which are set to four. The external power supply, for example, uses two 24V / 10A DC power supplies to power the main power module. The main power module converts the external power supply into the voltage rails required by each module inside the board. Inside each FPGA main control board, the power supply and detection module is composed of a POC power supply module, a current detection module, and a high-current supply module. Among them, the high-current supply module constitutes the power output stage of the aforementioned power supply output port. For example, each board is equipped with eight high-current supply modules, which provide independent and adjustable power supply outputs for eight radars under test. The POC power supply modules are set to correspond to the high-current supply modules. For example, each board is also equipped with eight POC power supply modules. The POC power supply modules provide remote power supply to the serialization and deserialization module at the radar under test through coaxial cables, so that power supply and high-speed data can be transmitted on the same cable, thereby reducing the number of cables passing through the wall of the test chamber. The current detection module constitutes the specific implementation of the aforementioned electrical parameter acquisition circuit. For example, each board is equipped with eight current detection modules, which correspond one-to-one with eight power supply output ports. The voltage and current values ​​of each power supply are collected in real time to continuously monitor whether the power supply status of each radar under test is within the normal range.

[0023] In terms of the data reception link, the MIPI CSI-2 data signal output by each radar under test is first transmitted over long distances via a serialization / deserialization module. The serialization / deserialization module, for example, uses a SerDes device based on the A-PHY or GMSL protocol. Each board has, for example, four serialization / deserialization modules. Each module supports the input of serial data from two radars under test. At the receiving end, the serialization / deserialization module performs equalization recovery and deserialization processing on the signal degraded after long-distance transmission, and its output re-outputs a standard MIPI DPHY data signal. The data receiving circuit configured inside the FPGA main control module is connected to the output of the serialization / deserialization module. For example, each board has four DPHY data receiving circuit modules, each receiving a corresponding MIPI DPHY data signal output from one serialization / deserialization module. For example, the receiving rate of the DPHY data receiving circuit module is, for example, 2.5 Gsps, to match the bandwidth requirements of the radar output data. The frame data parsed by the data receiving circuit module is then sent to the data verification unit. For example, each board is equipped with four ECC / CRC data verification units, which correspond one-to-one with the four data receiving circuit modules. Each data verification unit performs ECC and CRC checks on each packet of the received MIPI DPHY data signal and identifies whether the frame data carries an error frame flag, thereby realizing real-time frame-by-frame evaluation of the data transmission quality of each channel.

[0024] In addition, the FPGA main control module is also equipped with an I2C / SPI module. For example, each board is equipped with four I2C / SPI modules, which are used to configure the registers and read the status of the radar under test or the serialization unserialization module through the I2C or SPI bus. For example, the working mode parameters of the radar are configured or the link lock status of the serialization unserialization module is read.

[0025] Regarding data caching and uploading, each FPGA main control board is equipped with a high-speed cache module, which is implemented using a DDR4 storage module, providing a large-capacity concurrent cache space for the FPGA main control module. The FPGA main control module splices multiple consecutive frame data processed by the data verification unit into combined frame data according to the time sequence and temporarily stores it in the DDR4 storage module. Each board is also equipped with a high-speed transmission module, which is implemented using a 10 Gigabit Ethernet transmission module, which is connected to the data acquisition terminal on the host computer side through an optical module and optical fiber. For example, each board is configured with, for example, four 10G optical modules, which transmit the combined frame data and electrical parameters to the host computer side at high speed through optical fiber.

[0026] On the host computer side, a 40G Ethernet acquisition module is installed. This module receives all data streams from the four FPGA main control boards via, for example, a 40G optical module and fiber optic aggregation. The host computer also has a DDR4 storage module for caching and organizing the aggregated multi-channel data. The host computer connects to the host computer (PC) via, for example, a PCI-E 3.0×8 interface. For instance, the PCI-E 3.0×8 interface provides sufficient transmission bandwidth to ensure that the combined frame data and electrical parameters of the thirty-two radars can be transmitted to the host computer without bottlenecks for storage, parsing, and comprehensive analysis. After receiving the data from each channel, the host computer can separate and reconstruct the data based on the channel number and timestamp carried in the combined frame data. Combined with verification status information and electrical parameter change trends, it can comprehensively evaluate and determine the anomalies of each radar under test during the aging process.

[0027] Based on the above embodiments, as an optional implementation, the FPGA main control module includes multiple FPGA chips that work in parallel. Each FPGA chip instantiates multiple sets of DPHY data receiving IP cores, and each set of DPHY data receiving IP cores constitutes a set of MIPI DPHY input channels. Each MIPI DPHY input channel is configured to distinguish between two radar data streams via a MIPI virtual channel identifier and receive them alternately, enabling each MIPI DPHY input channel to concurrently receive MIPI data signals output from two radars under test.

[0028] In mass production aging test scenarios, it is necessary to simultaneously receive a large number of MIPI data signals output by the radars under test. If only a single FPGA chip is used to handle the data reception task of all channels, on the one hand, the high-speed transceiver pins and logic resources available inside the single FPGA chip are limited, making it difficult to instantiate a sufficient number of DPHY receiving interfaces simultaneously; on the other hand, concentrating a large number of data channels on a single chip will lead to on-chip wiring congestion and timing convergence difficulties, thereby affecting the stability and reliability of data reception for each channel. Based on this, the FPGA main control module of this embodiment includes multiple FPGA chips that work in parallel. For example, the system deploys, for example, four FPGA chips, each physically set on an independent main control board, which independently perform data reception and processing tasks, thereby evenly distributing the load of large-scale parallel reception to multiple chips. This reduces the resource occupancy and design complexity of a single chip and improves the overall scalability of the system. When the number of radars under test needs to be increased, only the number of FPGA chips needs to be increased accordingly.

[0029] Within each FPGA chip, a further solution is needed to efficiently utilize the limited DPHY physical interfaces to connect as many radars under test as possible. The MIPI CSI-2 protocol itself defines a virtual channel mechanism, where data streams from different image sources can be distinguished on the same set of physical data channels by the virtual channel identifier field in the packet header. Data from each virtual channel is transmitted alternately in time but completely isolated logically. This embodiment fully utilizes this protocol feature. Multiple sets of DPHY data receiving IP cores are instantiated within each FPGA chip. For example, each FPGA chip instantiates, for instance, four sets of DPHY data receiving IP cores, each forming a set of MIPI DPHY input channels. Each set of MIPI DPHY input channels is physically connected to the output of a serialization-to-deserialization module through a set of differential data lanes and a set of differential clock lanes. The remote end of this serialization-to-deserialization module simultaneously bridges the data outputs of two radars under test. The serialization-to-deserialization module maps the MIPI data signals output by the two radars under test to different virtual channel identifiers. For example, the data from one radar is mapped to virtual channel identifier VC0, and the data from the other radar is mapped to virtual channel identifier VC1. The two data streams are multiplexed at the output of the serialization-to-deserialization module and output alternately on the same physical DPHY signal line. Correspondingly, each MIPI DPHY input channel is configured to distinguish between the two radar data streams and receive them alternately using the MIPI virtual channel identifier. When the DPHY data receiving IP core parses each MIPI CSI-2 long packet, it determines which radar under test the current data packet belongs to based on the virtual channel identifier field carried in the packet header and distributes it to the corresponding data buffer path, thereby enabling each MIPI DPHY input channel to concurrently receive the MIPI data signals output by the two radars under test.

[0030] Using the above method, taking four DPHY data receiving IP cores instantiated on each FPGA chip as an example, each FPGA chip can concurrently receive data from, for example, eight channels of radar under test. Four FPGA chips working in parallel can simultaneously receive data from, for example, thirty-two channels of radar under test, while the total number of required DPHY physical interfaces is only, for example, sixteen. Compared to the scheme of allocating a separate DPHY physical interface to each radar under test, the number of physical channels is reduced by half, effectively saving high-speed transceiver pin resources on the FPGA chip and the number of high-speed differential traces on the PCB board, thus reducing hardware design complexity and manufacturing costs. Simultaneously, because the virtual channel mechanism naturally guarantees logical isolation between different radar data at the protocol level, data from different channels will not alias or interfere. When the data verification unit subsequently performs ECC verification, CRC verification, and error frame flag identification, it also independently verifies the frame data of the two radar channels based on the virtual channel identifier, ensuring that the accuracy and independence of the verification results are not affected by channel multiplexing.

[0031] Based on the above embodiments, as an optional implementation, the power supply and detection module includes a POC power supply unit and a high current supply unit; The output of the POC power supply unit is multiplexed with the coaxial signal line of the serialization and deserialization module, and then supplies power to the radar under test via the coaxial signal line. The output of the high-current supply unit supplies power to the radar under test via a power line independent of the coaxial signal line. The rated output current of the high-current supply unit is higher than that of the rated output current of the POC power supply unit.

[0032] Specifically, the output of the POC power supply unit is multiplexed with the coaxial signal line of the serialization / deserialization module. The DC power supply voltage output by the POC power supply unit is superimposed on the coaxial signal line used for transmitting high-speed serial data signals between the serialization / deserialization module and the radar under test through a coupling circuit, and then supplies power to the radar under test through this coaxial signal line. On the radar under test side, the serialization / deserialization module at the radar end integrates a corresponding power separation circuit, which can separate the DC component carried on the coaxial signal line from the high-frequency data signal. The DC component is used to power the serialization / deserialization module and the radar body at the radar end, while the high-frequency data signal is sent to the signal processing link. In this way, only one coaxial cable is needed between each radar under test and the FPGA main control board to simultaneously complete high-speed data backhaul and remote power supply, which greatly reduces the number of connecting cables. Especially in scenarios where a large number of radars under test are placed in the aging test chamber at the same time, it significantly reduces the wiring density and cable management difficulty of through-wall cables. The output current rating of the POC power supply unit is limited by the current carrying capacity of the coaxial cable and the power tolerance of the coupling circuit. For example, the single-channel output current rating of the POC power supply unit is in the hundreds of milliamps range, which is suitable for radars under test with low power consumption.

[0033] For radars under test with high power consumption and required current exceeding the capacity of the POC power supply unit, this embodiment provides supplementary or independent power supply through a high-current supply unit. The output of the high-current supply unit supplies power to the radar under test via a power line independent of the coaxial signal line. This means the power supply path of the high-current supply unit is physically separated from the data transmission path of the serialization / deserialization module. The power supply current is directly delivered to the power input port of the radar under test via a dedicated power cable, bypassing the coaxial signal line and thus not being limited by the current-carrying capacity of the coaxial cable. The rated output current of the high-current supply unit is higher than that of the POC power supply unit. For example, the rated single-channel output current of the high-current supply unit can reach several amperes, providing sufficient and stable operating current for lidars integrating high-power devices such as laser emitters or motor drives. The output voltage and current of the high-current supply unit can be digitally adjusted and set via the FPGA main control module and I2C / SPI module, allowing for flexible configuration of power supply parameters according to the rated operating voltage and current requirements of different radar models under test, further enhancing the adaptability of the aging device to different radar models under test.

[0034] In practical applications, for radars under test with low power consumption, only the POC power supply unit can be used for composite power supply via the coaxial signal line. In this case, the high-current supply unit is off, fully leveraging the advantages of single-cable simultaneous data and power transmission. For radars under test with high power consumption, the high-current supply unit can be used for high-current power supply via an independent power line. Simultaneously, the POC power supply unit can selectively shut down or maintain low-power output as needed, providing power only to the serialization / deserialization modules at the radar end. Alternatively, depending on the specific power supply architecture requirements of the radar under test, both the POC power supply unit and the high-current supply unit can be used in tandem. The POC power supply unit powers the serialization / deserialization modules at the radar end, while the high-current supply unit powers the core load of the radar itself, thus achieving tiered power supply. Through this dual-path complementary power supply architecture, the power supply and detection module of this embodiment can flexibly adapt to different types and power consumption levels of radars under test, eliminating the need to replace power supply hardware due to changes in the radar model, effectively improving the versatility and deployment efficiency of the aging device.

[0035] Based on the above embodiments, as an optional implementation, both the POC power supply unit and the high current supply unit include a DC / DC step-down circuit and an LDO linear regulator circuit connected in series. The feedback terminal of the LDO linear regulator circuit is connected to a digital potentiometer, and the control terminal of the digital potentiometer is connected to a digital control interface. The output of the LDO linear regulator circuit is connected to an overcurrent clamping protection circuit. The overcurrent clamping protection circuit includes a current sampling circuit and a current limiting circuit. When the current value detected by the current sampling circuit exceeds a preset threshold, the current limiting circuit clamps the output current to the preset threshold and re-enables the output of the LDO linear regulator circuit after a preset time.

[0036] Specifically, the DC / DC buck converter, as the first-stage voltage conversion circuit, receives the bus voltage output from the main power module, exemplarily 24V. The DC / DC buck converter efficiently steps this voltage down to an intermediate voltage, exemplarily the rated operating voltage of the radar under test plus a certain margin. The DC / DC buck converter operates using a switching conversion method, exhibiting high conversion efficiency, exemplarily exceeding 90%, effectively reducing the power consumption and heat generation of the power supply channels. This is particularly important when multiple power supply channels are densely integrated on the same board. The LDO linear regulator, as the second-stage regulator, receives the intermediate voltage output from the DC / DC buck converter at its input and performs fine linear regulation on this voltage, further suppressing the inherent switching ripple and noise components in the DC / DC buck converter output, ultimately outputting a low-ripple, high-precision stable voltage to supply the radar under test. Because the input voltage of the LDO linear regulator circuit only needs to be slightly higher than its output voltage, the voltage difference between the input and output is small. Therefore, the power consumption of the LDO linear regulator circuit itself is within a controllable range, and it will not introduce excessive heat load. A DC / DC buck converter handles large voltage conversions and ensures high efficiency, while the LDO linear regulator circuit handles fine voltage regulation with small voltage drops and ensures low ripple output. The two circuits each leverage their strengths and work together to achieve both overall conversion efficiency and meet the stringent requirements of the radar under test for the purity and stability of the power supply voltage.

[0037] Furthermore, since the aging device needs to be compatible with various models of radar under test, and the rated operating voltages of different radar models often differ (for example, some radars under test have a rated operating voltage of 5V, while others have a rated operating voltage of 12V), if the output voltage of each power supply channel is fixed and cannot be adjusted, then when switching radar models, it is necessary to replace the hardware circuit or adjust the resistor voltage divider network, which is cumbersome and not conducive to flexible scheduling of batch testing. To solve this problem, this embodiment connects a digital potentiometer to the feedback terminal of the LDO linear regulator circuit, and the control terminal of the digital potentiometer is connected to a digital control interface. For example, the digital control interface is, for example, an I2C bus or SPI bus brought out by the FPGA main control module through the I2C / SPI module. The LDO linear regulator circuit samples the output voltage through the feedback terminal and compares it with the internal reference voltage to adjust the magnitude of the output voltage, and the voltage division ratio at the feedback terminal is determined by the feedback resistor network. Digital potentiometers replace traditional fixed feedback resistors. The FPGA main control module sends resistance setting commands to the digital potentiometers via a digital control interface, thereby changing the voltage division ratio at the feedback terminal and achieving precise digital adjustment of the output voltage of the LDO linear regulator circuit. Similarly, the output voltage of the DC / DC buck circuit can also be adjusted in conjunction with a similar digital potentiometer to ensure that the intermediate output voltage of the DC / DC buck circuit is always higher than the target output voltage adjusted by the LDO linear regulator circuit, maintaining sufficient LDO input-output voltage margin. In this way, the FPGA main control module can automatically configure the output voltage of each power supply channel to the rated operating voltage required by the corresponding radar under test, based on the radar model parameters sent by the host computer, without any hardware modifications. This greatly improves the ease of operation and adaptation efficiency when switching between different radar models.

[0038] Furthermore, during aging tests, the radar under test may experience abnormal overcurrent or even short circuits due to its own malfunction or prolonged high-temperature operation. If the power supply channel continues to output large currents without restriction, it may cause damage to the circuit components of the power supply channel itself due to overheating, and may also exacerbate the burning of the faulty parts of the radar under test, causing irreversible damage and affecting subsequent fault analysis. Therefore, this embodiment connects an overcurrent clamping protection circuit to the output of the LDO linear regulator circuit. The overcurrent clamping protection circuit includes a current sampling circuit and a current limiting circuit. The current sampling circuit is connected in series on the power supply path between the output of the LDO linear regulator circuit and the power supply port of the radar under test. For example, the current sampling circuit includes a low-resistance, high-precision sampling resistor and a current detection amplifier. The voltage drop generated across the sampling resistor is amplified by the current detection amplifier and converted into an analog voltage signal proportional to the actual output current, thereby achieving real-time continuous monitoring of the output current. The current limiting circuit and the current sampling circuit work together. The current limiting circuit compares the current value detected by the current sampling circuit with a preset threshold. For example, the preset threshold can be set by adding a certain protection margin to the rated operating current of the radar under test. When the current value detected by the current sampling circuit does not exceed the preset threshold, the current limiting circuit does not operate, and the LDO linear regulator circuit outputs the power supply current normally. When the current value detected by the current sampling circuit exceeds the preset threshold, the current limiting circuit quickly operates and clamps the output current to the preset threshold, that is, it limits the output current from continuing to increase, but maintains it at the maximum safe current level allowed by the preset threshold, thereby effectively preventing excessive current from damaging the power supply circuit and the radar under test. After the current is clamped, the current limiting circuit enters a protection timing state. After a preset time, the output of the LDO linear regulator circuit is reactivated. For example, the preset time is several hundred milliseconds to several seconds. This preset time setting allows the power supply channel to automatically restore normal power supply after the overcurrent event is eliminated, and the aging test process can continue without manual intervention. If the overcurrent fault still exists, the current limiting circuit will trigger the clamping protection again. This cycle repeats, forming a periodic overcurrent protection and automatic retry mechanism. This automatic retry mechanism takes into account both safety and test continuity. It avoids interrupting the aging test process of the entire batch of radars due to a one-time false protection caused by transient disturbances. Under continuous fault conditions, it limits the output current to a safe range through repeated clamping, continuously protecting the power supply channel and the radar under test from overcurrent damage. At the same time, the FPGA main control module can record the occurrence time and duration of each overcurrent clamping event through the current detection module and report the relevant information to the host computer so that testers can focus on analyzing and troubleshooting the radar under test that frequently triggers overcurrent protection after the aging test.

[0039] Based on the above embodiments, as an optional implementation, the data verification unit includes multiple ECC / CRC verification sub-units corresponding one-to-one with the MIPIDPHY input channels, and each ECC / CRC verification sub-unit is integrated inside the FPGA main control module; Each ECC / CRC check subunit has: ECC check logic for performing ECC check on the packet header of the corresponding MIPI data signal, CRC check logic for performing CRC check on the packet payload, frame boundary identification logic for identifying frame header and frame tail flags, and counting logic for counting the number of valid data and erroneous frames within the frame. The output of the counting logic of each ECC / CRC check subunit is connected to the host computer via a high-speed transmission module, and outputs statistical data including the number of error frames and the corresponding channel identifier.

[0040] Each FPGA chip internally instantiates multiple DPHY data receiving IP cores. Each DPHY data receiving IP core constitutes a MIPI DPHY input channel, and each MIPI DPHY input channel concurrently receives MIPI data signals from two radars under test via a virtual channel identifier. After the DPHY data receiving IP core completes the physical layer signal deserialization and byte alignment, it outputs a data packet stream conforming to the MIPI CSI-2 protocol format. These data packet streams may carry various data errors introduced by transmission link noise, signal integrity degradation, or faults in the radar under test itself. One of the core purposes of aging testing is to detect the correctness and stability of the output data of the radar under test under long-term continuous operation. Therefore, it is necessary to perform real-time, packet-by-packet, and frame-by-frame integrity verification on each received MIPI data signal within the FPGA main control module, and report the verification results to the host computer in the form of quantitative statistics so that testers can evaluate the data output quality of each radar under test during the aging process. Based on this, the data verification unit of this embodiment includes multiple ECC / CRC verification subunits corresponding one-to-one with the MIPI DPHY input channels. For example, if each FPGA chip instantiates four sets of MIPI DPHY input channels, then four ECC / CRC verification subunits are set accordingly. Each ECC / CRC verification subunit is integrated inside the FPGA main control module and implemented in hardware logic, so that all verification operations can be completed at the line speed of data reception without introducing additional processing delays or relying on the software participation of external processors.

[0041] Each ECC / CRC check subunit integrates four collaborative logic functions: ECC check logic, CRC check logic, frame boundary identification logic, and counting logic. These four functions work together in sequence on the data stream processing link according to the packet and frame structures of the MIPICSI-2 protocol to complete the complete check process from single packet check to whole frame statistics.

[0042] Specifically, the MIPI CSI-2 protocol specifies that each data packet consists of two parts: a header and a payload. The header contains the data type, word count, and an ECC checksum to protect the integrity of the header information. The ECC check logic performs ECC verification on the header of the corresponding MIPI data signal. Its process is as follows: When the DPHY data receiving IP core outputs a complete data packet, the ECC check logic first extracts the data type field, word count field, and ECC checksum field from the header. It then recalculates the ECC checksum value for the valid information bits in the header according to the Hamming code verification algorithm specified in the MIPI CSI-2 protocol and compares the calculated checksum value with the actual ECC checksum carried in the header. If they match, the header information is considered complete and error-free; if they do not match, the ECC check logic further determines the error type based on the error symptom value. For single-bit errors, it can automatically correct and mark them as corrected; for multi-bit errors, it is marked as an uncorrectable error and a header error flag is generated. ECC verification logic can detect packet header corruption caused by transmission link interference at the packet level in a timely manner, avoiding the impact of incorrect data types or word count statistics on subsequent packet payload parsing.

[0043] The CRC check logic performs CRC checks on the packet payload. Its operation is as follows: The MIPI CSI-2 protocol specifies that a CRC checksum calculated based on the payload content is appended to the end of the long packet payload. During the reception of the packet payload, the CRC check logic performs CRC operations byte-by-byte on the payload data in a pipelined manner. For example, the CRC operation may use the CRC-16 polynomial specified in the MIPI CSI-2 protocol. After the entire packet payload is received, the CRC check logic compares its calculated CRC value with the CRC value carried at the end of the packet payload. If they match, it is determined that no bit flips or data loss occurred during the transmission of the packet payload data; if they do not match, it is determined that the packet payload contains data errors and a payload error flag is generated. The CRC check logic's check granularity covers every byte in the packet payload, thus it can sensitively detect data corruption occurring at any position in the packet payload, making it an important basis for measuring the integrity of data in the transmission link.

[0044] After performing single-packet level ECC and CRC checks, the frame boundary identification logic is responsible for identifying frame header and trailer markers in a continuous data packet stream to define the boundary range of each frame. The MIPI CSI-2 protocol uses start-of-frame (FOB) and end-of-frame (NOB) packets as frame delimiters. The FOB logic marks the start of a frame by detecting packets whose data type field is the FOB start identifier, and marks the end of a frame by detecting packets whose data type field is the NO B end identifier. All long packets contained between the FOB start and NO B packets constitute a complete frame of data. After identifying the frame boundary, the FOB logic also checks whether the timing relationship between the FOB start and NO B packets conforms to the protocol specification. For example, if no corresponding NO B packet is detected after a FOB start packet but another FOB start packet appears, it is determined that a frame loss or frame structure abnormality has occurred, and a frame abnormality flag is generated. By precisely delimiting the frame boundary identification logic, the subsequent counting logic can perform statistics on a frame-by-frame basis, ensuring that the statistical results strictly correspond to the actual frame sequence output by the radar under test.

[0045] Within the frame boundary defined by the frame boundary identification logic, the counting logic counts the number of valid data packets and the number of erroneous frames within a frame. Specifically, the counting logic maintains multiple counters. The valid data counter is reset to zero at the beginning of each frame and increments for each valid data packet that passes ECC and CRC checks without an error flag. The value of the valid data counter at the end of the frame represents the number of valid data packets in that frame, which can be further converted into the number of valid pixels or valid point clouds to assess the integrity of the frame data. The erroneous frame counter continuously accumulates throughout the aging test cycle. Whenever a frame contains at least one data packet that fails ECC or CRC checks, or when the frame boundary identification logic reports an abnormal frame structure, the frame is determined to be an erroneous frame, and the erroneous frame counter increments once. Furthermore, the counting logic can further subdivide the distribution of various types of errors, for example, separately counting the number of ECC single-bit corrections, the number of ECC multi-bit uncorrectable errors, the number of CRC check failures, and the number of frame structure anomalies, providing detailed classification data support for subsequent fault attribution analysis.

[0046] Since each MIPI DPHY input channel receives data from two radars under test concurrently through a virtual channel identifier, each ECC / CRC check subunit, when performing all the above check and statistical processes, independently distinguishes and processes the data from the two radars based on the virtual channel identifier. That is, logically, each virtual channel maintains its own independent ECC check state, CRC check state, frame boundary state, and counter group, ensuring that the check results of the two radars under test do not interfere with each other and are independent.

[0047] The output of the counting logic of each ECC / CRC check subunit is connected to the host computer via a high-speed transmission module, outputting statistical data including the number of error frames and the corresponding channel identifier. Specifically, the counting logic packages the currently accumulated statistical data into a reporting data packet according to a preset reporting period or after each frame check is completed. The reporting data packet contains at least the corresponding channel identifier information and the number of error frames. The channel identifier information is used to uniquely identify the radar under test to which the statistical data belongs. For example, the channel identifier information is composed of three parts: the FPGA chip number, the MIPI DPHY input channel number, and the virtual channel identifier, enabling the host computer to accurately map the statistical data to the corresponding radar under test based on the channel identifier information. The reported data packets are aggregated by the FPGA main control module and sent to the host computer through the high-speed transmission module. After receiving the statistical data, the host computer can display the cumulative number of error frames and the error rate trend of each radar under test in real time during the aging process. When the number of error frames or the error rate of a radar under test exceeds the preset quality judgment threshold, the host computer can automatically generate an alarm and mark the radar as a suspected defective product, thereby realizing comprehensive, real-time and quantitative monitoring of the data output quality of a large number of radars under test during the aging process.

[0048] Based on the above embodiments, as an optional implementation, the cache module includes multiple DDR memory chips, each of which is independently connected to a corresponding FPGA chip; Each FPGA chip receives continuous frame data from the radar under test and writes it sequentially into a DDR memory that is independently connected to it. Based on the frame sequence number field in the frame header, the FPGA chip splices multiple continuous frame data belonging to the same measurement period into a combined frame data in time sequence and then reads it out from the DDR memory.

[0049] In the aforementioned embodiments, each FPGA chip needs to concurrently receive MIPI data signals output from multiple radars under test. The data from each source continuously arrives in the form of consecutive frames. However, when the high-speed transmission module sends data to the host computer, there are overheads such as protocol encapsulation and link scheduling. A short-term mismatch may occur between its instantaneous throughput rate and the peak convergence rate of the multiple radar data streams. If a sufficiently large buffer is not set up for rate adaptation, data loss may occur during the peak data convergence period because the downstream link cannot send data in time. Furthermore, the radar under test typically outputs multiple consecutive frames of data in each measurement cycle. These consecutive frames arrive at different times and need to be temporarily stored in a buffer and spliced ​​together in sequence to form a complete combined frame for the host computer to parse and analyze. Therefore, the high-speed buffer module also needs to undertake the orderly temporary storage and splicing integration of frame data.

[0050] Based on the above requirements, the high-speed cache module of this embodiment includes multiple DDR memory chips, each of which is independently connected to a corresponding FPGA chip. For example, the high-speed cache module includes four DDR memory chips, each independently connected to one of four FPGA chips. Each DDR memory chip uses the DDR4 specification, and its capacity is several GB. Each DDR memory chip only serves its corresponding FPGA chip. The read and write operations of each FPGA chip on its respective DDR memory are independent and do not compete with each other, thereby avoiding bus arbitration conflicts and bandwidth bottlenecks that may occur when multiple FPGA chips share the same memory. This ensures that each FPGA chip can complete the concurrent writing and reading of multiple radar data with sufficient storage bandwidth.

[0051] During the data writing phase, each FPGA chip sequentially writes the continuous frame data received from the radar under test into its independently connected DDR memory. Specifically, the write control logic within the FPGA chip allocates an independent storage address range for each radar under test. After the ECC / CRC check unit completes the check of a frame of data, the write control logic sequentially writes the frame of data, along with its check status information, into the corresponding storage address range of that radar in a burst write manner, and updates the write pointer position. The write operations of multiple radars are time-division multiplexed and scheduled by the DDR controller inside the FPGA chip. Each write request obtains DDR bus access access according to priority. Since the bandwidth of DDR4 memory is much higher than the data rate of a single radar, time-division multiplexing can still ensure that the data of all channels is written in a timely manner without overflow.

[0052] During the data readout and splicing stage, the FPGA chip, based on the frame sequence number field in the frame header, splices multiple consecutive frames belonging to the same measurement period into a combined frame data in a time sequence before reading it from the DDR memory. Specifically, the frame headers of multiple consecutive frames output by the radar under test in each measurement period carry a frame sequence number field. Frames within the same measurement period share the same measurement period identifier, and the frame sequence numbers increase sequentially. The readout and splicing logic inside the FPGA chip determines whether all consecutive frames in the current measurement period have been completely written to the DDR memory by monitoring the continuity of the frame sequence number field and the consistency of the measurement period identifier. Once the readout and splicing logic confirms that all consecutive frames belonging to the same measurement period are ready to be cached, it reads each frame data sequentially from the DDR memory in ascending order of frame sequence number and splices them end-to-end into a combined frame data. The header of the combined frame data includes a channel identifier, a measurement period identifier, and a summary of the verification status of each frame within that period. The combined frame data is then sent to the host computer via a high-speed transmission module.

[0053] In this way, the high-speed cache module physically uses multiple DDR memory chips to independently serve each FPGA chip, eliminating storage bandwidth bottlenecks and access conflicts. Logically, the FPGA chip uses the frame sequence number field to complete the ordered caching and automatic splicing of continuous frame data within the same measurement cycle. This ensures that each combined frame data received by the host computer represents the entire output of a radar under test within a complete measurement cycle. The host computer no longer needs to perform frame-level reorganization and sorting, simplifying the data processing flow on the host computer side. At the same time, it also ensures that data is not lost or out of order under the condition of high concurrency convergence of multiple radar data.

[0054] Based on the above embodiments, as an optional implementation, the serialization-to-deserialization module includes a detachable deserialization board, whose serial input terminal is compatible with multiple serialization protocols, including GMSL and APHY protocols. The deserialization board is equipped with a link status signal pin and an error frame flag signal pin, which are connected to the general-purpose input / output pins of the FPGA main control module via hardware signal lines.

[0055] The serialization / deserialization module is responsible for equalizing, restoring, and deserializing the high-speed serial signals transmitted by the radar under test via long-distance coaxial cables, and outputting standard MIPI DPHY data signals for the FPGA main control module to receive. However, the serialization protocols used by different manufacturers and models of radar under test are not uniform. For example, some radars use the GMSL protocol for data serialization transmission, while others use the APHY protocol. The two protocols differ in physical layer encoding methods, link training mechanisms, and channel configuration methods, requiring the use of a matching deserialization chip for correct parsing. If the deserialization chip is directly soldered onto the FPGA main control board, when the serialization protocol of the radar under test changes, the entire FPGA main control board needs to be replaced or the hardware redesigned, which is costly and time-consuming, and not conducive to the aging device's flexible adaptation to various radar models.

[0056] Based on this, the serialization-to-deserialization module of this embodiment includes a detachable deserialization board. The deserialization board, as an independent daughter board, is connected to the FPGA main control board via a standardized inter-board connector. For example, the inter-board connector may be a high-speed board-to-board connector, which meets the high-speed transmission requirements of MIPI DPHY signals and facilitates manual insertion and removal. When testing radars using different serialization protocols, the tester only needs to remove the current deserialization board and replace it with a deserialization board equipped with the corresponding protocol deserialization chip; no hardware modifications are required to the FPGA main control board itself. The serial input of the deserialization board is compatible with multiple serialization protocols, including GMSL and APHY. For example, deserialization boards equipped with GMSL deserialization chips and deserialization boards equipped with APHY deserialization chips can be fabricated separately. The inter-board connector definitions of the deserialization boards of different models are kept uniform, so that the same FPGA main control board can be compatible with radars under test with different serialization protocols by replacing different models of deserialization boards. This decouples the serialization protocol adaptation layer from the main control processing layer and significantly reduces the hardware modification cost caused by protocol changes.

[0057] Furthermore, the deserialization board is equipped with link status signal pins and error frame flag signal pins, which are connected to the general-purpose input / output pins of the FPGA main control module via hardware signal lines. Specifically, after completing link training and locking with the serialization chip at the radar under test, the deserialization chip on the deserialization board outputs a level signal representing the current link locking status through its link status signal pin. For example, when the link training is successful and in a stable locking state, the link status signal pin outputs a high level; when the link is unlocked or no connection is established, it outputs a low level. The FPGA main control module samples the level value of this link status signal in real time through the general-purpose input / output pins to determine whether the physical link between each radar under test and the deserialization board is established normally. If a link status signal of a certain path remains at a low level, it indicates that the radar under test may have problems such as cable disconnection, interface failure, or abnormal serialization chip. The FPGA main control module can immediately report this abnormal information to the host computer for alarm. Similarly, if the deserialization chip detects an error in the received data during deserialization, it will output a pulse signal or a level-to-toggle signal through its error frame flag signal pin. The FPGA main control module captures this error frame flag signal through general-purpose input / output pins, thus obtaining error detection information at the deserialization chip level that is independent of the FPGA's internal ECC / CRC check subunit. Compared to polling the deserialization chip register via the I2C / SPI bus, this direct hardware signal line-connected state interaction method has the advantages of fast response speed and high real-time performance. The FPGA main control module can detect link status changes or error frame events within microseconds without waiting for the bus polling cycle. At the same time, the link status signal and the error frame flag signal serve as auxiliary verification information, which can be cross-checked and mutually verified with the verification results output by the FPGA's internal ECC / CRC check subunit. When both independent detection mechanisms report anomalies simultaneously, the source of the fault can be more accurately located—whether it occurs at the transmission link level or at the data output level of the radar under test—thereby improving the accuracy and reliability of fault diagnosis during aging tests.

[0058] Based on the above embodiments, as an optional implementation, the FPGA main control module further includes a configuration interface module. The configuration interface module includes an I2C interface and / or an SPI interface. The configuration interface module is connected to the following via the I2C interface and / or SPI interface: the protocol pass-through register of the serialization and deserialization module, the signal quality register of the serialization and deserialization module, the digital control interface of the digital potentiometer in the power supply and detection module, and the current acquisition register in the power supply and detection module. The FPGA main control module also includes feedback regulation logic. The input of the feedback regulation logic is connected to the read output of the current acquisition register and the signal quality register, and the output of the feedback regulation logic is connected to the digital control interface of the digital potentiometer via the configuration interface module.

[0059] The FPGA main control module needs to perform register-level parameter configuration and status reading for multiple peripheral modules, such as the serialization / deserialization module, power supply and detection module. These peripheral modules' configurable and readable devices are distributed across different board areas and each accesses its registers via a low-speed serial bus. If multiple independent bus controllers are instantiated internally within the FPGA main control module to drive each peripheral node separately, it will lead to wasted logic resources and difficulty in unified control timing management. Therefore, the FPGA main control module in this embodiment also includes a configuration interface module. This configuration interface module includes an I2C interface and / or an SPI interface, serving as a unified low-speed bus access channel between the FPGA main control module and each peripheral configurable device. The configuration interface module centrally manages the read / write scheduling of all peripheral registers.

[0060] Specifically, the configuration interface module connects to the following four types of peripheral register nodes via I2C and / or SPI interfaces. First, it connects to the protocol pass-through register of the serialization / deserialization module. The deserialization chip on the deserialization board supports reading and writing its internal registers via the I2C bus. Simultaneously, the deserialization chip integrates a protocol pass-through function, which can transmit I2C commands via the serial link to the serialization chip at the radar under test, thereby accessing the radar under test's own configuration registers. The configuration interface module can remotely configure the operating mode parameters of the radar under test without adding additional physical connections through the protocol pass-through register; for example, configuring the radar's frame rate, resolution, or trigger mode. Second, it connects to the signal quality register of the serialization / deserialization module. During operation, the deserialization chip continuously monitors the signal quality indicators of the receiving link and writes them to the signal quality register. For example, the signal quality register contains information such as link bit error rate statistics, adaptive equalizer gain values, and eye diagram margin indicators. The configuration interface module can periodically read these registers to obtain the current health status of the transmission link. Third, a digital control interface is connected to the digital potentiometer in the power supply and detection module. As in the previous embodiment, the digital potentiometer is used to adjust the output voltage of the LDO linear regulator circuit. The configuration interface module can change the power supply output voltage by writing resistance setting instructions to the digital potentiometer through the digital control interface. Fourth, a current acquisition register is connected to the power supply and detection module. The current detection module digitizes the real-time acquired power supply current values ​​of each channel and stores them in the current acquisition register. The configuration interface module can read this register at any time to obtain the current operating current of each radar under test. By unifying the above four types of peripheral register nodes into the same bus management framework through the configuration interface module, the FPGA main control module only needs to instantiate a set of bus scheduling logic to complete the read and write access of each node sequentially according to the preset polling order or event triggering method, simplifying the internal logic architecture.

[0061] Furthermore, the FPGA main control module also includes feedback adjustment logic. The input of the feedback adjustment logic is connected to the read output of the current acquisition register and the signal quality register, and the output of the feedback adjustment logic is connected to the digital control interface of the digital potentiometer via the configuration interface module. The feedback adjustment logic is implemented inside the FPGA main control module as a hardware state machine or an embedded soft-core processor. Its core function is to automatically determine whether the current power supply parameters need to be adjusted based on the real-time acquired power supply current and link signal quality information, and generate a resistance correction instruction for the digital potentiometer accordingly. Specifically, the feedback adjustment logic periodically reads the real-time current value of each power supply channel from the current acquisition register and compares it with the rated operating current range corresponding to the radar under test. If the real-time current value deviates from the rated range by more than the preset allowable deviation, it indicates that the current power supply voltage may have shifted due to factors such as cable voltage drop and temperature drift. Based on this, the feedback adjustment logic calculates the voltage compensation amount and writes a new resistance setting instruction to the corresponding digital potentiometer through the configuration interface module, fine-tuning the output voltage of the LDO linear regulator circuit so that the actual power supply voltage reaching the radar under test returns to near the rated value. Meanwhile, the feedback adjustment logic also reads the signal quality indicators of the transmission link from the signal quality register. When the signal quality indicators show that the link margin has dropped to the warning level, the feedback adjustment logic can combine the current acquisition information to comprehensively judge whether there is signal integrity degradation caused by unstable power supply. For example, if the current acquisition information shows that the power supply current of the line is abnormally fluctuating, the feedback adjustment logic will first adjust the power supply voltage to eliminate the unstable factors at the power supply end. If the current information is normal but the signal quality continues to decline, the abnormal information will be reported to the host computer for the testers to further investigate the problems at the physical level of the link.

[0062] Through the collaborative work of the above-mentioned configuration interface module and feedback adjustment logic, the FPGA main control module realizes closed-loop monitoring and automatic adjustment of power supply parameters and link status. During long-term aging tests, it can continuously maintain the accuracy of each power supply output and the stability of the transmission link without manual intervention, reducing the risk of misjudgment caused by power supply drift or environmental changes, and improving the reliability of aging test results.

[0063] Based on the above embodiments, as an optional implementation, the high-speed transmission module includes an optical module, an Ethernet acquisition submodule, and a PCIe interface; The high-speed serial transceiver of the FPGA main control module is connected to the electrical port of the optical module, and the optical port of the optical module is connected to the optical port of the Ethernet acquisition submodule via optical fiber. The Ethernet acquisition submodule includes an independent FPGA chip and an external transmission buffer memory. The data input terminal of the independent FPGA chip is connected to the optical port of the Ethernet acquisition submodule, and the data output terminal of the independent FPGA chip is connected to the PCIe interface, which is connected to the host computer.

[0064] Specifically, the high-speed serial transceiver of the FPGA main control module is connected to the electrical port of the optical module. The FPGA main control module encapsulates the combined frame data and statistical data to be uploaded into Ethernet data frames, for example, using the 10 Gigabit Ethernet protocol. The encapsulated data stream is output to the electrical port of the optical module in the form of a high-speed serial electrical signal through the high-speed serial transceiver inside the FPGA chip. The optical module converts the received high-speed serial electrical signal into an optical signal. The optical port of the optical module is connected to the optical port of the Ethernet acquisition submodule via optical fiber. For example, each FPGA chip is connected to, for example, four 10G optical modules. The optical signal is transmitted to the Ethernet acquisition submodule via optical fiber and then received by its optical port and converted back into an electrical signal. Optical fiber transmission has the advantages of high bandwidth, long distance, and strong resistance to electromagnetic interference, enabling long-distance high-speed interconnection between the FPGA main control board and the host computer while ensuring signal integrity.

[0065] The Ethernet acquisition submodule, acting as an intermediary for data aggregation and protocol conversion, is responsible for aggregating and integrating data streams from multiple fiber optic cables and converting them into an interface protocol that can be directly read by the host computer. The Ethernet acquisition submodule includes an independent FPGA chip and an external transmission buffer memory. The data input terminal of the independent FPGA chip is connected to the optical port of the Ethernet acquisition submodule, receiving multiple Ethernet data streams after photoelectric conversion. The independent FPGA chip internally instantiates an Ethernet MAC core to parse, verify, and split the received Ethernet data frames. Because the arrival time and instantaneous rate of the multiple fiber optic data streams may be uneven, the independent FPGA chip temporarily stores the received data in the external transmission buffer memory for rate adaptation and order reorganization. The transmission buffer memory, for example, uses DDR4 memory, providing sufficient buffer space for the independent FPGA chip to absorb burst traffic during multi-channel data aggregation. The data output of the independent FPGA chip is connected to the PCIe interface. The independent FPGA chip transmits the aggregated and processed data to the host computer through the PCIe interface. For example, the PCIe interface adopts the PCI-E 3.0×8 specification, which can provide sufficient transmission bandwidth to ensure that the combined frame data and statistical data of multiple radars are sent to the host computer without bottlenecks. After the PCIe interface is connected to the host computer, the host computer reads data directly from the PCIe interface through the PCIe driver. Compared with receiving Ethernet data through the network card, the PCIe interface has lower transmission latency and higher throughput efficiency, and does not occupy the host computer's network protocol stack resources.

[0066] Through the above architecture, the high-speed transmission module realizes high-speed long-distance optical interconnection between the FPGA main control board and the Ethernet acquisition sub-module using optical modules and optical fibers. It realizes the convergence caching and rate adaptation of multiple data streams using independent FPGA chips and transmission buffer memory. Finally, it realizes high-bandwidth, low-latency data injection to the host computer through the PCIe interface. The three-level links each perform their respective functions and work together to ensure that the massive amount of data generated by the large number of radars under test can be transmitted to the host computer for analysis and processing in a complete, orderly and efficient manner.

[0067] Based on the above embodiments, as an optional implementation, the output port of the power supply and detection module and the input port of the serialization and deserialization module are both led out via coaxial cables; The coaxial cable is suitable for passing through the wall of the high and low temperature test chamber, so that the aging device can collect the electrical parameters output by the electrical parameter acquisition circuit of the aging device placed outside the high and low temperature test chamber and the verification results output by the data verification unit in an environment where the radar under test is placed inside the high and low temperature test chamber.

[0068] In aging tests, the radar under test needs to be placed in a high and low temperature test chamber to undergo long-term continuous operation under a specified temperature curve. However, the precision electronic equipment in the aging device, such as the FPGA main control module, power supply and detection module, high-speed cache module, and high-speed transmission module, should not be exposed to extreme temperature environments; otherwise, they may malfunction or even be damaged, affecting the reliability of the test data. Therefore, the main equipment of the aging device needs to be placed in a normal temperature environment outside the high and low temperature test chamber, with only the radar under test placed inside. Power and data connections between the two are achieved through cables passing through the chamber walls. However, when there are many radars under test, if each radar requires multiple independent power and data lines to be led out through the walls, it will result in a large number of through-wall cables. This not only increases the wiring difficulty but may also compromise the test chamber's airtightness and temperature uniformity due to excessive through-wall holes.

[0069] Based on this, in this embodiment, the output port of the power supply and detection module and the input port of the serialization / deserialization module are both led out via coaxial cables. Specifically, as in the aforementioned embodiment, the output of the POC power supply unit is multiplexed with the coaxial signal line of the serialization / deserialization module. The MIPI data signal output by the radar under test is serialized by the radar-side serialization chip and then transmitted to the deserialization board outside the enclosure via a coaxial cable. At the same time, the DC power supply voltage output by the POC power supply unit is also sent in reverse to the radar under test via the same coaxial cable. Power supply and data are combined and transmitted bidirectionally on the same coaxial cable. For radars under test that require independent power supply from a high-current supply unit, the output of the high-current supply unit is led out through the wall via an independent power line to the power port of the radar inside the enclosure. Thus, only one coaxial cable is needed between each radar under test and the aging device outside the enclosure to simultaneously complete data transmission and POC power supply. For radars that require additional high-current power supply, at most one more power line is added. Compared to the scheme where data lines and power lines are led out separately, the number of through-wall cables is significantly reduced.

[0070] Coaxial cables are suitable for passing through the walls of high and low temperature test chambers. For example, the test chamber walls are equipped with sealed through-wall plates, and the coaxial cable exits through a sealed connector on the plate. The sealed connector ensures smooth cable passage while maintaining the sealing performance of the chamber wall, preventing temperature crosstalk between the inside and outside of the chamber from affecting the temperature control accuracy of the test chamber. Coaxial cables themselves have good shielding performance and temperature resistance, enabling them to maintain stable signal transmission quality within the operating temperature range of the high and low temperature test chamber.

[0071] Through the above deployment method, while the radar under test undergoes temperature stress testing inside the high and low temperature test chamber, the aging device placed in the ambient temperature environment outside the chamber continuously receives data from each radar and supplies power via through-wall coaxial cables. The electrical parameter acquisition circuit collects the voltage and current values ​​of each power supply channel in real time, and the data verification unit performs ECC and CRC checks on each MIPI data signal frame by frame. The output results of both are reported to the host computer via a high-speed transmission module. Based on this, the host computer can continuously monitor the power supply status and data output quality of each radar under test under different temperature conditions throughout the aging process, and promptly detect performance degradation or abnormal faults caused by temperature stress. This achieves centralized monitoring and management of a large number of radars under test outside the chamber during high and low temperature aging tests.

[0072] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0073] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0074] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0075] The above are merely exemplary embodiments of this disclosure and should not be construed as limiting the scope of this disclosure. Any equivalent changes and modifications made in accordance with the teachings of this disclosure shall still fall within the scope of this disclosure. Those skilled in the art will readily conceive of other embodiments of this disclosure upon considering the specification and practical application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not described in this disclosure.

Claims

1. A MIPI-based aging device for lidar and millimeter-wave radar, characterized in that, The aging device includes a power supply and detection module, a serialization and deserialization module, an FPGA main control module, a high-speed cache module, and a high-speed transmission module, wherein: The power supply and detection module has multiple independent power supply output ports suitable for connecting to the radar under test. The power supply voltage of each power supply output port is independently adjustable. The power supply and detection module also includes an electrical parameter acquisition circuit, which is set up corresponding to each power supply output port. The serialization deserialization module has an input port suitable for receiving high-speed serial signals output by the radar under test, and the output terminal of the serialization deserialization module outputs MIPI DPHY data signals. The FPGA main control module is connected to the output terminals of the electrical parameter acquisition circuit and the serialization and deserialization module, respectively. The FPGA main control module is internally configured with a data receiving circuit and a data verification unit. The data receiving circuit concurrently receives multiple MIPI DPHY data signals, and the data verification unit performs ECC verification, CRC verification, and error frame flag identification on each MIPI DPHY data signal. The high-speed cache module is connected to the FPGA main control module. The high-speed cache module provides concurrent cache space for the FPGA main control module. The FPGA main control module splices multiple consecutive frame data processed by the data verification unit into combined frame data in time sequence. The high-speed transmission module is connected to the FPGA main control module and the host computer respectively. The high-speed transmission module transmits the combined frame data and the electrical parameters output by the electrical parameter acquisition circuit to the host computer.

2. The MIPI-based lidar and millimeter-wave radar aging device according to claim 1, characterized in that, The FPGA main control module includes multiple FPGA chips that work in parallel. Each FPGA chip instantiates multiple sets of DPHY data receiving IP cores, and each set of DPHY data receiving IP cores constitutes a MIPI DPHY input channel. Each group of MIPI DPHY input channels is configured to distinguish between two radar data streams through a MIPI virtual channel identifier and receive them alternately, enabling each group of MIPI DPHY input channels to concurrently receive MIPI data signals output by two radars under test.

3. The aging device for MIPI-based lidar and millimeter-wave radar according to claim 1, characterized in that, The power supply and detection module includes a POC power supply unit and a high current supply unit; The output terminal of the POC power supply unit is multiplexed with the coaxial signal line of the serialization-deserialization module, and power is supplied to the radar under test through the coaxial signal line. The output terminal of the high current supply unit supplies power to the radar under test via a power line independent of the coaxial signal line. The rated output current of the high current supply unit is higher than the rated output current of the POC power supply unit.

4. The MIPI-based lidar and millimeter-wave radar aging device according to claim 3, characterized in that, Both the POC power supply unit and the high current supply unit include a DC / DC step-down circuit and an LDO linear regulator circuit connected in series. The feedback terminal of the LDO linear regulator circuit is connected to a digital potentiometer, and the control terminal of the digital potentiometer is connected to a digital control interface. The output terminal of the LDO linear regulator circuit is connected to an overcurrent clamping protection circuit. The overcurrent clamping protection circuit includes a current sampling circuit and a current limiting circuit. When the current value detected by the current sampling circuit exceeds a preset threshold, the current limiting circuit clamps the output current to the preset threshold and re-enables the output of the LDO linear regulator circuit after a preset time.

5. The MIPI-based lidar and millimeter-wave radar aging device according to claim 2, characterized in that, The data verification unit includes multiple ECC / CRC verification sub-units corresponding one-to-one with the MIPI DPHY input channels, and each ECC / CRC verification sub-unit is integrated inside the FPGA main control module; Each of the ECC / CRC check subunits has: ECC check logic for performing ECC check on the packet header of the corresponding MIPI data signal, CRC check logic for performing CRC check on the packet payload, frame boundary identification logic for identifying frame header and frame tail flags, and counting logic for counting the number of valid data and erroneous frames within a frame. The output of the counting logic of each ECC / CRC check subunit is connected to the host computer via the high-speed transmission module, and outputs statistical data including the number of error frames and the corresponding channel identifier.

6. The MIPI-based lidar and millimeter-wave radar aging device according to claim 2, characterized in that, The high-speed cache module includes multiple DDR memory chips, and each DDR memory chip is independently connected to a corresponding FPGA chip. Each FPGA chip receives continuous frame data from the radar under test and writes it sequentially into the DDR memory that is independently connected to it. The FPGA chip then reads out multiple continuous frame data belonging to the same measurement period from the DDR memory after combining them into a combined frame data according to the frame sequence number field in the frame header.

7. The aging device for MIPI-based lidar and millimeter-wave radar according to claim 1, characterized in that, The serialization and deserialization module includes a detachable deserialization board, whose serial input terminal is compatible with multiple serialization protocols, including GMSL and APHY protocols. The deserialization board is equipped with a link status signal pin and an error frame flag signal pin, which are respectively connected to the general-purpose input / output pins of the FPGA main control module through hardware signal lines.

8. The MIPI-based lidar and millimeter-wave radar aging device according to claim 4 or 7, characterized in that, The FPGA main control module also includes a configuration interface module, which includes an I2C interface and / or an SPI interface. The configuration interface module is connected to the following via the I2C interface and / or SPI interface: the protocol pass-through register of the serialization and deserialization module, the signal quality register of the serialization and deserialization module, the digital control interface of the digital potentiometer in the power supply and detection module, and the current acquisition register in the power supply and detection module. The FPGA main control module also includes feedback adjustment logic. The input of the feedback adjustment logic is connected to the read output of the current acquisition register and the signal quality register. The output of the feedback adjustment logic is connected to the digital control interface of the digital potentiometer via the configuration interface module.

9. The MIPI-based lidar and millimeter-wave radar aging device according to claim 1, characterized in that, The high-speed transmission module includes an optical module, an Ethernet acquisition submodule, and a PCIe interface; The high-speed serial transceiver of the FPGA main control module is connected to the electrical port of the optical module, and the optical port of the optical module is connected to the optical port of the Ethernet acquisition submodule via optical fiber. The Ethernet acquisition submodule includes an independent FPGA chip and an external transmission buffer memory. The data input terminal of the independent FPGA chip is connected to the optical port of the Ethernet acquisition submodule, and the data output terminal of the independent FPGA chip is connected to the PCIe interface. The PCIe interface is connected to the host computer.

10. The MIPI-based lidar and millimeter-wave radar aging device according to any one of claims 1 to 9, characterized in that, The output port of the power supply and detection module and the input port of the serialization and deserialization module are both led out via coaxial cables; The coaxial cable is adapted to pass through the wall of the high and low temperature test chamber, so that the aging device is adapted to collect the electrical parameters output by the electrical parameter acquisition circuit of the aging device placed outside the high and low temperature test chamber and the verification results output by the data verification unit in an environment where the radar under test is placed inside the high and low temperature test chamber.

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