Semiconductor device and method of forming the same

Abstract

A semiconductor device can include a waveguide layer, a dielectric layer adjacent to the waveguide layer, a first semiconductor waveguide segment located in the dielectric layer, a second semiconductor waveguide segment located in the dielectric layer, and a plurality of semiconductor optical waveguide branches located in the dielectric layer. Opposite ends of the plurality of semiconductor waveguide branches are coupled to the first semiconductor waveguide segment and the second semiconductor waveguide segment. First segments of the plurality of semiconductor waveguide branches and second segments of the plurality of semiconductor waveguide branches extend over the waveguide layer in a first direction. The first segments and the second segments are arranged in a second direction that is substantially perpendicular to the first direction. A connecting waveguide segment can be included in the dielectric layer and coupled to the first segments and the second segments. Embodiments of the present application also relate to semiconductor devices and methods of forming the same.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Semiconductor devices can be configured to transmit data at high speed and securely between integrated circuits and / or semiconductor dies using optical signals. Optical signals can be transmitted through waveguides within the semiconductor device. Waveguides confine the optical signal, reducing optical loss and increasing propagation efficiency. Data can be encoded into optical signals by modulating light into optical pulses using an optical modulator. These optical pulses are then transmitted to the waveguides to propagate to other areas of the semiconductor device. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device including: a waveguide layer; a dielectric layer adjacent to the waveguide layer; a first semiconductor waveguide segment located in the dielectric layer; a second semiconductor waveguide segment located in the dielectric layer; and a plurality of semiconductor optical waveguide branches located in the dielectric layer, wherein opposite ends of the plurality of semiconductor waveguide branches are coupled to the first semiconductor waveguide segment and the second semiconductor waveguide segment, wherein a first segment and a second segment of the plurality of semiconductor waveguide branches extend over the waveguide layer in a first direction, and wherein the first segment and the second segment are arranged in a second direction substantially perpendicular to the first direction; and a connecting waveguide segment located in the dielectric layer and coupled to the first segment and the second segment.

[0004] Other embodiments of this application provide a method for forming a semiconductor device, comprising: etching a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer; etching the semiconductor layer on the first side of the substrate to form a second semiconductor waveguide branch in the semiconductor layer; bonding a waveguide layer to a second side of the substrate opposite to the first side, such that a first segment and a second segment of the first semiconductor waveguide branch extend over the waveguide layer in a first direction, and such that a third segment and a fourth segment of the second semiconductor waveguide branch extend over the waveguide layer in the first direction, wherein the third segment is laterally located between the first segment and the second segment in a second direction substantially perpendicular to the first direction, wherein the second segment is laterally located between the third segment and the fourth segment in the second direction, wherein the first segment and the second segment are connected together, and wherein the third segment and the fourth segment are connected together; and forming a plurality of electrodes over the waveguide layer.

[0005] Further embodiments of this application provide a method for forming a semiconductor device, comprising: etching a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer, wherein a first segment and a second segment of the first semiconductor waveguide branch extend in a first direction; etching the semiconductor layer on the first side of the substrate to form a second semiconductor waveguide branch in the semiconductor layer, wherein a third segment and a fourth segment of the second semiconductor waveguide branch extend in the first direction, and wherein the first segment, the second segment, the third segment, and the fourth segment are arranged in a second direction substantially perpendicular to the first direction; bonding a waveguide layer to a second side of the substrate opposite to the first side; and forming a plurality of electrodes on the waveguide layer such that the waveguide layer is located between the electrodes and the first semiconductor waveguide branch and the second semiconductor waveguide branch. Attached Figure Description

[0006] Various aspects of the embodiments of this disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1A to 1D This is a diagram of an exemplary semiconductor device described in this article.

[0008] Figures 2A to 2Q This is a diagram illustrating an exemplary embodiment of the semiconductor device described herein.

[0009] Figures 3A to 3D This is a diagram of an exemplary embodiment of the waveguide layer described herein.

[0010] Figure 4A and Figure 4B This is a diagram of an exemplary semiconductor device described in this article.

[0011] Figure 5 This is a diagram of an exemplary semiconductor device described in this article.

[0012] Figure 6 This is a flowchart of an exemplary process related to forming the semiconductor device described herein. Detailed Implementation

[0013] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component on or over a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of embodiments of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations depicted in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0015] Photonic integrated circuits in semiconductor photonic devices can include optical modulator structures. Optical modulators can alter the properties of light, such as amplitude, phase, polarization, and / or frequency. They can be used to encode electrical signals onto light waves to allow for high-speed data transmission. Some optical modulators can use an applied electric field to change the refractive index of a material to modulate light. For example, a Mach-Zehnder modulator (MZM) induces phase modulation by applying different electric fields to different optical paths to modify the refractive index of those paths.

[0016] When silicon is used as the waveguide material for optical modulators, the bandwidth of the optical modulator may be limited, which can degrade the performance of analog optical communications and radio frequency (RF) photonic links. For example, in some cases using silicon, the bandwidth may be limited to 100 GHz. Therefore, materials other than silicon (Si) can be used to achieve higher bandwidths. In some cases, alternative materials such as lithium niobate (LiNbO3) and / or barium titanate (BaTiO3) can be used as waveguide materials to achieve even higher bandwidths. However, when such materials are used for the waveguide segment of an MZM, the length of the MZM may be too large to be compatible with various photonic device layouts and / or transceiver packages, due to the length required for the waveguide segment to achieve modulation efficiency comparable to the operating voltage of a complementary metal-oxide-semiconductor (CMOS) circuit.

[0017] In some embodiments described herein, an optical modulator (e.g., MZM) is fabricated by comprising a plurality of laterally arranged semiconductor waveguide segments situated on a waveguide layer of optional material to have a more compact top-view layout for a given optical path length (e.g., rather than having an elongated top-view length), wherein the laterally arranged semiconductor waveguide segments are connected together in an approximately serpentine top-view layout.

[0018] Each of the laterally arranged semiconductor waveguide segments includes a semiconductor waveguide branch of the optical modulator. The laterally arranged semiconductor waveguide segments are arranged in a direction substantially perpendicular to the length of the optical modulator, and each of the laterally arranged semiconductor waveguide segments has a length less than that if the laterally arranged semiconductor waveguide segments were connected in a continuous straight line along the top view length of the optical modulator (e.g., along the top view length of the optical modulator).

[0019] The near-serpentine top-view layout of the optical modulator enables a compact overall top-view length for the modulator, while allowing for a sufficiently long optical signal propagation path to support the use of optional materials for the waveguide layer, such as lithium niobate (LiNbO3) and barium titanate (BaTiO3). This allows for operating voltages comparable to those of CMOS circuits, while also enabling high optical bandwidth for the modulator without sacrificing compatibility and / or integration with various photonic device layouts and / or transceiver packages. Therefore, high-bandwidth optical modulators exhibiting enhanced optical communication performance can be easily integrated and mass-produced for use in a wide range of photonic devices and transceivers.

[0020] Optical paths between adjacent semiconductor waveguide branches can be established using connecting sections located outside the coverage area of ​​the waveguide layer. In these connecting sections, the semiconductor waveguide branches intersect and cross each other, ensuring that the propagation path lengths of the optical signals through the branches are approximately equal, thus maintaining synchronization of the optical signals propagating through the branches. This enables high reliability and a low error rate in the operation of the optical modulator.

[0021] Figures 1A to 1D This is a diagram of an exemplary semiconductor device 100 described herein. Semiconductor device 100 may be a silicon photonic device, a CMOS device with integrated optical circuitry (e.g., co-packaged optics), and / or another type of semiconductor device including photonic integrated circuits.

[0022] Figure 1A A top view of the photonic integrated circuit of the semiconductor device 100 is shown. (As shown) Figure 1AAs shown, the photonic integrated circuit includes an optical modulator structure 102, which in some embodiments may be an MZM-type optical modulator structure. The optical modulator structure 102 may include an input optical waveguide structure 104a for receiving an input optical signal and an output optical waveguide structure 104b for providing a modulated optical signal. The optical modulator structure 102 includes a splitter structure 106a (e.g., a multimode interference (MMI) coupler) coupled to the input optical waveguide structure 104a for splitting the input optical signal into multiple input optical signals (e.g., two input optical signals for 1×2 splitting), the multiple input optical signals being distributed to different semiconductor waveguide branches 108a and 108b of the optical modulator structure 102.

[0023] In semiconductor waveguide branches 108a and / or 108b, an input optical signal can be modulated to encode data onto the input optical signal. Optical modulation of the input optical signal can be achieved through electro-optic modulation, thermo-optic modulation, and / or another type of modulation, thereby modifying the refractive index in semiconductor waveguide branches 108a and / or 108b to achieve resonance at a specific wavelength or frequency of the input optical signal. By modulating the refractive index in semiconductor waveguide branches 108a and / or 108b, a data signal can be encoded onto the input optical signal to encode data from the data signal onto the input optical signal propagating through semiconductor waveguide branches 108a and / or 108b.

[0024] By combining (e.g., 2×1 multiplexing) the modulated optical signals from semiconductor waveguide branches 108a and 108b into a unified modulated optical signal provided to the output optical waveguide structure 104b, the modulated optical signals can be multiplexed together at the multiplexer structure 106b (e.g., another MMI coupler).

[0025] like Figure 1A As shown, semiconductor waveguide branch 108a may include multiple segments 108a-1 to 108a-13 connected in series to form an optical signal propagation path between splitter structure 106a and multiplexer structure 106b. Similarly, semiconductor waveguide branch 108b may include multiple segments 108b-1 to 108b-13 connected in series to form an optical signal propagation path between splitter structure 106a and multiplexer structure 106b. Segments 108a-1 to 108a-13 and segments 108b-1 to 108b-13 may each include a semiconductor material, such as silicon (Si) and / or another suitable material.

[0026] The first terminals of segments 108a-1 and 108b-1 can be coupled to the splitter structure 106a. The second terminals of segments 108a-1 and 108b-1 can be coupled to the first terminals of segments 108a-2 and 108b-2, respectively. The second terminals of segments 108a-2 and 108b-2 can be coupled to the first terminals of segments 108a-3 and 108b-3, respectively. The second terminals of segments 108a-3 and 108b-3 can be coupled to the first terminals of segments 108a-4 and 108b-4, respectively. The second terminals of segments 108a-4 and 108b-4 can be coupled to the first terminals of segments 108a-5 and 108b-5, respectively. The second terminals of segments 108a-6 and 108b-6 can be coupled to the first terminals of segments 108a-7 and 108b-7, respectively. The second ends of segments 108a-7 and 108b-7 can be coupled to the first ends of segments 108a-8 and 108b-8, respectively. The second ends of segments 108a-8 and 108b-8 can be coupled to the first ends of segments 108a-9 and 108b-9, respectively. The second ends of segments 108a-9 and 108b-9 can be coupled to the first ends of segments 108a-10 and 108b-10, respectively. The second ends of segments 108a-10 and 108b-10 can be coupled to the first ends of segments 108a-11 and 108b-11, respectively. The second ends of segments 108a-11 and 108b-11 can be coupled to the first ends of segments 108a-12 and 108b-12, respectively. The second ends of segments 108a-12 and 108b-12 can be coupled to the first ends of segments 108a-13 and 108b-13, respectively. The second ends of segments 108a-13 and 108b-13 can be coupled to multiplexer structure 106b.

[0027] like Figure 1AAs shown, segments 108a-1 to 108a-13 and 108b-1 to 108b-13 can be shaped and arranged such that semiconductor waveguide branches 108a and 108b form an approximately serpentine shape in the top view of the optical modulator structure 102. Specifically, each of the semiconductor waveguide branches 108a and 108b includes segments folded back relative to each other. For example, segments 108a-1, 108a-2, 108a-3, and 108a-4 can correspond to a first segment of semiconductor waveguide branch 108a, and segments 108a-6, 108a-7, and 108a-8 can correspond to a second segment of semiconductor waveguide branch 108a, the second segment extending alongside the first segment and folded back relative to the first segment by segment 108a-5 in the connecting optical waveguide segment 110a of the optical modulator structure 102. Similarly, segments 108b-1, 108b-2, 108b-3 and 108b-4 may correspond to the first segment of semiconductor waveguide branch 108b, and segments 108b-6, 108b-7 and 108b-8 may correspond to the second segment of semiconductor waveguide branch 108b, the second segment extending alongside the first segment and folded back relative to the first segment by segment 108b-5 in the connecting optical waveguide segment 110a of the optical modulator structure 102.

[0028] As another example, segments 108a-10, 108a-11, 108a-12, and 108a-13 can correspond to the third segment of semiconductor waveguide branch 108a, which extends alongside the second segment and is folded back relative to the second segment by segment 108a-9 in the connecting optical waveguide segment 110b via optical modulator structure 102. Similarly, segments 108b-10, 108b-11, 108b-12, and 108b-13 can correspond to the third segment of semiconductor waveguide branch 108b, which extends alongside the second segment and is folded back relative to the second segment by segment 108b-9 in the connecting optical waveguide segment 110b via optical modulator structure 102.

[0029] Semiconductor waveguide branches 108a and / or 108b may include... Figure 1A The diagram shows different numbers of foldback segments. The serpentine top-view shape of the semiconductor waveguide branches 108a and 108b, compared to the case where the segments of the semiconductor waveguide branches 108a and 108b are arranged in a completely straight line, allows for an increased optical signal propagation path through the semiconductor waveguide branches 108a and 108b while maintaining a compact coverage area for the optical modulator structure 102.

[0030] Segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 may extend (and can extend further) in the x-direction of the semiconductor device 100, and may be arranged in the y-direction of the semiconductor device 100. Specifically, segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 may extend substantially parallel to each other in the x-direction. Segments 108a-2, 108b-2, 108a-4, 108b-4, 108a-6, 108b-6, 108a-8, 108b-8, 108a-10, 108b-10, 108a-12, and 108b-12 may be referred to as transition segments. These segments have non-uniform widths and widths in segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 (in... Figure 1A The widths of segments 108a-1, 108b-1, 108a-5, 108b-5, 108a-9, 108b-9, 108a-13, and 108b-13 (represented as dimension D1) are also considered. Figure 1A The transition between dimensions is represented as D2. In some embodiments, dimension D2 is larger than dimension D1.

[0031] Connecting optical waveguide segments 110a and 110b includes curved and / or otherwise nonlinear segments that couple parallel segments (e.g., segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11) together to form a continuous optical signal propagation path. Segments 108a-5 and 108b-5 in connecting optical waveguide segment 110a may be curved and may intersect at intersection point 112a. Intersection point 112a allows segments 108a-5 and 108b-5 in connecting optical waveguide segment 110b to cross each other. Therefore, along a first section of connecting optical waveguide segment 110a up to intersection point 112a, the first portion of segment 108a-5 is the outer segment, and the first portion of segment 108b-5 is the inner segment. Following the intersection point 112a, along the second section connecting optical waveguide segment 110a, the second part of segment 108a-5 is an inner segment, and the second part of segment 108b-5 is an outer segment. The intersection of segments 108a-5 and 108b-5 allows segments 108a-5 and 108b-5 to have approximately the same length, ensuring that optical signals propagating through semiconductor waveguide branches 108a and 108b remain synchronized.

[0032] Similarly, segments 108a-9 and 108b-9 in connecting optical waveguide segment 110b can be curved and intersect at intersection point 112b. Intersection point 112b allows segments 108a-9 and 108b-9 in connecting optical waveguide segment 110b to cross each other. Therefore, along the first segment of connecting optical waveguide segment 110b up to intersection point 112b, the first portion of segment 108a-9 is the outer segment, and the first portion of segment 108b-9 is the inner segment. After intersection point 112b, along the second segment of connecting optical waveguide segment 110b, the second portion of segment 108a-9 is the inner segment, and the second portion of segment 108b-9 is the outer segment. The intersection of segments 108a-9 and 108b-9 allows segments 108a-9 and 108b-9 to have approximately the same length, ensuring that optical signals propagating through semiconductor waveguide branches 108a and 108b remain synchronized.

[0033] like Figure 1A As further shown, the optical modulator structure 102 may include a waveguide layer 114 located beneath segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11. Segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 may be located within the perimeter of the waveguide layer 114, thereby allowing optical signals to be transmitted between the waveguide layer 114 and segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 via evanescent coupling. Specifically, the proximity between waveguide layer 114 and segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11 and 108b-11 generates an evanescent field from the optical signals in segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11 and / or 108b-11, generating an optical signal generated in waveguide layer 114, and vice versa.

[0034] In some embodiments, one or more of segments 108a-2, 108b-2, 108a-4, 108b-4, 108a-6, 108b-6, 108a-8, 108b-8, 108a-10 and / or 108b-10 (e.g., one or more transition segments) are located within the perimeter of waveguide layer 114. In some embodiments, one or more of segments 108a-2, 108b-2, 108a-4, 108b-4, 108a-6, 108b-6, 108a-8, 108b-8, 108a-10 and / or 108b-10 are located outside the perimeter of waveguide layer 114. Transition segments (e.g., segments 108a-2, 108b-2, 108a-4, 108b-4, 108a-6, 108b-6, 108a-8, 108b-8, 108a-10, and 108b-10) facilitate the transition of optical signals between waveguide layer 114 and segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-10 by pushing the optical mode of the optical signal down into waveguide layer 114 or by pushing the optical mode of the optical signal up into semiconductor waveguide branches 108a and 108b. Specifically, the transition to the smaller width (size D3) of segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11 and 108b-11 pushes the optical mode of the optical signal downward into the waveguide layer 114, and the transition to the larger width (size D4) of segments 108a-1, 108b-1, 108a-5, 108b-5, 108a-9, 108b-9, 108a-13 and 108b-13 pushes the optical mode of the optical signal upward into the semiconductor waveguide branches 108a and 108b.

[0035] Waveguide layer 114 may include a material different from that of semiconductor waveguide branches 108a and 108b. For example, the semiconductor waveguide branches 108a and 108b may be made of silicon (Si), while waveguide layer 114 may be made of lithium niobate (LiNbO3), barium titanate (BaTiO3), and / or another material having a higher optical bandwidth than silicon.

[0036] The serpentine top-view layout of semiconductor waveguide branches 108a and 108b provides a sufficiently long light propagation path through the optical modulator structure 102, allowing materials such as thin-film lithium niobate (LiNbO3) (TFLN) and / or thin-film barium titanate (BaTiO3) (TFBT) to be used in waveguide layer 114 for increased optical bandwidth, while enabling a relatively compact coverage area for optical modulator structure 102. Materials such as TFLN and TFBT offer significantly higher optical bandwidth performance compared to materials such as silicon (Si) because the non-centrosymmetric crystal structure of TFLN and TFBT allows the refractive index in waveguide layer 114 to be linearly modulated in response to an electric field applied to waveguide layer 114. For very high-speed optical modulation of optical signals, the linear response provides a near-instantaneous response in refractive index modulation. Changes in the refractive index in waveguide layer 114 induce birefringence in the optical signal propagating through waveguide layer 114, causing different polarization components (e.g., TE polarization and TM polarization) to experience different phase velocities, and thus producing a phase shift. Changes in polarization or phase can be translated into amplitude modulation for modulating optical signals. The evanescent coupling between waveguide layer 114 and segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 provides multiple instances of modulation within waveguide layer 114, effectively providing a long optical signal propagation path that is divided into multiple channels through waveguide layer 114 (e.g., instead of a single long channel through the waveguide layer in the case of using a single straight and elongated set of branches).

[0037] The optical propagation path of the semiconductor waveguide branches 108a and 108b between the splitter structure 106a and the multiplexer structure 106b is greater than the length of the waveguide layer 114 in the x-direction (in Figure 1A The dimension is represented as D3), and is greater than the width of waveguide layer 114 in the y-direction (in Figure 1A (This is represented as dimension D4).

[0038] More specifically, the combined length of the light propagation path through segments 108a-3, 108a-7, and 108a-11 of semiconductor waveguide branch 108a is greater than the length of waveguide layer 114 in the x-direction and greater than the width of waveguide layer 114 in the y-direction. Similarly, the combined length of the light propagation path through segments 108b-3, 108b-7, and 108b-11 of semiconductor waveguide branch 108b is greater than the length of waveguide layer 114 in the x-direction and greater than the width of waveguide layer 114 in the y-direction.

[0039] In some aspects, the length of waveguide layer 114 (e.g., dimension D3 of the length along segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11) is greater than the width of waveguide layer 114 (e.g., dimension D4). In some embodiments, the ratio of the length to the width of waveguide layer 114 (e.g., D3:D4) may include a range of about 5:1 to about 1:1 to achieve a compact layout for optical modulator structure 102, while ensuring that a sufficient number of turns for semiconductor waveguide branches 108a and 108b are located within the perimeter of waveguide layer 114 to allow materials such as lithium niobate (LiNbO3) and / or barium titanate (BaTiO3) to be used in waveguide layer 114 for increased optical bandwidth. However, other ranges and values ​​are within the scope of embodiments of this disclosure. In some implementations, the width of waveguide layer 114 (e.g., dimension D2) may be based on the number of turns for semiconductor waveguide branches 108a and 108b, where more turns result in a larger width, or fewer turns result in a smaller width.

[0040] In some embodiments, the connecting optical waveguide segments 110a and 110b can be located adjacent to the opposite side of the waveguide layer 114, such as... Figure 1A As shown in the examples. In some embodiments, two or more connecting optical waveguide segments may be located on the same side of waveguide layer 114. In some embodiments, two or more connecting optical waveguide segments may be located on adjacent sides of waveguide layer 114.

[0041] like Figure 1A As further shown, electrodes 116a-116d and 118a-118c of an optical modulator structure 102 may be arranged alternately along the y-direction along and / or within the waveguide layer 114. The waveguide layer 114 may be vertically located between segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 and electrodes 116a-116d and 118a-118c.

[0042] Electrodes 116a-116d and 118a-118c can be arranged along the y-direction in the following order: electrode 116a, electrode 118a, electrode 116b, electrode 118b, electrode 116c, electrode 118c, and electrode 116d. Electrodes 116a-116d can correspond to the ground electrode of the optical modulator structure 102, and electrodes 118a-118c can correspond to the signal electrode of the optical modulator structure 102. Therefore, the arrangement of the electrodes of the optical modulator structure 102 along the y-direction can correspond to: ground electrode (electrode 116a), signal electrode (electrode 118a), ground electrode (electrode 116b), signal electrode (electrode 118b), ground electrode (electrode 116c), signal electrode (electrode 118c), and ground electrode (electrode 116d). However, other arrangements of the ground electrode and signal electrode are within the scope of embodiments of this disclosure.

[0043] Electrodes 116a and 118a may be located adjacent to the opposite side of segment 108a-3 of semiconductor waveguide branch 108a in the y-direction, and may extend alongside and generally parallel to segment 108a-3. A voltage bias may be applied across electrodes 116a and 118a to generate an electric field in the portion of waveguide layer 114 located below segment 108a-3 to modulate an optical signal transmitted between segment 108a-3 and waveguide layer 114. The electric field is modulated according to the Pockels effect, which is a direction-dependent linear change in the refractive index of waveguide layer 114 in response to the electric field applied across electrodes 116a and 118a.

[0044] Electrodes 116b and 118a may be located adjacent to the opposite side of segment 108b-3 of semiconductor waveguide branch 108b in the y-direction, and may extend alongside and substantially parallel to segment 108a-3. A voltage bias may be applied across electrodes 116b and 118a to generate an electric field in the portion of waveguide layer 114 located below segment 108b-3 to modulate optical signals transmitted between segment 108a-3 and waveguide layer 114.

[0045] Electrodes 116b and 118b may be located adjacent to the opposite side of segment 108a-7 of semiconductor waveguide branch 108a in the y-direction, and may extend alongside and substantially parallel to segment 108a-7. A voltage bias may be applied across electrodes 116b and 118b to generate an electric field in the portion of waveguide layer 114 located below segment 108a-7 to modulate optical signals transmitted between segment 108a-7 and waveguide layer 114.

[0046] Electrodes 116c and 118b may be located adjacent to the opposite side of segment 108b-7 of semiconductor waveguide branch 108b in the y-direction, and may extend alongside and substantially parallel to segment 108b-7. A voltage bias may be applied across electrodes 116c and 118b to generate an electric field in the portion of waveguide layer 114 located below segment 108b-7 to modulate optical signals transmitted between segment 108b-7 and waveguide layer 114.

[0047] Electrodes 116c and 118c may be located in the y-direction adjacent to the opposite side of segment 108a-11 of semiconductor waveguide branch 108a, and may extend alongside and generally parallel to segment 108a-11. A voltage bias may be applied across electrodes 116c and 118b to generate an electric field in the portion of waveguide layer 114 located below segment 108a-11 to modulate optical signals transmitted between segment 108a-11 and waveguide layer 114.

[0048] Electrodes 116d and 118c may be located in the y-direction adjacent to the opposite side of segment 108b-11 of semiconductor waveguide branch 108b, and may extend alongside and generally parallel to segment 108b-11. A voltage bias may be applied across electrodes 116d and 118c to generate an electric field in the portion of waveguide layer 114 located below segment 108b-11 to modulate optical signals transmitted between segment 108b-11 and waveguide layer 114.

[0049] In some embodiments, a voltage bias can be applied across electrodes 116a-116d and 118a-118c to generate a uniform electric field across waveguide layer 114, thereby uniformly modulating the optical signal propagating through waveguide layer 114. In some embodiments, different voltage biases can be applied across different pairs of electrodes 116a-116d and 118a-118c to generate a non-uniform electric field across waveguide layer 114.

[0050] In some embodiments, one or more of electrodes 116a-116d and 118a-118c are formed of a conductive material, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), or gold (Au), and other examples of conductive materials. In some embodiments, one or more of electrodes 116a-116d and 118a-118c are formed of a semiconductor material such as silicon (Si).

[0051] Figure 1B The optical modulator structure 102 is shown along... Figure 1A The cross-sectional view of line AA in the diagram. (See diagram below.) Figure 1BAs shown, electrodes 116a-116d and 118a-118c can be located below and / or beneath waveguide layer 114. Segments 108a-3, 108a-7, and 108a-11 of semiconductor waveguide branch 108a can be located above and / or above waveguide layer 114. Similarly, segments 108b-3, 108b-7, and 108b-11 of semiconductor waveguide branch 108b can be located above and / or above waveguide layer 114. Therefore, electrodes 116a-116d and 118a-118c, waveguide layer 114, and segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 can be arranged vertically in the z-direction within semiconductor device 100.

[0052] Electrodes 116a-116d and 118a-118c may be located in the dielectric layer 120 of the semiconductor device 100 below the waveguide layer 114. The waveguide layer 114 may be located in the dielectric layer 122 of the semiconductor device 100 above the dielectric layer 120. Semiconductor waveguide branches 108a and 108b may be located in the dielectric layer 124 of the semiconductor device 100 above the dielectric layer 122.

[0053] like Figure 1B As shown, portions of dielectric layer 122 may be located on the top and bottom surfaces of waveguide layer 114, such that a first portion of dielectric layer 122 is perpendicularly located between waveguide layer 114 and dielectric layer 120, and a second portion of dielectric layer 122 is perpendicularly located between waveguide layer 114 and dielectric layer 124. A portion of dielectric layer 124 may be located between semiconductor waveguide branches 108a and 108b and dielectric layer 122.

[0054] like Figure 1B As further shown, the electrodes (e.g., one or more of electrodes 116a-116d and / or one or more of electrodes 118a-118c) may have a lateral width in the y direction (in Figure 1B The dimension is represented as D5) and the spacing between the nearest segments of semiconductor waveguide branches 108a and 108b is (in Figure 1B The dimension is represented as D6. In some embodiments, the lateral width (e.g., dimension D5) may include a range of about 100 micrometers to about 200 micrometers. However, other values ​​and ranges are within the scope of embodiments of this disclosure. In some embodiments, the spacing (e.g., dimension D6) may include a range of about 0.3 micrometers to about 0.7 micrometers. However, other values ​​and ranges are within the scope of embodiments of this disclosure.

[0055] Figure 1C The optical modulator structure 102 is shown along... Figure 1A A cross-sectional view of line BB in the diagram. (See diagram below.) Figure 1CAs shown, the segments of semiconductor waveguide branches 108a and 108b can have an approximately trapezoidal cross-sectional profile, wherein the width of the base of the segment can be greater than the width of the top of the segment. However, in other embodiments, the segments of semiconductor waveguide branches 108a and 108b can have a different cross-sectional profile.

[0056] Figure 1D The optical modulator structure 102 is shown along... Figure 1A A cross-sectional view of line CC in the diagram. (See diagram below.) Figure 1D As shown, waveguide layer 114 can be separated from the segments of semiconductor waveguide branches 108a and 108b by a vertical distance (in... Figure 1D (represented as dimension D7). In some embodiments, the vertical distance includes a range of about 50 nanometers to about 300 nanometers. However, other values ​​and ranges are within the scope of embodiments of this disclosure.

[0057] As indicated above, Figures 1A to 1D It is provided as an instance. Other instances can be related to... Figures 1A to 1D The descriptions are different.

[0058] Figures 2A to 2Q This is a figure illustrating an exemplary embodiment 200 of the semiconductor device described herein. Although combined with… Figures 2A to 2Q The described operation is illustrated by combining the formation of semiconductor device 100, but the combination can be implemented. Figures 2A to 2Q The operations described herein are used to form another semiconductor device, such as Figure 4A and Figure 4B The semiconductor device 400 shown and / or Figure 5 The semiconductor device 500 shown is an example, as well as other examples. In some embodiments, it is combined with... Figures 2A to 2Q One or more operations described are performed using semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, bonding tools and / or annealing tools, and other examples.

[0059] like Figure 2A As shown, one or more of the operations in exemplary embodiment 200 may be implemented in conjunction with substrate 202. Substrate 202 may be provided in the form of a semiconductor wafer, a silicon-on-insulator (SOI) wafer, or another type of semiconductor substrate.

[0060] like Figure 2BAs shown, substrate 202 may include a layer stack comprising a semiconductor layer 204 (e.g., a silicon (Si) substrate and / or another type of semiconductor substrate), a portion of dielectric layer 124 located above and / or on the semiconductor layer 204 (e.g., a buried oxide or bottom oxide (BOX) layer and / or another type of insulating layer), and a semiconductor layer 206 located above and / or on the portion of dielectric layer 124 (e.g., a silicon (Si) layer and / or another type of semiconductor layer). Optionally, semiconductor layer 204 may be provided as a semiconductor wafer, and a deposition tool may be used to form a portion of dielectric layer 124 above and / or on semiconductor layer 204, and semiconductor layer 206 may be formed above and / or on the portion of dielectric layer 124. A deposition tool may be used to deposit portions of dielectric layer 124 using chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another type of deposition technique. A deposition tool can be used to form a semiconductor layer 206 using epitaxial technology and / or another type of deposition technology.

[0061] like Figure 2C and Figure 2D As shown, the semiconductor layer 206 of the substrate 202 can be etched to form the input optical waveguide structure 104a, output optical waveguide structure 104b, splitter structure 106a, multiplexer structure 106b, and semiconductor waveguide branches 108a and 108b of the optical modulator structure 102 of the semiconductor device 100. In particular, the semiconductor layer 206 can be etched to form segments 108a-1 to 108a-13 of the semiconductor waveguide branch 108a and segments 108b-1 to 108b-13 of the semiconductor waveguide branch 108b, such that segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11, and 108b-11 are arranged in the y-direction and extend substantially parallel to each other in the x-direction. In addition, the semiconductor layer 206 can be etched to form connecting optical waveguide segments 110a and 110b, such that connecting optical waveguide segments 110a and 110b connect segments 108a-3, 108a-7 and 108a-11 in series, and connect segments 108b-3, 108b-7 and 108b-11 in series.

[0062] In some embodiments, a pattern in the photoresist layer is used to etch the semiconductor layer 206 to form the input optical waveguide structure 104a, output optical waveguide structure 104b, splitter structure 106a, multiplexer structure 106b, and semiconductor waveguide branches 108a and 108b of the optical modulator structure 102. In these embodiments, a deposition tool can be used to form the photoresist layer on the semiconductor layer 206 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the semiconductor layer 206 based on the pattern to form the input optical waveguide structure 104a, output optical waveguide structure 104b, splitter structure 106a, multiplexer structure 106b, and semiconductor waveguide branches 108a and 108b of the optical modulator structure 102. In some embodiments, the etching operation includes dry etching (e.g., plasma-based etching, gas-based etching), wet chemical etching, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an optional technique for pattern-based etching of the semiconductor layer 206.

[0063] like Figure 2E As shown, additional material can be deposited on dielectric layer 124. This additional material may correspond to shallow trench isolation (STI) portions of dielectric layer 124. The STI portions may laterally surround the input optical waveguide structure 104a, output optical waveguide structure 104b, splitter structure 106a, multiplexer structure 106b, and semiconductor waveguide branches 108a and 108b of optical modulator structure 102.

[0064] Additional material for dielectric layer 124 can be deposited using deposition tools employing PVD, ALD, CVD, and / or another suitable deposition technique. In some embodiments, planarization tools can be used to perform planarization operations (e.g., chemical mechanical planarization (CMP) operations) to planarize dielectric layer 124 after the deposition of additional material.

[0065] like Figure 2F As shown, an additional dielectric layer can be formed over the front side of the semiconductor device 100. For example, an alternating arrangement of an interlayer dielectric (ILD) layer 208 and an etch stop layer (ESL) 210 can be formed over the optical modulator structure 102 and over the dielectric layer 124. The ILD layer 208 may include a low dielectric constant (low k) layer, which includes one or more low k materials, such as silicon oxide (SiO2). xESL 210 may include a high-k dielectric layer, which may comprise one or more high-k materials, such as silicon nitride (Si). x N y ).

[0066] Deposition tools can be used to deposit material for ILD layers 208 and / or ESL 210 using PVD, ALD, CVD, and / or another suitable deposition technique. In some embodiments, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize ILD layers 208 and / or ESL 210 after the deposition of additional material.

[0067] like Figure 2G As shown, the semiconductor device 100 can be bonded to the carrier substrate 212 using a bonding tool. Figure 2H As shown, the semiconductor device 100 can be flipped so that the back side of the semiconductor device 100 faces upward. The carrier substrate 212 may include a processing wafer, a silicon (Si) wafer, and / or another type of substrate that supports the semiconductor device 100 for back-side processing.

[0068] like Figure 2I As shown, the semiconductor layer 204 can be removed from the back side of the semiconductor device 100. Removal of the semiconductor layer 204 exposes the dielectric layer 124 on the back side of the semiconductor device 100. In some embodiments, material of the dielectric layer 124 can also be removed from the back side of the semiconductor device 100.

[0069] In some embodiments, a polishing tool may be used to perform a wafer polishing operation to remove material from the semiconductor layer 204 and / or the dielectric layer 124. In some embodiments, a planarization tool may be used to perform a planarization operation (e.g., a CMP operation) to remove material from the semiconductor layer 204 and / or the dielectric layer 124. In some embodiments, an etching tool may be used to perform one or more etching operations to remove material from the semiconductor layer 204 and / or the dielectric layer 124.

[0070] like Figure 2J and Figure 2K As shown, the waveguide layer 114 of the optical modulator structure 102 can be bonded to the back side of the semiconductor device 100. A layer stack 214 including the waveguide layer 114 and the dielectric layer 122 can be formed on the carrier substrate 216 (bonded). Figures 3A to 3D Examples thereof are shown and described, and the layer stack 214 can be bonded to the semiconductor device 100. A bonding tool can be used to perform the bonding operation to form a dielectric-to-dielectric bond between dielectric layers 122 and 124.

[0071] like Figure 2L As shown, waveguide layer 114 may be located on segments 108a-3, 108b-3, 108a-7, 108b-7, 108a-11 and 108b-11 of semiconductor waveguide branches 108a and 108b of optical modulator structure 102.

[0072] like Figure 2M As shown, the carrier substrate 216 can be removed from the back side of the semiconductor device 100. Removal of the carrier substrate 216 exposes the dielectric layer 122 on the back side of the semiconductor device 100. In some embodiments, the material of the dielectric layer 122 can also be removed from the back side of the semiconductor device 100.

[0073] In some embodiments, a polishing tool may be used to perform a wafer polishing operation to remove material from the carrier substrate 216 and / or the dielectric layer 122. In some embodiments, a planarization tool may be used to perform a planarization operation (e.g., CMP operation) to remove material from the carrier substrate 216 and / or the dielectric layer 122. In some embodiments, an etching tool may be used to perform one or more etching operations to remove material from the carrier substrate 216 and / or the dielectric layer 122.

[0074] like Figure 2N and Figure 2O As shown, electrodes 116a-116d and 118a-118c of the optical modulator structure 102 can be formed over a waveguide layer 114 on the back side of the semiconductor device 100. In some embodiments, electrodes 116a-116d and 118a-118c are formed by depositing and etching a material layer over the waveguide layer 114 to form electrodes 116a-116d and 118a-118c. Subsequently, a material of the dielectric layer 120 can be deposited and planarized around electrodes 116a-116d and 118a-118c, such that the top of the dielectric layer 120 and the tops of electrodes 116a-116d and 118a-118c are substantially coplanar. In some embodiments, the dielectric layer 120 is deposited and etched over the waveguide layer 114 to form a groove in the dielectric layer 120. The material for electrodes 116a-116d and 118a-118c can then be deposited and planarized in the grooves.

[0075] like Figure 2P As shown, another dielectric layer 218 can be formed over electrodes 116a-116d and 118a-118c on the back side of semiconductor device 100, and back-side interconnects 220 can be formed on electrodes 116a-116d and 118a-118c, such that the back-side interconnects 220 are located in dielectric layer 218.

[0076] In some embodiments, the back-side interconnect 220 is formed by depositing a metal material layer over the dielectric layer 120 and electrodes 116a-116d and 118a-118c and etching the material layer to form the back-side interconnect 220 on the electrodes 116a-116d and 118a-118c. Subsequently, a material of the dielectric layer 218 may be deposited and planarized around the electrodes 116a-116d and 118a-118c such that the top of the dielectric layer 218 and the top of the back-side interconnect 220 are substantially coplanar.

[0077] In some embodiments, a dielectric layer 218 is deposited and etched over the dielectric layer 120 to form a groove in the dielectric layer 218. Electrodes 116a-116d and 118a-118c can be exposed through the groove. Subsequently, material for the back-side interconnect 220 can be deposited and planarized in the groove, such that the back-side interconnect 220 rests on electrodes 116a-116d and 118a-118c.

[0078] like Figure 2Q As shown, the carrier substrate 212 can be removed from the front side of the semiconductor device 100. In some embodiments, a polishing tool can be used to perform a wafer polishing operation to remove the material from the carrier substrate 212. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., CMP operation) to remove the material from the carrier substrate 212. In some embodiments, an etching tool can be used to perform one or more etching operations to remove the material from the carrier substrate 212 by etching.

[0079] As indicated above, Figures 2A to 2Q It is provided as an instance. Other instances can be related to... Figures 2A to 2Q The descriptions are different.

[0080] Figures 3A to 3D This is a diagram illustrating an exemplary embodiment 300 of the waveguide layer 114 described herein. The waveguide layer may be bonded to semiconductor device 100, semiconductor device 400, semiconductor device 500, and / or another semiconductor device, such as... Figure 2J and Figure 2K As shown. In some embodiments, combined with Figures 3A to 3D One or more operations described are performed using semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools and / or another type of semiconductor processing tool.

[0081] like Figure 3A As shown, a carrier substrate 216 may be provided. The carrier substrate 216 may include a silicon wafer and / or another type of carrier substrate.

[0082] like Figure 3B As shown, a dielectric layer 122 may be formed over and / or on a carrier substrate 216. Deposition tools may be used to deposit the material of the dielectric layer 122 using PVD, ALD, CVD, and / or another suitable deposition technique. In some embodiments, planarization tools may be used to perform a planarization operation (e.g., CMP operation) to planarize the dielectric layer 122 after deposition.

[0083] like Figure 3C As shown, a waveguide layer 114 may be formed over and / or on the dielectric layer 122. In some embodiments, the dielectric layer 122 is etched to form a groove in the dielectric layer 122, and the waveguide layer 114 is formed in the groove. In these embodiments, a deposition tool may be used to form a photoresist layer on the dielectric layer 122 (e.g., using spin coating and / or another suitable deposition technique). An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the dielectric layer 122 based on the pattern to form the groove. In some embodiments, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some implementations, a hard mask layer is used as an optional technique for pattern-based etching of the dielectric layer 122.

[0084] Deposition tools can be used to deposit material for the waveguide layer 114 in the groove using PVD, ALD, CVD, and / or another suitable deposition technique. In some embodiments, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize the waveguide layer 114 after deposition.

[0085] like Figure 3D As shown, additional material can be deposited over and / or on the dielectric layer 122, thereby sealing the waveguide layer 114 within the dielectric layer 122. Deposition tools can be used to deposit additional material of the dielectric layer 122 in the trench using PVD, ALD, CVD, and / or another suitable deposition technique. In some embodiments, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize the dielectric layer 122 after depositing additional material.

[0086] As indicated above, Figures 3A to 3D It is provided as an instance. Other instances can be related to... Figures 3A to 3DThe descriptions are different.

[0087] Figure 4A and Figure 4B This is a diagram of the exemplary semiconductor device 400 described herein. Figure 4A and Figure 4B As shown, semiconductor device 400 may be similar to semiconductor device 100 and may include a photonic integrated circuit that includes an optical modulator structure 102. Figure 4A and Figure 4B As further shown, the photonic integrated circuit of semiconductor device 400 may include additional photonic components, such as photodetector structure 402 and / or dielectric waveguide structure 404, and other examples. Photodetector structure 402 includes a semiconductor photonic component configured to generate current, voltage, and / or another type of electrical output signal based on the absorption of photons from an input optical signal. Dielectric waveguide structure 404 may be an edge coupler waveguide or another type of waveguide configured to receive optical signals from an external structure such as an optical fiber cable and transmit the optical signals to the photonic integrated circuit of semiconductor device 400.

[0088] like Figure 4B As shown, the photodetector structure 402 may include a contact 406 corresponding to a collection region for an electrical output signal generated by the absorption region 408 of the photodetector structure 402. The contact 406 may include a p-type doped collection region and an n-type doped collection region located on opposite sides of the absorption region 408. The contact 406 may include a semiconductor material, such as silicon (Si), and may be formed from a semiconductor layer 206 of the substrate 202.

[0089] Absorption region 408 can be configured to absorb photons of an optical signal, wherein the photons generate electron-hole pairs within absorption region 408. The electrons and holes are separated and migrate toward the opposing contact 406 (e.g., the opposing collection region), thereby generating an electric field (e.g., a built-in electric field). Absorption region 408 may include an epitaxially grown region of a semiconductor material, including germanium (Ge), germanium-tin (GeSn), silicon-germanium (SiGe), indium gallium arsenide (InGaAs), and / or gallium arsenide (GaAs), and other examples.

[0090] like Figure 4BAs further shown, the contacts 406 of the photodetector structure 402 can be electrically coupled and / or physically coupled to the interconnect 410. The interconnect 410 can extend through one or more of the ILD layers 208 and / or ESL 210, and can be coupled to one or more metallization structure layers 412. In some embodiments, the photodetector structure 402 is electrically coupled to a back-side interconnect 220, which extends through one or more of the dielectric layers 120, 122, 124 and / or 218, through one or more ILD layers 208, and / or through one or more ESL 210. The back-side interconnect 220 can be coupled to the metallization structure layer 412.

[0091] like Figure 4B As further shown, the dielectric waveguide structure 404 can be located within the ILD layer 208 above the optical modulator structure 102. The dielectric waveguide structure 404 includes a high-dielectric-constant (high-k) or high-refractive-index material core sandwiched between a low-dielectric-constant (low-k) or low-refractive-index material cladding layer of the ILD layer 208. The difference in dielectric constant between the high-k material of the dielectric waveguide structure 404 and the low-k material of the ILD layer 208 enables loose coupling of optical signal modes within the dielectric waveguide structure 404, while providing a relatively low critical angle for achieving total internal reflection within the dielectric waveguide structure 404. This allows the dielectric waveguide structure 404 to be used with high-frequency optical signals in high-speed and / or high-bandwidth applications such as data center communications, millimeter-wave telecommunications (e.g., fifth-generation (5G), sixth-generation (6G), or next-generation telecommunications), autonomous driving, the Internet of Things (IoT), and / or artificial intelligence, among other examples.

[0092] The cross-sectional shape of the dielectric waveguide structure 404 may include a strip waveguide structure. Additionally and / or optionally, the cross-sectional shape of the dielectric waveguide structure 404 may include a ribbed waveguide structure, a deep-ribbed waveguide structure, and / or another type of waveguide structure.

[0093] As indicated above, Figure 4A and Figure 4B It is provided as an instance. Other instances can be related to... Figure 4A and Figure 4B The descriptions are different.

[0094] Figure 5 This is a diagram of the exemplary semiconductor device 500 described herein. Figure 5As shown, semiconductor device 500 may be similar to semiconductor device 100 and may include a photonic integrated circuit including an optical modulator structure 102. The optical modulator structure 102 of semiconductor device 500 may be similar to the optical modulator structure 102 of semiconductor device 100, except that semiconductor waveguide branches 108a and 108b begin and terminate on the same side of waveguide layer 114, instead of starting and terminating on different sides of waveguide layer 114 in the x-direction as in semiconductor device 100. Therefore, the input optical waveguide structure 104a, the output optical waveguide structure 104b, the splitter structure 106a, and the multiplexer structure 106b may all be located on the same side of waveguide layer 114.

[0095] exist Figure 5 In one arrangement, the optical modulator structure 102 includes a single connecting optical waveguide segment 110 and a single intersection point 112. However, in other arrangements where semiconductor waveguide branches 108a and 108b begin and end on the same side of waveguide layer 114, the optical modulator structure 102 may include multiple connecting optical waveguide segments 110 and multiple intersection points 112.

[0096] As indicated above, Figure 5 It is provided as an instance. Other instances can be related to... Figure 5 The descriptions are different.

[0097] Figure 6 This is a flowchart of an exemplary process 600 associated with forming the semiconductor device described herein. In some embodiments, Figure 6 One or more process frames are implemented using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools and / or another type of semiconductor processing tool.

[0098] like Figure 6 As shown, process 600 may include etching a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer (block 610). For example, one or more semiconductor processing tools may be used to etch a semiconductor layer (e.g., semiconductor layer 206) on a first side of a substrate (e.g., substrate 202) to form a first semiconductor waveguide branch (e.g., semiconductor waveguide branch 108a) in the semiconductor layer, as described herein. In some embodiments, a first segment (e.g., segment 108a-3) and a second segment (e.g., segment 108a-7) of the first semiconductor waveguide branch extend in a first direction (e.g., the x-direction).

[0099] like Figure 6As further shown, process 600 may include etching a semiconductor layer on a first side of the substrate to form a second semiconductor waveguide branch in the semiconductor layer (block 620). For example, one or more semiconductor processing tools may be used to etch the semiconductor layer on the first side of the substrate to form a second semiconductor waveguide branch (e.g., semiconductor waveguide branch 108b) in the semiconductor layer, as described herein. In some embodiments, a third segment (e.g., segment 108b-3) and a fourth segment (e.g., segment 108b-7) of the second semiconductor waveguide branch extend in a first direction. In some embodiments, the first, second, third, and fourth segments are arranged in a second direction (e.g., the y-direction) substantially perpendicular to the first direction.

[0100] like Figure 6 As further shown, process 600 may include bonding a waveguide layer to a second side of the substrate opposite to the first side (block 630). For example, one or more semiconductor processing tools may be used to bond the waveguide layer (e.g., waveguide layer 114) to the second side of the substrate opposite to the first side, as described herein.

[0101] like Figure 6 As further shown, process 600 may include forming a plurality of electrodes on the waveguide layer such that the waveguide layer is located between the electrodes and the first semiconductor waveguide branch and the second semiconductor waveguide branch (box 640). For example, one or more semiconductor processing tools may be used to form a plurality of electrodes (e.g., electrodes 116a-116d, e.g., electrodes 118a-118c) on the waveguide layer such that the waveguide layer is located between the electrodes and the first semiconductor waveguide branch and the second semiconductor waveguide branch, as described herein.

[0102] Process 600 may include additional implementations, such as any single implementation or any combination of implementations of one or more other processes described below and / or described elsewhere herein.

[0103] In a first embodiment, process 600 includes: depositing a first dielectric layer (e.g., dielectric layer 124) over a first semiconductor waveguide branch and a second semiconductor waveguide branch; and depositing a second dielectric layer (e.g., dielectric layer 122) over the waveguide layer.

[0104] In the second embodiment, multiple electrodes are formed, either alone or in combination with the first embodiment, including forming multiple electrodes on the second dielectric layer.

[0105] In the third embodiment, alone or in combination with one or more of the first and second embodiments, process 600 includes etching a semiconductor layer on a first side of a substrate to form connecting optical waveguide segments (e.g., connecting optical waveguide segment 110a, connecting optical waveguide segment 110b) in the semiconductor layer, wherein the connecting optical waveguide segments couple the first segment and the second segment together, and wherein the connecting optical waveguide segments couple the third segment and the fourth segment together.

[0106] In the fourth embodiment, bonding the waveguide layer to a second side of the substrate, alone or in combination with one or more of the first to third embodiments, includes bonding the waveguide layer to a second side of the substrate such that the connecting optical waveguide segment is located outside the perimeter of the waveguide layer.

[0107] In the fifth embodiment, bonding the waveguide layer to the second side of the substrate, alone or in combination with one or more of the first to fourth embodiments, includes bonding the waveguide layer to the second side of the substrate such that the first segment, the second segment, the third segment, and the fourth segment are located within the perimeter of the waveguide layer.

[0108] Although Figure 6 An exemplary block diagram of process 600 is shown, but in some embodiments, process 600 includes... Figure 6 The frames depicted in the diagram may be additional frames, fewer frames, different frames, or frames with different arrangements. Alternatively or optionally, two or more frames in process 600 may be implemented in parallel.

[0109] In this way, an optical modulator (e.g., MZM) is fabricated by comprising multiple laterally arranged semiconductor waveguide segments situated on a waveguide layer of optional material to have a more compact top-view layout for a given optical path length (e.g., rather than having an elongated top-view length), wherein the laterally arranged semiconductor waveguide segments are connected together in an approximately serpentine top-view layout.

[0110] Each of the laterally arranged semiconductor waveguide segments includes a semiconductor waveguide branch of the optical modulator. The laterally arranged semiconductor waveguide segments are arranged in a direction substantially perpendicular to the length of the optical modulator, and each of the laterally arranged semiconductor waveguide segments has a length less than that if the laterally arranged semiconductor waveguide segments were connected in a continuous straight line along the top view length of the optical modulator (e.g., along the top view length of the optical modulator).

[0111] The near-serpentine top-view layout of the optical modulator enables a compact overall top-view length for the modulator, while allowing for a sufficiently long optical signal propagation path to support the use of optional materials for the waveguide layer, such as lithium niobate (LiNbO3) and / or barium titanate (BaTiO3). This allows for operating voltages comparable to those of CMOS circuits, while enabling high optical bandwidth for the modulator without sacrificing compatibility and / or integration with various photonic device layouts and / or transceiver packages. Therefore, high-bandwidth optical modulators exhibiting enhanced optical communication performance can be easily integrated and mass-produced for use in a wide range of photonic devices and transceivers.

[0112] The following provides an overview of some aspects of embodiments of this disclosure:

[0113] Aspect 1: A semiconductor device comprising: a waveguide layer; a dielectric layer adjacent to the waveguide layer; a first semiconductor waveguide segment located in the dielectric layer; a second semiconductor waveguide segment located in the dielectric layer; and a plurality of semiconductor optical waveguide branches located in the dielectric layer, wherein opposite ends of the plurality of semiconductor waveguide branches are coupled to the first semiconductor waveguide segment and the second semiconductor waveguide segment, wherein the first segment and the second segment of the plurality of semiconductor waveguide branches extend over the waveguide layer in a first direction, and wherein the first segment and the second segment are arranged in a second direction substantially perpendicular to the first direction; and a connecting waveguide segment located in the dielectric layer and coupled to the first segment and the second segment.

[0114] Aspect 2: According to the semiconductor device of Aspect 1, the waveguide layer includes a lithium niobate (LiNbO3) waveguide layer or a barium titanate (BaTiO3) waveguide layer.

[0115] Aspect 3: A semiconductor device according to any one of Aspects 1-2, wherein the first semiconductor optical waveguide segment and the second semiconductor optical waveguide segment are located outside the perimeter of the waveguide layer.

[0116] Aspect 4: A semiconductor device according to any one of Aspects 1-3, wherein the connecting optical waveguide segment is located outside the perimeter of the waveguide layer.

[0117] Aspect 5: A semiconductor device according to any one of Aspects 1-4, wherein each of the first and second segments is substantially straight and extends in a first direction.

[0118] Aspect 6: A semiconductor device of any one of Aspects 1-5, wherein the connecting optical waveguide segment comprises: a third segment of a plurality of semiconductor optical waveguide branches, the third segment connecting the first segment and the second segment.

[0119] Aspect 7: According to the semiconductor device of aspect 6, the third segment has a non-linear top view shape.

[0120] Aspect 8: A method comprising: etching a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer; etching a semiconductor layer on the first side of the substrate to form a second semiconductor waveguide branch in the semiconductor layer; bonding a waveguide layer to a second side of the substrate opposite to the first side, such that a first segment and a second segment of the first semiconductor waveguide branch extend over the waveguide layer in a first direction, and such that a third segment and a fourth segment of the second semiconductor waveguide branch extend over the waveguide layer in a first direction, wherein the third segment is laterally located between the first segment and the second segment in a second direction substantially perpendicular to the first direction, wherein the second segment is laterally located between the third segment and the fourth segment in the second direction, wherein the first segment and the second segment are connected together, and wherein the third segment and the fourth segment are connected together; and forming a plurality of electrodes over the waveguide layer.

[0121] Aspect 9: According to the method of aspect 8, wherein a plurality of electrodes extend in a first direction.

[0122] Aspect 10: The method according to any one of Aspects 8-9, wherein forming a plurality of electrodes includes forming a plurality of electrodes after bonding the waveguide layer to a second side of the substrate.

[0123] Aspect 11: The method according to any one of Aspects 8-10, wherein a plurality of electrodes extend along a first segment, a second segment, a third segment and a fourth segment.

[0124] Aspect 12: According to any one of Aspects 8-11, wherein the length of the waveguide layer in the first direction is greater than the width of the waveguide layer in the second direction.

[0125] Aspect 13: According to the method of any one of Aspects 8-12, wherein the fifth segment is coupled to the first and second segments, and the sixth segment is coupled to the third and fourth segments.

[0126] Aspect 14: According to the method of aspect 13, the fifth and sixth paragraphs intersect each other.

[0127] Aspect 15: A method comprising: etching a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer, wherein a first segment and a second segment of the first semiconductor waveguide branch extend in a first direction; etching a semiconductor layer on the first side of the substrate to form a second semiconductor waveguide branch in the semiconductor layer, wherein a third segment and a fourth segment of the second semiconductor waveguide branch extend in the first direction, and wherein the first segment, the second segment, the third segment and the fourth segment are arranged in a second direction substantially perpendicular to the first direction; bonding a waveguide layer to a second side of the substrate opposite to the first side; and forming a plurality of electrodes on the waveguide layer such that the waveguide layer is located between the electrodes and the first semiconductor waveguide branch and the second semiconductor waveguide branch.

[0128] Aspect 16: The method according to aspect 15 further includes: depositing a material of a first dielectric layer over the first semiconductor waveguide branch and the second semiconductor waveguide branch; and depositing a material of a second dielectric layer over the waveguide layer.

[0129] Aspect 17: According to the method of aspect 16, forming a plurality of electrodes includes: forming a plurality of electrodes on a second dielectric layer.

[0130] Aspect 18: The method according to any one of Aspects 15-17 further includes: etching a semiconductor layer on a first side of the substrate to form a connecting optical waveguide segment in the semiconductor layer, wherein the connecting optical waveguide segment couples the first segment and the second segment together, and wherein the connecting optical waveguide segment couples the third segment and the fourth segment together.

[0131] Aspect 19: According to the method of aspect 18, wherein bonding the waveguide layer to a second side of the substrate comprises bonding the waveguide layer to a second side of the substrate such that the connecting optical waveguide segment is located outside the perimeter of the waveguide layer.

[0132] Aspect 20: The method according to any one of Aspects 15-19, wherein bonding the waveguide layer to a second side of the substrate comprises bonding the waveguide layer to a second side of the substrate such that the first segment, the second segment, the third segment and the fourth segment are located within the perimeter of the waveguide layer.

[0133] Some embodiments of this application provide a semiconductor device including: a waveguide layer; a dielectric layer adjacent to the waveguide layer; a first semiconductor waveguide segment located in the dielectric layer; a second semiconductor waveguide segment located in the dielectric layer; and a plurality of semiconductor optical waveguide branches located in the dielectric layer, wherein opposite ends of the plurality of semiconductor waveguide branches are coupled to the first semiconductor waveguide segment and the second semiconductor waveguide segment, wherein a first segment and a second segment of the plurality of semiconductor waveguide branches extend over the waveguide layer in a first direction, and wherein the first segment and the second segment are arranged in a second direction substantially perpendicular to the first direction; and a connecting waveguide segment located in the dielectric layer and coupled to the first segment and the second segment.

[0134] In some embodiments, the waveguide layer comprises a lithium niobate (LiNbO3) waveguide layer or a barium titanate (BaTiO3) waveguide layer. In some embodiments, the first semiconductor optical waveguide segment and the second semiconductor optical waveguide segment are located outside the perimeter of the waveguide layer. In some embodiments, the connecting optical waveguide segment is located outside the perimeter of the waveguide layer. In some embodiments, each of the first and second segments is substantially straight and extends in the first direction. In some embodiments, the connecting optical waveguide segment comprises a third segment of the plurality of semiconductor optical waveguide branches, the third segment connecting the first and second segments. In some embodiments, the third segment has a non-linear top-view shape.

[0135] Other embodiments of this application provide a method for forming a semiconductor device, comprising: etching a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer; etching the semiconductor layer on the first side of the substrate to form a second semiconductor waveguide branch in the semiconductor layer; bonding a waveguide layer to a second side of the substrate opposite to the first side, such that a first segment and a second segment of the first semiconductor waveguide branch extend over the waveguide layer in a first direction, and such that a third segment and a fourth segment of the second semiconductor waveguide branch extend over the waveguide layer in the first direction, wherein the third segment is laterally located between the first segment and the second segment in a second direction substantially perpendicular to the first direction, wherein the second segment is laterally located between the third segment and the fourth segment in the second direction, wherein the first segment and the second segment are connected together, and wherein the third segment and the fourth segment are connected together; and forming a plurality of electrodes over the waveguide layer.

[0136] In some embodiments, the plurality of electrodes extend in the first direction. In some embodiments, forming the plurality of electrodes includes forming the plurality of electrodes after bonding the waveguide layer to a second side of the substrate. In some embodiments, the plurality of electrodes extend along the first segment, the second segment, the third segment, and the fourth segment. In some embodiments, the length of the waveguide layer in the first direction is greater than the width of the waveguide layer in the second direction. In some embodiments, a fifth segment is coupled to the first segment and the second segment, and a sixth segment is coupled to the third segment and the fourth segment. In some embodiments, the fifth segment and the sixth segment intersect each other.

[0137] Further embodiments of this application provide a method for forming a semiconductor device, comprising: etching a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer, wherein a first segment and a second segment of the first semiconductor waveguide branch extend in a first direction; etching the semiconductor layer on the first side of the substrate to form a second semiconductor waveguide branch in the semiconductor layer, wherein a third segment and a fourth segment of the second semiconductor waveguide branch extend in the first direction, and wherein the first segment, the second segment, the third segment, and the fourth segment are arranged in a second direction substantially perpendicular to the first direction; bonding a waveguide layer to a second side of the substrate opposite to the first side; and forming a plurality of electrodes on the waveguide layer such that the waveguide layer is located between the electrodes and the first semiconductor waveguide branch and the second semiconductor waveguide branch.

[0138] In some embodiments, the method further includes: depositing a material of a first dielectric layer over the first semiconductor waveguide branch and the second semiconductor waveguide branch; and depositing a material of a second dielectric layer over the waveguide layer. In some embodiments, forming the plurality of electrodes includes: forming the plurality of electrodes over the second dielectric layer. In some embodiments, the method further includes: etching the semiconductor layer on the first side of the substrate to form a connecting optical waveguide segment in the semiconductor layer, wherein the connecting optical waveguide segment couples the first segment and the second segment together, and wherein the connecting optical waveguide segment couples the third segment and the fourth segment together. In some embodiments, bonding the waveguide layer to the second side of the substrate includes: bonding the waveguide layer to the second side of the substrate such that the connecting optical waveguide segment is located outside the perimeter of the waveguide layer. In some embodiments, bonding the waveguide layer to the second side of the substrate includes: bonding the waveguide layer to the second side of the substrate such that the first segment, the second segment, the third segment, and the fourth segment are located within the perimeter of the waveguide layer.

[0139] The terms "approximately" and "substantially" can refer to the value of a given quantity that varies within 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, given embodiments of this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0140] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand various aspects of the embodiments of this disclosure. Those skilled in the art should understand that they can readily use the embodiments of this disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the embodiments of this disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of this disclosure.

Claims

1. A semiconductor device, comprising: waveguide layer; Dielectric layer, adjacent to the waveguide layer; The first semiconductor waveguide segment is located in the dielectric layer; The second semiconductor waveguide segment is located in the dielectric layer; as well as Multiple semiconductor waveguide branches are located in the dielectric layer, wherein the opposite ends of the multiple semiconductor waveguide branches are coupled to a first semiconductor waveguide segment and a second semiconductor waveguide segment, wherein the first segment and the second segment of the multiple semiconductor waveguide branches extend above the waveguide layer in a first direction, and wherein the first segment and the second segment are arranged in a second direction substantially perpendicular to the first direction; and A connecting waveguide segment is located in the dielectric layer and coupled to the first segment and the second segment.

2. The semiconductor device according to claim 1, wherein, The waveguide layer includes a lithium niobate (LiNbO3) waveguide layer or a barium titanate (BaTiO3) waveguide layer.

3. The semiconductor device according to claim 1, wherein, The first semiconductor optical waveguide segment and the second semiconductor optical waveguide segment are located outside the perimeter of the waveguide layer.

4. The semiconductor device according to claim 1, wherein, The connecting optical waveguide segment is located outside the perimeter of the waveguide layer.

5. The semiconductor device according to claim 1, wherein, The first segment and the second segment are each substantially straight and extend in the first direction.

6. The semiconductor device according to claim 1, wherein, The connecting optical waveguide segment includes: The third segment of the plurality of semiconductor optical waveguide branches, wherein the third segment connects the first segment and the second segment.

7. The semiconductor device according to claim 6, wherein, The third segment has a non-linear top-view shape.

8. A method of forming a semiconductor device, comprising: The semiconductor layer on the first side of the substrate is etched to form a first semiconductor waveguide branch in the semiconductor layer; The semiconductor layer on the first side of the substrate is etched to form a second semiconductor waveguide branch in the semiconductor layer; A waveguide layer is bonded to a second side of the substrate opposite to the first side, such that a first and second segment of the first semiconductor waveguide branch extends over the waveguide layer in a first direction, and a third and fourth segment of the second semiconductor waveguide branch extends over the waveguide layer in the first direction, wherein the third segment is laterally located between the first and second segments in a second direction substantially perpendicular to the first direction, wherein the second segment is laterally located between the third and fourth segments in the second direction, wherein the first and second segments are connected together, and wherein the third and fourth segments are connected together; and Multiple electrodes are formed above the waveguide layer.

9. The method according to claim 8, wherein, The plurality of electrodes extend in the first direction.

10. A method of forming a semiconductor device, comprising: Etch a semiconductor layer on a first side of a substrate to form a first semiconductor waveguide branch in the semiconductor layer, wherein a first segment and a second segment of the first semiconductor waveguide branch extend in a first direction; The semiconductor layer on the first side of the substrate is etched to form a second semiconductor waveguide branch in the semiconductor layer, wherein a third and a fourth segment of the second semiconductor waveguide branch extends in the first direction, and wherein the first, second, third, and fourth segments are arranged in a second direction substantially perpendicular to the first direction. Bonding the waveguide layer to a second side of the substrate opposite to the first side; and Multiple electrodes are formed on the waveguide layer, such that the waveguide layer is located between the electrodes and the first semiconductor waveguide branch and the second semiconductor waveguide branch.

Images