A multi-path second pulse measurement method, device, equipment and medium

Abstract

The application discloses a kind of multi-path second pulse measurement method, device, equipment and medium, it is related to time frequency measurement technical field.The scheme is with the rising edge and falling edge of reference clock respectively to each lane second pulse signal sampling, according to two sampling results determine the state bit of each cycle and arrange as state code, the number of first value before the first second value in state code is obtained to obtain coarse count value, simultaneously, the edge to be measured in the first second value corresponding period is injected into delay chain to obtain fine measurement value.Therefore, the end point of coarse count and the cycle where fine measurement is located are jointly defined by the same position in state code, so that coarse measurement and fine measurement share the same clock edge boundary, without splicing coarse and fine two results, fundamentally eliminates the measurement dead zone and count ambiguity near clock edge;Meanwhile, coarse count value expands range with state code bit width, fine measurement value provides picosecond resolution through delay chain, both measurement range and single-channel resolution, high-precision measurement is realized.

Description

Technical Field

[0001] This application relates to the field of time and frequency measurement technology, and in particular to a method, apparatus, equipment and medium for measuring multi-channel second pulses. Background Technology

[0002] High-precision measurement and comparison of pulse-per-second (PPS) signals are widely used in satellite navigation timing, power system synchronization phasor measurement, communication network time synchronization, and precision time measurement. With the advancement of Field Programmable Gate Array (FPGA) technology, the delay of its internal logic units has been reduced to the tens of picoseconds. On-chip time-to-digital converters (TDCs) built using the carry chain delay chain structure inside the FPGA are widely used due to their low cost, high integration, and flexible configuration of the number of channels.

[0003] However, existing FPGA-based TDC solutions struggle to balance single-channel resolution and measurement range when used for multi-channel PPS signal measurement: pure delay chain structures offer high resolution, but their range is limited by the number of delay chain stages; while two-stage structures consisting of counters and delay chains can extend the measurement range, the boundary splicing of coarse and fine measurement results relies on complex algorithms, which can easily generate measurement dead zones and counting ambiguities near the clock edge, leading to measurement result jumps or even failures.

[0004] Therefore, how to solve the problem of balancing single-channel resolution and measurement range in FPGA-based TDC solutions, as well as the dead zone and counting ambiguity in the splicing of coarse and fine measurement results, is an urgent problem for technicians in this field. Summary of the Invention

[0005] The purpose of this application is to provide a multi-channel second pulse measurement method, device, equipment and medium to solve the problems of difficulty in balancing single-channel resolution and measurement range in FPGA-based TDC solutions, and the dead zone and counting ambiguity in splicing coarse and fine measurement results.

[0006] To address the aforementioned technical problems, this application provides a multi-channel second pulse measurement method applied to an FPGA, the method comprising: Each second pulse signal is sampled based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle; The state bits for the corresponding period are determined based on the two sampling results, and the state bits are arranged in periodic order to obtain the state code; where the state bit is the first or second value that indicates whether the edge to be measured has been reached. The number of first values ​​before the first second value in the status code is counted to obtain a coarse count value, and the edge to be tested within the period corresponding to the first second value is injected into the delay chain inside the FPGA; Based on the state of each stage of the latch delay chain from the reference clock, and according to the number of stages of the state flip and the single-stage delay of the delay chain, the detailed measurement value is determined. The measurement results of each second pulse signal are determined based on the coarse count value, the period of the reference clock, and the fine measurement value.

[0007] On the one hand, the edge to be tested within the period corresponding to the first second value is injected into the delay chain inside the FPGA, including: Connect the edge to be measured of each second pulse signal to the carry input terminal of the first carry unit of the carry chain; The delay chain is composed of multiple cascaded carry units from the carry chain inside the FPGA; the total delay of the delay chain is not less than the period of the reference clock. Correspondingly, based on the state of each stage of the reference clock latch delay chain, and according to the number of toggles in each stage and the single-stage delay of the delay chain, detailed measurement values ​​are determined, including: Based on the reference clock triggering and connected to the output terminals of each carry unit, the output level of each carry unit is latched to obtain the thermometer code composed of the first logic value and the second logic value; wherein, the first logic value is the output level of the carry unit at the latching time when the edge to be measured has arrived; The number of first logic values ​​in the thermometer code is counted to determine the number of toggle levels. Determine the product of the number of flips and the single-stage delay of the delay chain to obtain a fine measurement.

[0008] On the other hand, the two sampling results include a first sampling result obtained based on the rising edge of the reference clock, and a second sampling result obtained based on the falling edge of the reference clock; Correspondingly, the state bit for the corresponding period is determined based on the two sampling results, including: When both the first and second sampling results are low, the status bit of the corresponding period is determined as the first value; When the first sampling result is low and the second sampling result is high, or when both the first sampling result and the second sampling result are high, the status bit of the corresponding period is determined as the second value. When the first sampling result is high and the second sampling result is low, the status bit of the corresponding period is determined as the first value; The first value is 0, and the second value is 1.

[0009] On the other hand, it also includes: When performing calibration, the reference second pulse signal is used as the first second pulse signal in the multiple second pulse signals to obtain the measurement result of the first channel, and the measurement result of the first channel is used as the reference calibration value. The reference second pulse signal is used as the second pulse signal of each of the other channels in the multi-channel second pulse signal by the gating system, so as to obtain the measurement results of each of the other channels respectively, and the measurement results of the other channels are used as the channel calibration values ​​of the other channels. The calibration values ​​of the remaining channels are subtracted from the reference calibration values ​​to obtain the calibration parameters of the remaining channels, and the calibration parameters are written into the memory. When performing a measurement, the calibration parameters in the memory are read, and the difference between the measurement results of the remaining channels and the corresponding calibration parameters is determined to obtain the calibrated measurement results of the remaining channels. The measurement results of the first channel and the calibrated measurement results of the other channels are used as the measurement results of the calibrated second pulse signals of each channel.

[0010] On the other hand, it also includes: Repeat the steps of obtaining the reference calibration value, the calibration value of each channel, and the calibration parameters of each channel a preset number of times to obtain the preset number of calibration parameters for each channel. Determine the arithmetic mean of the preset number of calibration parameters for the remaining channels, and update the calibration parameters for the remaining channels. The updated calibration parameters are used to determine the post-calibration measurement results for the remaining channels.

[0011] On the other hand, determining the single-stage delay of the delay chain includes: Based on multiple temperature points, test edges with known delay values ​​are injected into the delay chain, and the state of each stage of the delay chain at each temperature point is recorded. Based on the number of flips and the delay value in each state, determine the single-stage delay corresponding to each temperature point, and establish the correspondence between temperature and single-stage delay. Collect the current temperature of the FPGA; Based on the correspondence, two temperature points adjacent to the current temperature are determined, and interpolation is performed on the single-stage delay corresponding to the two temperature points to obtain the single-stage delay at the current temperature; The single-stage delay at the current temperature is used as the single-stage delay of the delay chain.

[0012] On the other hand, each second pulse signal is sampled based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle, including: Multiple second pulse signals are respectively connected to the same clock domain driven by the reference clock in the FPGA; Multiple second pulse signals are sampled in parallel based on the same rising edge and the same falling edge of the reference clock to obtain two sampling results of each second pulse signal in each cycle. Correspondingly, the method also includes: Measurement results of each second pulse signal are acquired in parallel within the same second pulse period; Determine the difference between the measurement results of any two channels in the multi-channel second pulse signal to obtain the time interval between any two channels.

[0013] To address the aforementioned technical problems, this application also provides a multi-channel second pulse measurement device applied to an FPGA, the device comprising: The sampling module is used to sample each second pulse signal based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle; The sorting module is used to determine the status bits of the corresponding period based on the two sampling results, and arrange the status bits in period order to obtain the status code; wherein, the status bit is the first value or the second value that indicates whether the edge to be tested has been reached; The statistical injection module is used to count the number of first values ​​before the first second value in the status code to obtain a coarse count value, and inject the edge to be tested within the period corresponding to the first second value into the delay chain inside the FPGA; The latch determination module is used to latch the state of each stage of the delay chain based on the reference clock, and determine the fine measurement value according to the number of flips in each stage of the state and the single-stage delay of the delay chain. The result determination module is used to determine the measurement results of each second pulse signal based on the coarse count value, the period of the reference clock, and the fine measurement value.

[0014] To address the aforementioned technical problems, this application also provides a multi-channel second pulse measurement device, comprising: Memory, used to store computer programs; An FPGA is used to implement the steps of the above-described multi-channel second pulse measurement method when executing a computer program.

[0015] To address the aforementioned technical problems, this application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the aforementioned multi-channel second pulse measurement method.

[0016] The multi-channel second pulse measurement method provided in this application samples each second pulse signal at the rising and falling edges of a reference clock. Based on the two sampling results, the status bits for each cycle are determined and arranged into status codes. The number of first values ​​before the first second value in the status code is counted to obtain a coarse count. Simultaneously, the measured edge within the cycle corresponding to the first second value is injected into a delay chain to obtain a fine measurement value. Thus, the endpoint of the coarse count and the cycle of the fine measurement are jointly defined by the same position in the status code, allowing coarse and fine measurements to share the same clock edge boundary. No additional algorithm is needed to concatenate the coarse and fine results, fundamentally eliminating measurement dead zones and counting ambiguities near the clock edge, and avoiding measurement result jumps and failures. Furthermore, the coarse count value expands the measurement range with the width of the status code, while the fine measurement value provides picosecond-level resolution via the delay chain. The two work together in the same process, balancing measurement range and single-channel resolution, achieving high-precision measurement of multi-channel second pulse signals.

[0017] In addition, this application also provides a multi-channel second pulse measuring device, equipment and medium, with the same effect as above. Attached Figure Description

[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 A block diagram of the overall structure of the measuring device to which the multi-channel second pulse measurement method provided in the embodiments of this application is applicable; Figure 2 A circuit schematic diagram of the multi-channel second pulse signal input conditioning module provided in an embodiment of this application; Figure 3 This is a schematic diagram of the internal architecture of the FPGA core processing module provided in the embodiments of this application; Figure 4 A schematic diagram of the two-level measurement architecture of the TDC time measurement unit provided in this application embodiment; Figure 5 A flowchart of a multi-channel second pulse measurement method provided in this application embodiment; Figure 6 The delay chain structure and time quantization principle diagram provided in the embodiments of this application; Figure 7 A block diagram illustrating the working principle of the temperature compensation module provided in this application embodiment; Figure 8 A schematic diagram of a multi-channel second pulse measuring device provided in an embodiment of this application; Figure 9This is a structural diagram of the multi-channel second pulse measurement device provided in the embodiments of this application.

[0020] Among them, 1 is the multi-channel second pulse signal input conditioning module, 2 is the FPGA core processing module, 3 is the TDC time measurement unit, 4 is the temperature compensation module, 5 is the data buffer and interface module, 6 is the host computer communication module, 7 is the multi-channel inter-delay calibration module, 11 is the input protection unit, 12 is the level conversion unit, 13 is the filtering and shaping unit, 21 is the clock management unit, 22 is the synchronization acquisition unit, 23 is the TDC measurement core, 31 is the coarse measurement counter, 32 is the fine measurement TDC, and 33 is the measurement result synthesis unit. Detailed Implementation

[0021] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0022] The core of this application is to provide a multi-channel second pulse measurement method, device, equipment and medium to solve the problems in the FPGA-based TDC scheme where it is difficult to balance single-channel resolution and measurement range, and there are dead zones and counting ambiguities when splicing coarse and fine measurement results.

[0023] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0024] This application provides a multi-channel second pulse measurement method, which is applied to FPGA. Figure 1 The overall structural block diagram of the measuring device applicable to the multi-channel second pulse measurement method provided in the embodiments of this application is as follows: Figure 1 As shown, the measuring device includes a multi-channel second pulse signal input conditioning module 1, an FPGA core processing module 2, a TDC time measurement unit 3, a temperature compensation module 4, a data buffer and interface module 5, and a host computer communication module 6. The multi-channel PPS signals undergo level conversion and filtering / shaping by the input conditioning module 1 before being sent to the FPGA core processing module 2. The TDC time measurement unit 3 integrated within the FPGA core processing module 2 performs the time measurement of each second pulse signal. This embodiment uses 8-channel second pulse measurement as an example. The number of second pulse signals can be flexibly configured according to application requirements; this embodiment does not impose any limitations on this, and it depends on the specific implementation.

[0025] Figure 2 The circuit schematic of the multi-channel second pulse signal input conditioning module provided in the embodiments of this application is as follows: Figure 2 As shown, the input conditioning module 1 includes an input protection unit 11, a level conversion unit 12, and a filtering and shaping unit 13. Multiple second pulse signals originate from external time sources (such as GPS, BeiDou, atomic clocks, rubidium clocks, etc.). The amplitude and level format of each second pulse signal may differ; therefore, they are uniformly conditioned by the input conditioning module 1. The input protection unit 11 is constructed using a transient voltage suppressor (TVS) diode in conjunction with a current-limiting resistor to prevent electrostatic discharge (ESD) and surge voltage damage to subsequent circuits. As an optional implementation, the TVS diode is an SMAJ5.0A diode, and the current-limiting resistor is 100 ohms. Level conversion unit 12 is individually configured for each signal channel, employing a high-speed comparator or level conversion chip to uniformly convert various external input level formats (such as transistor-to-transistor logic TTL, low-voltage TTL (LVTTL), complementary metal-oxide-semiconductor CMOS, RS-422, low-voltage differential signal LVDS, etc.) into FPGA-compatible LVTTL or low-voltage complementary metal-oxide-semiconductor LVCMOS levels. Filtering and shaping unit 13 uses a Schmitt trigger or RC low-pass filter to filter out high-frequency noise and glitches in the signal, outputting a shaped pulse signal with steep edges and low jitter. As an optional implementation, filtering and shaping unit 13 uses a Schmitt trigger 74LVC14 to output a standard LVTTL pulse signal with rise and fall times less than 5 nanoseconds. The specific device models used in each unit of input conditioning module 1 do not constitute a limitation of this application and depend on the specific implementation.

[0026] The FPGA core processing module 2 uses a field-programmable gate array (FPGA) as the main control device. As an optional implementation, a Xilinx Artix-7 series FPGA (model XC7A100T-2FGG484I) is used, which has approximately 100,000 logic cells, an on-chip PLL / MMCM clock manager, and high-speed IOB resources, meeting the requirements for 8-channel TDC measurement, temperature acquisition, and data communication. The specific model of the FPGA device does not constitute a limitation of this application and depends on the specific implementation. In addition to generating the aforementioned 400MHz reference clock, the clock management unit 21 can also generate the system operating clock and communication clock. As an optional implementation, a 100MHz system operating clock and a 125MHz Ethernet communication clock are also generated.

[0027] The data buffer and interface module 5 is used to buffer the measurement results of each second pulse signal and upload them to the host computer. As an optional implementation, the data buffer and interface module 5 uses a dual-port random access memory (RAM) or a first-in-first-out (FIFO) memory to buffer the measurement data and uploads the data to the host computer via a high-speed communication interface. The high-speed communication interface used includes at least one of a Gigabit Ethernet interface (supporting UDP / TCP protocol stack), a Universal Serial Bus (USB) 3.0 interface, and a Peripheral Component Interconnect Express (PCIe) interface. The specific type of buffer structure and communication interface does not constitute a limitation of this application and depends on the specific implementation.

[0028] The host computer communication module 6 is used to realize high-speed data transmission between the FPGA and the host computer, supporting real-time display of measurement results, historical data storage, and statistical analysis. As an optional implementation, the host computer communication module 6 is equipped with dedicated measurement software. This software establishes a TCP connection with the FPGA via Gigabit Ethernet and uses a custom application layer protocol for data interaction. The data frame includes fields such as frame header, channel number, timestamp value, temperature value, and checksum. The software includes a real-time waveform display interface, a data statistical analysis unit, an Allan variance analysis unit, and a data recording and playback unit. The real-time waveform display interface plots time-stamped curves of each channel's second pulse signal with the time axis as the horizontal axis and the measured value as the vertical axis. The data statistical analysis unit calculates statistics such as the period, pulse width, time interval between any two channels, and root mean square jitter of each channel's second pulse signal. The Allan variance analysis unit is used to evaluate the long-term frequency stability of the second pulse signal, supporting the calculation of classical Allan variance, overlapped Allan variance, and corrected Allan variance. The data recording and playback unit supports continuous storage of multi-channel measurement data to local storage media, with selectable comma-separated values ​​(CSV) text or binary format, and supports offline playback analysis of historical data. The specific development language, operating platform, and interface implementation of the host computer software do not constitute a limitation of this application and are determined according to the specific implementation.

[0029] Figure 3 This is a schematic diagram of the internal architecture of the FPGA core processing module provided in the embodiments of this application, as shown below. Figure 3 As shown, the FPGA core processing module 2 includes a clock management unit 21, a synchronization acquisition unit 22, and a TDC measurement core 23. Figure 4 The schematic diagram of the two-level measurement architecture of the TDC time measurement unit provided in the embodiments of this application is as follows: Figure 4 As shown, the TDC time measurement unit 3 includes a coarse measurement counter 31, a fine measurement TDC 32, and a measurement result synthesis unit 33. The following describes in detail each step of the multi-channel second pulse measurement method provided in this application, in conjunction with the aforementioned measurement device.

[0030] Figure 5 This is a flowchart illustrating a multi-channel second pulse measurement method provided in an embodiment of this application. Figure 5 As shown, the method includes: S10: Sample each second pulse signal based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle.

[0031] Specifically, the reference clock is generated by the clock management unit 21. The clock management unit 21 can employ a phase-locked loop (PLL) or a mixed-mode clock manager (MMCM) to multiply the clock signal output from the external reference clock source to obtain the reference clock. As an optional implementation, the external reference clock source uses a 50MHz oven-controlled crystal oscillator (OCXO), which is multiplied to 400MHz by the MMCM to serve as the reference clock, corresponding to a clock period of 2.5 nanoseconds. The frequency of the reference clock can be determined according to the measurement accuracy requirements. This embodiment does not limit the specific frequency of the reference clock; it depends on the specific implementation.

[0032] Subsequently, the synchronization acquisition unit 22 samples each second pulse signal at the rising edge of the reference clock in each cycle of the reference clock to obtain a first sampling result, and samples each second pulse signal at the falling edge of the reference clock to obtain a second sampling result. The first sampling result and the second sampling result constitute two sampling results for the corresponding cycle. As an optional implementation, the synchronization acquisition unit 22 uses the Input Double Data Rate (IDDR) primitive in the FPGA's Input / Output Block (IOB) to implement the above-mentioned dual-edge sampling. The IDDR primitive can sample the same second pulse signal once at the rising edge and once at the falling edge of the reference clock, thereby obtaining two sampling results within one reference clock cycle. The specific primitive used for sampling does not constitute a limitation of this application and depends on the specific implementation.

[0033] S11: Determine the status bits for the corresponding period based on the two sampling results, and arrange the status bits in periodic order to obtain the status code.

[0034] The status bit is either the first or second value that indicates whether the edge to be tested has been reached.

[0035] Furthermore, the edge to be measured is the rising edge of the second pulse signal. For each reference clock cycle, a status bit is determined based on the two sampling results obtained within that cycle. The status bit is used to indicate whether the edge to be measured of the second pulse signal has arrived within that cycle: when the status bit is the first value, it indicates that the edge to be measured has not yet arrived within that cycle; when the status bit is the second value, it indicates that the edge to be measured has arrived within that cycle. The status bits obtained from each reference clock cycle are arranged in chronological order according to the reference clock cycle, thus obtaining a string of status codes composed of the first and second values.

[0036] In one optional implementation, the first value is 0 and the second value is 1, so the status code is a binary code consisting of 0s and 1s. For example, a status code obtained from a measurement might be 0000000000000000 1111111111111111 (the first 16 bits are 0, and the last 16 bits are 1), indicating that the edge to be measured has not yet arrived within the first 16 reference clock cycles, and has arrived from the 17th reference clock cycle onwards. It should also be noted that in this embodiment, the bit width of the status code (i.e., the number of reference clock cycles recorded) can be determined based on the period of the second pulse signal and the required measurement range. Since the period of the second pulse signal is typically 1 second, which is much larger than the time range that the status code can cover, in one optional implementation, a counter driven by the reference clock is also provided to record the number of complete cycles of the second pulse signal, while the status code is used to record the position of the edge to be measured within the current measurement window. The two work together to determine the complete time position of the edge to be measured relative to the reference time.

[0037] S12: Count the number of first values ​​before the first second value in the status code to obtain a coarse count value, and inject the edge to be tested within the period corresponding to the first second value into the delay chain inside the FPGA.

[0038] Subsequently, the coarse measurement counter 31 counts the number of first values ​​preceding the first second value in the status code, and uses this number as the coarse count value. For example, in the status code 0000000000000001111111111111111, there are 16 first values ​​(i.e., 16 zeros) preceding the first second value (i.e., the first 1), so the coarse count value is 16. This indicates that the edge under test has undergone 16 reference clock cycles relative to the reference time, and the corresponding coarse measurement time is 16 multiplied by 2.5ns, or 40ns.

[0039] Simultaneously, the edge under test within the reference clock cycle corresponding to the first second value is injected into the delay chain inside the FPGA for subsequent fine measurements within that cycle. In other words, the endpoint of the coarse measurement and the reference clock cycle in which the fine measurement takes place are both defined by the same position of the first second value in the status code, thus connecting the coarse and fine measurements with the same reference clock cycle boundary.

[0040] Figure 6 The delay chain structure and time quantization schematic diagram provided in the embodiments of this application are as follows: Figure 6 As shown, as an optional implementation, the delay chain is the carry chain inside the FPGA, and the edge under test is injected into the carry input (CIN) of the carry chain. The specific implementation structure of the delay chain does not constitute a limitation of this application and depends on the specific implementation.

[0041] S13: Based on the reference clock, latch the state of each stage of the delay chain and determine the detailed measurement value according to the number of flips in each stage and the single-stage delay of the delay chain.

[0042] like Figure 6 As shown, in this embodiment, the states of each stage of the delay chain are latched under the action of a reference clock. Since the edge under test requires time to propagate through each stage of the delay chain, at the latching moment, each stage reached by the edge under test outputs one logic level, and each stage not yet reached by the edge under test outputs another logic level, thus obtaining a set of states for each stage reflecting the propagation depth of the edge under test in the delay chain. Based on the number of stages where states flip and the single-stage delay of the delay chain, a fine measurement value can be determined. This fine measurement value is the sub-cycle time interval between the edge under test and the reference clock.

[0043] As an optional implementation, the single-stage delay is approximately 25 ps. If the number of flipping stages is 16, the fine measurement value is 16 multiplied by 25 ps, which is 400 ps. The specific value of the single-stage delay is related to the device's speed class, process angle, and operating voltage. This embodiment does not limit the specific value of the single-stage delay; it depends on the specific implementation.

[0044] S14: Determine the measurement results of each second pulse signal based on the coarse count value, the period of the reference clock, and the fine measurement value.

[0045] Finally, the measurement result synthesis unit 33 adds the product of the coarse count value and the period of the reference clock, and the fine measurement value, to obtain the measurement result T of the second pulse signal, as shown in the following formula: T=N×T clk +Δt; Where N is the coarse count value, T clkThe reference clock period is Δt, which is the fine measurement value. For example, when the clock period is 2.5ns, the number of toggles is 16, and the fine measurement value is 400ps, the measurement result T = 16 × 2.5ns + 400ps = 40.4ns.

[0046] It is understandable that by performing the above steps on each of the eight second pulse signals, the measurement results of each second pulse signal can be obtained.

[0047] In this embodiment, each second pulse signal is sampled at the rising and falling edges of the reference clock. The status bits for each cycle are determined based on the two sampling results and arranged into status codes. The number of first values ​​before the first second value in the status code is counted to obtain a coarse count. Simultaneously, the measured edge within the cycle corresponding to the first second value is injected into the delay chain to obtain a fine measurement value. Thus, the endpoint of the coarse count and the cycle of the fine measurement are jointly defined by the same position in the status code, allowing coarse and fine measurements to share the same clock edge boundary. No additional algorithm is needed to concatenate the coarse and fine results, fundamentally eliminating measurement dead zones and counting ambiguities near the clock edge, and avoiding measurement result jumps and failures. Furthermore, the coarse count value expands the measurement range with the width of the status code, while the fine measurement value provides picosecond-level resolution via the delay chain. The two work together in the same process, balancing measurement range and single-channel resolution, achieving high-precision measurement of multiple second pulse signals.

[0048] Based on the above embodiments, in some embodiments, the edge to be tested within the period corresponding to the first second value is injected into the delay chain inside the FPGA, including: S101: Connect the edge to be measured of each second pulse signal to the carry input terminal of the carry chain first-level carry unit.

[0049] The delay chain is composed of multiple carry units cascaded in the carry chain inside the FPGA; the total delay of the delay chain is not less than the period of the reference clock.

[0050] In this embodiment, the fine measurement TDC32 is implemented based on the carry chain structure inside the FPGA, with multiple carry units cascaded to form a delay chain. As an optional implementation, the delay chain is constructed using cascaded CARRY4 primitives in the Xilinx FPGA. Each CARRY4 primitive contains 4 carry units, and the propagation delay of a single carry unit is approximately 25 ps. To ensure that the total delay of the delay chain fully covers one reference clock cycle (2.5 ns for 400 MHz), 32 CARRY4 primitives are cascaded, forming a total of 128 carry units (i.e., 128 delay stages). The total delay of the delay chain is approximately 3.2 ns, which is greater than 2.5 ns for one reference clock cycle, thus ensuring that any position of the edge under test within one reference clock cycle falls within the measurable range of the delay chain.

[0051] Correspondingly, based on the state of each stage of the reference clock latch delay chain, and according to the number of toggles in each stage and the single-stage delay of the delay chain, detailed measurement values ​​are determined, including: S102: Based on the reference clock trigger, the array of flip-flops connected to the output terminals of each carry unit latches the output level of each carry unit to obtain the thermometer code composed of the first logic value and the second logic value; wherein, the first logic value is the output level of the carry unit whose edge to be measured has been reached at the latching time.

[0052] S103: Count the number of first logic values ​​in the thermometer code to determine the number of toggles.

[0053] S104: Determine the product of the number of flips and the single-stage delay of the delay chain to obtain a fine measurement value.

[0054] like Figure 6 As shown, in this embodiment, the end of the delay chain is equipped with a D flip-flop array triggered by a reference clock (such as a 400MHz sampling clock). Each flip-flop is connected to the output of its corresponding first-level carry unit. When the reference clock triggers the D flip-flop array to latch, the carry units at each level that have been flipped by the edge under test before the latching time output logic 1 (i.e., the first logic value), and the carry units at each level that have not yet been reached by the edge under test output logic 0 (i.e., the second logic value), thus obtaining a thermometer code composed of 0s and 1s. By counting the number of logic 1s in this thermometer code, the number of stages the edge under test has traveled through in the delay chain (i.e., the number of flips) can be obtained. Multiplying the number of flips by the single-stage delay gives the fine measurement value. For example, if the number of logic 1s in the thermometer code is 16 and the single-stage delay is 25ps, then the fine measurement value is 16 multiplied by 25ps, which is 400ps.

[0055] It should be noted that the thermometer code in this embodiment is obtained by the state latch of the carry units at each stage of the delay chain, and is used to determine the fine measurement value of the sub-cycle. It is a different concept from the state code obtained by the dual-edge sampling decision mentioned above, and the two should not be confused.

[0056] In this embodiment, a delay chain is formed by cascading carry chains, and the total delay of the delay chain is not less than the period of the reference clock. This ensures that any sub-period position of the edge under test within one reference clock period can be quantized and measured by the delay chain, avoiding the generation of fine measurement blind spots within the reference clock period due to insufficient range of the delay chain, and further ensuring the continuity and accuracy of the measurement results.

[0057] Based on the above embodiments, in some embodiments, the two sampling results include a first sampling result obtained based on the rising edge of the reference clock and a second sampling result obtained based on the falling edge of the reference clock; Correspondingly, the state bit for the corresponding period is determined based on the two sampling results, including: S111: When both the first and second sampling results are low, the status bit of the corresponding period is determined as the first value.

[0058] S112: When the first sampling result is low and the second sampling result is high, or when both the first sampling result and the second sampling result are high, the status bit of the corresponding period is determined to be the second value.

[0059] S113: When the first sampling result is high and the second sampling result is low, the status bit of the corresponding period is determined as the first value; The first value is 0, and the second value is 1.

[0060] In a specific embodiment, the first sampling result is the sampled value of the second pulse signal at the rising edge of the reference clock, and the second sampling result is the sampled value of the second pulse signal at the falling edge of the reference clock. Let (first sampling result, second sampling result) represent two sampling results within one reference clock cycle. The correspondence between the four sampling combinations and the status bits is as follows: (0, 0) indicates that both the rising and falling edges are sampled at low levels, and the edge to be measured has not yet arrived within this cycle, so the status bit is 0; (0, 1) indicates that the rising edge sampling is low level and the falling edge sampling is high level. The edge to be measured arrives after the rising edge and before the falling edge in this cycle, and the status bit is 1. (1,1) indicates that both the rising and falling edge samples are at a high level, the edge to be measured has arrived and the second pulse signal is at a high level, and the status bit is 1; (1, 0) indicates that the rising edge sampling is high level and the falling edge sampling is low level. The sampled in this cycle is the falling edge of the second pulse signal, not the rising edge to be measured, and the status bit is 0.

[0061] Therefore, both combinations (0, 1) and (1, 1) are judged as the second value 1. Thus, regardless of whether the edge to be tested falls in the first half or the second half of the reference clock cycle, the cycle is marked as the cycle of the edge to be tested, and it will not be missed or counted repeatedly because the edge to be tested is close to the reference clock edge.

[0062] In this embodiment, the state bit of each cycle is determined by dual-edge sampling and the above-mentioned decision rules. On the one hand, the redundancy of sampling at the rising and falling edges of the reference clock is utilized to avoid sampling errors caused by metastability when the edge to be measured is close to the edge of the reference clock. On the other hand, by making reasonable decisions on the four sampling combinations, the interference of the falling edge of the second pulse signal is eliminated, and the edge to be measured is accurately marked no matter where it falls in the reference clock cycle, ensuring the accuracy of the coarse count value and further eliminating the counting ambiguity near the edge of the reference clock.

[0063] Based on the above embodiments, in some embodiments, the method further includes: S121: When performing calibration, the reference second pulse signal is used as the first second pulse signal in the multiple second pulse signals to obtain the measurement result of the first channel, and the measurement result of the first channel is used as the reference calibration value.

[0064] S122: The reference second pulse signal is sequentially used as the second pulse signal of the other channels in the multi-channel second pulse signal through the selector, so as to obtain the measurement results of the other channels respectively, and the measurement results of the other channels are used as the channel calibration values ​​of the other channels.

[0065] S123: Subtract the calibration value of each of the remaining channels from the reference calibration value to obtain the calibration parameters of the remaining channels, and write the calibration parameters into the memory.

[0066] S124: When performing a measurement, read the calibration parameters in the memory and determine the difference between the measurement results of the remaining channels and the corresponding calibration parameters to obtain the calibrated measurement results of the remaining channels.

[0067] S125: Take the measurement result of the first channel and the calibrated measurement results of the other channels as the measurement results of the calibrated second pulse signals of each channel.

[0068] In this embodiment, inter-channel delay calibration is achieved by combining the multi-channel inter-delay calibration module 7. Taking an 8-channel system as an example, the first channel (channel 1) is selected as the reference channel. When calibration is performed, a high-precision reference second pulse signal is connected to channel 1, and the measurement result t1 of channel 1 is measured as the reference calibration value. The same reference second pulse signal is sequentially switched to channels 2 to 8 through a selector, and the measurement results t2 to t8 of each channel are measured as the channel calibration values ​​for each channel. The delay difference Δti = ti - t1 (i = 2, 3, ..., 8) of each channel relative to the reference channel is calculated as the calibration parameter for each channel, and the calibration parameters are written into the memory.

[0069] It should be noted that in specific implementations, the selector can be implemented using analog switches or relays, and the memory can be implemented using the FPGA's internal Block Random Access Memory (BRAM) or an external Electrically Erasable Programmable Read-Only Memory (EEPROM). The specific implementation of the selector and memory does not constitute a limitation on this application and depends on the specific implementation. When performing measurements, the corresponding calibration parameter is subtracted from the measurement results of each channel, i.e., ti corrected=ti-Δti, thus unifying the measurement results of the 8 channels to the time reference of the reference channel. Among them, the calibration parameter of the reference channel (the first channel) is zero, and its measurement result is directly used as the calibrated measurement result.

[0070] In this embodiment, by switching the same reference second pulse signal to each channel in a time-division manner and measuring the inherent delay of each channel relative to the reference channel, the measurement results of each channel are corrected accordingly. This eliminates the inconsistency in the routing delay of each channel caused by the asymmetry of the internal routing resources of the FPGA, reduces the measurement deviation between channels to the picosecond level, and ensures the consistency and reliability of the comparison results of multiple second pulse signals.

[0071] Furthermore, based on the above embodiments, in some embodiments the method further includes: S126: Repeat the steps of obtaining the reference calibration value, the calibration value of each channel and the calibration parameters of each channel a preset number of times to obtain the preset number of calibration parameters of each channel. S127: Determine the arithmetic mean of the preset number of calibration parameters for the remaining channels to update the calibration parameters for the remaining channels; wherein, the updated calibration parameters are used to determine the post-calibration measurement results for the remaining channels.

[0072] To reduce random errors during the calibration process, in specific implementations, the process of obtaining calibration parameters can be repeated a preset number of times to obtain multiple calibration parameters for each channel. Then, the arithmetic mean of these multiple calibration parameters for each channel is taken, and the average result is used to update the calibration parameters for that channel. The updated calibration parameters are then used for subsequent channel calibrations. As an optional implementation, the preset number of times is 100. The specific value of the preset number of times does not constitute a limitation of this application and depends on the specific implementation. In this way, updating the calibration parameters through multiple measurements and arithmetic averaging reduces the impact of random errors on the calibration parameters in a single calibration, improves the accuracy and stability of the channel calibration parameters, and further enhances the effect of inter-channel consistency calibration.

[0073] Based on the above embodiments, in some embodiments, determining the single-stage delay of the delay chain includes: S131: Inject test edges with known delay values ​​into the delay chain based on multiple temperature points, and record the state of each stage of the delay chain at each temperature point.

[0074] S132: Based on the number of flips and the delay value in each state, determine the single-stage delay corresponding to each temperature point, and establish the correspondence between temperature and single-stage delay.

[0075] S133: Collect the current temperature of the FPGA.

[0076] S134: Based on the correspondence, determine the two temperature points adjacent to the current temperature, and perform interpolation on the single-stage delay corresponding to the two temperature points to obtain the single-stage delay at the current temperature.

[0077] S135: Use the single-stage delay at the current temperature as the single-stage delay of the delay chain.

[0078] Figure 7 This is a block diagram illustrating the working principle of the temperature compensation module provided in the embodiments of this application, as follows: Figure 7 As shown, in this embodiment, temperature compensation for single-stage delay is achieved by combining temperature compensation module 4. In specific implementation, before the device leaves the factory, the entire unit is placed in a high and low temperature test chamber and calibrated at seven temperature points: -40℃, -20℃, 0℃, 25℃, 50℃, 70℃, and 85℃. Two clock signals with the same frequency and adjustable phase are generated by the PLL inside the FPGA as test inputs. One signal is used as the start signal, and the other signal is used as the stop signal after passing through a controllable delay line. By adjusting the delay value of the delay line (covering the range of 0 to 2.5ns), test edges with known delay values ​​are injected into the delay chain, and the state of each stage of the delay chain at each temperature point is recorded. Based on the number of stages flipped in each stage and the known delay value, the single-stage delay corresponding to each temperature point is determined, thereby establishing the correspondence between temperature and single-stage delay (i.e., temperature-single-stage delay lookup table). The number and values ​​of temperature calibration points do not constitute a limitation on this application and are determined according to the specific implementation.

[0079] During actual measurement, the current temperature of the FPGA is acquired. In this implementation, the Xilinx Analog-to-Digital Converter (XADC) on the FPGA chip is used as the temperature sensing unit. Its built-in temperature sensor can directly measure the junction temperature of the FPGA chip, with a measurement range of -40℃ to +125℃ and a resolution of approximately 0.1℃. The chip junction temperature is acquired every 100ms. Based on the current temperature, two temperature calibration points adjacent to the current temperature are found in the temperature-single-stage delay correspondence. The single-stage delay at the current temperature is calculated through linear interpolation and used as the single-stage delay of the delay chain for the calculation of fine measurement values. The specific type of temperature sensor and the acquisition cycle do not constitute a limitation of this application and are determined according to the specific implementation.

[0080] In addition, as another optional implementation, temperature compensation can also be achieved by correcting the raw code value of the fine measurement: the dynamic compensation operation unit calculates the single-stage delay correction coefficient k(T) at the current temperature through linear interpolation in the correspondence between temperature and single-stage delay, and then corrects the raw code value Raw output by the delay chain. Code Revised to: Corrected Code=Raw Code ×k(T) / k(T ref ); Among them, Corrected Code T is the corrected original code value. ref Using a reference calibration temperature (25°C as an optional implementation), the corrected code value is multiplied by the single-stage delay at the reference calibration temperature to obtain the temperature-compensated fine measurement value. This implementation is mathematically equivalent to the aforementioned method of directly interpolating the single-stage delay. This embodiment does not limit the specific calculation method of temperature compensation, but depends on the specific implementation situation.

[0081] In this embodiment, by calibrating the single-stage delay of the delay chain at multiple temperature points and establishing the correspondence between temperature and single-stage delay, the single-stage delay at the current temperature is obtained by real-time interpolation based on the current temperature during actual measurement. This dynamically compensates for the temperature dependence of the transmission delay of the logic unit inside the FPGA, enabling the device to maintain high measurement accuracy over a wide operating temperature range and suppressing measurement errors caused by temperature drift.

[0082] Based on the above embodiments, in some embodiments, each second pulse signal is sampled based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle, including: S141: Connect the multiple second pulse signals to the same clock domain driven by the reference clock in the FPGA.

[0083] S142: Based on the same rising edge and the same falling edge of the reference clock, multiple second pulse signals are sampled in parallel to obtain two sampling results of each second pulse signal in each cycle.

[0084] Correspondingly, the method also includes: S151: Acquire the measurement results of each second pulse signal in parallel within the same second pulse period.

[0085] S152: Determine the difference between the measurement results of any two channels in the multi-channel second pulse signal to obtain the time interval between any two channels.

[0086] In this embodiment, eight second pulse signals are respectively connected to the same clock domain driven by the same reference clock in the FPGA. The eight second pulse signals are sampled in parallel at the same rising edge of the reference clock to obtain the first sampling result of each signal, and then sampled in parallel at the same falling edge of the reference clock to obtain the second sampling result of each signal. This ensures that the eight second pulse signals are sampled synchronously within the same reference clock cycle. As an optional implementation, the eight second pulse signals are respectively connected to the dedicated clock input pins of the FPGA, and parallel synchronous sampling of the eight signals is achieved using a Global Buffer (BUFG) and the IDDR primitive. Furthermore, the measurement results of the eight second pulse signals are acquired in parallel within the same second pulse cycle. By determining the difference between the measurement results of any two second pulse signals, the time interval between the two second pulse signals can be obtained.

[0087] In this embodiment, by connecting multiple second pulse signals to the same clock domain and sampling them in parallel at the same rising and falling edges of the reference clock, the multiple second pulse signals are synchronously sampled and measured within the same second pulse period, eliminating the asynchronous error caused by the traditional polling-by-channel measurement method; and by subtracting the measurement results of any two channels to obtain the time interval between channels, it can reflect the time deviation between channels at the same moment, meeting the measurement requirements of strict synchronous comparison scenarios such as common-view comparison and dual-mode monitoring.

[0088] The multi-channel second pulse measurement method has been described in detail in the above embodiments. This application also provides embodiments of the multi-channel second pulse measurement device.

[0089] Figure 8 This is a schematic diagram of a multi-channel second pulse measurement device provided in an embodiment of this application. The device is applied to an FPGA, such as... Figure 8 As shown, the device includes: The sampling module 40 is used to sample each second pulse signal based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle. The sorting module 41 is used to determine the state bit of the corresponding period based on the two sampling results, and arrange the state bits in the period order to obtain the state code; wherein, the state bit is the first value or the second value that indicates whether the edge to be tested has been reached. The statistical injection module 42 is used to count the number of first values ​​before the first second value in the status code to obtain a coarse count value, and inject the edge to be tested within the period corresponding to the first second value into the delay chain inside the FPGA. The latch determination module 43 is used to latch the state of each stage of the delay chain based on the reference clock, and determine the fine measurement value according to the number of flips in each stage of the state and the single-stage delay of the delay chain. The result determination module 44 is used to determine the measurement results of each second pulse signal based on the coarse count value, the period of the reference clock, and the fine measurement value.

[0090] In some embodiments, the statistical injection module 42 includes: The access module is used to connect the edge to be measured of each second pulse signal to the carry input terminal of the first carry unit of the carry chain; The delay chain is composed of multiple cascaded carry units from the carry chain inside the FPGA; the total delay of the delay chain is not less than the period of the reference clock. Correspondingly, the latch determination module 43 includes: The trigger module is used to trigger the array of flip-flops connected to the output terminals of each carry unit based on the reference clock, and latch the output level of each carry unit to obtain the thermometer code composed of the first logic value and the second logic value; wherein, the first logic value is the output level of the carry unit whose measured edge has been reached at the latching time; The statistics submodule is used to count the number of first logic values ​​in the thermometer code, which is used as the number of toggles. The first determining submodule is used to determine the product of the number of flips and the single-stage delay of the delay chain to obtain a fine measurement value.

[0091] In some embodiments, the two sampling results include a first sampling result obtained based on the rising edge of the reference clock and a second sampling result obtained based on the falling edge of the reference clock; Correspondingly, the sorting module 41 includes: The second determining submodule is used to determine the status bit of the corresponding period as the first value when both the first sampling result and the second sampling result are low. The third determining submodule is used to determine the status bit of the corresponding period as the second value when the first sampling result is low and the second sampling result is high, or when both the first sampling result and the second sampling result are high. The fourth determination submodule is used to determine the status bit of the corresponding period as the first value when the first sampling result is high and the second sampling result is low. The first value is 0, and the second value is 1.

[0092] In some embodiments, it also includes: The fifth determination submodule is used to take the reference second pulse signal as the first second pulse signal in the multiple second pulse signals when performing calibration, so as to obtain the measurement result of the first channel, and use the measurement result of the first channel as the reference calibration value; The sixth determination submodule is used to sequentially use the reference second pulse signal as the second pulse signal of the other channels in the multi-channel second pulse signal through the selector, so as to obtain the measurement results of the other channels respectively, and use the measurement results of the other channels as the channel calibration values ​​of the other channels. The seventh determination submodule is used to subtract the calibration values ​​of the remaining channels from the reference calibration values ​​to obtain the calibration parameters of the remaining channels, and write the calibration parameters into the memory. The eighth determination submodule is used to read the calibration parameters in the memory when the measurement is performed, and determine the difference between the measurement results of the remaining channels and the corresponding calibration parameters, so as to obtain the calibrated measurement results of the remaining channels. The ninth determination submodule is used to take the measurement results of the first channel and the calibrated measurement results of the other channels as the measurement results of the calibrated second pulse signals of each channel.

[0093] In some embodiments, it also includes: The repeat execution module is used to repeatedly execute the steps of obtaining the reference calibration value, the calibration values ​​of the other channels, and the calibration parameters of the other channels a preset number of times, so as to obtain the preset number of calibration parameters of the other channels. The tenth determination submodule is used to determine the arithmetic mean of the preset number of calibration parameters for the remaining channels, so as to update the calibration parameters for the remaining channels. The updated calibration parameters are used to determine the post-calibration measurement results for the remaining channels.

[0094] In some embodiments, it also includes: The injection recording module is used to inject test edges with known delay values ​​into the delay chain based on multiple temperature points, and record the state of each stage of the delay chain at each temperature point. The relationship establishment module is used to determine the single-stage delay corresponding to each temperature point based on the number of flips and delay values ​​in each state, and to establish the correspondence between temperature and single-stage delay. Temperature acquisition module, used to acquire the current temperature of the FPGA; The interpolation module is used to determine two temperature points adjacent to the current temperature based on the correspondence, and to perform interpolation calculations on the single-stage delays corresponding to the two temperature points to obtain the single-stage delay at the current temperature. The single-stage delay determination module is used to determine the single-stage delay at the current temperature as the single-stage delay of the delay chain.

[0095] In some embodiments, the sampling module 40 includes: The clock domain access module is used to connect multiple second pulse signals to the same clock domain driven by the reference clock in the FPGA. The sampling submodule is used to sample multiple second pulse signals in parallel based on the same rising edge and the same falling edge of the reference clock, so as to obtain two sampling results of each second pulse signal in each cycle; Correspondingly, the device also includes: The acquisition module is used to acquire the measurement results of each second pulse signal in parallel within the same second pulse period; The difference determination module is used to determine the difference between the measurement results of any two channels in the multi-channel second pulse signal, so as to obtain the time interval between the two channels.

[0096] Since the embodiments of the apparatus and the embodiments of the method correspond to each other, please refer to the description of the embodiments of the method for the embodiments of the apparatus, which will not be repeated here.

[0097] Figure 9 A structural diagram of the multi-channel second pulse measurement device provided in the embodiments of this application is shown below. Figure 9 As shown, the multi-channel second pulse measurement device includes: Memory 45 is used to store computer programs; FPGA46 is used to implement the steps of the multi-channel second pulse measurement method mentioned in the above embodiments when executing computer programs.

[0098] The multi-channel second pulse measurement device provided in this embodiment can be, but is not limited to, a smartphone, tablet, laptop, or desktop computer. Those skilled in the art will understand that... Figure 9 The structure shown does not constitute a limitation on the multi-channel second pulse measurement device and may include more or fewer components than shown.

[0099] Finally, this application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiments.

[0100] It is understood that if the methods in the above embodiments are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0101] The foregoing provides a detailed description of a multi-channel second pulse measurement method, apparatus, device, and medium provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

[0102] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

Claims

1. A method for measuring multi-channel second pulses, characterized in that, Applied to FPGA, the method includes: Each second pulse signal is sampled based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle; Based on the two sampling results, the state bits of the corresponding period are determined, and the state bits are arranged in periodic order to obtain the state code; wherein, the state bit is a first value or a second value that indicates whether the edge to be tested has been reached. The number of the first values ​​preceding the first second value in the status code is counted to obtain a coarse count value, and the edge to be tested within the period corresponding to the first second value is injected into the delay chain inside the FPGA; Based on the reference clock, the state of each stage of the delay chain is latched, and a detailed measurement value is determined according to the number of stages flipped in each stage of the state and the single-stage delay of the delay chain. The measurement results of each second pulse signal are determined based on the coarse count value, the period of the reference clock, and the fine measurement value.

2. The multi-channel second pulse measurement method according to claim 1, characterized in that, Injecting the edge under test within the period corresponding to the first second value into the delay chain inside the FPGA includes: The edge to be measured of each of the second pulse signals is connected to the carry input terminal of the first carry unit of the carry chain; The delay chain is composed of multiple cascaded carry units from the carry chain inside the FPGA; the total delay of the delay chain is not less than the period of the reference clock. Correspondingly, the states of each stage of the delay chain are latched based on the reference clock, and detailed measurement values ​​are determined according to the number of stages toggled in each stage of the state and the single-stage delay of the delay chain, including: Based on the reference clock, a trigger array connected to the output terminals of each carry unit is triggered, and the output level of each carry unit is latched to obtain a thermometer code composed of a first logic value and a second logic value; wherein, the first logic value is the output level of the carry unit at the latching time when the edge to be measured has been reached; The number of the first logic values ​​in the thermometer code is counted to determine the number of toggles. The product of the number of the flipping stages and the single-stage delay of the delay chain is determined to obtain the fine measurement value.

3. The multi-channel second pulse measurement method according to claim 1, characterized in that, The two sampling results include a first sampling result obtained based on the rising edge of the reference clock, and a second sampling result obtained based on the falling edge of the reference clock; Correspondingly, the state bit of the corresponding period is determined based on the two sampling results, including: When both the first sampling result and the second sampling result are low, the status bit of the corresponding period is determined to be the first value; When the first sampling result is low and the second sampling result is high, or when both the first sampling result and the second sampling result are high, the status bit of the corresponding period is determined to be the second value. When the first sampling result is high and the second sampling result is low, the status bit of the corresponding period is determined to be the first value; Wherein, the first value is 0 and the second value is 1.

4. The multi-channel second pulse measurement method according to claim 1, characterized in that, Also includes: When performing calibration, the reference second pulse signal is used as the first second pulse signal among the multiple second pulse signals to obtain the measurement result of the first channel, and the measurement result of the first channel is used as the reference calibration value; The reference second pulse signal is sequentially used as the second pulse signal of the other channels among the multiple second pulse signals by the selector, so as to obtain the measurement results of the other channels respectively, and the measurement results of the other channels are used as the channel calibration values ​​of the other channels. The calibration values ​​of the remaining channels are subtracted from the reference calibration value to obtain the calibration parameters of the remaining channels, and the calibration parameters are written into the memory. When a measurement is performed, the calibration parameters in the memory are read, and the difference between the measurement results of the remaining channels and the corresponding calibration parameters is determined to obtain the calibrated measurement results of the remaining channels. The measurement results of the first channel and the calibrated measurement results of the remaining channels are used as the measurement results of the second pulse signals of each calibrated channel.

5. The multi-channel second pulse measurement method according to claim 4, characterized in that, Also includes: Repeat the steps of obtaining the reference calibration value, the channel calibration value of each other channel, and the calibration parameter of each other channel a preset number of times to obtain the calibration parameter of each other channel a preset number of times; Determine the arithmetic mean of the preset number of calibration parameters for the remaining paths, and update the calibration parameters for the remaining paths. The updated calibration parameters are used to determine the post-calibration measurement results for the remaining channels.

6. The multi-channel second pulse measurement method according to claim 1, characterized in that, Determining the single-stage delay of the delay chain includes: Based on multiple temperature points, test edges with known delay values ​​are injected into the delay chain, and the state of each stage of the delay chain at each temperature point is recorded; Based on the number of flips in each state and the delay value, determine the single-stage delay corresponding to each temperature point, and establish the correspondence between temperature and single-stage delay. Collect the current temperature of the FPGA; Based on the correspondence, two temperature points adjacent to the current temperature are determined, and interpolation is performed on the single-stage delay corresponding to the two temperature points to obtain the single-stage delay at the current temperature; The single-stage delay at the current temperature is used as the single-stage delay of the delay chain.

7. The multi-channel second pulse measurement method according to claim 1, characterized in that, Each second pulse signal is sampled based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle, including: The multiple second pulse signals are respectively connected to the same clock domain in the FPGA driven by the reference clock; Multiple second pulse signals are sampled in parallel based on the same rising edge and the same falling edge of the reference clock to obtain the two sampling results of each second pulse signal in each period; Correspondingly, the method further includes: The measurement results of each second pulse signal are acquired in parallel within the same second pulse period; The difference between the measurement results of any two channels in the multi-channel second pulse signal is determined to obtain the time interval between the two channels.

8. A multi-channel second pulse measuring device, characterized in that, The device, applied to an FPGA, includes: The sampling module is used to sample each second pulse signal based on the rising and falling edges of the reference clock to obtain two sampling results for each cycle; The sorting module is used to determine the state bit of the corresponding period based on the two sampling results, and arrange the state bits in period order to obtain the state code; wherein, the state bit is a first value or a second value that indicates whether the edge to be tested has been reached. The statistical injection module is used to count the number of the first values ​​before the first second value in the status code to obtain a coarse count value, and inject the edge to be tested within the period corresponding to the first second value into the delay chain inside the FPGA; The latch determination module is used to latch the state of each stage of the delay chain based on the reference clock, and determine the detailed measurement value according to the number of flips in each stage of the state and the single-stage delay of the delay chain; The result determination module is used to determine the measurement results of each of the second pulse signals based on the coarse count value, the period of the reference clock, and the fine measurement value.

9. A multi-channel second pulse measuring device, characterized in that, include: Memory, used to store computer programs; An FPGA is used to implement the steps of the multi-channel second pulse measurement method as described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the multi-channel second pulse measurement method as described in any one of claims 1 to 7.

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