Semiconductor integrated circuit

Abstract

An embodiment of the present application provides a semiconductor integrated circuit capable of stably generating a constant voltage, which has a first transistor, a second transistor, a first resistance element, a second resistance element, a first compensation circuit, and a second compensation circuit. A base of the first transistor is connected to an output node. The second transistor has a different size from the first transistor. A base of the second transistor is connected to the output node. The first resistance element is connected between an emitter of the first transistor and an emitter of the second transistor. The second resistance element is connected between the emitter of the second transistor and a reference node. The first compensation circuit draws a first current from a first node. The first node is a node between the emitter of the first transistor and the first resistance element. The first current corresponds to a base current of the first transistor. The second compensation circuit draws a second current from a second node. The second node is a node between the emitter of the second transistor and the second resistance element. The second current corresponds to a base current of the second transistor.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-048028 (filed on March 24, 2025). This application includes all contents of the basic application by reference to that basic application. Technical Field

[0003] This implementation relates to semiconductor integrated circuits. Background Technology

[0004] In semiconductor integrated circuits, transistors are sometimes used to generate a constant voltage that should be used as a reference voltage. The goal in semiconductor integrated circuits is to generate a constant voltage stably. Summary of the Invention

[0005] Embodiments of the present invention provide a semiconductor integrated circuit capable of stably generating a constant voltage.

[0006] The semiconductor integrated circuit of this embodiment provides a semiconductor integrated circuit having a first transistor, a second transistor, a first resistive element, a second resistive element, a first compensation circuit, and a second compensation circuit. The base of the first transistor is connected to an output node. The second transistor has a different dimension than the first transistor. The base of the second transistor is connected to the output node. The first resistive element is connected between the emitter of the first transistor and the emitter of the second transistor. The second resistive element is connected between the emitter of the second transistor and a reference node. The first compensation circuit draws a first current from the first node. The first node is the node between the emitter of the first transistor and the first resistive element. The first current is equivalent to the base current of the first transistor. The second compensation circuit draws a second current from the second node. The second node is the node between the emitter of the second transistor and the second resistive element. The second current is equivalent to the base current of the second transistor. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the schematic configuration of the semiconductor integrated circuit according to the first embodiment.

[0008] Figure 2 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit in the first embodiment.

[0009] Figure 3 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the first embodiment.

[0010] Figure 4 This is a graph showing the current density dependence of the current amplification rate in the first embodiment according to temperature.

[0011] Figure 5This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit in the first variation of the first embodiment.

[0012] Figure 6 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the first variation of the first embodiment.

[0013] Figure 7 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit in the second variation of the first embodiment.

[0014] Figure 8 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the second variation of the first embodiment.

[0015] Figure 9 This is a circuit diagram showing the general configuration of the constant voltage generation circuit in the second embodiment.

[0016] Figure 10 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the second embodiment.

[0017] Figure 11 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit in the first variation of the second embodiment.

[0018] Figure 12 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the first variation of the second embodiment.

[0019] Figure 13 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit in the second variation of the second embodiment.

[0020] Figure 14 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the second variation of the second embodiment.

[0021] Figure 15 This is a circuit diagram showing the general configuration of the constant voltage generation circuit in the third embodiment.

[0022] Figure 16 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the third embodiment.

[0023] Figure 17 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit in the first variation of the third embodiment.

[0024] Figure 18 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the first variation of the third embodiment.

[0025] Figure 19This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit in the second variation of the third embodiment.

[0026] Figure 20 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit in the second variation of the third embodiment. Detailed Implementation

[0027] Hereinafter, the semiconductor integrated circuit according to the embodiments will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to these embodiments.

[0028] (First Implementation)

[0029] The semiconductor integrated circuit of the first embodiment uses transistors to generate a constant voltage that should be used as a reference voltage, but measures are implemented to stably generate the constant voltage.

[0030] Semiconductor integrated circuit 100 can be like Figure 1 It is constructed as shown. Figure 1 This is a circuit diagram showing the configuration of the semiconductor integrated circuit 100.

[0031] The semiconductor integrated circuit 100 has a power supply terminal Tvdd and a reference terminal Tg. The power supply terminal Tvdd is connected to an external power supply potential Vdd. The reference terminal Tg is connected to an external reference potential (e.g., ground potential) Vg.

[0032] The semiconductor integrated circuit 100 includes a constant voltage generation circuit 1. The constant voltage generation circuit 1 has a power supply node Nvdd, a reference node Ng, and an output node Nout. The power supply node Nvdd is connected to an external power supply potential Vdd via a power supply terminal Tvdd, and can receive the power supply potential Vdd from the outside via the power supply terminal Tvdd. The reference node Ng is connected to an external reference potential Vg via a reference terminal Tg, and can receive the reference potential Vg from the outside via the power supply terminal Tvdd.

[0033] The constant voltage generation circuit 1 uses the received power supply potential Vdd and the reference voltage Vg to generate a constant voltage Vbgr. The constant voltage generation circuit 1 may also include, for example, a bandgap reference (BGR) type voltage generation circuit to generate a constant voltage Vbgr corresponding to the bandgap of the semiconductor. The constant voltage generation circuit 1 may also output the constant voltage Vbgr as a reference voltage from the output node Nout.

[0034] The semiconductor integrated circuit 1 can be formed by mounting a constant voltage generation circuit 1 on a single chip, or by mounting a power supply circuit 2 containing the constant voltage generation circuit 1 on a chip, or by mounting the power supply circuit 2 containing the constant voltage generation circuit 1 and internal circuitry 3 on a chip. Figure 1The example illustrates a semiconductor integrated circuit 100 on a chip, which includes a power supply circuit 2 comprising a constant voltage generation circuit 1 and an internal circuit 3.

[0035] Figure 1 The power supply circuit 2 shown includes a constant voltage generation circuit 1. Power supply circuit 2 can use the constant voltage Vbgr generated by the constant voltage generation circuit 1 as a reference voltage to generate an internal power supply voltage Vint. Power supply circuit 2 can supply the internal power supply voltage Vint to the internal circuit 3. Therefore, the internal circuit 3 can operate using the internal power supply voltage Vint.

[0036] Constant voltage generator circuit 1 can, as Figure 2 It is constructed as shown. Figure 2 This is a circuit diagram showing the approximate structure of the constant voltage generating circuit 1.

[0037] The constant voltage generating circuit 1 includes transistor Q1, transistor Q2, transistor M6, resistor R1, resistor R2, load circuit 4, current mirror circuit 5, compensation circuit 6, and compensation circuit 7.

[0038] Transistor Q1 is connected between transistor Q2, resistor R1, load circuit 4, current mirror circuit 5, and compensation circuit 6. Transistor Q1 can also be an NPN bipolar transistor. The collector of transistor Q1 is connected to load circuit 4, the emitter is connected to resistor R1 and compensation circuit 6, and the base is connected to transistor Q2, current mirror circuit 5, and output node Nout.

[0039] Transistor Q2 is connected between transistor Q1, resistor R1, load circuit 4, current mirror circuit 5, and compensation circuit 7. Transistor Q2 can also be an NPN bipolar transistor. The collector of transistor Q2 is connected to load circuit 4, the emitter is connected to resistor R1 and compensation circuit 7, and the base is connected to transistor Q1, current mirror circuit 5, and output node Nout.

[0040] The size of transistor Q1 is n times the size of transistor Q2. n is any number greater than 1.

[0041] Transistor M6 is connected between transistor Q2, load circuit 4, and current mirror circuit 5. Transistor M6 can also be an N-type field-effect transistor. The drain of transistor M6 is connected to current mirror circuit 5, the gate is connected to the node between load circuit 4 and transistor Q2, and the source is connected to reference node Ng.

[0042] Resistor R1 is connected between transistors Q1 and Q2. When transistors Q1 and Q2 are NPN bipolar transistors, resistor R1 can be connected between the emitters of transistors Q1 and Q2. One end of resistor R1 is connected to the emitter of transistor Q1 and the compensation circuit 6, and the other end is connected to the emitter of transistor Q2, the node between resistor R1 and the compensation circuit 6.

[0043] Resistor R2 is connected between transistor Q2 and reference node Ng. When transistor Q2 is an NPN bipolar transistor, resistor R2 can also be connected between the emitter of transistor Q2 and reference node Ng. One end of resistor R2 is connected to the emitter of transistor Q2, the other end of resistor R1, and compensation circuit 7, while the other end is connected to reference node Ng.

[0044] Load circuit 4 is connected between power node Nvdd and transistors Q1 and Q2. When transistors Q1 and Q2 are NPN bipolar transistors, load circuit 4 is connected between power node Nvdd and the collectors of transistors Q1 and Q2.

[0045] Load circuit 4 can be as follows Figure 3 It is constructed as shown. Figure 3 This is a circuit diagram showing the detailed configuration of the constant voltage generating circuit 1.

[0046] Load circuit 4 has transistors M1 and M2. Transistor M1 is connected between power node Nvdd and transistor Q1. Transistor M2 is connected between power node Nvdd and transistor Q2. When transistors Q1 and Q2 are NPN bipolar transistors, transistor M1 is connected between power node Nvdd and the collector of transistor Q1. Transistor M2 is connected between power node Nvdd and transistor Q2.

[0047] Transistors M1 and M2 are connected by a current mirror. When transistors M1 and M2 are P-type field-effect transistors, the source of transistor M1 is connected to the power node Nvdd, and the gate and drain of transistor M1 are connected to the gate of transistor M2 and transistor Q2, respectively. The source of transistor M2 is connected to the power node Nvdd, its drain is connected to transistor Q2, and its gate is connected to the gate of transistor M1.

[0048] Load circuit 4 supplies equal current to transistors Q1 and Q2. When transistors Q1 and Q2 are NPN bipolar transistors, load circuit 4 supplies equal current to the collectors of transistors Q1 and Q2.

[0049] Here, since the size of transistor Q1 is n times the size of transistor Q2, the current density Jc1 of transistor Q1 is different from the current density Jc2 of transistor Q2, becoming approximately 1 / n times. Therefore, the base-emitter voltage of transistor Q1 and the base-emitter voltage of transistor Q2 are different from each other.

[0050] In contrast, by connecting a resistor R1 between the emitter of transistor Q1 and the emitter of transistor Q2, a voltage equivalent to the base-emitter voltage difference of transistors Q1 and Q2 can be generated across the resistor R1 when current flows through it.

[0051] Furthermore, when the ambient temperature changes, the base-emitter voltages of transistors Q1 and Q2 may change with temperature. For example, the base-emitter voltages of transistors Q1 and Q2 may change with a negative function of temperature.

[0052] On the other hand, such as Figure 4 As shown, the current amplification β of transistors Q1 and Q2 has both current density dependence and temperature dependence. Figure 4 This is a graph showing the dependence of current density on current amplification β at temperature. Figure 4 In the figure, the solid line represents the current density dependence of the current amplification β at temperature T1, the dashed line represents the current density dependence of the current amplification β at temperature T2 (> T1), and the single-dot dashed line represents the current density dependence of the current amplification β at temperature T3 (< T1).

[0053] For the case where the current density Jc1 of transistor Q1 and the current density Jc2 of transistor Q2 are different, the current amplification β of transistor Q1 and the current amplification β of transistor Q2 are as follows: Figure 4 As shown, the values ​​are different at each temperature T.

[0054] At the current ambient temperature T1, the current density dependence of the current amplification β varies as shown by the solid line. For a current density of Jc1, the current amplification of transistor Q1 becomes β11. For a current density of Jc2 (>Jc1), the current amplification of transistor Q2 is β12 (>β11).

[0055] At the current ambient temperature T2, the current density dependence of the current amplification β varies as shown by the dashed line. For a current density of Jc1, the current amplification of transistor Q1 is β21 (>β11). For a current density of Jc2 (>Jc1), the current amplification of transistor Q2 is β22 (>β21, >β12).

[0056] At the current ambient temperature T3, the current density dependence of the current amplification β varies as shown by the dashed line. For a current density of Jc1, the current amplification of transistor Q1 becomes β31 (<β11). For a current density of Jc2 (>Jc1), the current amplification of transistor Q2 becomes β32 (>β31, <β12).

[0057] That is, the current amplification of transistors Q1 and Q2 can vary with temperature as a positive function of increase. Correspondingly, the emitter currents of transistors Q1 and Q2 can vary with temperature as a positive function of increase.

[0058] Therefore, by connecting resistor R2 between the emitters of transistors Q1 and Q2 and the reference node Ng, the voltage across resistor R2 can vary with a positive function of temperature. Thus, it is expected that the temperature dependence of the base-emitter voltage of transistors Q1 and Q2, which varies with a negative function of temperature, can be reduced by utilizing the temperature dependence of the voltage across resistor R2.

[0059] However, in transistors Q1 and Q2, the collector current, which includes the emitter current, and the base current, exhibit different temperature characteristics. The collector current changes symmetrically with respect to the base-emitter voltage, while the base current changes asymmetrically with respect to the base-emitter voltage. Therefore, when the base current of transistors Q1 and Q2 flows through resistor R2, it may not be possible to completely reduce the temperature dependence.

[0060] In contrast, the constant voltage generation circuit 1 is configured with a compensation circuit 6, a current mirror circuit 5, and a compensation circuit 7. Base current IB1 is drawn from node N1, and base current IB2 is drawn from node N2. Node N1 is located between transistor Q1 and resistor R1. Node N2 is located between transistor Q2 and resistor R2.

[0061] Compensation circuit 6 is connected between power supply node Nvdd, node N1, node N3 and reference node Ng. Compensation circuit 6 generates a current IB1 equivalent to the base current IB1 of transistor Q1, and draws current IB1 out from nodes N1 and N3.

[0062] like Figure 3 As shown, the compensation circuit 6 includes a load circuit 61, a replica transistor Q11, a current mirror circuit 62, and a current mirror circuit 63.

[0063] Load circuit 61 is connected between power node Nvdd and replica transistor Q11. If replica transistor Q11 is an NPN bipolar transistor, load circuit 4 is connected between power node Nvdd and the collectors of transistors Q1 and Q2.

[0064] The load circuit 61 has a transistor M11. Transistor M11 is connected between the power supply node Nvdd and the replica transistor Q11. When the replica transistor Q11 is an NPN bipolar transistor, transistor M1 is connected between the power supply node Nvdd and the collector of the replica transistor Q11.

[0065] The replica transistor Q11 is connected between transistor Q2, load circuit 61, current mirror circuit 62, and reference node Ng. The replica transistor Q11 can also be an NPN bipolar transistor. The collector of the replica transistor Q11 is connected to load circuit 61, the emitter is connected to reference node Ng, and the base is connected to current mirror circuit 62.

[0066] The replica transistor Q11 is configured as a copy of transistor Q1. The dimensions of the replica transistor Q11 are approximately the same as those of transistor Q1. Consequently, a current IB1, equivalent to the base current IB1 of transistor Q1, flows through the base of the replica transistor Q11.

[0067] The current mirror circuit 62 is connected between the power supply node Nvdd, the replica transistor Q11, and the current mirror circuit 62. The input side of the current mirror circuit 62 is connected to the node between the load circuit 61 and the replica transistor Q11 via transistor M16, and the output side is connected to the current mirror circuit 62.

[0068] The current mirror circuit 62 includes transistors M13, M14, and M15. Transistors M13, M14, and M15 are interconnected via current mirrors. When the replica transistor Q11 is an NPN bipolar transistor and transistors M13, M14, and M15 are P-type field-effect transistors, the source of transistor M13 is connected to the power node Nvdd, its drain is connected to the base of the replica transistor Q11, and its gate is connected to the gates of transistors M14 and M15. The source of transistor M14 is connected to the power node Nvdd, and its gate / drain is connected to the gates of transistors M13, M15, and M16. The source of transistor M15 is connected to the power node Nvdd, its drain is connected to the current mirror circuit 63, and its gate is connected to the gates of transistors M13 and M14.

[0069] The dimensions of transistors M13, M14, and M15 are approximately the same. Correspondingly, the mirror ratio is approximately 1.

[0070] In addition, the gate of transistor M16 is connected to the drain of transistor M11, and the source is connected to the reference node Ng, enabling it to function as an inverting amplifier.

[0071] The loop comprising the drain of transistor M16 → drain of transistor M14 → gate of transistor M14 → gate of transistor M13 → drain of transistor M13 → base of replica transistor Q11 → collector of replica transistor Q11 → gate of transistor M16 → drain of transistor M16 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 61 is applied to the gate of transistor M16. Correspondingly, the drain current flowing through transistor M16 is replicated from the drain of transistor M14 to the drain of transistor M13 at approximately a mirror ratio of 1. The replicated current flows into the base of replica transistor Q11, but because the load circuit 61 supplies current Ic, feedback is applied such that the drain current flowing through transistor M16 becomes IB1.

[0072] The current mirror circuit 62 receives the base current IB1 of the replica transistor Q11 on the input side, replicates the current IB1 to the output side with a mirror ratio of approximately 1, and supplies the current IB1 to the current mirror circuit 63 from the output side.

[0073] The input side of current mirror circuit 63 is connected to the output side of current mirror circuit 62. The output side is connected in parallel with resistor R1 relative to node N1 and in parallel with compensation circuit 7 relative to node N3. Node N3 is positioned between current mirror circuit 5 and compensation circuit 7.

[0074] The current mirror circuit 63 includes transistors M17, M18, and M19. Transistors M17, M18, and M19 are interconnected via current mirrors. When transistors Q1 and Q2 are NPN bipolar transistors and transistors M17, M18, and M19 are N-type field-effect transistors, the source of transistor M17 is connected to the reference node Ng, and its gate / drain is connected to the gates of transistors M18 and M19. The source of transistor M18 is connected to the reference node Ng, its drain is connected to node N1, and its gate is connected to the gates of transistors M17 and M18. The source of transistor M19 is connected to the reference node Ng, its drain is connected to node N3, and its gate is connected to the gates of transistors M17 and M18.

[0075] The dimensions of transistor M17, transistor M18, and transistor M19 are approximately equal. Correspondingly, the mirror image ratio is approximately 1.

[0076] The current mirror circuit 63 receives current IB1 on the input side, replicates current IB1 to the output side with a mirror ratio of approximately 1, and allows current IB1 to flow on the output side. Thus, the current mirror circuit 63 draws base current IB1 from node N1 and base current IB1 from node N3.

[0077] The current mirror circuit 5 is connected between transistors Q1 and Q2 and the compensation circuit 7. When transistors Q1 and Q2 are NPN bipolar transistors, the input side of the current mirror circuit 5 is connected to the node between the load circuit 4 and transistor Q2 via transistor M6, and the output side is connected to the compensation circuit 7.

[0078] like Figure 3 As shown, the current mirror circuit 5 includes transistors M3, M4, and M5. Transistors M3, M4, and M5 are interconnected via current mirrors. When transistors Q1 and Q2 are NPN bipolar transistors and transistors M3, M4, and M5 are P-type field-effect transistors, the source of transistor M3 is connected to the power node Nvdd, its drain is connected to the bases of transistors Q1 and Q2, and its gate is connected to the gates of transistors M4 and M5. The source of transistor M4 is connected to the power node Nvdd, its drain is connected to the compensation circuit 7, and its gate is connected to the gates of transistors M3 and M4. The source of transistor M5 is connected to the power node Nvdd, and its gate / drain is connected to the gates of transistors M3, M4, and M6.

[0079] The dimensions of transistors M3, M4, and M5 are approximately the same. Correspondingly, the mirror image ratio is approximately 1.

[0080] In addition, the gate of transistor M6 is connected to the drain of transistor M2, and the source is connected to the reference node Ng, enabling it to function as an inverting amplifier.

[0081] The loop containing the drain of transistor M6 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → gate of transistor M6 → drain of transistor M6 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the gate of transistor M6. Correspondingly, the drain current flowing through transistor M6 is replicated from the drain of transistor M5 to the drain of transistor M3 with approximately a mirror ratio of 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies equal current to transistors Q1 and Q2, feedback is applied so that the drain current flowing through transistor M6 becomes IB1 + IB2.

[0082] The current mirror circuit 5 receives the sum of the base currents IB of transistor Q1 and IB of transistor Q2 at the input side (drain of transistor M5), and replicates the current IB1+IB2 at the output side (drain of transistor M4) with a mirror ratio of approximately 1, and supplies the current IB1+IB2 from the output side to the compensation circuit 7.

[0083] Figure 2 The compensation circuit 7 shown is connected between nodes N1, N2, N3 and the reference node Ng.

[0084] like Figure 3 As shown, the compensation circuit 7 includes a current mirror circuit 73. The input side of the current mirror circuit 73 is connected to the output side of the current mirror circuit 5 via node N3, and is connected in parallel with the current mirror circuit 63 relative to node N3. The output side is connected in parallel with the resistor element R2 relative to node N2.

[0085] The current mirror circuit 73 includes transistors M7 and M9. Transistors M7 and M9 are interconnected via a current mirror connection. When transistors Q1 and Q2 are NPN bipolar transistors and transistors M7, M8, and M9 are N-type field-effect transistors, the source of transistor M7 is connected to the reference node Ng, and its gate / drain is connected to the gate of transistor M9 and node N3. The source of transistor M9 is connected to the reference node Ng, its drain is connected to node N2, and its gate is connected to the gate of transistor M7.

[0086] The dimensions of transistor M7 are approximately the same as those of transistor M9. Correspondingly, the mirror image ratio is approximately 1.

[0087] As described above, the current mirror circuit 63 draws base current IB1 from node N1 and base current IB2 from node N3. Current IB1 + IB2 flows into node N3 from current mirror circuit 5, but current mirror circuit 63 draws current IB1 out of node N3, thus supplying current IB2 to current mirror circuit 73.

[0088] The current mirror circuit 73 receives current IB2 on the input side, replicates current IB2 to the output side with a mirror ratio of approximately 1, and allows current IB2 to flow on the output side. Thus, the current mirror circuit 73 draws the base current IB2 from node N2.

[0089] As described above, in the first embodiment, in the constant voltage generation circuit 1 of the semiconductor integrated circuit 100, the compensation circuit 6 generates a current IB1 equivalent to the base current of transistor Q1 and draws it out from node N1. Furthermore, the current mirror circuit 5 supplies the sum of the currents IB1+IB2 received from the bases of transistors Q1 and Q2 to node N3, the compensation circuit 6 draws current IB1 out from node N3, and the remaining current IB2 is supplied to the compensation circuit 7. The compensation circuit 7 replicates the received current IB2 to the output side with a mirror ratio of approximately 1, and draws the base current IB2 out from node N2 on the output side. Thus, the influence of the temperature dependence of the base currents of transistors Q1 and Q2 can be suppressed, and the influence of the temperature dependence of the base-emitter voltage of transistors Q1 and Q2, which varies with temperature as a function of temperature, can be eliminated by the temperature dependence of the voltage across the resistive element R2, which varies with temperature as a function of ... As a result, the voltage between the collectors of transistors Q1 and Q2 and the reference node Ng can be maintained at a relatively constant relative to changes in ambient temperature, and the constant voltage Vbgr output from the output node Nout can be maintained at a relatively constant.

[0090] Furthermore, in the first embodiment, in the constant voltage generation circuit 1 of the semiconductor integrated circuit 100, the compensation circuit 6 draws out a current IB1 corresponding to the base current of transistor Q1, and the compensation circuit 7 draws out a current IB2 corresponding to the base current of transistor Q2. Thus, while suppressing the effects of differences in base currents IB1 and IB2 corresponding to the size differences of transistors Q1 and Q2, the temperature dependence of the voltage across the resistive element R2, which varies with a positive function of temperature, can be utilized to eliminate the influence of the temperature dependence of the base / emitter voltage of transistors Q1 and Q2, which varies with a negative function of temperature.

[0091] Furthermore, as a first variation of the first embodiment, in the constant voltage generation circuit 201 of the semiconductor integrated circuit 200, for example, when transistors Q1 and Q2 are NPN type bipolar transistors, measures can also be implemented to stably equalize the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0092] like Figure 5 and Figure 6 As shown, the constant voltage generation circuit 201 of the semiconductor integrated circuit 200 may also have a compensation circuit 208. Figure 5 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit 201 in the first variation of the implementation. Figure 6 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 201 in the first modified embodiment.

[0093] Figure 5 The compensation circuit 208 shown is connected between the load circuit 4, transistors Q1 and Q2, and transistor M6. The compensation circuit 208 receives the voltages from the transistor Q1 side and the transistor Q2 side from the load circuit 4, respectively, and supplies the load circuit 4 with a control signal corresponding to the difference between the currents on the transistor Q1 side and the currents on the transistor Q2 side.

[0094] like Figure 6 As shown, the compensation circuit 208 includes a differential amplifier 209. The non-inverting input terminal 209a of the differential amplifier 209 is connected to node N11, the inverting input terminal 209b is connected to node N12, and the output terminal 209c is connected to the gates of transistors M1 and M2. Node N11 is connected between the load circuit 4 and transistor Q1. Node N12 is connected between the load circuit 4 and transistor Q2.

[0095] When transistors M1 and M2 are P-type field-effect transistors and transistors Q1 and Q2 are NPN bipolar transistors, node N11 is connected between the drain of transistor M1 and the collector of transistor Q1. Node N12 is connected between the drain of transistor M2 and the collector of transistor Q2. Transistors M1 and M2 can also be considered as being connected via a current mirror through differential amplifier 209.

[0096] Differential amplifier 209 receives the voltage of node N11 at the non-inverting input terminal 209a and the voltage of node N12 at the inverting input terminal 209b. Differential amplifier 209 outputs a voltage from the output terminal 209c corresponding to the difference between the voltages of node N11 and node N12. Differential amplifier 209 can supply this voltage, corresponding to the difference between the voltages of node N11 and node N12, as a control signal to the load circuit 4.

[0097] Therefore, the compensation circuit 208 can adjust the load circuit 4 to make the current on the transistor Q1 side equal to the current on the transistor Q2 side. Based on the adjustment result, the compensation circuit 208 supplies the current on the transistor Q1 side to the transistor Q1 and the current on the transistor Q2 side to the transistor Q2.

[0098] Furthermore, the loop comprising the drain of transistor M6 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → gate of transistor M6 → drain of transistor M6 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the gate of transistor M6, and correspondingly, the drain current flowing through transistor M6 is replicated from the drain of transistor M5 to the drain of transistor M3 at approximately a mirror ratio of 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies current Ic to transistors Q1 and Q2 respectively, feedback is applied such that the drain current flowing through transistor M6 becomes IB1 + IB2. This is the same as in the first embodiment.

[0099] In this way, the compensation circuit 208 can perform compensation to ensure that the load circuit 4 stably supplies equal current to transistors Q1 and Q2. This allows the collector current IC of transistor Q1 and the collector current IC of transistor Q2 to be stably equalized.

[0100] Alternatively, as a second variation of the first embodiment, in the constant voltage generation circuit 301 of the semiconductor integrated circuit 300, for example when transistors Q1 and Q2 are NPN bipolar transistors, measures can be implemented to suppress the effect of the difference between the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0101] like Figure 7 and Figure 8 As shown, the constant voltage generation circuit 301 of the semiconductor integrated circuit 300 may also have a compensation circuit 308. Figure 7 This is a circuit diagram showing a schematic configuration of the constant voltage generating circuit 301 in the second variation of the implementation. Figure 8 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 301 in the second variation of the implementation.

[0102] Figure 7 The compensation circuit 308 shown is connected between the load circuit 4, the current mirror circuit 5, and transistors Q1 and Q2. The compensation circuit 308 receives the voltages from the load circuit 4 on the side of transistor Q1 and the side of transistor Q2, respectively, and supplies the current mirror circuit 5 with a control signal corresponding to the difference between the currents on the side of transistor Q1 and the side of transistor Q2.

[0103] like Figure 8As shown, the compensation circuit 308 includes a differential amplifier 309. The non-inverting input terminal 309a of the differential amplifier 309 is connected to node N11, the inverting input terminal 309b is connected to node N12, and the output terminal 309c is connected to the drain of transistor M5. Node N11 is connected between the load circuit 4 and transistor Q1. Node N12 is connected between the load circuit 4 and transistor Q2.

[0104] When transistors M1 and M2 are P-type field-effect transistors and transistors Q1 and Q2 are NPN type bipolar transistors, node N11 is connected between the drain of transistor M1 and the collector of transistor Q1. Node N12 is connected between the drain of transistor M2 and the collector of transistor Q2.

[0105] The differential amplifier 309 receives the voltage of node N11 at the non-inverting input terminal 309a and the voltage of node N12 at the inverting input terminal 309b. The differential amplifier 309 outputs a voltage from the output terminal 309c corresponding to the difference between the voltages of node N11 and node N12. The differential amplifier 309 can supply this voltage, corresponding to the difference between the voltages of node N11 and node N12, as a control signal to the current mirror circuit 5.

[0106] Therefore, the current mirror circuit 5 replicates the correction current corresponding to the difference between the collector current on the transistor Q1 side and the collector current on the transistor Q2 side to the input side and the output side with a mirror ratio of approximately 1. The correction current is supplied from the input side to the transistors Q1 and Q2, and from the output side to the compensation circuit 6.

[0107] Furthermore, the loop comprising the output node 309c of differential amplifier 309 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → input node 309b of differential amplifier 309 → output node 309c of differential amplifier 309 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the input node 309b of differential amplifier 309. Correspondingly, the current flowing through the output node 309c of differential amplifier 309 is replicated from the drain of transistor M5 to the drain of transistor M3 with a mirror ratio of approximately 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies current Ic to transistors Q1 and Q2 respectively, feedback is applied such that the drain current flowing through transistor M6 becomes IB1 + IB2. This is the same as in the first embodiment.

[0108] Thus, in the compensation circuit 308, the current mirror circuit 5 directs the correction current corresponding to the difference between the collector current on the transistor Q1 side and the collector current on the transistor Q2 side to the input and output sides of the current mirror circuit 5. This corrects the current IB1+IB2 flowing through the input and output sides of the current mirror circuit 5, and suppresses the influence of the difference between the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0109] (Second Implementation)

[0110] Next, the semiconductor integrated circuit according to the second embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first embodiment.

[0111] In the first embodiment, a configuration is shown in which current IB2 is obtained by generating current IB1 and subtracting current IB1 from current IB1+IB2. However, in the second embodiment, a configuration is shown in which current IB1 is obtained by generating current IB2 and subtracting current IB2 from current IB1+IB2.

[0112] Semiconductor integrated circuit 100i can be like Figure 9 It is constructed as shown. Figure 9 This is a circuit diagram showing the approximate structure of the semiconductor integrated circuit 100i.

[0113] Semiconductor integrated circuit 100i replaces compensation circuit 6 and compensation circuit 7 (see reference) Figure 2 It has compensation circuit 6i and compensation circuit 7i.

[0114] The compensation circuit 7i is connected between the power supply node Nvdd, node N2, node N3, and reference node Ng. The compensation circuit 7i generates a current IB2 equivalent to the base current IB2 of transistor Q2, and draws the current IB2 out from nodes N2 and N3.

[0115] like Figure 10 As shown, the compensation circuit 7i includes a load circuit 71i, a replica transistor Q12, a current mirror circuit 72i, and a current mirror circuit 73i. Figure 10 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 1i in the second embodiment.

[0116] Load circuit 71i is connected between power node Nvdd and replica transistor Q12. When replica transistor Q12 is an NPN bipolar transistor, load circuit 71i is connected between power node Nvdd and the collector of replica transistor Q12.

[0117] The load circuit 71i has a transistor M31. Transistor M31 is connected between the power node Nvdd and the replica transistor Q12. When the replica transistor Q12 is an NPN bipolar transistor, transistor M31 is connected between the power node Nvdd and the collector of the replica transistor Q12.

[0118] The replica transistor Q12 is connected between the load circuit 71i, the current mirror circuit 72i, and the reference node Ng. The replica transistor Q12 can also be an NPN bipolar transistor. The collector of the replica transistor Q12 is connected to the load circuit 71i, the emitter is connected to the reference node Ng, and the base is connected to the current mirror circuit 72i.

[0119] The replica transistor Q12 is configured as a copy of transistor Q2. The dimensions of the replica transistor Q12 are approximately the same as those of transistor Q2. Consequently, a current IB2, equivalent to the base current IB2 of transistor Q2, flows through the base of the replica transistor Q12.

[0120] The current mirror circuit 72i is connected between the power node Nvdd and the replica transistor Q12 and the current mirror circuit 73i. The input side of the current mirror circuit 72i is connected to the base of the replica transistor Q12, and the output side is connected to the current mirror circuit 73i.

[0121] The current mirror circuit 72i includes transistors M33, M34, and M35. Transistors M33, M34, and M35 are interconnected via current mirrors. When the replica transistor Q12 is an NPN bipolar transistor and transistors M33, M34, and M35 are P-type field-effect transistors, the source of transistor M33 is connected to the power node Nvdd, its drain is connected to the base of the replica transistor Q12, and its gate is connected to the gates of transistors M34 and M35. The source of transistor M34 is connected to the power node Nvdd, and its gate / drain is connected to the gates of transistors M33, M35, and M36. The source of transistor M35 is connected to the power node Nvdd, its drain is connected to the current mirror circuit 73i, and its gate is connected to the gates of transistors M33 and M34.

[0122] The dimensions of transistor M33, transistor M34, and transistor M35 are approximately the same. Correspondingly, the mirror image ratio is approximately 1.

[0123] In addition, the gate of transistor M36 is connected to the drain of transistor M31, and the source is connected to the reference node Ng, enabling it to function as an inverting amplifier.

[0124] The loop comprising the drain of transistor M36 → drain of transistor M34 → gate of transistor M34 → gate of transistor M33 → drain of transistor M33 → base of replica transistor Q12 → collector of replica transistor Q12 → gate of transistor M36 → drain of transistor M36 functions as a feedback loop. For example, when a voltage corresponding to the current Ic from the load circuit 71i is applied to the gate of transistor M36, the drain current flowing through transistor M36 is replicated from the drain of transistor M34 to the drain of transistor M33 at a mirror ratio of approximately 1. The replicated current flows into the base of replica transistor Q12, but because the load circuit 71i supplies current Ic, feedback is applied such that the drain current flowing through transistor M36 becomes IB2.

[0125] The current mirror circuit 72i receives the base current IB2 of the replica transistor Q12 on the input side (drain of transistor M34), replicates the current IB2 to the output side (drain of transistor M35) with a mirror ratio of approximately 1, and supplies the current IB2 to the current mirror circuit 73i from the output side.

[0126] The input side of current mirror circuit 73i is connected to the output side of current mirror circuit 72i. The output side is connected in parallel with resistor R2 relative to node N2, and in parallel with compensation circuit 6i relative to node N3. Node N3 is configured between current mirror circuit 5 and compensation circuit 6i.

[0127] The current mirror circuit 73i includes transistors M37, M29, and M39. Transistors M37, M29, and M39 are interconnected via current mirrors. When transistors M37, M29, and M39 are N-type field-effect transistors, the source of transistor M37 is connected to the reference node Ng, and its gate / drain is connected to the gates of transistors M38 and M39. The source of transistor M29 is connected to the reference node Ng, its drain is connected to node N2, and its gate is connected to the gates of transistors M37 and M29. The source of transistor M39 is connected to the reference node Ng, its drain is connected to node N3, and its gate is connected to the gates of transistors M37 and M29.

[0128] The dimensions of transistor M37, transistor M29, and transistor M39 are approximately equal. Correspondingly, the mirror image ratio is approximately 1.

[0129] The current mirror circuit 73i receives current IB2 on the input side and replicates it to the output side with a mirror ratio of approximately 1, allowing current IB2 to flow on the output side. Thus, the current mirror circuit 73i draws base current IB2 from node N2 and base current IB2 from node N3.

[0130] The current mirror circuit 5 is connected between transistors Q1 and Q2 and compensation circuit 6i. When transistors Q1 and Q2 are NPN bipolar transistors, the input side of the current mirror circuit 5 is connected to the node between the load circuit 4 and transistor Q2 via transistor M6, and the output side is connected to compensation circuit 6i.

[0131] like Figure 10 As shown, the current mirror circuit 5 includes transistors M3, M4, and M5. Transistors M3, M4, and M5 are interconnected via current mirrors. When transistors Q1 and Q2 are NPN bipolar transistors and transistors M3, M4, and M5 are P-type field-effect transistors, the source of transistor M3 is connected to the power node Nvdd, its drain is connected to the bases of transistors Q1 and Q2, and its gate is connected to the gates of transistors M4 and M5. The source of transistor M4 is connected to the power node Nvdd, its drain is connected to the compensation circuit 6i, and its gate is connected to the gates of transistors M3 and M4. The source of transistor M5 is connected to the power node Nvdd, and its gate / drain is connected to the gates of transistors M3, M4, and M6.

[0132] The dimensions of transistors M3, M4, and M5 are approximately the same. Correspondingly, the mirror image ratio is approximately 1.

[0133] In addition, the gate of transistor M6 is connected to the drain of transistor M2, and the source is connected to the reference node Ng, enabling it to function as an inverting amplifier.

[0134] The loop containing the drain of transistor M6 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → gate of transistor M6 → drain of transistor M6 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the gate of transistor M6. Correspondingly, the drain current flowing through transistor M6 is replicated from the drain of transistor M5 to the drain of transistor M3 with approximately a mirror ratio of 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies equal current to transistors Q1 and Q2, feedback is applied so that the drain current flowing through transistor M6 becomes IB1 + IB2.

[0135] The current mirror circuit 5 receives the sum of the base current IB1 of transistor Q1 and the base current IB2 of transistor Q2 on the input side, and replicates the current IB1+IB2 to the output side with a mirror ratio of approximately 1, and supplies the current IB1+IB2 to the compensation circuit 6i from the output side.

[0136] Figure 9 The compensation circuit 6i shown is connected between nodes N1, N3 and the reference node Ng.

[0137] like Figure 10 As shown, the compensation circuit 6i includes a current mirror circuit 63i. The input side of the current mirror circuit 63i is connected to the output side of the current mirror circuit 5 via node N3, and is connected in parallel with the current mirror circuit 73i relative to node N3. The output side is connected in parallel with the resistive element R1 relative to node N1.

[0138] The current mirror circuit 63i includes transistors M27 and M38. Transistors M27 and M38 are interconnected via current mirroring. When transistors Q1 and Q2 are NPN bipolar transistors and transistors M27 and M38 are N-type field-effect transistors, the source of transistor M27 is connected to the reference node Ng, and its gate / drain is connected to the gate of transistor M38 and node N3. The source of transistor M38 is connected to the reference node Ng, its drain is connected to node N1, and its gate is connected to the gate of transistor M27.

[0139] The dimensions of transistor M27 are approximately the same as those of transistor M38. Correspondingly, the mirror image ratio is approximately 1.

[0140] As described above, the current mirror circuit 73i draws base current IB2 from node N2 and base current IB2 from node N3. Current IB1+IB2 flows into node N3 from current mirror circuit 5, but current mirror circuit 73i draws current IB2 out from node N3, thus supplying current IB1 to current mirror circuit 63i.

[0141] The current mirror circuit 63i receives current IB1 on the input side, replicates current IB1 to the output side with a mirror ratio of approximately 1, and allows current IB1 to flow on the output side. Thus, the current mirror circuit 63i draws the base current IB1 from node N1.

[0142] As described above, in the second embodiment, in the constant voltage generation circuit 1i of the semiconductor integrated circuit 100i, the compensation circuit 7i generates a current IB2 equivalent to the base current of transistor Q2 and draws it out from node N2. Furthermore, the current mirror circuit 5 supplies the sum of the currents IB1+IB2 received from the bases of transistors Q1 and Q2 to node N3, the compensation circuit 7i draws the current IB2 out from node N3, and the remaining current IB1 is supplied to the compensation circuit 6i. The compensation circuit 6i replicates the received current IB1 to the output side with a mirror ratio of approximately 1, and draws the base current IB1 from node N1 at the output side. Therefore, the influence of the temperature dependence of the base currents of transistors Q1 and Q2 can be suppressed, and the influence of the temperature dependence of the base-emitter voltage of transistors Q1 and Q2, which varies with temperature as a function of temperature, can be reduced by utilizing the temperature dependence of the voltage across the resistive element R2, which varies with temperature as a function of ... As a result, the voltage between the collectors of transistors Q1 and Q2 and the reference node Ng can be maintained at a relatively constant relative to changes in ambient temperature, and the constant voltage Vbgr output from the output node Nout can be maintained at a relatively constant.

[0143] Furthermore, in the second embodiment, in the constant voltage generation circuit 1i of the semiconductor integrated circuit 100i, the compensation circuit 6i draws out a current IB1 corresponding to the base current of Q1, and the compensation circuit 7i draws out a current IB2 corresponding to the base current of transistor Q2. This suppresses the effects of differences in base currents IB1 and IB2 corresponding to the size differences of transistors Q1 and Q2, and reduces the influence of the temperature dependence of the base / emitter voltage of transistors Q1 and Q2, which varies with temperature as a function of temperature, by utilizing the temperature dependence of the voltage across the resistive element R2, which varies with temperature as a function of temperature increases positively.

[0144] Furthermore, as a first variation of the second embodiment, in the constant voltage generation circuit 201i of the semiconductor integrated circuit 200i, for example, when transistors Q1 and Q2 are NPN type bipolar transistors, measures can also be implemented to stably equalize the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0145] like Figure 11 and Figure 12 As shown, the constant voltage generation circuit 201i of the semiconductor integrated circuit 200i may also have a compensation circuit 208. Figure 11 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 201i in the first variation of the second embodiment. Figure 12 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 201i in the first variation of the second embodiment.

[0146] Figure 11 The compensation circuit 208 shown is connected between the load circuit 4, transistors Q1 and Q2, and transistor M6. The compensation circuit 208 receives the voltages from the transistor Q1 side and the transistor Q2 side from the load circuit 4, respectively, and supplies the load circuit 4 with a control signal corresponding to the difference between the currents on the transistor Q1 side and the currents on the transistor Q2 side.

[0147] like Figure 12 As shown, the compensation circuit 208 includes a differential amplifier 209. The non-inverting input terminal 209a of the differential amplifier 209 is connected to node N11, the inverting input terminal 209b is connected to node N12, and the output terminal 209c is connected to the gates of transistors M1 and M2. Node N11 is connected between the load circuit 4 and transistor Q1. Node N12 is connected between the load circuit 4 and transistor Q2.

[0148] When transistors M1 and M2 are P-type field-effect transistors and transistors Q1 and Q2 are NPN bipolar transistors, node N11 is connected between the drain of transistor M1 and the collector of transistor Q1. Node N12 is connected between the drain of transistor M2 and the collector of transistor Q2. Transistors M1 and M2 can also be considered as being connected via a current mirror through differential amplifier 209.

[0149] Differential amplifier 209 receives the voltage of node N11 at the non-inverting input terminal 209a and the voltage of node N12 at the inverting input terminal 209b. Differential amplifier 209 outputs a voltage from the output terminal 209c corresponding to the difference between the voltages of node N11 and node N12. Differential amplifier 209 can supply this voltage, corresponding to the difference between the voltages of node N11 and node N12, as a control signal to the load circuit 4.

[0150] Therefore, the compensation circuit 208 can adjust the load circuit 4 to make the current on the transistor Q1 side equal to the current on the transistor Q2 side. Based on the adjustment result, the compensation circuit 208 supplies the current on the transistor Q1 side to the transistor Q1 and the current on the transistor Q2 side to the transistor Q2.

[0151] Furthermore, the loop comprising the drain of transistor M36 → drain of transistor M34 → gate of transistor M34 → gate of transistor M33 → drain of transistor M33 → base of replica transistor Q11 → collector of replica transistor Q11 → gate of transistor M36 → drain of transistor M36 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 61 is applied to the gate of transistor M36, and correspondingly, the drain current flowing through transistor M36 is replicated from the drain of transistor M34 to the drain of transistor M33 at a mirror ratio of approximately 1. The replicated current flows into the base of replica transistor Q11, but because the load circuit 61 supplies current Ic, feedback is applied such that the drain current flowing through transistor M36 becomes IB2. This is the same as in the second embodiment.

[0152] Furthermore, the loop comprising the drain of transistor M6 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → gate of transistor M6 → drain of transistor M6 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the gate of transistor M6, and correspondingly, the drain current flowing through transistor M6 is replicated from the drain of transistor M5 to the drain of transistor M3 with a mirror ratio of approximately 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies equal current to transistors Q1 and Q2, feedback is applied so that the drain current flowing through transistor M6 becomes IB1 + IB2. This is the same as in the second embodiment.

[0153] In this way, the compensation circuit 208 can perform compensation to ensure that the load circuit 4 stably supplies equal current to transistors Q1 and Q2. This allows the collector current IC of transistor Q1 and the collector current IC of transistor Q2 to be stably equalized.

[0154] Alternatively, as a second variation of the second embodiment, in the constant voltage generation circuit 301i of the semiconductor integrated circuit 300i, for example when transistors Q1 and Q2 are NPN bipolar transistors, measures can be implemented to suppress the effect of the difference between the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0155] like Figure 13 and Figure 14 As shown, the constant voltage generation circuit 301i of the semiconductor integrated circuit 300i may also have a compensation circuit 308. Figure 13 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 301i in the second variation of the second embodiment. Figure 14This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 301i in the second variation of the second embodiment.

[0156] Figure 13 The compensation circuit 308 shown is connected between the load circuit 4, the current mirror circuit 5, and transistors Q1 and Q2. The compensation circuit 308 receives the voltages from the load circuit 4 on the side of transistor Q1 and the side of transistor Q2, respectively, and supplies the current mirror circuit 5 with a control signal corresponding to the difference between the currents on the side of transistor Q1 and the side of transistor Q2.

[0157] like Figure 14 As shown, the compensation circuit 308 includes a differential amplifier 309. The non-inverting input terminal 309a of the differential amplifier 309 is connected to node N11, the inverting input terminal 309b is connected to node N12, and the output terminal 309c is connected to the drain of transistor M5. Node N11 is connected between the load circuit 4 and transistor Q1. Node N12 is connected between the load circuit 4 and transistor Q2.

[0158] When transistors M1 and M2 are P-type field-effect transistors and transistors Q1 and Q2 are NPN type bipolar transistors, node N11 is connected between the drain of transistor M1 and the collector of transistor Q1. Node N12 is connected between the drain of transistor M2 and the collector of transistor Q2.

[0159] The differential amplifier 309 receives the voltage of node N11 at the non-inverting input terminal 309a and the voltage of node N12 at the inverting input terminal 309b. The differential amplifier 309 outputs a voltage from the output terminal 309c corresponding to the difference between the voltages of node N11 and node N12. The differential amplifier 309 can supply this voltage, corresponding to the difference between the voltages of node N11 and node N12, as a control signal to the current mirror circuit 5.

[0160] Therefore, the current mirror circuit 5 replicates the correction current corresponding to the difference between the collector current on the transistor Q1 side and the collector current on the transistor Q2 side to the input side and the output side with a mirror ratio of approximately 1. The correction current is supplied from the input side to the transistors Q1 and Q2, and from the output side to the compensation circuit 6.

[0161] Furthermore, the loop comprising the drain of transistor M36 → drain of transistor M34 → gate of transistor M34 → gate of transistor M33 → drain of transistor M33 → base of replica transistor Q11 → collector of replica transistor Q11 → gate of transistor M36 → drain of transistor M36 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 61 is applied to the gate of transistor M36, and correspondingly, the drain current flowing through transistor M36 is replicated from the drain of transistor M34 to the drain of transistor M33 at a mirror ratio of approximately 1. The replicated current flows into the base of replica transistor Q11, but because the load circuit 61 supplies current Ic, feedback is applied such that the drain current flowing through transistor M36 becomes IB2. This is the same as in the second embodiment.

[0162] Additionally, the loop comprising the output node 309c of differential amplifier 309 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → input node 309b of differential amplifier 309 → output node 309c of differential amplifier 309 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the input node 309b of differential amplifier 309. Correspondingly, the current flowing through the output node 309c of differential amplifier 309 is replicated from the drain of transistor M5 to the drain of transistor M3 with a mirror ratio of approximately 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies equal current to transistors Q1 and Q2, feedback is applied so that the current flowing through the output node 309c of differential amplifier 309 becomes IB1 + IB2. This is the same as in the second embodiment.

[0163] Thus, in the compensation circuit 308, the current mirror circuit 5 directs the correction current corresponding to the difference between the collector current on the transistor Q1 side and the collector current on the transistor Q2 side to the input and output sides of the current mirror circuit 5. This corrects the current IB1+IB2 flowing through the input and output sides of the current mirror circuit 5, and suppresses the influence of the difference between the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0164] (Third Implementation)

[0165] Next, the semiconductor integrated circuit according to the third embodiment will be described. Hereinafter, the description will focus on the parts that differ from the first and second embodiments.

[0166] In the first embodiment, a configuration is shown in which current IB2 is obtained by generating current IB1 and subtracting current IB1 from current IB1+IB2. In the second embodiment, a configuration is shown in which current IB1 is obtained by generating current IB2 and subtracting current IB2 from current IB1+IB2. However, in the third embodiment, a configuration is shown in which currents IB1 and IB2 are generated separately.

[0167] Semiconductor integrated circuit 100j can be like Figure 15 It is constructed as shown. Figure 15 This is a circuit diagram showing the approximate structure of semiconductor integrated circuit 100j.

[0168] Semiconductor integrated circuit 100j has a current mirror circuit 5j and a compensation circuit 7j to replace the current mirror circuit 5 and the compensation circuit 7 (see reference). Figure 2 ).

[0169] The current mirror circuit 5j is connected between transistors Q1 and Q2 and the reference node Ng. When transistors Q1 and Q2 are NPN bipolar transistors, the input side of the current mirror circuit 5j is connected to the base of transistors Q1 and Q2, and the output side is connected to the reference node Ng.

[0170] like Figure 16 As shown, the current mirror circuit 5j has transistors M3 and M4. Figure 16 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 1j in the third embodiment. Transistors M3 and M4 are connected to each other via current mirrors. When transistors Q1 and Q2 are NPN bipolar transistors and transistors M3 and M4 are P-type field-effect transistors, the source of transistor M3 is connected to the power supply node Nvdd, its drain is connected to the bases of transistors Q1 and Q2, and its gate is connected to the gate of transistor M4. The source of transistor M4 is connected to the power supply node Nvdd, its drain is connected to the compensation circuit 6i, and its gate is connected to the gates of transistors M3 and M4.

[0171] Transistor M3 is approximately the same size as transistor M4. Correspondingly, the mirror image ratio is approximately 1.

[0172] The current mirror circuit 5 receives the sum of the base current IB1 of transistor Q1 and the base current IB2 of transistor Q2 on the input side, replicates the current IB1+IB2 to the output side with a mirror ratio of approximately 1, and outputs the current IB1+IB2 to the reference node Ng from the output side via transistor M6.

[0173] In addition, the gate of transistor M6 is connected to the drain of transistor M2, and the source is connected to the reference node Ng, enabling it to function as an inverting amplifier.

[0174] The loop comprising the drain of transistor M6 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → gate of transistor M6 → drain of transistor M6 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the gate of transistor M6. Correspondingly, the drain current flowing through transistor M6 is replicated from the drain of transistor M5 to the drain of transistor M3 at approximately a mirror ratio of 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies current Ic to transistors Q1 and Q2 respectively, feedback is applied such that the drain current flowing through transistor M6 becomes IB1 + IB2. This is the same as in the first embodiment.

[0175] The compensation circuit 7j is connected between the power supply node Nvdd, node N2, and reference node Ng. The compensation circuit 7j generates a current IB2 equivalent to the base current IB2 of transistor Q2, and draws the current IB2 out from node N2.

[0176] like Figure 16 As shown, the compensation circuit 7j includes a load circuit 71i, a replica transistor Q12, a current mirror circuit 72i, and a current mirror circuit 73j.

[0177] Load circuit 71i is connected between power node Nvdd and replica transistor Q12. When replica transistor Q12 is an NPN bipolar transistor, load circuit 71i is connected between power node Nvdd and the collector of replica transistor Q12.

[0178] The load circuit 71i has a transistor M31. Transistor M31 is connected between the power node Nvdd and the replica transistor Q12. When the replica transistor Q12 is an NPN bipolar transistor, transistor M31 is connected between the power node Nvdd and the collector of the replica transistor Q12.

[0179] The replica transistor Q12 is connected between the load circuit 71i, the current mirror circuit 72i, and the reference node Ng. The replica transistor Q12 can also be an NPN bipolar transistor. The collector of the replica transistor Q12 is connected to the load circuit 71i, the emitter is connected to the reference node Ng, and the base is connected to the current mirror circuit 72i.

[0180] The replica transistor Q12 is configured as a copy of transistor Q2. The dimensions of the replica transistor Q12 are approximately the same as those of transistor Q2. Consequently, a current IB2, equivalent to the base current IB2 of transistor Q2, flows through the base of the replica transistor Q12.

[0181] The current mirror circuit 72i is connected between the power node Nvdd, the replica transistor Q12, and the current mirror circuit 73j. The input side of the current mirror circuit 72i is connected to the base of the replica transistor Q12, and the output side is connected to the current mirror circuit 73j.

[0182] The current mirror circuit 72i includes transistors M33, M34, and M35. Transistors M33, M34, and M35 are interconnected via current mirrors. When the replica transistor Q12 is an NPN bipolar transistor and transistors M33, M34, and M35 are P-type field-effect transistors, the source of transistor M33 is connected to the power node Nvdd, its drain is connected to the base of the replica transistor Q12, and its gate is connected to the gates of transistors M34 and M35. The source of transistor M34 is connected to the power node Nvdd, and its gate / drain is connected to the gates of transistors M33, M35, and M36. The source of transistor M35 is connected to the power node Nvdd, its drain is connected to the current mirror circuit 73j, and its gate is connected to the gates of transistors M33 and M34.

[0183] The dimensions of transistor M33, transistor M34, and transistor M35 are approximately the same. Correspondingly, the mirror image ratio is approximately 1.

[0184] The current mirror circuit 72i receives the base current IB2 of the replica transistor Q12 on the input side, replicates the current IB2 to the output side with a mirror ratio of approximately 1, and supplies the current IB2 from the output side to the current mirror circuit 73j.

[0185] In addition, the gate of transistor M36 is connected to the drain of transistor M31, and the source is connected to the reference node Ng, enabling it to function as an inverting amplifier.

[0186] The loop comprising the drain of transistor M36 → drain of transistor M34 → gate of transistor M34 → gate of transistor M33 → drain of transistor M33 → base of replica transistor Q12 → collector of replica transistor Q12 → gate of transistor M36 → drain of transistor M36 functions as a feedback loop. For example, when a voltage corresponding to the current Ic from the load circuit 71i is applied to the gate of transistor M36, the drain current flowing through transistor M36 is replicated from the drain of transistor M34 to the drain of transistor M33 at a mirror ratio of approximately 1. The replicated current flows into the base of replica transistor Q12, but because the load circuit 71i supplies current Ic, feedback is applied such that the drain current flowing through transistor M36 becomes IB2.

[0187] The input side of the current mirror circuit 73j is connected to the output side of the current mirror circuit 72i, and the output side is connected in parallel with the resistor element R2 relative to node N2.

[0188] The current mirror circuit 73j includes transistors M37 and M29. Transistors M37 and M29 are interconnected via current mirrors. When transistors M37 and M29 are N-type field-effect transistors, the source of transistor M37 is connected to the reference node Ng, and its gate / drain is connected to the gate of transistor M29. The source of transistor M29 is connected to the reference node Ng, its drain is connected to node N2, and its gate is connected to the gate of transistor M37.

[0189] The dimensions of transistor M37 and transistor M29 are approximately the same. Correspondingly, the mirror image ratio is approximately 1.

[0190] The current mirror circuit 73j receives current IB2 on the input side, replicates current IB2 to the output side with a mirror ratio of approximately 1, and allows current IB2 to flow on the output side. Thus, the current mirror circuit 73j draws the base current IB2 from node N2.

[0191] In addition, the gate of transistor M16 is connected to the drain of transistor M11, and the source is connected to the reference node Ng, enabling it to function as an inverting amplifier.

[0192] The loop comprising the drain of transistor M16 → drain of transistor M14 → gate of transistor M14 → gate of transistor M13 → drain of transistor M13 → base of replica transistor Q11 → collector of replica transistor Q11 → gate of transistor M16 → drain of transistor M16 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 61 is applied to the gate of transistor M16, and correspondingly, the drain current flowing through transistor M16 is replicated from the drain of transistor M14 to the drain of transistor M13 at approximately a mirror ratio of 1. The replicated current flows into the base of replica transistor Q11, but because the load circuit 61 supplies current Ic, feedback is applied such that the drain current flowing through transistor M16 becomes IB1. This is the same as in the first embodiment.

[0193] As described above, in the third embodiment, in the constant voltage generation circuit 1j of the semiconductor integrated circuit 100j, the compensation circuit 6 generates a current IB1 equivalent to the base current of transistor Q1 and leads it out from node N1. The compensation circuit 7j generates a current IB2 equivalent to the base current of transistor Q2 and leads it out from node N2. Therefore, the influence of the temperature dependence of the base currents of transistors Q1 and Q2 can be suppressed, and the influence of the temperature dependence of the base-emitter voltage of transistors Q1 and Q2, which varies with temperature as a function of temperature, can be reduced by the temperature dependence of the voltage across the resistive element R2, which varies with temperature as a function of temperature increases positively. As a result, the voltage between the collectors of transistors Q1 and Q2 and the reference node Ng can be maintained approximately constant relative to changes in ambient temperature, and the constant voltage Vbgr output from the output node Nout can be maintained approximately constant.

[0194] Furthermore, in the third embodiment, in the constant voltage generation circuit 1j of the semiconductor integrated circuit 100j, the compensation circuit 6 draws out a current IB1 corresponding to the base current of Q1, and the compensation circuit 7j draws out a current IB2 corresponding to the base current of transistor Q2. This suppresses the effects of differences in base currents IB1 and IB2 corresponding to the size differences of transistors Q1 and Q2, and reduces the influence of the temperature dependence of the base / emitter voltage of transistors Q1 and Q2, which varies with temperature as a function of temperature, by utilizing the temperature dependence of the voltage across the resistive element R2, which varies with temperature as a function of temperature increases positively.

[0195] Furthermore, as a first variation of the third embodiment, in the constant voltage generation circuit 201j of the semiconductor integrated circuit 200j, for example, when transistors Q1 and Q2 are NPN type bipolar transistors, measures can also be implemented to stably equalize the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0196] like Figure 17 and Figure 18 As shown, the constant voltage generation circuit 201j of the semiconductor integrated circuit 200j may also have a compensation circuit 208. Figure 17 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit 201j in the first variation of the third embodiment. Figure 18 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 201j in the first variation of the third embodiment.

[0197] The compensation circuit 208 is connected between the load circuit 4 and transistors Q1 and Q2. The compensation circuit 208 receives the voltages from the transistor Q1 side and the transistor Q2 side from the load circuit 4, respectively, and supplies the load circuit 4 with a control signal corresponding to the difference between the currents on the transistor Q1 side and the currents on the transistor Q2 side.

[0198] The compensation circuit 208 includes a differential amplifier 209. The non-inverting input terminal 209a of the differential amplifier 209 is connected to node N11, the inverting input terminal 209b is connected to node N12, and the output terminal 209c is connected to the gates of transistors M1 and M2. Node N11 is connected between the load circuit 4 and transistor Q1. Node N12 is connected between the load circuit 4 and transistor Q2.

[0199] When transistors M1 and M2 are P-type field-effect transistors and transistors Q1 and Q2 are NPN bipolar transistors, node N11 is connected between the drain of transistor M1 and the collector of transistor Q1. Node N12 is connected between the drain of transistor M2 and the collector of transistor Q2. Transistors M1 and M2 can also be considered as being connected via a current mirror through differential amplifier 209.

[0200] Differential amplifier 209 receives the voltage of node N11 at the non-inverting input terminal 209a and the voltage of node N12 at the inverting input terminal 209b. Differential amplifier 209 outputs a voltage from the output terminal 209c corresponding to the difference between the voltages of node N11 and node N12. Differential amplifier 209 can supply this voltage, corresponding to the difference between the voltages of node N11 and node N12, as a control signal to the load circuit 4.

[0201] Therefore, the compensation circuit 208 can adjust the load circuit 4 to make the current on the transistor Q1 side equal to the current on the transistor Q2 side. Based on the adjustment result, the compensation circuit 208 supplies the current on the transistor Q1 side to the transistor Q1 and the current on the transistor Q2 side to the transistor Q2.

[0202] Furthermore, the loop comprising the drain of transistor M6 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → gate of transistor M6 → drain of transistor M6 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the gate of transistor M6, and correspondingly, the drain current flowing through transistor M6 is replicated from the drain of transistor M5 to the drain of transistor M3 at approximately a mirror ratio of 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies current Ic to transistors Q1 and Q2 respectively, feedback is applied such that the drain current flowing through transistor M6 becomes IB1 + IB2. This is the same as in the third embodiment.

[0203] Furthermore, the loop comprising the drain of transistor M16 → drain of transistor M14 → gate of transistor M14 → gate of transistor M13 → drain of transistor M13 → base of replica transistor Q11 → collector of replica transistor Q11 → gate of transistor M16 → drain of transistor M16 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 61 is applied to the gate of transistor M16, and correspondingly, the drain current flowing through transistor M16 is replicated from the drain of transistor M14 to the drain of transistor M13 at approximately a mirror ratio of 1. The replicated current flows into the base of replica transistor Q11, but since the load circuit 61 supplies current Ic, feedback is applied such that the drain current flowing through transistor M16 becomes IB1. This is the same as in the third embodiment.

[0204] Furthermore, the loop comprising the drain of transistor M36 → drain of transistor M34 → gate of transistor M34 → gate of transistor M33 → drain of transistor M33 → base of replica transistor Q12 → collector of replica transistor Q12 → gate of transistor M36 → drain of transistor M36 functions as a feedback loop. For example, when a voltage corresponding to the current Ic from the load circuit 71i is applied to the gate of transistor M36, the drain current flowing through transistor M36 is replicated from the drain of transistor M34 to the drain of transistor M33 at a mirror ratio of approximately 1. The replicated current flows into the base of replica transistor Q12, but because the load circuit 71i supplies current Ic, feedback is applied such that the drain current flowing through transistor M36 becomes IB2. This is the same as in the third embodiment.

[0205] In this way, the compensation circuit 208 can perform compensation to ensure that the load circuit 4 stably supplies equal current to transistors Q1 and Q2. This allows the collector current IC of transistor Q1 and the collector current IC of transistor Q2 to be stably equalized.

[0206] Alternatively, as a second variation of the third embodiment, in the constant voltage generation circuit 301j of the semiconductor integrated circuit 300j, for example when transistors Q1 and Q2 are NPN bipolar transistors, measures can be implemented to suppress the effect of the difference between the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0207] like Figure 19 and Figure 20 As shown, the constant voltage generation circuit 301j of the semiconductor integrated circuit 300j may also have a compensation circuit 308. Figure 19 This is a circuit diagram showing a schematic configuration of the constant voltage generation circuit 301j in the second variation of the third embodiment. Figure 20 This is a circuit diagram showing the detailed configuration of the constant voltage generation circuit 301j in the second variation of the third embodiment.

[0208] The compensation circuit 308 is connected between the load circuit 4 and the current mirror circuit 5 and transistors Q1 and Q2. The compensation circuit 308 receives the voltages on the side of transistor Q1 and the side of transistor Q2 from the load circuit 4, respectively, and supplies the current mirror circuit 5 with a control signal corresponding to the difference between the currents on the side of transistor Q1 and the side of transistor Q2.

[0209] The compensation circuit 308 includes a differential amplifier 309. The non-inverting input terminal 309a of the differential amplifier 309 is connected to node N11, the inverting input terminal 309b is connected to node N12, and the output terminal 309c is connected to the drain of transistor M5. Node N11 is connected between the load circuit 4 and transistor Q1. Node N12 is connected between the load circuit 4 and transistor Q2.

[0210] When transistors M1 and M2 are P-type field-effect transistors and transistors Q1 and Q2 are NPN type bipolar transistors, node N11 is connected between the drain of transistor M1 and the collector of transistor Q1. Node N12 is connected between the drain of transistor M2 and the collector of transistor Q2.

[0211] The differential amplifier 309 receives the voltage of node N11 at the non-inverting input terminal 309a and the voltage of node N12 at the inverting input terminal 309b. The differential amplifier 309 outputs a voltage from the output terminal 309c corresponding to the difference between the voltages of node N11 and node N12. The differential amplifier 309 can supply this voltage, corresponding to the difference between the voltages of node N11 and node N12, as a control signal to the current mirror circuit 5.

[0212] Furthermore, the loop comprising the output node 309c of differential amplifier 309 → drain of transistor M5 → gate of transistor M5 → gate of transistor M3 → drain of transistor M3 → base of transistor Q2 → collector of transistor Q2 → input node 309b of differential amplifier 309 → output node 309c of differential amplifier 309 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 4 is applied to the input node 309b of differential amplifier 309. Correspondingly, the current flowing through the output node 309c of differential amplifier 309 is replicated from the drain of transistor M5 to the drain of transistor M3 with a mirror ratio of approximately 1. The replicated current flows into the bases of transistors Q1 and Q2, but since the load circuit 4 supplies current Ic to transistors Q1 and Q2 respectively, feedback is applied such that the current flowing through the output node 309c of differential amplifier 309 becomes IB1 + IB2. This is the same as in the third embodiment.

[0213] Furthermore, the loop comprising the drain of transistor M16 → drain of transistor M14 → gate of transistor M14 → gate of transistor M13 → drain of transistor M13 → base of replica transistor Q11 → collector of replica transistor Q11 → gate of transistor M16 → drain of transistor M16 functions as a feedback loop. For example, a voltage corresponding to the current Ic from the load circuit 61 is applied to the gate of transistor M16, and correspondingly, the drain current flowing through transistor M16 is replicated from the drain of transistor M14 to the drain of transistor M13 at approximately a mirror ratio of 1. The replicated current flows into the base of replica transistor Q11, but since the load circuit 61 supplies current Ic, feedback is applied such that the drain current flowing through transistor M16 becomes IB1. This is the same as in the third embodiment.

[0214] Furthermore, the loop comprising the drain of transistor M36 → drain of transistor M34 → gate of transistor M34 → gate of transistor M33 → drain of transistor M33 → base of replica transistor Q12 → collector of replica transistor Q12 → gate of transistor M36 → drain of transistor M36 functions as a feedback loop. For example, when a voltage corresponding to the current Ic from the load circuit 71i is applied to the gate of transistor M36, the drain current flowing through transistor M36 is replicated from the drain of transistor M34 to the drain of transistor M33 at a mirror ratio of approximately 1. The replicated current flows into the base of replica transistor Q12, but because the load circuit 71i supplies current Ic, feedback is applied such that the drain current flowing through transistor M36 becomes IB2. This is the same as in the third embodiment.

[0215] Therefore, the current mirror circuit 5 replicates the correction current corresponding to the difference between the collector current on the transistor Q1 side and the collector current on the transistor Q2 side to the input side with a mirror ratio of approximately 1, and supplies the correction current to transistors Q1 and Q2 from the input side.

[0216] Thus, in the compensation circuit 308, the current mirror circuit 5 directs a correction current corresponding to the difference between the collector current on the transistor Q1 side and the collector current on the transistor Q2 side to the input side of the current mirror circuit 5. This corrects the current IB1+IB2 flowing to the input side of the current mirror circuit 5, suppressing the effect of the difference between the collector current IC of transistor Q1 and the collector current IC of transistor Q2.

[0217] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0218] Explanation of reference numerals in the attached figures

[0219] 1. Constant voltage generation circuit, 1i, 1j, 201, 201i, 201j, 301, 301i, 301j; 2. Power supply circuit; 3. Internal circuit; 4. Load circuit; 5. Current mirror circuit; 6. 6i; 7. 7i, 7j; 208, 308 compensation circuit; 100, 200, 300 semiconductor integrated circuits.

Claims

1. A semiconductor integrated circuit, characterized in that, have: The first transistor has its base connected to the output node; The second transistor has a different size than the first transistor, and its base is connected to the output node; A first resistive element is connected between the emitter of the first transistor and the emitter of the second transistor; The second resistive element is connected between the emitter of the second transistor and the reference node; The first compensation circuit draws a first current equivalent to the base current of the first transistor from a first node between the emitter of the first transistor and the first resistive element. as well as The second compensation circuit draws a second current equivalent to the base current of the second transistor from a second node between the emitter of the second transistor and the second resistive element.

2. The semiconductor integrated circuit according to claim 1, characterized in that, It also includes a first current mirror circuit whose input side is connected to the base of the first transistor and the base of the second transistor. The second compensation circuit is connected to the output side of the first current mirror circuit. The first compensation circuit further draws out the first current from the third node between the first current mirror circuit and the second compensation circuit.

3. The semiconductor integrated circuit according to claim 1, characterized in that, The first compensation circuit generates the first current, and the first current is drawn out from the first node. The second compensation circuit obtains the sum of the first current and the second current, obtains the second current by drawing the first current from the sum of the first current, and draws the second current from the second node.

4. The semiconductor integrated circuit according to claim 1, characterized in that, It also includes a first current mirror circuit whose input side is connected to the base of the first transistor and the base of the second transistor. The first compensation circuit is connected to the output side of the first current mirror circuit. The second compensation circuit further draws out the first current from the fourth node between the first current mirror circuit and the first compensation circuit.

5. The semiconductor integrated circuit according to claim 1, characterized in that, The second compensation circuit generates the second current, and the second current is drawn from the second node. The first compensation circuit obtains the sum of the first current and the second current, obtains the first current by drawing the second current from the sum of the first current, and draws the first current from the first node.

6. The semiconductor integrated circuit according to claim 1, characterized in that, The first compensation circuit generates the first current, and the first current is drawn out from the first node. The second compensation circuit generates the second current and draws the second current out from the second node.

7. The semiconductor integrated circuit according to claim 2, characterized in that, The first compensation circuit has: The first replica transistor has the same dimensions as the first transistor; The second current mirror circuit has its input side connected to the base of the first replica transistor; as well as The third current mirror circuit has its input side connected to the output side of the second current mirror circuit, and its output side connected in parallel with the first resistive element at the fifth node between the emitter of the first transistor and the reference node. The second compensation circuit has a fourth current mirror circuit, the input side of which is connected to the output side of the first current mirror circuit, and the output side is connected in parallel with the second resistive element relative to the second node.

8. The semiconductor integrated circuit according to claim 3, characterized in that, The first compensation circuit has: The first replica transistor has the same dimensions as the first transistor; The second current mirror circuit has its input side connected to the base of the first replica transistor; as well as The third current mirror circuit has its input side connected to the output side of the second current mirror circuit, and its output side connected in parallel with the first resistive element at the fifth node between the emitter of the first transistor and the reference node. The second compensation circuit has a fourth current mirror circuit, the input side of which is connected to the output side of the first current mirror circuit, and the output side is connected in parallel with the second resistive element relative to the second node.

9. The semiconductor integrated circuit according to claim 4, characterized in that, The second compensation circuit has: The second replica transistor has the same dimensions as the second transistor; The sixth current mirror circuit has its input side connected to the base of the second replica transistor; as well as The seventh current mirror circuit has its input side connected to the output side of the sixth current mirror circuit, and its output side connected in parallel with the second resistive element at the sixth node between the emitter of the second transistor and the reference node. The first compensation circuit has an eighth current mirror circuit, the input side of which is connected to the output side of the first current mirror circuit, and the output side is connected in parallel with the first resistive element relative to the first node.

10. The semiconductor integrated circuit according to claim 5, characterized in that, The second compensation circuit has: The second replica transistor has the same dimensions as the second transistor; The sixth current mirror circuit has its input side connected to the base of the second replica transistor; as well as The seventh current mirror circuit has its input side connected to the output side of the sixth current mirror circuit, and its output side connected in parallel with the second resistive element at the sixth node between the emitter of the second transistor and the reference node. The first compensation circuit has an eighth current mirror circuit, the input side of which is connected to the output side of the first current mirror circuit, and the output side is connected in parallel with the first resistive element relative to the first node.

11. The semiconductor integrated circuit according to claim 1, characterized in that, The first compensation circuit has: The first replica transistor has the same dimensions as the first transistor; The second current mirror circuit has its input side connected to the base of the first replica transistor; as well as The third current mirror circuit has its input side connected to the output side of the second current mirror circuit, and its output side connected in parallel with the first resistive element at the fifth node between the emitter of the first transistor and the reference node. The second compensation circuit has: The second replica transistor has the same dimensions as the second transistor; The sixth current mirror circuit has its input side connected to the base of the second replica transistor; as well as The seventh current mirror circuit has its input side connected to the output side of the sixth current mirror circuit, and its output side is connected in parallel with the second resistor element at the sixth node between the emitter of the second transistor and the reference node.

12. The semiconductor integrated circuit according to claim 6, characterized in that, The first compensation circuit has: The first replica transistor has the same dimensions as the first transistor; The second current mirror circuit has its input side connected to the base of the first replica transistor; as well as The third current mirror circuit has its input side connected to the output side of the second current mirror circuit, and its output side connected in parallel with the first resistive element at the fifth node between the emitter of the first transistor and the reference node. The second compensation circuit has: The second replica transistor has the same dimensions as the second transistor; The sixth current mirror circuit has its input side connected to the base of the second replica transistor; as well as The seventh current mirror circuit has its input side connected to the output side of the sixth current mirror circuit, and its output side is connected in parallel with the second resistive element relative to the sixth node between the emitter of the second transistor and the reference node.

13. The semiconductor integrated circuit according to claim 1, characterized in that, It also includes a load circuit that supplies equal current to the collectors of the first transistor and the second transistor.

14. The semiconductor integrated circuit according to claim 13, characterized in that, It also includes a differential amplifier circuit, which has a first input node connected to the collector of the first transistor, a second input node connected to the collector of the second transistor, and an output node connected to the control node of the load circuit.

15. The semiconductor integrated circuit according to claim 2, characterized in that, It also includes a differential amplifier circuit, which has a first input node connected to the collector of the first transistor, a second input node connected to the collector of the second transistor, and an output node connected to the first current mirror circuit.

16. The semiconductor integrated circuit according to claim 1, characterized in that, When n is set to a number greater than 1, the size of the first transistor is n times the size of the second transistor.

17. The semiconductor integrated circuit according to claim 2, characterized in that, The mirror ratio of the first current mirror circuit is approximately 1.

18. The semiconductor integrated circuit according to claim 7, characterized in that, The mirror ratios of the first current mirror circuit, the second current mirror circuit, the third current mirror circuit, and the fourth current mirror circuit are approximately 1.

19. The semiconductor integrated circuit according to claim 1, characterized in that, The current amplification of the first transistor and the current amplification of the second transistor are respectively dependent on current density and temperature.

20. The semiconductor integrated circuit according to claim 1, characterized in that, The base-emitter voltage of the first transistor and the base-emitter voltage of the second transistor both change with respect to temperature in a negative increasing function. The voltage across the second resistive element changes with respect to temperature as a positive function of increase.

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