A current mirror circuit and a frequency locked loop circuit supporting dynamic element matching and trimming

Abstract

The application discloses a current mirror circuit and a frequency-locked loop circuit supporting dynamic element matching and trimming, and the current mirror circuit comprises a rolling selection control logic module, a unit current mirror array module, a switch array module and a pre-biasing module. The rolling selection control logic module determines a current replication scale in real time according to a trimming control word and outputs an enable signal; the unit current mirror array module switches N unit current mirrors to different working states in time according to the enable signal; and the pre-biasing module provides potential pre-compensation for the N unit current mirrors according to different working states of the N unit current mirrors. The application determines the working role of the unit current mirror through the rolling selection control logic module, realizes current replication ratio trimming and dynamic element matching under the same hardware architecture, and eliminates coupling conflicts; and the pre-biasing module provides potential follow-up compensation for the unit current mirror in a silent state, thereby inhibiting transient current burr and phase disturbance.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a current mirror circuit and a frequency-locked loop circuit that support dynamic component matching and adjustment. Background Technology

[0002] A current mirror is a fundamental current replication unit in analog integrated circuits. It uses a diode-connected MOSFET to apply the gate voltage to a matching MOSFET, replicating the current based on the device size ratio. Ideally, the output current and input current satisfy the geometric ratio of the device dimensions. However, due to random deviations in wafer manufacturing processes, MOSFETs with consistent layout and dimensions generally exhibit device mismatch, including deviations in threshold voltage, transconductance, and gate oxide thickness. Device mismatch causes the actual replication ratio of the current mirror to deviate from the design specifications, introducing static gain error and integral nonlinearity. When applied to frequency-locked loop circuits, mismatch directly translates into output frequency error, and this error drifts with process, voltage, and temperature (PVT) conditions.

[0003] Dynamic element matching (DEM) is a common method for suppressing device mismatch. This approach breaks down the current mirror into multiple unit current mirrors with identical nominal parameters, and rotates the operating role of each unit periodically using a clock. Static mismatch is converted into a high-frequency time-varying signal through rotational modulation, avoiding DC errors and low-frequency drift in the target frequency band. After long-term time-domain averaging, the inherent mismatches of each unit cancel each other out, improving current replication accuracy and suppressing low-frequency noise and temperature drift. In frequency-locked loop systems, dynamic element matching can reduce frequency deviation caused by device mismatch, improve output frequency stability, and reduce clock phase noise.

[0004] To achieve output frequency calibration under full PVT conditions, frequency-locked loops typically adjust the number of replica cells using an n-bit tuning control word to digitally tune the current replication ratio. Traditional current mirror architectures are difficult to reconcile with digital tuning and dynamic component matching mechanisms. Digital tuning alters the number of effective working cells, conflicting with the requirement for equal cell rotation in dynamic component matching, potentially leading to poor loop control convergence. When idle cells are not under potential control, re-entering the working state will result in severe charge redistribution, inducing transient current spikes, phase disturbances, and spectral spurious signals.

[0005] Most existing solutions can only activate all devices under the maximum trimming code. After the trimming code is adjusted, some units remain idle for a long time and cannot participate in dynamic component matching and rotation, thus limiting the error averaging effect. Conventional architectures use ring shift registers to allocate unit roles. Changes in the trimming code will change the effective working window length, and the register needs to be reinitialized. The hardware has difficulty distinguishing between the three working roles of being copied, copying, and being silent at the same time, and the complexity of the control logic increases rapidly with the trimming bit width. Summary of the Invention

[0006] The purpose of this invention is to provide a current mirror circuit and frequency-locked loop circuit that support dynamic component matching and adjustment. By adjusting the control word, the current replication ratio can be adjusted, the dynamic component matching and rotation of the entire unit can be achieved, and the silent current mirror can be adaptively pre-biased to suppress switching transient disturbances, reduce device mismatch errors, and improve the current replication accuracy and PVT stability of the frequency-locked loop output frequency.

[0007] To solve the above-mentioned technical problems, on the one hand, the present invention provides a current mirror circuit that supports dynamic component matching and adjustment, including a rolling selection control logic module, a unit current mirror array module, a switch array module and a pre-bias module; The rolling selection control logic module receives a dynamic element matching clock signal and a trimming control word, and is used to determine the current replication scale in real time according to the trimming control word and output an enable signal. The unit current mirror array module includes N unit current mirrors. The unit current mirror array module is connected to the rolling selection control logic module and is used to switch the N unit current mirrors to different working states in a time-division manner according to the enable signal. The pre-bias module is used to provide potential pre-compensation for the N unit current mirrors according to their different operating states.

[0008] Furthermore, each unit current mirror is in only one of the following states at any given time: being copied, copying, or silent. When the unit current mirror is in the replication state, the gate of the unit current mirror is connected to its own drain through the switch array module, the source is connected to the power supply voltage, and the drain is connected to the replicated bus through the switch array module. When the unit current mirror is in the replication state, the gate of the unit current mirror is connected to the replicated bus through the switch array module, the source is connected to the power supply voltage, and the drain is connected to the replication bus through the switch array module. When the unit current mirror is in a quiescent state, the gate and drain of the unit current mirror are connected to the quiescent bus through the switch array module, and the source is connected to the power supply voltage.

[0009] Furthermore, the switch array module includes multiple switch units, each of which is connected to each unit current mirror; Each of the aforementioned switching units includes a first copied bus switch, a first silent bus switch, a second copied bus switch, a copied bus switch, and a second silent bus switch; the enable signal includes a copied enable signal, a copied enable signal, and a silent enable signal; The control terminal of the first copied bus switch is connected to the copied enable signal, one end is connected to the copied bus, and the other end is connected to the gate of the unit current mirror. The control terminal of the first silent bus switch is connected to the silent enable signal, one end is connected to the silent bus, and the other end is connected to the gate of the unit current mirror. The control terminal of the second copied bus switch is connected to the copied enable signal, one end is connected to the copied bus, and the other end is connected to the drain of the unit current mirror. The control terminal of the replication bus switch is connected to the replication enable signal, one end is connected to the replication bus, and the other end is connected to the drain of the N unit current mirrors. The control terminal of the second silent bus switch is connected to the silent enable signal, one end is connected to the silent bus, and the other end is connected to the drain of the N unit current mirrors.

[0010] Furthermore, the rolling selection control logic module includes a modulo-N rotation counter, a trimming code decoder, a position offsetter, and a role decision unit; The modulo-N cyclic counter receives a matching clock signal from the dynamic element and outputs a cyclic pointer under the drive of the matching clock signal from the dynamic element. The position offset device is connected to the modulo-N rotating counter and is used to receive the cyclic pointer and calculate the relative position for each unit current mirror based on the cyclic pointer. The tuning code decoder receives the tuning control word and decodes the tuning control word into the working window length; The role decision unit is connected to the position offset unit and the tuning decoder respectively, and is used to compare the working window length and the number of replicated tubes in the default state according to the relative position of each received unit current mirror, output the enable signal and drive the switch array module.

[0011] Furthermore, the role decision unit includes a first comparator, a second comparator, a first inverter, a second inverter, and an AND gate; The first input of the first comparator is connected to the position offset device, the second input receives the number of the copied tubes in the default state, and the output outputs a copy enable signal. The first input of the second comparator is connected to the position offset device, and the second input is connected to the trim code decoder. The input terminal of the first inverter is connected to the output terminal of the first comparator; The input of the second inverter is connected to the output of the second comparator, and the output of the second inverter outputs a mute enable signal. The first input terminal of the AND gate is connected to the output terminal of the first inverter, the second input terminal is connected to the output terminal of the second inverter, and the output terminal outputs a copy enable signal.

[0012] Furthermore, it also includes a first non-overlapping clock generation module, which is connected to the role decision unit and is used to perform timing processing on the enable signal and output a non-overlapping enable signal.

[0013] Furthermore, the pre-bias module includes a reference transistor, a unity-gain buffer, and a first transistor; The gate of the reference transistor is connected to the bus being replicated, the source is connected to the power supply voltage, and the drain is connected to the non-inverting input of the unity-gain buffer. Both the inverting input and output terminals of the unity-gain buffer are connected to the silent bus. The gate and drain of the first transistor are both connected to the inverting input of the unity-gain buffer, and the source is grounded.

[0014] On the other hand, the present invention also provides a frequency-locked loop circuit, including a current comparison module, a low-pass filter, a voltage-controlled oscillator, a buffer, a frequency divider, a second non-overlapping clock generation module, and a frequency-current conversion module; The current comparison module includes the aforementioned current mirror circuit that supports dynamic component matching and adjustment. The current comparison module, the low-pass filter, the voltage-controlled oscillator, and the buffer are connected in sequence, and the buffer outputs an oscillation clock signal; The frequency divider includes a 16-divider and a 2-divider. One end of the 16-divider and the 2-divider are connected between the voltage-controlled oscillator and the buffer. The other end of the 16-divider outputs a dynamic element matching clock signal. The other end of the 2-divider is connected to one end of the second non-overlapping clock generation module. The other end of the second non-overlapping clock generation module outputs a control signal to control the switching state of the frequency-current conversion module.

[0015] Furthermore, the current comparison module also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a first operational amplifier, a second operational amplifier, and a second transistor; The first resistor, the second resistor, and the third resistor are connected in series, with one end of the series connection connected to the power supply voltage and the other end grounded. One end of the first capacitor is connected between the first resistor and the second resistor, and the other end is grounded; One end of the second capacitor is connected between the second resistor and the third resistor, and the other end is grounded; One end of the current mirror circuit is connected to the power supply voltage, and the other end is grounded through the fourth resistor; The non-inverting input of the first operational amplifier is connected between the first resistor and the second resistor, the inverting input is connected between the current mirror circuit and the fourth resistor, and the output is connected to the current mirror circuit. The drain of the second transistor is connected to the other end of the current mirror circuit, and the source is connected to the frequency-current conversion module. The non-inverting input of the second operational amplifier is connected between the second resistor and the third resistor, the inverting input is connected between the source of the second transistor and the frequency-current conversion module, and the output is connected to the gate of the second transistor.

[0016] Furthermore, the frequency-current conversion module includes a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor; The first switch and the second switch are connected in series, the third switch and the fourth switch are connected in series, the first switch and the second switch are connected in parallel with the third switch and the fourth switch, one end of the parallel connection is connected to the same point, and the other end is connected to the source of the second transistor; The first capacitor is connected in parallel with the first switch, and the second capacitor is connected in parallel with the third switch.

[0017] Compared with the prior art, the present invention has at least the following beneficial effects: This invention determines the working role of the unit current mirror through the rolling selection control logic module, achieving current replication ratio adjustment and dynamic component matching under the same hardware architecture, eliminating coupling conflicts. Simultaneously, it ensures that all unit current mirrors in the array participate in periodic role rotation, reducing low-frequency mismatch noise and 1 / f noise. This invention provides potential following compensation for the unit current mirror in the silent state through the pre-bias module, suppressing transient current spikes and phase disturbances. In frequency-locked loop applications, it can first complete coarse calibration of the output frequency, and then rely on dynamic component matching to eliminate residual frequency errors, significantly improving the PVT robustness and current replication accuracy of the output frequency. Attached Figure Description

[0018] Figure 1 This is a block diagram illustrating dynamic component matching and adjustment in one embodiment of the present invention. Figure 2 This is a partial structural schematic diagram of a current mirror circuit supporting dynamic element matching and adjustment in one embodiment of the present invention. Figure 3 This is a schematic diagram of the specific structure of the switch array module in one embodiment of the present invention; Figure 4This is a schematic diagram of the specific structure of the scrolling selection control logic module in one embodiment of the present invention; Figure 5 This is a schematic diagram of another structure of a current mirror circuit that supports dynamic component matching and adjustment in one embodiment of the present invention. Figure 6 This is a timing diagram of the role switching of the unit current mirror in one embodiment of the present invention; Figure 7 This is a comparison chart of the output noise of different current mirror schemes when N=9. Figure 8 This is a schematic diagram of the frequency-locked loop circuit in one embodiment of the present invention; Figure 9 This is a comparison chart of the output clock noise of different frequency-locked loop schemes when using a current mirror N=639 in the frequency-locked loop.

[0019] Reference numerals: CLK_DEM, Dynamic Component Matching Clock Signal; T[n-1:0], Tuning Control Word; SRC, Copy Unit; REP, Copy Unit; SIL, Silence Unit; V SRC The bus being copied; V REP , Copy bus; V SIL 1. Silent bus; EN, Enable signal; EN_SRC, Copy enable signal; EN_REP, Copy enable signal; EN_SIL, Silent enable signal; SW_SRC1, First copied bus switch; SW_SIL1, First silent bus switch; SW_SRC2, Second copied bus switch; SW_REP, Copy bus switch; SW_SIL2, Second silent bus switch; p, Cycle pointer; W, Working window length; d i The relative position of each unit current mirror; M, the number of replicated transistors in the default state; K, the number of replicated transistors; CM, the unit current mirror; VCCA, the power supply voltage; M ref、 Reference transistor; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; C1, first capacitor; C2, second capacitor; D1, first operational amplifier; D2, second operational amplifier; M1, first transistor; M2, second transistor; SW1, first switch; SW2, second switch; SW3, third switch; SW4, fourth switch. Detailed Implementation

[0020] Based on the teachings of this specification, those skilled in the art can form new technical solutions by combining different implementation methods without creating technical contradictions. Such variations should be considered to fall within the protection scope of this application.

[0021] The following is a more detailed description of a current mirror circuit supporting dynamic element matching and adjustment according to the present invention, with reference to schematic diagrams illustrating preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0022] The invention is described more specifically by way of example in the following paragraphs with reference to the accompanying drawings. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0023] Example 1 like Figure 1 As shown, this embodiment proposes a current mirror circuit that supports dynamic component matching and adjustment, including a rolling selection control logic module, a unit current mirror array module, a switch array module, and a pre-bias module.

[0024] The rolling selection control logic module receives the dynamic element matching clock signal CLK_DEM and the adjustment control word T[n-1:0], and uses it to determine the current replication scale in real time according to the adjustment control word T[n-1:0], and outputs an enable signal to the switch array module. The highest bit of the adjustment control word T[n-1:0] is T[n-1], the lowest bit is T[0], and T[n-1:0] is a combination of n bits. The dynamic element matching clock signal CLK_DEM controls the working window to slide forward one bit in each clock cycle, and the adjustment control word T[n-1:0] determines the number of unit current mirrors participating in current replication in the current clock cycle, thereby achieving flexible adjustment of the current replication ratio without changing the hardware structure.

[0025] If the decimal value of the modifier control word T[n-1:0] is t, Then the length W of the working window within the current clock cycle is .in, To adjust the bit width of the control word, M is the number of tubes being copied in the default state. K is the number of replication tubes. If n=2, then N=9, M=4, and the range of K is [2, 5]; if n=8, N=639, M=256, and the range of K is [128, 383].

[0026] The unit current mirror array module includes N unit current mirrors (CMs). The unit current mirror array module is connected to the rolling selection control logic module and is used to switch the N unit current mirrors (CMs) to different working states in a time-division manner according to the enable signal EN. That is, according to the enable signal EN, the N unit current mirrors (CMs) are switched to different working states in a time-division manner within each dynamic element matching clock cycle, so that all N unit current mirrors (CMs) participate in the dynamic element matching rotation and there are no idle devices, thereby maximizing the average depth of dynamic element matching and the mismatch cancellation effect.

[0027] The N unit current mirrors CM are numbered sequentially as 0, 1, 2, ..., N-1, and the number N of the unit current mirrors CM satisfies the following condition: ,Right now It equals the sum of the number of tubes being replicated in the default state and the maximum number of tubes to replicate. Where K... max This is the maximum number of replication tubes. .

[0028] When the adjustment control word T[n-1:0] takes the default value (Total n digits, i.e.) )hour, At this time, the number of replicated transistors M is equal to the number of replicated transistors K, the current replication ratio is 1:1, and it corresponds to the nominal output frequency of the frequency-locked loop.

[0029] The pre-bias module is used to provide potential pre-compensation for the N unit current mirrors CM according to their different operating states, suppressing transient charge disturbances generated during operating state switching and reducing current spikes and phase disturbances caused by switching.

[0030] Through the above structure, this application implements adjustment control and dynamic element matching within the same hardware framework, solving problems such as strong coupling between the two, improper handling of silent units, and rapid expansion of control logic with adjustment bit width in traditional solutions.

[0031] In this embodiment, each unit current mirror CM is in only one of the following states at any given time: the copied SRC state, the copied REP state, or the silent SIL state. That is, at any given time, there are exactly M unit current mirror CMs in the copied state, K in the copied state, and NW in the silent state.

[0032] When the unit current mirror CM is in the replication state, the gate of the unit current mirror CM is connected to its own drain through the switch array module, the source is connected to the power supply voltage, and the drain is connected to the replication bus V through the switch array module. SRC The drain currents of all M unit current mirrors CM in the replicated state converge at the replicated bus V. SRCThis forms the input current I. in Where M is a fixed value, representing the number of tubes being copied in the default state. .

[0033] When the unit current mirror CM is in replication mode, the gate of the unit current mirror CM is connected to the replicated bus V through the switch array module. SRC The source is connected to the power supply voltage, and the drain is connected to the replication bus V through the switch array module. REP The drain currents of all K unit current mirrors CM in the replication state converge at the replication bus V. REP This generates an output current I. out The number of replica tubes K is determined by the decimal value t of the trimming control word T[n-1:0], satisfying the following conditions: The range of values ​​for K is .when hour, That is, by default there is One unit current mirror CM participates in the work, of which the number of unit current mirror CMs being replicated is... Number of units, replicating the current mirror CM There are 1, The unit current mirror CM is in a silent state.

[0034] at this time, The input current to output current ratio is 1:1, corresponding to the nominal output frequency of the frequency-locked loop. By changing the K value, the current replication ratio can be flexibly adjusted without replacing any hardware, thereby precisely tuning the output frequency of the frequency-locked loop to cope with different PVT conditions.

[0035] When the unit current mirror CM is in a silent state, the gate and drain of the unit current mirror CM are connected to the silent bus V through the switch array module. SIL The source is connected to the power supply voltage VCCA. The gate and drain are simultaneously connected to the quiescent bus V. SIL This ensures that the unit current mirror CM, which is in a silent state, does not supply power to the replicated bus V during the silent period. SRC Nor will it copy bus V REP Inject or extract current.

[0036] like Figure 3 As shown, in this embodiment, the switch array module includes multiple switch units, and each switch unit is connected to each unit current mirror CM.

[0037] Each of the aforementioned switching units includes a first copied bus switch SW_SRC1, a first silent bus switch SW_SIL1, a second copied bus switch SW_SRC2, a copied bus switch SW_REP, and a second silent bus switch SW_SIL2. The enable signal EN includes a copied enable signal EN_SRC, a copied enable signal EN_REP, and a silent enable signal EN_SIL, and the three enable signals are mutually exclusive at any given time.

[0038] The control terminal of the first copied bus switch SW_SRC1 is connected to the copied enable signal EN_SRC, and one end is connected to the copied bus V. SRC The other end is connected to the gate of the unit current mirror CM. When the replication enable signal EN_SRC is valid, the first replicated bus switch SW_SRC1 is turned on, switching the replicated bus V... SRC The voltage is introduced into the gate of the unit current mirror CM.

[0039] The control terminal of the first silent bus switch SW_SIL1 is connected to the silent enable signal EN_SIL, and one end is connected to the silent bus V. SIL The other end is connected to the gate of the unit current mirror CM. When the silence enable signal EN_SIL is valid, the first silence bus switch SW_SIL1 is turned on, connecting the gate of the unit current mirror CM to the silence bus V. SIL This allows the gate potential to be maintained by the pre-bias module, thereby keeping the unit current mirror CM in a pre-biased quiescent state.

[0040] The control terminal of the second copied bus switch SW_SRC2 is connected to the copied enable signal EN_SRC, and one end is connected to the copied bus V. SRC The other end is connected to the drain of the unit current mirror CM. When the replication enable signal EN_SRC is valid, the second replicated bus switch SW_SRC2 and the first replicated bus switch SW_SRC1 are simultaneously turned on, and the gate of the unit current mirror CM is connected to the silent bus V. SIL .

[0041] The control terminal of the replication bus switch SW_REP is connected to the replication enable signal EN_REP, and one terminal is connected to the replication bus V. REP The other end is connected to the drain of the N unit current mirrors CM. When the replication enable signal EN_REP is valid, the replication bus switch SW_REP is turned on, outputting the drain current of the unit current mirror CM to the replication bus V. REP .

[0042] The control terminal of the second silent bus switch SW_SIL2 is connected to the silent enable signal EN_SIL, and one end is connected to the silent bus V. SIL The other end is connected to the drain of the N unit current mirrors CM. When the silence enable signal EN_SIL is valid, the second silence bus switch SW_SIL2 is turned on, connecting the drain of the unit current mirror CM to the silence bus V. SIL In conjunction with the pre-biasing module, the drain potential is pre-biased to near the operating potential, preparing the potential for subsequent switching to the operating state.

[0043] The three enable signals are controlled by the rolling selection control logic module. At any given time, only one switch combination corresponding to a certain state is turned on in each unit current mirror CM, thereby avoiding short circuits between different buses and charge disturbances during switching, and maintaining the stability of the potential of each bus.

[0044] In this embodiment, as Figure 2 and Figure 4 As shown, the rolling selection control logic module includes a modulo-N rotation counter, a trimming code decoder, a position offsetter, and N sets of role decision units.

[0045] The modulo-N cyclic counter receives the dynamic element matching clock signal CLK_DEM and outputs a pointer under the drive of the dynamic element matching clock signal CLK_DEM. The modulo-N cyclic counter is... A binary counter and a feedback logic that resets the counter when the count value equals N-1 constitute the system. The modulo-N rotating counter increments sequentially under the continuous drive of the dynamic element matching clock signal CLK_DEM. When the count value reaches N-1, the reset feedback logic is triggered, the count value is reset to zero, and the incrementing restarts. This periodically outputs a loop pointer p, whose value range is {0, 1, ..., N-1}, corresponding to the numbers of all unit current mirrors (CMs) in the array. The loop pointer p indicates the starting position of the current working window on the N unit current mirrors (CMs) and is the core control variable for implementing the cyclic sliding of the working window. As the loop pointer p gradually increases, the working window slides one position on the numbering axis each clock cycle, and the roles of all unit current mirrors (CMs) are updated synchronously. The specific timing diagram is shown below. Figure 6 As shown.

[0046] exist Figure 6In the diagram, the vertical axis represents the unit current mirror number i, and the horizontal axis corresponds to different periods k of the dynamic element matching clock CLK_DEM. Cell labels SRC represent the copied state, REP represents the copied state, and SIL represents the silent state. As the cycle pointer p increments periodically, the position of the silent state shifts sequentially along the array. The effective working windows for the copied and copied states scroll synchronously, and all unit current mirrors sequentially cycle through the copied, copied, and silent states, thus achieving time-domain averaging for dynamic element matching. Simultaneously, the number of copied units can be changed by adjusting the working window length, allowing for digital adjustment while completing role rotation.

[0047] The position offset device is connected to the modulo-N rotating counter and is used to receive the cyclic pointer p and calculate the relative position d for each unit current mirror CM based on the cyclic pointer p. i The loop pointer p ∈ {0, 1, ..., N-1} increments by 1 bit after the rising edge of each dynamic element matched clock CLK_DEM, i.e., p... j +1=(p j +1) mod N. The relative position d i Satisfying d i [j]=(ip j ) mod N, where i is the number of the unit current mirror CM, i∈{0,1,...,N-1}; p j When the rising edge of the matching clock signal CLK_DEM for the j-th dynamic element arrives, the instantaneous value of the cycle pointer output by the modulo-N switching counter, p j ∈{0, 1, ..., N-1}. The relative position d i This reflects the offset of the unit current mirror CM (numbered i) relative to the starting point of the working window at the current moment, and is the direct basis for role determination. Through modulo operation, the instantaneous value p of the loop pointer is used... j As the reference starting point of the array, p is updated with the rising edge of the matching clock signal CLK_DEM for each dynamic element. j The relative positions of all unit current mirrors are synchronously iterated, enabling the working window to slide cyclically along the array, driving the array units to periodically change their working roles.

[0048] In practical use, the position offset device includes an N-way barrel shifter, which shifts the preset position constant sequence {0, 1, ..., N-1} to the left in a loop under the control of the loop pointer p. There is no need to perform subtraction operations for each unit separately, resulting in high hardware efficiency and small area.

[0049] The trimming code decoder receives the trimming control word T[n-1:0], decodes the trimming control word T[n-1:0] into the working window length W, that is, determines the number K of unit current mirrors in the copying state according to the decimal value t of the trimming code decoder, and further determines the value of the working window length W (W=M+K). Since M is a constant, the generation of the working window length W only requires one adder or a simple bit splicing logic. In terms of hardware, the generation of the working window length W can be achieved by combining the trimming control word T[n-1:0] with M+2 n-1 to directly obtain the sum, and it is not necessary to first obtain the number K of copying transistors and then add it to the number M of copied transistors. When the trimming control word T[n-1:0] changes, only the threshold of the working window length W needs to be updated, and there is no need to reinitialize any status register, which realizes seamless processing of dynamic switching of trimming codes.

[0050] The N groups of role decision judges are respectively connected to the position offsetter and the trimming decoder, and are configured to obtain the relative position d of each unit current mirror CM based on reception i , compare the working window length W with the number W of copied transistors in the default state, determine the working state of each unit current mirror CM, and output the enable signal to drive the switch array module.

[0051] By independently calculating the relative position for each unit current mirror CM and completing the working role judgment unit by unit current mirror CM, within N consecutive DEM clock cycles, the unit current mirror CM numbered i will sequentially go through three roles: copied, copying and silent, and its time duty cycles are M / N, K / N and (N-W) / N respectively. Therefore, in the sense of long-term average, the contribution of all N unit current mirrors CMs to the total output current is completely equivalent, device mismatch is effectively averaged and eliminated, and both static gain error and integral nonlinearity error are significantly reduced. Since the role judgment of each unit current mirror CM is completely independent, the judgment of N unit current mirrors CMs can be completed in parallel, with small logic delay and sufficient timing margin.

[0052] The specific rules for the role judgment of unit current mirror CM are as follows: When 0≤d i [j]<M is satisfied, the corresponding unit current mirror CM is allocated to the copied state, and serves as a reference current source to provide stable reference bias potential and reference current.

[0053] When M≤d i [j]<W is satisfied, the corresponding unit current mirror CM is allocated to the copying role, which is used to proportionally copy the reference current and provide adjustable output compensation current.

[0054] When W≤d iWhen j < N, the corresponding unit current mirror CM is assigned a silent role, only maintaining the potential pre-bias state and not participating in current copying output.

[0055] That is, within any dynamic element matching clock cycle, the array always maintains a steady-state distribution relationship of M copied current mirrors, K copying current mirrors, and N-W silent current mirrors in a fixed manner. The sum of the number of the three types of units is always equal to the total number of units N of the array. As the cyclic pointer p is dynamically updated, the relative position d of each unit current mirror CM i performs synchronous cyclic iteration, so that all units alternately go through the three working roles of copied, copying and silent in the time domain, realizing full-unit uniform rotation dynamic element matching. Meanwhile, by adjusting the trimming control word T[n-1:0] to change the number K of copying unit current mirrors CM and the working window length W in real time, the number of effective copying units can be accurately adjusted without disrupting the rotation mechanism, so as to realize digital trimming of current copying gain and complete the decoupling cooperative work of dynamic matching and gain trimming.

[0056] Further, as Figure 4 shows, each role decision unit comprises a first comparator, a second comparator, a first inverter, a second inverter and an AND gate.

[0057] A first input end of the first comparator is connected to the position shifter, a second input end receives the number of copied transistors in a default state, and an output end outputs a copied enable signal EN_SRC. The first input end of the first comparator receives the relative position d of the unit current mirror CM numbered i i the second input end receives the number M of the copied transistors in the default state (a fixed constant, M=2 n ). When d i is less than M, the first comparator outputs a high level, and the output end directly outputs the unit current mirror CM numbered i i corresponding copied enable signal EN_SRC i to determine that the unit current mirror CM numbered i is in a copied state. Since M is a constant, the first comparator can be further simplified into a simple size comparison between the relative position d of the unit current mirror CM i and the constant M.

[0058] A first input end of the second comparator is connected to the position shifter and receives the relative position d of the unit current mirror CM numbered i i ; a second input end is connected to the trimming code decoder and receives the working window length W. When di is less than W, the second comparator outputs a high level and outputs the working window enable signal EN_WIN corresponding to the unit current mirror CM numbered i i, indicating that the unit current mirror CM numbered i is within the working window and is in a copied state or a copying state. The working window length W is updated in real time as the trimming control word T[n-1:0] changes, so that the working window length can be adjusted flexibly.

[0059] An input terminal of the first inverter is connected to an output terminal of the first comparator, and is configured to process the copied enable signal EN_SRC corresponding to the unit current mirror CM numbered i i for inversion, and outputs an inverted copied enable signal ¬EN_SRC corresponding to the unit current mirror CM numbered i i， to provide a signal for subsequent logical operations, which is used to distinguish between the copying state and the copied state.

[0060] An input terminal of the second inverter is connected to an output terminal of the second comparator, and an output terminal outputs a silence enable signal EN_SIL corresponding to the unit current mirror CM numbered i i . The second inverter inverts the working window enable signal EN_WIN corresponding to the unit current mirror CM numbered i i to generate the silence enable signal EN_SIL corresponding to the unit current mirror CM numbered i i . When di≥W, the silence enable signal EN_SIL corresponding to the unit current mirror CM numbered i i is active at a high level, and it is determined that the unit current mirror CM numbered i is in a silence state; when di<W, the silence enable signal EN_SIL corresponding to the unit current mirror CM numbered i i outputs a low level, and the unit current mirror CM numbered i exits the silence state.

[0061] A first input terminal of the AND gate is connected to an output terminal of the first inverter, and receives the inverted copied enable signal ¬EN_SRC corresponding to the unit current mirror CM numbered i i a second input terminal of the AND gate is connected to an output terminal of the second inverter, and receives the working window enable signal EN_WIN corresponding to the unit current mirror CM numbered i i and an output terminal outputs the copying enable signal EN_REP corresponding to the unit current mirror CM numbered i i . Only when d i <M∧¬(d i <M), that is EN_WIN i ∧¬EN_SRC i is satisfied, EN_REP i is active at a high level, and it is determined that the unit current mirror CM numbered i is in the copying state.

[0062] The three enable signals are mutually exclusive at the logical level. For the same unit current mirror CM, only one enable signal is active at any given time, thus preventing a single unit current mirror CM from being assigned multiple working roles simultaneously. Within each dynamic element matching clock cycle, there are consistently M unit current mirror CMs in the replicated state, K unit current mirror CMs in the replicated state, and (NMK) unit current mirror CMs in the silent state. The sum of the total number of units corresponding to these three states is always equal to the total number of units N in the array. Even as the dynamic element matching clock continues to trigger, and all unit current mirror CMs cycle through the replicated, replicated, and silent roles, the ratio of each type of unit in the array remains constant and does not change with the pointer rotation. This ensures a stable and accurate current replication ratio throughout the complete DEM cycle, avoiding fluctuations in the output compensation current amplitude caused by dynamic switching of unit roles.

[0063] In this embodiment, as Figure 5 As shown, the current mirror circuit also includes a first non-overlapping clock generation module, which is connected to the role decision unit and is used to perform timing processing on the enable signal and output a non-overlapping enable signal EN.

[0064] When switching between operating states in adjacent clock cycles, if both switches are turned on simultaneously, the replicated bus V... SRC With the replica bus V REP Or silent bus V SIL A brief charge redistribution occurs between them, introducing current glitches. If both switches are turned off simultaneously, the drain node of the corresponding unit current mirror CM will be briefly suspended, causing the node potential to be uncertain, thus introducing setup time errors. The first non-overlapping clock generation module updates the three mutually exclusive enable signals output by the role decision unit sequentially through the master-slave latch in two non-overlapping phases of the dynamic element matching clock. It first turns off the switch that is currently on, and then turns on the switch corresponding to the target state in the next non-overlapping phase, driving the switch array module with a "turn off first, then turn on" timing to avoid the situation where two switches are turned on or off simultaneously at any time.

[0065] Through non-overlapping timing processing, all unit current mirror CM drain nodes are in a defined connection state at any time within each DEM clock cycle. This effectively suppresses transient charge disturbances during switching, ensures current continuity and phase stability, and further reduces phase noise and frequency jitter of the frequency-locked loop output clock.

[0066] In this embodiment, as Figure 2 As shown, the pre-bias module includes a reference transistor M. ref A unity-gain buffer and a first transistor M1. The reference transistor M... refThe reference transistor M has the same layout and size as the N unit current mirrors CM, uses the same process parameters and geometric dimensions as the unit current mirrors CM, and the reference transistor M... ref It does not participate in role rotation and is used to provide a stable reference potential.

[0067] The reference transistor M ref The gate and the replicated bus V SRC The reference transistor M is connected to receive the same gate bias voltage as the unit current mirror CM in the copied state; the source is connected to the power supply voltage VCCA, and the drain is connected to the non-inverting input of the unity-gain buffer. ref The bias conditions are exactly the same as those of the replicated state unit current mirror CM, and the reference transistor M ref Drain potential V REF _INT is the drain potential V of the transistor being replicated during operation. SRC The deviation is only at the mV level introduced by phase component mismatch and does not jump instantaneously with the rotation.

[0068] The inverting input and output terminals of the unity-gain buffer are both connected to the silent bus V. SIL The connection forms a unity-gain negative feedback structure, thereby forcing the silent bus V to... SIL Equal to the reference transistor M ref Drain potential V REF _INT. Through this connection method, the drain of all unit current mirrors CM in the silent state is continuously biased to almost the same potential as the drain of the replicated transistor during the silent period; once switched into replication or being replicated role, the drain potential of the unit current mirror CM does not need to be re-established, and there is no significant drain potential difference at the moment of switching, thereby almost eliminating the setup time loss and charge loss introduced by the switching transient, and avoiding the current glitches and phase disturbances of the frequency lock loop caused by them.

[0069] The gate and drain of the first transistor M1 are both connected to the inverting input of the unity-gain buffer, i.e., connected to the silent bus V. SIL The transistors are connected to form a diode connection structure, with the source of the first transistor M1 grounded.

[0070] The first transistor M1 is the silent bus V SIL Provide the necessary DC bias path. In extreme tuning conditions, if the number of unit current mirrors (CMs) in the quiescent state is zero, the quiescent bus V... SIL The first transistor M1 is still maintained at a fixed operating potential, which enables the unity-gain buffer to work stably under the full range of modulated codes, thus improving the robustness of the circuit.

[0071] Compared to the scheme that directly uses an external fixed reference voltage as the buffer input, the reference transistor M... ref As a potential reference, the silent bus V SIL It can adaptively track changes in the drain potential of the replicated transistor according to actual PVT conditions, without requiring additional PVT calibration. Compared to the approach of using the average value of the drain values ​​of multiple replicated transistors as a reference, since the reference transistor M... ref It does not participate in the rotation, its drain potential does not contain the rotation transient, the non-inverting input of the unity-gain buffer is free of glitch injection, and the silent bus V SIL The continuous and stable operation further ensures the purity of the switching timing and the stability of the circuit.

[0072] In addition, such as Figure 7 As shown in the figure, curve A represents the scheme without DEM, which has significantly higher output noise across the entire frequency band than the other two schemes, with noise gradually decreasing as the frequency increases. Curve B represents the traditional DEM scheme that is not compatible with Trim, which achieves a significant reduction in noise through dynamic component matching. Curve C represents the DEM scheme of this application that is compatible with Trim and utilizes silent devices (unit current mirrors in a silent state in the array), achieving the lowest output noise across the entire frequency range. Simulation results show that the DEM architecture can effectively suppress current mirror output noise, and this scheme, by introducing silent devices to optimize the rotation mechanism, achieves even better noise suppression compared to the traditional DEM.

[0073] Example 2 The current mirror circuit that supports dynamic component matching and adjustment described in Example 1 can be applied to circuits such as frequency lock loops, digital-to-analog converters, and low-noise reference current sources. This example uses its application in a frequency lock loop circuit for specific illustration.

[0074] like Figure 8 As shown, a frequency-locked loop circuit specifically includes a current comparison module 2, a low-pass filter, a voltage-controlled oscillator, a buffer BUF, a frequency divider, a second non-overlapping clock generation module, and a frequency-current conversion module.

[0075] Specifically, the current comparison module 2 includes the current mirror circuit 1 that supports dynamic component matching and adjustment as described in Embodiment 1. Utilizing the high-precision current replication and adjustment characteristics of the current mirror circuit 1, a precisely adjustable reference current is provided to the frequency-locked loop, thereby accurately controlling the oscillation frequency of the voltage-controlled oscillator. The current replication ratio of the current mirror circuit 1 is flexibly set by the adjustment control word T[n-1:0]. Under different PVT conditions, the output frequency of the frequency-locked loop can be adjusted to the target value. Simultaneously, the dynamic component matching rotation mechanism performs long-term time averaging on the unit current mirror CM mismatch, further eliminating residual frequency errors.

[0076] The current comparison module 2, the low-pass filter, the voltage-controlled oscillator (VCO), and the buffer BUF are connected in sequence. The buffer BUF outputs an oscillation clock signal. The output current of the current comparison module 2, after passing through the low-pass filter, outputs a control voltage VCTRL. The VCO outputs an oscillation signal based on the control voltage VCTRL. The buffer BUF shapes and enhances the oscillation signal before outputting an oscillation clock signal CLK_IMO. The VCO can be implemented using a three-stage ring VCO, whose oscillation frequency changes linearly with the control voltage VCTRL. By precisely controlling the input current, the output frequency can be locked to the target value.

[0077] The frequency divider includes a 16-divider and a 2-divider. One end of the 16-divider and the 2-divider are connected between the voltage-controlled oscillator and the buffer BUF. The other end of the 16-divider outputs a dynamic element matching clock signal CLK_DEM. The other end of the 2-divider is connected to one end of the second non-overlapping clock generation module.

[0078] The 16-divider divides the oscillation signal by 16 and outputs the dynamic element matching clock signal CLK_DEM. The CLK_DEM drives the rolling selection control logic module in the current mirror circuit 1, enabling the periodic role rotation of the unit current mirror CM. The CLK_DEM is directly derived from the frequency division output of the frequency-locked loop, eliminating the need for an additional independent clock source, thus reducing hardware overhead and power consumption. Furthermore, the frequency of the CLK_DEM maintains a fixed proportional relationship with the frequency output of the frequency-locked loop, ensuring natural coordination between the dynamic element matching timing and the operating state of the frequency-locked loop. The 2-divider divides the oscillation signal by 2 and outputs it to one end of the second non-overlapping clock generation module, providing a clock basis for the sampling and integration operations of the feedback loop.

[0079] The other end of the second non-overlapping clock generation module outputs a control signal to control the switching state of the frequency-current conversion module, generate the non-overlapping sampling and integration timing required by the frequency-locked loop feedback loop, ensure that no timing competition occurs during frequency comparison and current integration, and suppress charge injection error.

[0080] Furthermore, in this embodiment, the current comparison module 2 also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, a first operational amplifier D1, a second operational amplifier D2, and a second transistor M2.

[0081] Specifically, the first resistor R1, the second resistor R2, and the third resistor R3 are connected in series. One end of the series connection is connected to the power supply voltage VCCA, and the other end is grounded, forming a voltage divider network. This voltage divider network generates a high reference voltage VREFH (VREFH = 0.5 × VCCA) at the connection node of the first resistor R1 and the second resistor R2, and a low reference voltage VREFL (VREFL = 0.2 × VCCA) at the connection node of the second resistor R2 and the third resistor R3. These two reference voltages provide stable operating references for the two negative feedback loops of the current comparison module 2.

[0082] One end of the first capacitor C1 is connected between the first resistor R1 and the second resistor R2, and the other end is grounded. The first capacitor C1 filters and decouples the high reference voltage VREFH, suppressing the influence of power supply noise and high-frequency interference, and improving the stability of the input potential.

[0083] One end of the second capacitor C2 is connected between the second resistor R2 and the third resistor R3, and the other end is grounded. The second capacitor C2 filters and decouples the low reference voltage VREFL, suppressing power supply noise interference to the non-inverting input of the second operational amplifier D2.

[0084] One end of the current mirror circuit 1 is connected to the power supply voltage VCCA, and the other end is grounded through the fourth resistor R4. The non-inverting input of the first operational amplifier D1 is connected between the first resistor R1 and the second resistor R2, the inverting input is connected between the current mirror circuit 1 and the fourth resistor R4, and the output is connected to the current mirror circuit 1.

[0085] The drain of the second transistor M2 is connected to the other end of the current mirror circuit 1, and the source is connected to the frequency-current conversion module. The non-inverting input of the second operational amplifier D2 is connected between the second resistor R2 and the third resistor R3, receiving a low reference voltage VREFL; the inverting input is connected between the source of the second transistor M2 and the frequency-current conversion module, and the output is connected to the gate of the second transistor M2.

[0086] The source voltage of the second transistor M2 is precisely controlled to the low reference voltage VREFL through the negative feedback loop, so that the drain voltage of the second transistor M2 remains stable, reducing the impact of drain-source voltage changes on current transmission accuracy, improving the linearity of current transmission, and reducing the sensitivity of the frequency lock loop output frequency to changes in power supply voltage VCCA.

[0087] Through the dual operational amplifier dual negative feedback loop structure, the current comparison module 2 achieves precise control of the current injected into the low-pass filter. Combined with the tuning and dynamic component matching characteristics of the current mirror circuit 1, the frequency accuracy and phase noise performance of the frequency-locked loop under different PVT conditions are significantly improved.

[0088] In this embodiment, the frequency-current conversion module includes a first switch SW1, a second switch SW2, a third switch SW3, a fourth switch SW4, a first capacitor C1, and a second capacitor C2.

[0089] Specifically, the first switch SW1 and the second switch SW2 are connected in series to form the first branch; the third switch SW3 and the fourth switch SW4 are connected in series to form the second branch. The first switch SW1 and the second switch SW2 are connected in parallel with the third switch SW3 and the fourth switch SW4, that is, the first branch and the second branch are connected in parallel, with one end of the parallel connection being common and the other end being connected to the source of the second transistor M2.

[0090] The first capacitor C1 is connected in parallel with the first switch SW1. When the first switch SW1 is open, the first capacitor C1 maintains its charging voltage, providing a potential preset for the next working cycle of the first branch and reducing the setup transient when the first branch is turned on again. When the first switch SW1 is on, the first capacitor C1 is short-circuited, and the reference current is directly injected into the low-pass filter through the first branch.

[0091] The second capacitor C2 is connected in parallel with the third switch SW3. Its working mechanism is the same as that of the first capacitor C1 and the first switch SW1. It provides potential preset and charge retention functions for the second branch, ensuring the charge continuity of the two branches when they work alternately.

[0092] The first switch SW1, the second switch SW2, the third switch SW3 and the fourth switch SW4 are all driven by non-overlapping control signals. They are alternately turned on according to the "break first, turn on" timing sequence under two non-overlapping clock phases, ensuring that there is no current path in the two parallel branches at any time, thereby eliminating the situation where the two currents are injected into the low-pass filter at the same time and suppressing the control voltage VCTRL ripple caused by it.

[0093] The overall workflow of the frequency lock ring is divided into three stages: power-on startup, adjustment, and dynamic component matching.

[0094] During the power-on and startup phase, the adjustment control word T[n-1:0] is loaded with preset default values, the dynamic element matching clock signal CLK_DEM remains in an disabled state, and the modulo-N rotation counter remains reset; the frequency lock loop performs frequency capture according to the nominal current replication ratio of 1:1 to complete the initial oscillation of the loop.

[0095] During the calibration phase, the calibration control word T[n-1:0] is iteratively adjusted based on the output frequency error corresponding to the current process-voltage-temperature (PVT) conditions. The current gain is adjusted by changing the number of replication units in the array to perform coarse calibration of the output frequency, making the output frequency approach the target frequency. During this phase, the dynamic component matching clock signal CLK_DEM remains off, and the unit current mirror does not perform role rotation to avoid introducing disturbances into the frequency calibration convergence due to dynamic switching.

[0096] During the dynamic component matching phase, after the frequency-locked loop (LLL) completes locking and the output frequency stabilizes, it outputs the dynamic component matching clock signal CLK_DEM. The N unit current mirrors M within the array traverse the three working roles—SRC (Simulated Replication), REP (Replication), and SIL (Silent)—evenly and periodically according to a rotation sequence. The time-domain averaging effect of the dynamic component matching (DEM) offsets the current deviation caused by MOS device process mismatch, eliminating residual frequency errors. Simultaneously, the unit current mirrors in the silent state are continuously pre-biased, mitigating transient disturbances caused by charge redistribution during role switching, ultimately significantly reducing the phase noise of the LLL output clock and optimizing the purity of the output clock spectrum.

[0097] like Figure 9 As shown, curve A represents the frequency-locked loop circuit using the DEM scheme in this application, while curve B represents the scheme without using DEM. Across the entire frequency band, curve A is consistently below curve B, indicating that this application has lower output clock noise.

[0098] As shown in Table 1 below, the phase jitter values ​​are statistically analyzed in different frequency offset intervals, with the frequency offset unit being Hz. Across the entire integration interval, the phase jitter of the DEM scheme using Trim compatibility is significantly less than that of the scheme without DEM. Simulation results demonstrate that by dynamically matching components to average device mismatch, the output clock noise of the frequency-locked loop is effectively suppressed, phase jitter is significantly reduced, and the purity of the output clock spectrum is optimized.

[0099] Table 1

[0100] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A current mirror circuit supporting dynamic component matching and adjustment, characterized in that, This includes a rolling selection control logic module, a unit current mirror array module, a switch array module, and a pre-bias module; The rolling selection control logic module receives a dynamic element matching clock signal and a trimming control word, and is used to determine the current replication scale in real time according to the trimming control word and output an enable signal. The unit current mirror array module includes N unit current mirrors. The unit current mirror array module is connected to the rolling selection control logic module and is used to switch the N unit current mirrors to different working states in a time-division manner according to the enable signal. The pre-bias module is used to provide potential pre-compensation for the N unit current mirrors according to their different operating states.

2. The current mirror circuit supporting dynamic component matching and adjustment as described in claim 1, characterized in that, Each unit current mirror is in only one of the following states at any given time: being copied, copying, or silent. When the unit current mirror is in the replication state, the gate of the unit current mirror is connected to its own drain through the switch array module, the source is connected to the power supply voltage, and the drain is connected to the replicated bus through the switch array module. When the unit current mirror is in the replication state, the gate of the unit current mirror is connected to the replicated bus through the switch array module, the source is connected to the power supply voltage, and the drain is connected to the replication bus through the switch array module. When the unit current mirror is in a quiescent state, the gate and drain of the unit current mirror are connected to the quiescent bus through the switch array module, and the source is connected to the power supply voltage.

3. The current mirror circuit supporting dynamic component matching and adjustment as described in claim 2, characterized in that, The switch array module includes multiple switch units, and each switch unit is connected to each unit current mirror. Each of the aforementioned switching units includes a first copied bus switch, a first silent bus switch, a second copied bus switch, a copied bus switch, and a second silent bus switch; the enable signal includes a copied enable signal, a copied enable signal, and a silent enable signal; The control terminal of the first copied bus switch is connected to the copied enable signal, one end is connected to the copied bus, and the other end is connected to the gate of the unit current mirror. The control terminal of the first silent bus switch is connected to the silent enable signal, one end is connected to the silent bus, and the other end is connected to the gate of the unit current mirror. The control terminal of the second copied bus switch is connected to the copied enable signal, one end is connected to the copied bus, and the other end is connected to the drain of the unit current mirror. The control terminal of the replication bus switch is connected to the replication enable signal, one end is connected to the replication bus, and the other end is connected to the drain of the N unit current mirrors. The control terminal of the second silent bus switch is connected to the silent enable signal, one end is connected to the silent bus, and the other end is connected to the drain of the N unit current mirrors.

4. The current mirror circuit supporting dynamic component matching and adjustment as described in claim 1, characterized in that, The rolling selection control logic module includes a modulo-N rotation counter, a trimming code decoder, a position offsetter, and a role decision unit. The modulo-N cyclic counter receives a matching clock signal from the dynamic element and outputs a cyclic pointer under the drive of the matching clock signal from the dynamic element. The position offset device is connected to the modulo-N rotating counter and is used to receive the cyclic pointer and calculate the relative position for each unit current mirror based on the cyclic pointer. The tuning code decoder receives the tuning control word and decodes the tuning control word into the working window length; The role decision unit is connected to the position offset unit and the tuning decoder respectively, and is used to compare the working window length and the number of replicated tubes in the default state according to the relative position of each received unit current mirror, output the enable signal and drive the switch array module.

5. The current mirror circuit supporting dynamic component matching and adjustment as described in claim 4, characterized in that, The role decision unit includes a first comparator, a second comparator, a first inverter, a second inverter, and an AND gate; The first input of the first comparator is connected to the position offset device, the second input receives the number of the copied tubes in the default state, and the output outputs a copy enable signal. The first input of the second comparator is connected to the position offset device, and the second input is connected to the trim code decoder. The input terminal of the first inverter is connected to the output terminal of the first comparator; The input of the second inverter is connected to the output of the second comparator, and the output of the second inverter outputs a mute enable signal. The first input terminal of the AND gate is connected to the output terminal of the first inverter, the second input terminal is connected to the output terminal of the second inverter, and the output terminal outputs a copy enable signal.

6. The current mirror circuit supporting dynamic component matching and adjustment as described in claim 4, characterized in that, It also includes a first non-overlapping clock generation module, which is connected to the role decision unit and is used to perform timing processing on the enable signal and output a non-overlapping enable signal.

7. The current mirror circuit supporting dynamic component matching and adjustment as described in claim 1, characterized in that, The pre-bias module includes a reference transistor, a unity-gain buffer, and a first transistor; The gate of the reference transistor is connected to the bus being replicated, the source is connected to the power supply voltage, and the drain is connected to the non-inverting input of the unity-gain buffer. Both the inverting input and output terminals of the unity-gain buffer are connected to the silent bus. The gate and drain of the first transistor are both connected to the inverting input of the unity-gain buffer, and the source is grounded.

8. A frequency-locked loop circuit, characterized in that, It includes a current comparison module, a low-pass filter, a voltage-controlled oscillator, a buffer, a frequency divider, a second non-overlapping clock generation module, and a frequency-to-current conversion module; The current comparison module includes a current mirror circuit that supports dynamic component matching and adjustment as described in any one of claims 1-7. The current comparison module, the low-pass filter, the voltage-controlled oscillator, and the buffer are connected in sequence, and the buffer outputs an oscillation clock signal; The frequency divider includes a 16-divider and a 2-divider. One end of the 16-divider and the 2-divider are connected between the voltage-controlled oscillator and the buffer. The other end of the 16-divider outputs a dynamic element matching clock signal. The other end of the 2-divider is connected to one end of the second non-overlapping clock generation module. The other end of the second non-overlapping clock generation module outputs a control signal to control the switching state of the frequency-current conversion module.

9. The frequency-locked loop circuit as described in claim 8, characterized in that, The current comparison module further includes a first resistor, a second resistor, a third resistor, a fourth resistor, a first capacitor, a second capacitor, a first operational amplifier, a second operational amplifier, and a second transistor; The first resistor, the second resistor, and the third resistor are connected in series, with one end of the series connection connected to the power supply voltage and the other end grounded. One end of the first capacitor is connected between the first resistor and the second resistor, and the other end is grounded; One end of the second capacitor is connected between the second resistor and the third resistor, and the other end is grounded; One end of the current mirror circuit is connected to the power supply voltage, and the other end is grounded through the fourth resistor; The non-inverting input of the first operational amplifier is connected between the first resistor and the second resistor, the inverting input is connected between the current mirror circuit and the fourth resistor, and the output is connected to the current mirror circuit. The drain of the second transistor is connected to the other end of the current mirror circuit, and the source is connected to the frequency-current conversion module. The non-inverting input of the second operational amplifier is connected between the second resistor and the third resistor, the inverting input is connected between the source of the second transistor and the frequency-current conversion module, and the output is connected to the gate of the second transistor.

10. The frequency-locked loop circuit as described in claim 9, characterized in that, The frequency-current conversion module includes a first switch, a second switch, a third switch, a fourth switch, a first capacitor, and a second capacitor; The first switch and the second switch are connected in series, the third switch and the fourth switch are connected in series, the first switch and the second switch are connected in parallel with the third switch and the fourth switch, one end of the parallel connection is connected to the same point, and the other end is connected to the source of the second transistor; The first capacitor is connected in parallel with the first switch, and the second capacitor is connected in parallel with the third switch.

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