A time synchronization method, apparatus, storage medium, and electronic device

Abstract

The application discloses a time synchronization method and device, a storage medium and an electronic device, and relates to the technical field of chips. The method comprises the following steps: sending a read request to a slave computing module connected to a master computing module in a chip; receiving a request response, which is a response generated by the slave computing module to the read request; determining transmission delay information of the slave computing module relative to the master computing module according to a sending time of the read request and a receiving time of the request response; determining target time information according to the transmission delay information and a sending time of a second write request; and sending the second write request to the slave computing module, wherein the second write request contains the target time information, and the target time information is used for time synchronization between the slave computing module and the master computing module. According to the application, a special clock hardware does not need to be additionally arranged, and clock alignment between the master computing module and the slave computing module can be realized.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a time synchronization method, apparatus, storage medium and electronic device. Background Technology

[0002] In single-chip multi-die architectures, server multi-AI accelerator card clusters, and multi-node server distributed systems across switches, different dies, boards, and server nodes have independent local clock counters. Affected by factors such as the physical distance of internal chip interconnects, wafer process deviations, inter-board link transmission delays, and crystal oscillator drift, the clock counters between dies continuously experience numerical offsets. When the master and slave die counters are inconsistent, the system responsible for task scheduling cannot accurately predict the actual execution time of each distributed task and chip read / write operation, resulting in distorted task scheduling timing judgments. This directly reduces the efficiency of distributed training and online inference operations, causing significant system performance loss.

[0003] Existing clock synchronization solutions all require the slave device to actively initiate message exchanges to complete clock correction. However, in scenarios such as multi-die chips and resource-constrained embedded devices, where slave devices are prohibited from actively sending packets and are only allowed to passively respond to read and write commands from the master device, dedicated circuitry is required to complete clock correction, resulting in additional hardware costs. Therefore, there is an urgent need for a synchronization solution that can achieve master-slave die clock alignment without additional hardware. Summary of the Invention

[0004] In view of this, this application provides a time synchronization method, apparatus, storage medium and electronic device, the main purpose of which is to solve the technical problem of master-slave device clock alignment without adding dedicated hardware in scenarios where slave devices can only passively respond to instructions.

[0005] Firstly, this application provides a time synchronization method, including: Send a read request to the slave computing module connected to the main computing module in the chip; Receive request and response, the request and response containing the response time from the computing module to the read request.

[0006] Based on the sending time of the read request, the response time of the read request, and the receiving time of the request response, the time offset information of the slave computing module relative to the master computing module is determined; and based on the sending time of the read request and the receiving time of the request response, the transmission delay information of the slave computing module relative to the master computing module is determined.

[0007] If the time offset information does not meet the time synchronization execution conditions, at least one first write request is sent to the slave computing module based on the time offset information and the incremental adjustment step size. The first write request contains the current time increment information, which is used to superimpose the time information of the slave computing module to generate new time information, so as to reduce the time offset of the slave computing module relative to the master computing module.

[0008] If the time offset information meets the time synchronization execution conditions, the target time information is determined based on the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request.

[0009] A second write request is sent to the slave computing module. The second write request contains target time information, which is used for time synchronization between the slave computing module and the master computing module.

[0010] Secondly, this application provides a time synchronization device, comprising: The sending module is configured to send read requests to the slave computing module connected to the main computing module in the chip.

[0011] The receiving module is configured to receive request responses, which include the response time from the computing module to the read request.

[0012] The calculation module is configured to determine the time offset information of the calculation module relative to the main calculation module based on the sending time of the read request, the response time of the read request, and the receiving time of the request response; and to determine the transmission delay information of the calculation module relative to the main calculation module based on the sending time of the read request and the receiving time of the request response.

[0013] The sending module is also configured to send at least one first write request to the slave computing module based on the time offset information and the incremental adjustment step size if the time offset information does not meet the time synchronization execution conditions. The first write request contains the current time increment information, which is used to superimpose the time information of the slave computing module to generate new time information, so as to reduce the time offset of the slave computing module relative to the master computing module.

[0014] The determination module is configured to determine the target time information based on the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request, provided that the time offset information meets the time synchronization execution conditions.

[0015] The sending module is also configured to send a second write request to the slave computing module. The second write request contains target time information, which is used for time synchronization between the slave computing module and the master computing module.

[0016] Thirdly, this application provides a computer storage medium on which a computer program is stored, and when the computer program is executed by a processor, it implements the time synchronization method as described in the first aspect above.

[0017] Fourthly, this application provides an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement the time synchronization method described in the first aspect.

[0018] By employing the above technical solutions, this application provides a time synchronization method, apparatus, storage medium, and electronic device. Compared with existing technologies, this application eliminates the need for the computing module to actively send message interactions; clock synchronization can be achieved solely through the main computing module initiating unidirectional read / write commands, thus adapting to scenarios where the slave device passively responds to commands. This application utilizes a pure software synchronization logic where the main computing module actively sends read requests and collects round-trip timestamps to calculate latency. This eliminates the need for additional dedicated clock hardware circuitry, reducing hardware material and chip design costs. By estimating transmission latency based on send and receive timestamps and combining this with the main computing module's local counting to calculate the target time, the data is sent to the slave computing module, thereby offsetting the deviation caused by link transmission delay and achieving clock alignment between the master and slave modules. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 A flowchart illustrating a time synchronization method provided in an embodiment of this application is shown; Figure 2 This illustration shows a schematic diagram of the overall implementation process of a time synchronization method provided in an embodiment of this application; Figure 3 A schematic diagram of a coarse-tuning synchronization process provided in an embodiment of this application is shown; Figure 4 A schematic diagram of a fine-tuning synchronization process provided in an embodiment of this application is shown; Figure 5 This illustration shows a fine-tuning synchronization process adapted to a multi-die architecture, provided by an embodiment of this application. Figure 6A schematic diagram of the structure of a time synchronization device provided in an embodiment of this application is shown; Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0022] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0023] This application can be applied to, but is not limited to, the following three application scenarios: Single-chip multi-die architecture scenario: This scenario involves integrating multiple independent computing dies (modules) within a single packaged chip. The dies interact with each other through an on-chip interconnect bus. The hardware architecture limits only the master die to be able to initiate read and write operations, while the slave dies do not have the ability to actively send messages. Due to the influence of trace length and wafer process deviation, the local counting clock of each die naturally has a nanosecond-level offset. Even a tiny time difference can cause chip timing violations and task scheduling errors. Traditional hardware synchronization circuits will increase chip design and tape-out costs.

[0024] Server-based distributed cluster scenarios with multiple AI accelerator cards: This scenario is divided into two categories: single-machine multi-computing-power cards and multi-server distributed deployment across switches. It mainly carries large model training and online inference services. Some slave accelerator cards and slave servers are limited by bus protocols and switching links, and can only passively receive instructions from the master controller and cannot actively upload synchronization messages. The continuous drift of the crystal oscillators of each hardware will cause time differences, resulting in timing disorder of distributed tasks, difficulty in model convergence, and broken link tracing in system logs.

[0025] Resource-constrained embedded device scenarios: This scenario includes terminal hardware such as low-computing-power control chips and edge acquisition modules. The hardware resources are streamlined, no active message sending channel is reserved, and only passive response to master control read and write commands is supported. The device's computing power is insufficient to run bidirectional synchronization protocols such as Network Time Protocol (NTP) and Precision Time Protocol (PTP). If additional dedicated clock synchronization hardware is added, the terminal material cost will be significantly increased.

[0026] In addition, this application is also applicable to various unidirectional communication constraint systems similar to the three scenarios mentioned above, where the slave device (unit, module, die) is constrained by hardware architecture and communication protocol, and can only passively receive read and write instructions from the master device and cannot actively initiate communication messages. These will not be described in detail here.

[0027] In the above scenario, neither of the slave devices has the capability to actively send messages, and conventional bidirectional clock synchronization protocols cannot be adapted. If master-slave clock alignment is to be achieved, additional dedicated clock synchronization hardware must be added, which will lead to increased design, material, and tape-out costs.

[0028] This application relies on the pure software synchronization logic led by the master device and reuses the existing hardware counting capability. Without adding new synchronization hardware, the clock alignment of the master and slave devices can be completed by simply having the slave device passively respond.

[0029] This embodiment provides a time synchronization method. For example... Figure 1 The diagram shows a flowchart of a time synchronization method, which includes: S101. Send a read request to the slave computing module connected to the main computing module in the chip.

[0030] The main computing module is the aforementioned main die or main computing unit, and the slave computing module is the aforementioned slave die or slave computing unit. In this solution, the master and slave roles are not fixed in hardware and can be dynamically specified through system software configuration rules: any computing unit with complete timestamp reading, offset calculation, and clock sending logic can be configured as the master computing module, while units that only retain basic clock counting, passive response to read / write instructions with simplified logic, and no synchronous processing capabilities can be designated as slave computing modules. For example, when business scheduling requirements change, the configuration parameters can be modified to switch the master and slave roles. The original master computing module stops synchronous processing logic and retains only basic counting functions, downgrading to a slave computing module, while the original slave computing module loads complete synchronous processing logic and upgrades to a master module. The entire switching process does not require modification of the slave module's underlying hardware logic. The slave module only undertakes the basic functions of local clock counting and passive response to read / write interactions, and does not bear any latency measurement or offset compensation related calculations.

[0031] In one implementation, after receiving a scheduling instruction from the upper-layer system or reaching a preset periodic synchronization trigger time, the main computing module generates a read request and sends the read request to the corresponding slave computing module through the chip's internal interconnect bus. At the same time as sending the read request, the main computing module records the local time T1 when it sends the read request, which is also the time when the read request is sent.

[0032] S102. Receive the request response, which includes the response time from the computing module to the read request.

[0033] The request and response are passively generated and passively returned by the computing module. The computing module does not actively construct or actively send any interactive messages.

[0034] In one implementation, the main computing module listens to link data through the on-chip interconnect bus. When the passively generated request response is fed back from the computing module, the main computing module captures and receives the request response and records its own local reception time T4, which is also the reception time of the request response.

[0035] For example, the response time is the local hardware count value sampled when the read request is captured from the computing module hardware. The computing module only performs hardware sampling and does not perform any calculation processing. It directly encapsulates the count value into the request response and sends it back to the main computing module.

[0036] S103. Determine the time offset information of the slave computing module relative to the master computing module based on the sending time of the read request, the response time of the read request, and the receiving time of the request response; and determine the transmission delay information of the slave computing module relative to the master computing module based on the sending time of the read request and the receiving time of the request response.

[0037] In one implementation, the master computing module records the local time T1 when the read request is sent and the local time T4 when the request response is received. The difference between T4 and T1 is the total round-trip transmission delay. The total round-trip delay is divided equally to obtain the one-way transmission delay between the master and slave computing modules. This one-way transmission delay is the transmission delay information.

[0038] In one implementation, the main computing module collects multiple sets of raw one-way transmission delay values ​​multiple times, and uses EWMA filtering and integer Kalman filtering to smooth the multiple sets of raw delays, filtering out link jitter noise caused by a single measurement, and outputting a stable and smooth one-way delay as the final transmission delay information.

[0039] In one implementation, the master computing module determines the time offset information of the slave computing module relative to the master computing module based on the sending time of the read request, the receiving time of the request response, and the response time. The time offset information refers to the deviation of the slave computing module's local clock from the master computing module's local clock; a positive offset indicates that the slave computing module's clock is faster than the master computing module's clock; a negative offset indicates that the slave computing module's clock is slower than the master computing module's clock.

[0040] For example, the main computing module obtains the read request sending time T1, the request response receiving time T4, and the slave computing module's response time T2 carried in the request response; according to offset=(T1+T4) / 2 T2 completes the offset calculation, and the output offset is the time offset information. This calculation is based on the premise that the round-trip delay is evenly distributed to obtain the one-way transmission delay. After deducting the time consumption caused by link transmission, the actual clock deviation between master and slave is obtained.

[0041] S104. If the time offset information does not meet the time synchronization execution conditions, send at least one first write request to the slave computing module according to the time offset information and the incremental adjustment step size. The first write request contains the current time increment information. The time increment information is used to superimpose the time information of the slave computing module to generate new time information, so as to reduce the time offset of the slave computing module relative to the master computing module.

[0042] For example, the time synchronization execution condition is that the absolute value of the time offset between the slave computing module and the master computing module is less than or equal to a preset offset threshold. If the time offset between the master and slave computing modules is within a small range, indicating that the time offset is within the time synchronization adaptation interval, then the condition is met, and the time synchronization can be executed.

[0043] In one implementation, the main computing module compares the calculated offset with a preset offset threshold. If the absolute value of the time offset is less than or equal to the preset offset threshold, it is determined that the time synchronization execution condition is met, and the fine time synchronization process of determining the target time information and issuing the second write request continues. If the absolute value of the time offset is greater than the preset offset threshold, it means that the master-slave clock deviation is large and exceeds the adaptation range of fine synchronization. In this case, a coarse synchronization process needs to be entered first to compress the time offset to less than or equal to the preset deviation threshold before fine synchronization is enabled. This avoids synchronization anomalies caused by directly writing the clock under large offsets and ensures synchronization accuracy.

[0044] S105. If the time offset information meets the time synchronization execution conditions, determine the target time information based on the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request.

[0045] In one implementation, the main computing module calculates the target time by adding T_send, which is the local sending time T_send when the second write request is about to be issued, to the one-way transmission delay. This target time is the target time information.

[0046] For example, the numerical calculation at the target time and the second write request message packet assembly operation are completed within the same clock cycle. The second write request is sent immediately after the calculation is completed, reducing the additional time error introduced by the main calculation module.

[0047] S106. Send a second write request to the slave computing module. The second write request contains target time information, which is used for time synchronization between the slave computing module and the master computing module.

[0048] In one implementation, the main computing module sends a second write request carrying target time information to the slave computing module via the on-chip interconnect bus; after receiving the second write request, the slave computing module directly sets the atomicity of its local clock to the target time, thus completing clock synchronization with the main computing module.

[0049] It is known that after the single-chip internal multi-die clock synchronization is completed in this step, the chip can expose a standardized synchronization call interface. Server AI acceleration cards and distributed server nodes can reuse this synchronization processing logic and complete cross-device clock synchronization at the board level and server cluster level in the same working mode of master device unidirectional read and write and slave device passive response.

[0050] Compared with existing technologies, this application eliminates the need for the computing module to actively send message interactions. Clock synchronization can be achieved solely through the main computing module initiating read and write commands, thus adapting to scenarios where the slave device passively responds to commands. This application employs a pure software synchronization logic where the main computing module actively sends read requests and collects round-trip timestamps to calculate latency. This eliminates the need for dedicated clock hardware circuitry, reducing hardware material and chip design costs. By estimating transmission latency based on send and receive timestamps and combining this with the main computing module's local counting to calculate the target time, the data is sent to the slave computing module. This offsets the deviation caused by link transmission latency, achieving clock alignment between the master and slave modules.

[0051] The time synchronization method provided in the embodiments of this application will now be described in detail.

[0052] This application also provides an embodiment for sending a read request to a slave computing module connected to a master computing module in a chip. In this embodiment, the read request is sent to the slave computing module through the on-chip interconnect bus in the chip; the hardware counter in the master computing module is read to obtain the first count value of the hardware counter corresponding to the read request, and the first count value is determined as the time of sending the read request.

[0053] The on-chip interconnect bus can be a Universal Chip Interconnect Express (UCIE), a Network-on-Chip (NoC) bus, an Advanced Xtensible Interface (AXI) high-speed bus, or other inter-chip / on-chip interconnect channels. This application does not impose specific limitations on this.

[0054] It is known that for scenarios involving multi-chip interaction within AI acceleration boards and distributed clusters composed of multiple servers, the above-mentioned on-chip synchronization logic can be migrated, and high-speed inter-board interconnection links can be used to replace the internal interconnection bus of the chips. The synchronization mechanism of the master device initiating read and write requests in one direction and the slave device passively responding can still be used. Without modifying the core synchronization algorithm, cross-device clock synchronization at the board level and server cluster level can be achieved.

[0055] In one implementation, after receiving a periodic synchronization trigger signal or an upper-layer scheduling instruction, the master computing module assembles a read request message. The actions of outputting the message to the interconnect bus and sampling the hardware counter to capture the first count value are all within the same hardware counting cycle, avoiding timestamp offsets caused by crossing counting cycles. The sampled first count value is used as the transmission time of the read request. The entire process does not involve software buffering or secondary forwarding, reducing time errors introduced by software scheduling. The read request message is output to the slave computing module via the selected inter-chip or intra-chip interconnect bus.

[0056] For example, if the hardware timing constraints cannot guarantee that two actions fall within the same hardware counting cycle, the count value of the counting cycle closest to the message output action is selected as the sending time, and the corresponding cycle deviation is recorded for subsequent compensation.

[0057] The above embodiments obtain timestamps by sampling with a hardware counter, avoiding software scheduling jitter and improving the accuracy of synchronization moment acquisition.

[0058] This application also provides an embodiment for determining the transmission delay information of the slave computing module relative to the master computing module based on the sending time of the read request and the receiving time of the request response. In this embodiment, multiple basic transmission delay information is obtained based on the sending time of multiple read requests and the receiving time of multiple request responses; the multiple basic transmission delay information is smoothed to obtain smoothed transmission delay information; and the smoothed transmission delay information is determined as the transmission delay information of the slave computing module relative to the master computing module.

[0059] In one implementation, the smoothing process can employ at least one of Exponentially-Weighted Moving Average (EWMA), Integer Kalman Filter, or Median Filter, with the calculation implemented using integer count values ​​to adapt to the chip's hardware counting logic.

[0060] For example, the main calculation module continuously collects N round-trip measurements (N can be set according to requirements) to calculate N sets of original one-way basic transmission delays (multiple basic transmission delay information). First, it performs abnormal sample removal, discarding abrupt samples exceeding preset delay thresholds and filtering out abnormal data caused by instantaneous link disturbances. If EWMA is selected, it iteratively updates the valid samples according to preset weights, retaining the corresponding weights for historical delay results, assigning another portion of weight to newly collected basic transmission delays, and iteratively outputting stable delay results, which are the transmission delay information. If integer Kalman filtering is selected, preset integer measurement noise parameters and process noise parameters are configured, and the delay state is iteratively updated based on valid samples to suppress random link jitter. Finally, smoothed transmission delay information is output for subsequent target time calculation. If median filtering is selected, the multiple sets of filtered valid one-way basic transmission delays are sorted, and the delay value in the middle position after sorting is selected as the output result, avoiding interference from individual spike noise samples. The output median result is used as smoothed transmission delay information for subsequent target time calculation.

[0061] The above embodiments, through multiple sampling combined with anomaly elimination and various optional integer smoothing processes, suppress random jitter and instantaneous abnormal interference caused by interconnection links, obtain more accurate one-way transmission delay, provide reliable delay input for subsequent target time calculation, and improve the stability of clock synchronization between master and slave computing modules.

[0062] This application also provides an embodiment for determining the time offset information of the slave computing module relative to the master computing module based on the sending time of the read request, the response time of the read request, and the receiving time of the request response. In this embodiment, multiple basic time offset information is obtained based on the sending time, response time, and receiving time of multiple read requests; the multiple basic time offset information is smoothed to obtain smoothed time offset information; and the smoothed time offset information is determined as the time offset information of the slave computing module relative to the master computing module.

[0063] Optionally, the smoothing method for time offset information in this embodiment is similar to the smoothing method used for transmission delay information. At least one of exponentially weighted moving average (EWMA), integer Kalman filtering, or median filtering can be used. All calculations are implemented using integer counting values ​​to adapt to the chip's hardware counting logic. The main calculation module can simultaneously collect and perform smoothing operations on the basic transmission delay and basic time offset data in parallel during a single round-trip read request interaction. The two sets of filtering logic are independent and do not interfere with each other.

[0064] In one implementation, the main computing module continuously executes multiple rounds of read request interactions. Each round of interaction synchronously collects three sets of timestamps: T1, T2, and T4. This is done to calculate the basic transmission delay sample by calculating the original one-way delay for each round, and to use offset=(T1+T4) / 2. T2 calculates the basic time offset sample by calculating the original clock offset of a single round. Outlier removal is performed on the two types of samples respectively, discarding abrupt samples that exceed their respective preset thresholds; then, the same set of optional integer filtering logic is called in parallel to synchronously complete the smoothing iterative calculation of transmission delay and time offset, and output the stable and smoothed transmission delay information and smoothed time offset information respectively.

[0065] The above embodiments reuse the same set of integer filtering logic to process delay and offset samples in parallel, saving hardware resources, shortening calculation time, and providing stable and reliable measurement parameters for the synchronization process.

[0066] This application also provides an embodiment in which at least one first write request is sent to the slave computing module based on time offset information and incremental adjustment step size. In this embodiment, if the time offset information does not meet the time synchronization execution condition, the number of incremental processing and the time increment information corresponding to each incremental processing are determined based on the time offset information and incremental adjustment step size. The first write request is then sent to the slave computing module according to the number of incremental processing and the time increment information corresponding to each incremental processing.

[0067] The incremental adjustment step size is, for example, the maximum single time adjustment amount that will not cause business timing violations or read / write operation anomalies within the computing module.

[0068] In one implementation, when the absolute value of the time offset between the slave computing module and the master computing module is large, exceeding the fine synchronization adaptation threshold (i.e., the preset deviation threshold) (e.g., absolute offset > 1ms), a one-time absolute clock rewrite cannot be directly performed. This embodiment uses a coarse-adjustment synchronization logic with fixed step size (incremental adjustment step size) incremental compensation + retest closed-loop negative feedback to reduce the master-slave clock deviation, avoiding the problem of business timing disorder and read / write timing violations caused by a single large clock jump. Even if there is an error in the single step size estimation, it can be stably converged to the fine synchronization range through multiple retests and corrections, thereby avoiding synchronization anomalies caused by directly writing the clock under large offsets and ensuring synchronization accuracy. For example, the coarse-adjustment synchronization process includes the following steps: Step 1: The main computing module sends a read request and records the local sending time T1. It receives the request response from the computing module, which carries the local response time T2, and records the local receiving time T4. The offset is calculated as offset = (T1 + T4) / 2. T2 calculates the time offset; Step 2: Compare the absolute value of the offset with the preset threshold STEP_THRESHOLD. If the absolute value of the offset is less than or equal to the preset threshold STEP_THRESHOLD, exit the coarse adjustment synchronization process. If the absolute value of the offset is greater than the preset threshold STEP_THRESHOLD, enter the incremental compensation process.

[0069] Step 3: Combine the current offset with the fixed compensation step size STEP_SIZE to perform integer division and calculate the total number of times n (incremental processing number information) that needs to be compensated this time.

[0070] Step 4: Determine whether the calculated number of compensations n exceeds the preset maximum number of single compensations (e.g., 10 times). If it exceeds the limit, then limit n to this maximum value.

[0071] Step 5: Send a first write request carrying a fixed time increment STEP_SIZE to the slave computing module, and rewrite the local clock value of the slave computing module using a relative accumulation adjustment method.

[0072] Step 6: Wait for the preset stabilization time (e.g., 100μs) to ensure that the clock register is updated and the local counting is stable from the computing module.

[0073] Step 7: Verify whether all n compensations have been completed. If not, return to Step 5 and continue sending the first write request.

[0074] Step 8: After all compensation cycles have been completed, return to Step 1 to remeasure the time offset between the master and slave calculation modules to achieve closed-loop negative feedback control.

[0075] The above process is repeated until the absolute value of the offset obtained from the retest is less than or equal to STEP_THRESHOLD, which means that the time synchronization execution condition is met, the coarse adjustment ends and the fine adjustment synchronization process begins.

[0076] This coarse-tuning synchronization process avoids interference caused by a single large clock jump to the running program and hardware read / write timing within the computing module through step-by-step incremental compensation and closed-loop retesting mechanisms. The closed-loop retesting structure can automatically correct errors caused by step size estimation and link noise, ensuring that the offset converges stably to the fine-tuning synchronization threshold range. At the same time, it sets an upper limit on the maximum number of compensations per cycle, constraining the total number of message exchanges in the coarse-tuning synchronization process and saving interconnect bus bandwidth and chip power consumption.

[0077] Optionally, after all incremental processing has been completed based on the number of incremental processing operations, and the time offset information after incremental processing meets the time synchronization execution conditions, the target time information is determined based on the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request.

[0078] Optionally, once any incremental processing is completed and the remeasured time offset information meets the time synchronization execution conditions, the remaining incremental compensation operations will not be executed, and the fine-tuning synchronization process will be directly entered. The target time information will be determined by combining the transmission delay information and the sending time of the second write request.

[0079] After sending the second write request to the slave computing module, this application determines the interval length information for sending the next round of read requests based on the deviation degree corresponding to the time offset information. The interval length information is negatively correlated with the deviation degree. Based on the interval length information, the next round of read requests is sent to the slave computing module.

[0080] In one implementation, the master computing module compares the smoothed absolute value of the time offset with a preset error threshold (e.g., 1 μs) and classifies it into multiple interval lengths. When the absolute value of the offset is greater than the preset error threshold, it indicates that there is a significant clock deviation between the master and slave computing modules, crystal oscillator drift, or strong link jitter. In this case, a short interval length is selected to maintain high-frequency synchronization and quickly correct the clock deviation. When the absolute value of the offset is less than or equal to the preset error threshold, it indicates that the clock alignment accuracy meets the standard. In this case, a longer interval length is selected to reduce the synchronization interaction frequency. The larger the offset value, the shorter the allocated synchronization waiting interval; the two are negatively correlated. After waiting for the corresponding interval length, a read request is re-initiated (the next round of read requests), and the fine synchronization process is executed periodically.

[0081] The above embodiments measure the clock deviation amplitude based on the absolute value of the offset, dynamically and hierarchically configure the synchronization interval, and only perform high-frequency synchronization correction when the deviation is large, while reducing bus interaction when the deviation is small. This reduces the bandwidth occupation of the on-chip interconnect bus and chip power consumption while maintaining high-precision clock alignment between the master and slave computing modules in the long term.

[0082] Below, with reference to the above embodiments, some detailed embodiments applicable to the time synchronization method described in this application are introduced.

[0083] In one embodiment, such as Figure 2 The diagram illustrates the overall implementation process of a time synchronization method. The time synchronization method includes a coarse-tuning synchronization process and a fine-tuning synchronization process, wherein: S200, Startup Time Synchronization Process.

[0084] For example, the start-up trigger conditions can be system power-on initialization, setting of external synchronization enable signal, issuance of synchronization start command by upper-layer service, or switching of the internal synchronization state machine of the main computing module to working state.

[0085] S201, Coarse adjustment of the synchronization process, obtaining the time offset information of the slave computing module relative to the master computing module.

[0086] For example, the main computing module sends a read request and records the local sending time T1; it receives a request response from the computing module carrying the local response time T2 and records the local receiving time T4, based on offset = (T1 + T4) / 2. T2 calculation yields the original (basic) time offset information.

[0087] S202. Determine whether the absolute value of the offset is greater than the preset coarse adjustment threshold.

[0088] If the determination is yes, then execute S203; if the determination is no, then execute S204.

[0089] S203. Perform step-by-step compensation according to step size and time increment.

[0090] For example, based on the current time offset and a fixed compensation step size, the total number of compensations n is calculated by integer division. If the calculated n exceeds the preset maximum number of single compensations, then n is limited to this maximum value. The first write request carrying the corresponding time increment is sent to the slave computing module in stages, and the clock of the slave computing module is adjusted by accumulating in a relative increment manner to avoid a large jump in the clock value at one time. After each compensation operation is completed, a preset clock stabilization time is waited for the slave computing module to complete register updates and hardware count stabilization. After all n compensations are completed, the process returns to S201 to reacquire the time offset information between the master and slave, forming a coarse-adjustment closed-loop negative feedback control.

[0091] S204. Fine-tune the synchronization process and obtain basic transmission delay information and basic time offset information of multiple master and slave computing modules.

[0092] For example, the master computing module and the slave computing module conduct bidirectional time interaction, repeatedly initiating multiple rounds of read request round-trip interaction; in each round of interaction, the read request sending time T1, the slave computing module response time T2, and the master computing module receiving response time T4 are synchronously collected, and the original transmission delay sample and basic time offset sample of a single round are calculated respectively, and multiple sets of basic transmission delay information and basic time offset information are output for subsequent smoothing processing.

[0093] S205, Smoothing process.

[0094] For example, outlier removal is first performed on multiple sets of basic transmission delay information and multiple sets of basic time offset information, discarding abrupt changes that exceed their respective preset thresholds. Considering the limited chip hardware resources and the lack of a floating-point arithmetic unit, an integer filtering algorithm is used. For example, at least one of the following can be selected: EWMA filter (weight α=1 / 8), median filter, or two-dimensional state integer Kalman filter. Smoothing iterations are performed on both types of information in parallel, outputting smoothed transmission delay information and smoothed time offset information.

[0095] S206. Calculate the target time information.

[0096] For example, the target time information that should be written by the calculation module is calculated based on the smoothed transmission delay information, and the target time information is sent to the calculation module through the second write request to complete the clock calibration.

[0097] S207. Determine whether to continue synchronization.

[0098] For example, the determination is made based on the upper-layer business instructions, the synchronization enable status, and the clock synchronization accuracy conditions. If the upper layer has not issued a stop synchronization instruction, and the business still needs the master-slave computing modules to maintain time synchronization, then it is determined as yes; if a synchronization stop instruction is received, or the business no longer needs the time synchronization service, then it is determined as no.

[0099] If the determination is yes, return to S204; at the same time, determine the interval length information of the next round of read requests based on the degree of deviation of the current smoothed time offset information. The degree of deviation is negatively correlated with the interval length information. Wait for the corresponding interval length before executing S204 again, and periodically carry out the fine synchronization process.

[0100] S208, End Time Synchronization Process.

[0101] In one embodiment, such as Figure 3 The diagram illustrates a coarse-tuning synchronization process. The specific steps of the coarse-tuning synchronization process are as follows: S301, The main computing module sends a read request, and the time T1 when the main computing module sends the request is recorded.

[0102] S302. After receiving the read request from the computing module, return a request response, which carries the response time T2.

[0103] S303, The main computing module receives the request response and records the receiving time T4.

[0104] S304. Calculate time offset information.

[0105] S305. Determine whether the absolute value of the offset is greater than the preset threshold STEP_THRESHOLD.

[0106] The preset threshold STEP_THRESHOLD is the coarse adjustment threshold in S202 above. If the determination is negative, the process jumps to the fine adjustment synchronization process; if the determination is positive, S306 is executed.

[0107] S306. Calculate the number of compensations, n.

[0108] S307. Is the number of compensation attempts n greater than the preset maximum number of attempts?

[0109] If the determination is yes, then execute S308; if the determination is no, then execute S309.

[0110] S308. Set the number of compensations n to the preset maximum number of compensations.

[0111] S309. Send the STEP_SIZE command to the slave computing module.

[0112] Adding the STEP_SIZE command is the same as the first write request in the example above.

[0113] S310, Waiting for the clock from the computing module to stabilize.

[0114] For example, wait 100μs for the computation module to complete register updates and stabilize the internal clock level.

[0115] S311. Determine whether n compensations have been completed.

[0116] If the determination is negative, execute S309 and continue to issue the STEP_SIZE command; if the determination is positive, return to S301 and re-execute the read request interactive measurement offset to form a coarse adjustment closed-loop negative feedback, and iterate repeatedly until the absolute value of the offset is less than or equal to the preset threshold STEP_THRESHOLD.

[0117] In one embodiment, such as Figure 4 The diagram shows a fine-tuning synchronization process. The specific steps of the fine-tuning synchronization process are as follows: S401, The main computing module sends a read request, and the time T1 when the main computing module sends the request is recorded.

[0118] S402. Receive a read request from the computing module and record the receiving time T2.

[0119] S403. Prepare the request response from the calculation module, record the sending time T3, and carry the timestamp information T2 and T3 in the request response.

[0120] For example, the request and response are assembled from the computing module, the time when the request and response are sent is captured to obtain T3, and T2 and T3 are encapsulated into the request and response.

[0121] S404, Send a request response from the computing module.

[0122] S405. The main computing module receives the request response and records the reception time T4.

[0123] S406. Calculate the basic time offset information and the basic transmission delay information.

[0124] For example, based on the interactive timestamps T1, T2, T3, and T4, the basic time offset information offset and the basic transmission delay information delay are calculated.

[0125] S407. Filtering and smoothing process to obtain smoothed time offset information and smoothed transmission delay information.

[0126] For example, outlier removal is performed on multiple sets of basic time offset information and basic transmission delay information; an integer filtering algorithm is used to perform smoothing iterative calculations on the two types of information in parallel, and the time offset information est_offset and the transmission delay information est_delay are output.

[0127] S408, The main calculation module records the current transmission time.

[0128] For example, when the main computing module is preparing to issue a write command, it captures the local current time and records it as T_send, which is also the time when the second write request is sent.

[0129] S409. Calculate the target time information.

[0130] S410, Send the first write command, which carries the target time information.

[0131] S411. Set the clock from the atomic setting of the calculation module to the target time information to complete the clock calibration.

[0132] For example, atomic write operations are used to ensure that the clock of the computing module is updated to the target time information in one go, avoiding errors in intermediate states.

[0133] S412. Determine whether the absolute value of the current offset error is less than the preset threshold.

[0134] If the determination is yes, execute S413; if the determination is no, execute S414.

[0135] S413. Reduce the synchronization frequency and configure a longer synchronization interval.

[0136] S414. Maintain high-frequency synchronization and configure a shorter synchronization interval.

[0137] S415, Waiting for synchronization interval duration.

[0138] After the synchronization interval expires, return to S401 and periodically execute the fine synchronization process.

[0139] In one embodiment, such as Figure 5 The diagram illustrates a fine-tuning synchronization process adapted to a multi-die architecture. The specific steps of the fine-tuning synchronization process are as follows: S501, The main die calculation module sends a read request and records the main die sending time T1.

[0140] S502, Receive a read request from the Die calculation module and record the receiving time T2.

[0141] S503. The Die calculation module returns a request response, which carries the receiving time T2.

[0142] S504, the main die calculation module receives the request response and records the reception time T4.

[0143] S505, Calculate basic transmission delay information.

[0144] S506, Integer filtering and smoothing process, to obtain smoothed transmission delay information.

[0145] S507, the main die calculation module records the current transmission time.

[0146] S508, Calculate the target time information.

[0147] For example, the target time information target is calculated based on the smoothed transmission delay information filtered_d. Where target = T_send + filtered_d.

[0148] S509. Send the first write command, which carries the target time information.

[0149] S510: Set the clock from the Die calculation module atomically to the target time information to complete cross-Die clock calibration.

[0150] S511, Waiting for synchronization interval duration.

[0151] For example, the synchronization interval can be configured to 1 second; after the synchronization interval expires, return to S501 and periodically execute the fine synchronization process under the multi-die architecture.

[0152] In this embodiment, for multi-die cross-die communication scenarios, a simplified set of three timestamps (T1, T2, T4) is used to complete the delay and offset calculations, and integer filtering is used to suppress cross-die link noise interference. The master die calculates the target time only based on the smoothed one-way delay, and atomic clocks are written from the dies, periodically synchronizing to achieve high-precision clock alignment between multiple dies, adapting to the Chiplet hardware integer operation environment.

[0153] Compared with existing technologies, this application eliminates the need for the computing module to actively send message interactions. Clock synchronization can be achieved solely through the main computing module initiating read and write commands, thus adapting to scenarios where the slave device passively responds to commands. This application employs a pure software synchronization logic where the main computing module actively sends read requests and collects round-trip timestamps to calculate latency. This eliminates the need for dedicated clock hardware circuitry, reducing hardware material and chip design costs. By estimating transmission latency based on send and receive timestamps and combining this with the main computing module's local counting to calculate the target time, the data is sent to the slave computing module. This offsets the deviation caused by link transmission latency, achieving clock alignment between the master and slave modules.

[0154] In addition, this application also has the following technical advantages: Firstly, a two-stage synchronization mechanism—coarse adjustment and fine adjustment—is distinguished to balance convergence speed and synchronization accuracy. When a large offset is detected during the coarse adjustment stage, a step-by-step incremental compensation strategy is adopted. An upper limit protection restricts the maximum number of compensations per cycle to avoid clock step jumps. The iterative closed loop compresses the clock offset to within the threshold before entering the fine adjustment process. This can quickly eliminate large initial clock deviations between master and slave, while avoiding business timing errors caused by directly writing large values ​​to the clock.

[0155] Secondly, the fine-tuning process supports two timestamp acquisition modes, adaptable to different die hardware resource conditions. When hardware resources are sufficient, it can acquire both the receiving and sending timestamps from the die, enabling more precise latency and offset assessment. When the die hardware capabilities are limited and cannot capture the message sending time, it can complete the synchronization calculation based solely on the receiving timestamp, which is compatible with the hardware constraints of some die modes in the Chiplet multi-die architecture where only passive acknowledgment is supported, making the solution more flexible in hardware adaptation.

[0156] Thirdly, all operations employ integer filtering, eliminating the need for floating-point units. Multiple sets of delay and offset information obtained from round-trip acquisition are processed with anomaly removal and integer smoothing iterations to suppress random noise and jitter caused by cross-die interconnect links. This eliminates the need for chip-configured floating-point IP, saving chip computing power and area costs, and facilitating RTL hardware implementation.

[0157] Fourthly, it has the ability to dynamically and adaptively adjust the synchronization interval. The synchronization frequency is dynamically adjusted according to the magnitude of the real-time clock offset error. When the error is large, the synchronization interval is shortened to maintain high-frequency synchronization. After the error converges, the synchronization interval is lengthened to reduce the interaction frequency. While ensuring synchronization accuracy, the number of cross-die message interactions is reduced, and the bandwidth occupation of the on-chip interconnect bus is reduced.

[0158] Fifthly, atomic clock write operations are adopted from the computing module side. The target time is written all at once, avoiding intermediate illegal timing states caused by step-by-step clock updates, reducing the risk of synchronization failure caused by message jitter and out-of-order delivery during cross-die instruction transmission, and improving the reliability of clock synchronization in multi-die systems.

[0159] Furthermore, as Figures 1 to 5 The specific implementation of the method shown in this embodiment provides a time synchronization device, such as... Figure 6 The diagram shows the structure of a time synchronization device 600, which includes a transmitting module 610, a receiving module 620, a calculation module 630, and a determining module 640; wherein: The sending module 610 is configured to send a read request to the slave computing module connected to the main computing module in the chip.

[0160] The receiving module 620 is configured to receive a request response, which includes the response time from the computing module to the read request.

[0161] The calculation module 630 is configured to determine the time offset information of the slave calculation module relative to the master calculation module based on the sending time of the read request, the response time of the read request, and the receiving time of the request response; and to determine the transmission delay information of the slave calculation module relative to the master calculation module based on the sending time of the read request and the receiving time of the request response.

[0162] The sending module 610 is also configured to send at least one first write request to the slave computing module based on the time offset information and the incremental adjustment step size when the time offset information does not meet the time synchronization execution conditions. The first write request contains the current time increment information, which is used to superimpose the time information of the slave computing module to generate new time information, so as to reduce the time offset of the slave computing module relative to the master computing module.

[0163] The determination module 640 is configured to determine the target time information based on the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request, provided that the time offset information meets the time synchronization execution conditions.

[0164] The sending module 610 is also configured to send a second write request to the slave computing module. The second write request contains target time information, which is used for time synchronization between the slave computing module and the master computing module.

[0165] It should be noted that other corresponding descriptions of the functional units involved in the time synchronization device provided in this embodiment can be found in [reference]. Figures 1 to 5 The corresponding description in [the document] will not be repeated here.

[0166] Based on the above, Figures 1 to 5Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figures 1 to 5 The method shown.

[0167] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0168] like Figure 7 The diagram shown is a hardware structure schematic of an electronic device according to the present invention, comprising: At least one processor 701; and, A memory 702 is communicatively connected to at least one of the processors 701; wherein, The memory 702 stores instructions that can be executed by at least one of the processors to enable the at least one of the processors to perform the time synchronization method as described above.

[0169] Figure 7 Take the 701 processor as an example.

[0170] The electronic device may also include an input device 703 and a display device 704.

[0171] The processor 701, memory 702, input device 703, and display device 704 can be connected via a bus or other means. Figure 7 Taking the example of a connection between China and Israel via a bus.

[0172] The memory 702, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the time synchronization method in the embodiments of this application, for example, Figures 1 to 5 The method flow is shown. The processor 701 executes various functional applications and data processing by running non-volatile software programs, instructions, and modules stored in the memory 702, thereby implementing the time synchronization method in the above embodiments.

[0173] The memory 702 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the time synchronization method, etc. Furthermore, the memory 702 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory 702 may optionally include memory remotely located relative to the processor 701, and these remote memories may be connected to the apparatus performing the time synchronization method via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0174] The input device 703 can receive user clicks and generate signal inputs related to user settings and function control for time synchronization methods. The display device 704 may include a display screen or other display device.

[0175] When one or more modules are stored in the memory 702, and are run by one or more processors 701, the time synchronization method in any of the above method embodiments is executed.

[0176] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0177] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0178] The storage medium may also include an operating system and a network communication module. The operating system is a program that manages the hardware and software resources of the aforementioned physical device, supporting the operation of information processing programs and other software and / or programs. The network communication module is used to enable communication between the various components within the storage medium, as well as communication with other hardware and software in the information processing physical device.

[0179] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. By applying the solution of this embodiment, compared with the prior art, this application does not require the computing module to actively send message interaction, but only relies on the main computing module to unidirectionally initiate read and write commands to complete clock synchronization, adapting to the constraint scenario where the slave device only passively responds to commands. This application uses pure software synchronization logic to actively issue read requests and collect round-trip timestamps to complete latency calculation, without the need for additional dedicated clock hardware circuits, reducing hardware material and chip design costs; it estimates the transmission latency based on the send and receive timestamps, and after combining the target time calculated by the local counting of the main computing module, it sends it to the slave computing module, thereby offsetting the deviation caused by the link transmission delay and realizing clock alignment between the master and slave modules.

[0180] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0181] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A time synchronization method, characterized in that, include: Send a read request to the slave computing module connected to the main computing module in the chip; Receive a request response, the request response including the time of the response from the computing module to the read request; Based on the sending time of the read request, the response time of the read request, and the receiving time of the request response, the time offset information of the slave computing module relative to the master computing module is determined; And determine the transmission delay information of the slave computing module relative to the master computing module based on the sending time of the read request and the receiving time of the request response; If the time offset information does not meet the time synchronization execution conditions, at least one first write request is sent to the slave computing module according to the time offset information and the incremental adjustment step size. The first write request contains the current time increment information. The time increment information is used to superimpose the time information of the slave computing module to generate new time information, so as to reduce the time offset of the slave computing module relative to the master computing module. If the time offset information satisfies the time synchronization execution condition, the target time information is determined based on the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request. A second write request is sent to the slave computing module. The second write request contains the target time information, which is used for time synchronization between the slave computing module and the master computing module. Determining the time offset information of the slave computing module relative to the master computing module based on the sending time of the read request, the response time of the read request, and the receiving time of the request response includes: obtaining multiple basic time offset information based on multiple sending times and response times of the read requests and multiple receiving times of the request responses; smoothing the multiple basic time offset information to obtain smoothed time offset information; and determining the smoothed time offset information as the time offset information of the slave computing module relative to the master computing module. Sending at least one first write request to the slave computing module based on the time offset information and the incremental adjustment step size includes: determining the number of incremental processing steps and the time increment information corresponding to each incremental processing step based on the time offset information and the incremental adjustment step size; and sending the first write request to the slave computing module according to the number of incremental processing steps and the time increment information corresponding to each incremental processing step.

2. The method according to claim 1, characterized in that, Determining the transmission delay information of the slave computing module relative to the master computing module based on the sending time of the read request and the receiving time of the request response includes: Based on the sending time of the multiple read requests and the receiving time of the multiple request responses, multiple basic transmission delay information is obtained; The multiple basic transmission delay information is smoothed to obtain smoothed transmission delay information; The smoothed transmission delay information is determined as the transmission delay information of the slave computing module relative to the master computing module.

3. The method according to claim 1, characterized in that, The method further includes: After all incremental processing has been completed according to the incremental processing count information, and the time offset information after incremental processing satisfies the time synchronization execution condition, the target time information is determined according to the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request.

4. The method according to claim 1, characterized in that, Sending a read request to the slave computing module connected to the main computing module in the chip includes: A read request is sent to the slave computing module via the on-chip interconnect bus in the chip; The hardware counter in the main computing module is read to obtain the first count value of the hardware counter corresponding to the read request, and the first count value is determined as the time when the read request is sent.

5. The method according to claim 1, characterized in that, After sending the second write request to the computing module, the method further includes: Based on the degree of deviation corresponding to the time offset information, the interval duration information for sending the next round of read requests is determined, and the interval duration information is negatively correlated with the degree of deviation; Based on the interval duration information, the next round of read request is sent to the slave computing module.

6. A time synchronization device, characterized in that, include: The sending module is configured to send read requests to the slave computing module connected to the main computing module in the chip. The receiving module is configured to receive a request response, the request response including the response time of the computing module to the read request; The calculation module is configured to determine the time offset information of the slave calculation module relative to the master calculation module based on the sending time of the read request, the response time of the read request, and the receiving time of the request response; And determine the transmission delay information of the slave computing module relative to the master computing module based on the sending time of the read request and the receiving time of the request response; The sending module is further configured to send at least one first write request to the slave computing module according to the time offset information and the incremental adjustment step size when the time offset information does not meet the time synchronization execution condition. The first write request includes the current time increment information, which is used to superimpose the time information of the slave computing module to generate new time information, so as to reduce the time offset of the slave computing module relative to the master computing module. The determining module is configured to determine the target time information based on the transmission delay information of the slave computing module relative to the master computing module and the sending time of the second write request, provided that the time offset information satisfies the time synchronization execution condition. The sending module is further configured to send a second write request to the slave computing module, the second write request containing the target time information, the target time information being used for time synchronization between the slave computing module and the master computing module; The calculation module, which determines the time offset information of the slave calculation module relative to the master calculation module based on the sending time of the read request, the response time of the read request, and the receiving time of the request response, is configured to: obtain multiple basic time offset information based on multiple sending times, response times, and multiple receiving times of the request responses; The multiple basic time offset information is smoothed to obtain smoothed time offset information; The smoothed time offset information is determined as the time offset information of the slave computing module relative to the master computing module; The sending module, which executes the step of sending at least one first write request to the calculation module based on the time offset information and the incremental adjustment step size, is configured to: determine the number of incremental processing steps and the time increment information corresponding to each incremental processing step based on the time offset information and the incremental adjustment step size. The first write request is sent to the slave computing module according to the number of incremental processing operations and the time increment information corresponding to each incremental processing operation.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 5.

8. An electronic device comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 5.

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