Memory management method, storage device, and host system

Abstract

The present application provides a memory management method, a storage device and a host system. The method comprises: obtaining a first write instruction from the host system, the first write instruction indicating writing target data to a target logical unit; performing a data write operation corresponding to the target logical unit according to the first write instruction; in response to the first write instruction meeting a preset condition, returning physical identification information of at least one target physical unit mapped by the target logical unit to the host system; and if the first write instruction does not meet the preset condition, not returning the physical identification information to the host system. Thus, the access performance of the data storage system for specific types of data can be effectively improved without affecting the normal operation of the data storage system as much as possible.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and more particularly to a memory management method, storage device, and host system. Background Technology

[0002] With the continuous development of artificial intelligence technology, the collaborative performance between the host system and storage devices is gradually becoming a key factor affecting the overall computing speed of the device. Once the collaborative performance between the host system and storage devices (such as read and write speeds) cannot keep up with the computing speed of the artificial intelligence chip, no matter how much the computing speed of the artificial intelligence chip improves, the overall computing speed of the device may still be lower than expected. Summary of the Invention

[0003] This invention provides a memory management method, a storage device, and a host system, which can effectively improve the access performance of a data storage system for specific types of data without affecting the normal operation of the data storage system as much as possible.

[0004] This invention provides a memory management method for a storage device, the storage device including a memory module, and the memory management method comprising: obtaining a first write instruction from a host system, wherein the first write instruction is used to instruct target data to be written to a target logical unit; performing a data write operation corresponding to the target logical unit according to the first write instruction; in response to the first write instruction meeting a preset condition, sending back entity identification information of at least one target entity unit mapped to the target logical unit to the host system; and if the first write instruction does not meet the preset condition, not sending back the entity identification information to the host system.

[0005] This invention also provides a storage device, which includes a connection interface, a memory module, and a memory controller. The connection interface is used to connect to a host system. The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute a memory management method.

[0006] This invention also provides a memory management method for a host system connected to a storage device. The memory management method includes: sending a write instruction based on target data, wherein the write instruction indicates that the target data is written to a target logical unit; after sending the write instruction, obtaining entity identification information of at least one target entity unit from the storage device, wherein the at least one target entity unit is mapped to a target logical unit; and storing the entity identification information in a buffer memory of the host system.

[0007] Another embodiment of the present invention provides a host system including a processor and a buffer memory. The buffer memory is connected to the processor. The processor executes a memory management method.

[0008] This invention also provides a memory management method for a storage device, the storage device including a memory module, and the memory management method comprising: obtaining a query instruction from a host system; obtaining initial mapping information corresponding to a target logical range according to the query instruction, wherein the initial mapping information reflects the mapping relationship between at least one candidate logical unit belonging to the target logical range and at least one candidate entity unit in the memory module; and providing the initial mapping information to the host system.

[0009] Based on the above, this embodiment of the invention, by sending entity identification information back to the host system after writing data, providing initial mapping information to the host system according to query instructions, and caching entity identification information by the host system, enables the host system to more effectively utilize the mapping information for subsequent data access. Thus, it can effectively improve the access performance of the data storage system for specific types of data without significantly affecting the normal operation of the data storage system. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention;

[0011] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention;

[0012] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention;

[0013] Figure 4 This is a schematic diagram illustrating how entity identification information is included in response information and sent back to the host system according to a first write instruction, as shown in an embodiment of the present invention.

[0014] Figure 5 This is a schematic diagram of the mapping information pairs shown in an embodiment of the present invention;

[0015] Figure 6 This is a schematic diagram illustrating how entity identification information is carried along with transmission readiness information and response information and transmitted back to the host system according to a first write instruction, based on an embodiment of the present invention.

[0016] Figure 7 This is a schematic diagram illustrating the acquisition of initial mapping information according to an embodiment of the present invention;

[0017] Figure 8 This is a flowchart illustrating a memory management method according to an embodiment of the present invention;

[0018] Figure 9 This is a flowchart illustrating a memory management method according to an embodiment of the present invention;

[0019] Figure 10 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Detailed Implementation

[0020] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0021] Figure 1 This is a schematic diagram of a data storage system according to an embodiment of the present invention. Please refer to... Figure 1 The data storage system 10 includes a host system 11 and a storage device 12. The storage device 12 can be connected to the host system 11 and can be used to store data from the host system 11. For example, the host system 11 can be a smartphone, tablet computer, laptop computer, desktop computer, industrial computer, game console, server, or computer system installed in a specific carrier (such as a vehicle, aircraft, or ship), and the type of host system 11 is not limited to these. In addition, the storage device 12 may include a solid-state drive, USB flash drive, memory card, or other types of non-volatile storage device.

[0022] The host system 11 may include a processor 111 and a buffer memory 112. The processor 111 is used to handle all or part of the operation of the host system 11. For example, the processor 111 may include a central processing unit (CPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0023] Buffer memory 112 is connected to processor 111 and used to cache data. For example, buffer memory 112 may include static random access memory (SRAM), dynamic random access memory (DRAM), or other types of volatile memory. Buffer memory 112 can be used as the main memory of host system 11. In addition, host system 11 may also include various hardware circuit modules such as power management circuitry, mouse, keyboard, screen, and / or wired / wireless communication circuitry, which will not be described in detail here.

[0024] Storage device 12 includes a connection interface 121, a memory module 122, and a memory controller 123. The connection interface 121 is used to connect storage device 12 to host system 11. For example, connection interface 121 may support embedded multi-media card (eMMC), universal flash storage (UFS), peripheral component interconnect express (PCI Express), non-volatile memory express (NVM express), Serial Advanced Technology Attachment (SATA), universal serial bus (USB), or other types of connection interface standards. Therefore, storage device 12 can communicate with host system 11 (e.g., exchange signals, instructions, and / or data) via connection interface 121.

[0025] Memory module 122 is used to store data. For example, memory module 122 may include one or more rewritable non-volatile memory modules. Each rewritable non-volatile memory module may include one or more memory cell arrays. The memory cells in the memory cell array store data in the form of voltage (also known as threshold voltage). For example, memory module 122 may include a Single Level Cell (SLC) NAND flash memory module, a Multi Level Cell (MLC) NAND flash memory module, a Triple Level Cell (TLC) NAND flash memory module, a Quad Level Cell (QLC) NAND flash memory module, and / or other memory modules with the same or similar characteristics.

[0026] Memory controller 123 is connected to connection interface 121 and memory module 122. Memory controller 123 can be considered the control core of storage device 12 and is used to control storage device 12. For example, memory controller 123 can be used to control or manage the overall or partial operation of storage device 12. For example, memory controller 123 may include a CPU, or other programmable general-purpose or special-purpose microprocessor, DSP, programmable controller, ASIC, PLD, or other similar device or a combination of these devices. In one embodiment, memory controller 123 may include a flash memory controller.

[0027] The memory controller 123 can send instruction sequences to the memory module 122 to access the memory module 122. For example, the memory controller 123 can send a write instruction sequence to the memory module 122 to instruct the memory module 122 to store data in a specific memory cell. For example, the memory controller 123 can send a read instruction sequence to the memory module 122 to instruct the memory module 122 to read data from a specific memory cell. For example, the memory controller 123 can send an erase instruction sequence to the memory module 122 to instruct the memory module 122 to erase data stored in a specific memory cell. Furthermore, the memory controller 123 can also send other types of instruction sequences to the memory module 122 to instruct the memory module 122 to perform other types of operations; this invention is not limited thereto. The memory module 122 can receive instruction sequences from the memory controller 123 and access its internal memory cells according to these instruction sequences.

[0028] Figure 2 This is a schematic diagram of a memory controller according to an embodiment of the present invention. Please refer to... Figure 1 and Figure 2 The memory controller 123 includes a host interface 21, a memory interface 22, and a memory control circuit 23. The host interface 21 is used to connect to the host system 11 via the connection interface 121 to communicate with the host system 11. The memory interface 22 is used to connect to the memory module 122 to access the memory module 122.

[0029] Memory control circuitry 23 is connected to host interface 21 and memory interface 22. Memory control circuitry 23 can be used to control or manage the overall or partial operation of memory controller 123. For example, memory control circuitry 23 can communicate with host system 11 via host interface 21 and access memory module 122 via memory interface 22. For example, memory control circuitry 23 may include control circuitry such as embedded controllers or microcontrollers. In the following embodiments, the description of memory control circuitry 23 is equivalent to the description of memory controller 123.

[0030] In one embodiment, the memory controller 123 may further include a buffer memory 24. The buffer memory 24 is connected to the memory control circuitry 23 and is used to cache data. For example, the buffer memory 24 may be used to cache instructions from the host system 11, data from the host system 11, and / or data from the memory module 122. The buffer memory 24 may include SRAM, DRAM, or other types of volatile memory.

[0031] In one embodiment, the memory controller 123 may further include a decoding circuit 25. The decoding circuit 25 is connected to the memory control circuit 23 and is used to encode and decode data to ensure data integrity. For example, the decoding circuit 25 may support various encoding / decoding algorithms such as Low Density Parity Check code (LDPC code), BCH code, Reed-solomon code (RS code), and Exclusive OR (XOR) code. In one embodiment, the memory controller 123 may also include other types of circuit modules (e.g., power management circuits), which are not limited by the present invention.

[0032] Figure 3 This is a schematic diagram of a memory management module according to an embodiment of the present invention. Please refer to... Figures 1 to 3 The memory module 122 includes multiple physical units 301(1) to 301(C). Each physical unit includes multiple storage units for non-volatile storage of data.

[0033] In one embodiment, an entity unit may include at least one entity programmable unit. For example, an entity programmable unit is the smallest unit of synchronously written data in memory module 122. For example, when performing a programming operation (also called a write operation) on an entity programmable unit to write data to that entity programmable unit, multiple memory cells in that entity programmable unit may be synchronously programmed to store the corresponding data. For example, when programming an entity programmable unit, a write voltage may be applied to that entity programmable unit to change the threshold voltage of at least some of the memory cells in that entity programmable unit. For example, the threshold voltage of a memory cell may reflect the bit data stored in that memory cell. In one embodiment, an entity programmable unit is also referred to as an entity page. For example, the storage capacity of an entity programmable unit may be 16 kilobytes, and the invention is not limited thereto.

[0034] In one embodiment, an entity programming unit includes multiple entity sectors. For example, the data capacity of an entity sector may be 512 bytes (B), and an entity programming unit may include 32 entity sectors. However, the data capacity of an entity sector and / or the total number of entity sectors included in an entity programming unit can be adjusted according to practical needs, and the present invention is not limited thereto.

[0035] In one embodiment, a physical erase unit may include multiple physical programmable units. For example, the multiple physical programmable units in a physical erase unit may be erased simultaneously. For example, when an erase operation is performed on a physical erase unit, an erase voltage may be applied to the multiple physical programmable units in this physical erase unit to change the threshold voltage of at least a portion of the memory cells in these physical programmable units. By performing an erase operation on a physical erase unit, the data stored in this physical erase unit can be erased. In one embodiment, a physical erase unit is also referred to as a physical block.

[0036] In one embodiment, an entity unit may include at least one entity erasure unit. In another embodiment, if an entity unit includes multiple entity erasure units, this entity unit is also referred to as a virtual block. Multiple entity erasure units contained in the same virtual block can operate synchronously.

[0037] In one embodiment, the memory control circuit 23 can logically associate entity units 301(1)-301(A) and 301(A+1)-301(B) with the data area 31 and the idle area 32, respectively. Entity units 301(1)-301(A) in the data area 31 all store data (also called user data) from the host system 11. For example, any entity unit in the data area 31 can store valid data and / or invalid data. In addition, entity units 301(A+1)-301(B) in the idle area 32 do not store any data (e.g., valid data).

[0038] In one embodiment, if a certain entity unit does not store valid data, this entity unit can be associated with the free area 32. Furthermore, entity units in the free area 32 can be erased to clear the data in that entity unit. In one embodiment, entity units in the free area 32 are also referred to as idle entity units. In one embodiment, the free area 32 is also referred to as the free pool.

[0039] In one embodiment, when data needs to be stored, the memory control circuit 23 can select one or more physical units from the idle area 32 and instruct the memory module 122 to store the data into the selected physical units. After the data is stored into this physical unit, this physical unit can be associated with the data area 31. In other words, one or more physical units can be used alternately between the data area 31 and the idle area 32.

[0040] In one embodiment, the memory control circuit 23 may be configured with multiple logic units 302(1)-302(C) to map physical units (i.e., physical units 301(1)-301(A)) in the data area 31. For example, a logic unit may correspond to a logical block address (LBA) or other logical management unit. A logic unit may be mapped to one or more physical units.

[0041] In one embodiment, if a physical unit is currently mapped by any logical unit, the memory control circuit 23 can determine that the data currently stored in this physical unit includes valid data. Conversely, if a physical unit is not currently mapped by any logical unit, the memory control circuit 23 can determine that this physical unit does not currently store any valid data.

[0042] In one embodiment, the memory control circuit 23 may record the mapping relationship between logic units and physical units in at least one management table (also known as a logic-to-physical mapping table). In one embodiment, the memory control circuit 23 may instruct the memory module 122 to perform operations such as data reading, writing, or erasing based on the information (also known as mapping information) in this management table (i.e., the logic-to-physical mapping table).

[0043] In one embodiment, when it is desired to store specific data (also referred to as target data), the processor 111 may send a write instruction (also referred to as a first write instruction) to the storage device 12 according to the target data. The first write instruction may be used to instruct the storage device 12 to write the target data to a specific logical unit (also referred to as a target logical unit). For example, the target logical unit may include Figure 3 At least one of the logic units 302(1)-302(C).

[0044] In one embodiment, the processor 111 may determine whether to add a preset flag to the first write instruction based on the type of the specific data to be stored (i.e., the target data). This preset flag may reflect the type of the target data. However, in one embodiment, the processor 111 may not add the preset flag to the first write instruction regardless of the type of the target data.

[0045] In one embodiment, if (or in response to) the target data being data of a certain type (also referred to as first type data), the processor 111 may add a preset flag to the first write instruction. For example, if (or in response to) the target data being first type data, the processor 111 may modify a reserved bit (also referred to as the target reserved bit) in the first write instruction according to the preset flag. In one embodiment, after the preset flag is added to the first write instruction, the target reserved bit in the first write instruction may carry this preset flag (e.g., bit "1").

[0046] In one embodiment, if (or in response to) the target data not being of the first type (e.g., the target data being of the second type), the processor 111 may not add a preset flag to the first write instruction. For example, if the preset flag is not added to the first write instruction, the target reserved bit in the first write instruction may not carry this preset flag. In one embodiment, if the preset flag is not added to the first write instruction, the target reserved bit in the first write instruction may be bit "0". It should be noted that the preset flag may also be implemented in other forms, and the present invention is not limited thereto.

[0047] In one embodiment, the memory control circuit 23 may obtain a first write instruction from the host system 11. Based on the first write instruction, the memory control circuit 23 may perform a data write operation corresponding to a target logic unit. For example, in this data write operation, the memory control circuit 23 may first perform a mapping conversion operation to determine at least one physical unit (also referred to as the target physical unit) mapped to the target logic unit. After determining the target physical unit, the memory control circuit 23 may instruct the memory module 122 to write (i.e., store) the target data into the target physical unit.

[0048] In one embodiment, the mapping conversion operation can be used to determine a target entity unit based on a target logical unit. In one embodiment, the mapping conversion operation can be used to convert a target logical unit into a target entity unit. In one embodiment, during the mapping conversion operation, the memory control circuit 23 can query a management table (such as the logic-to-entity mapping table described above) based on the identification information (also called logical identification information) of the target logical unit to obtain the query result. For example, the logical identification information of the target logical unit may include the number or identification code of the target logical unit. Based on this query result, the memory control circuit 23 can obtain the identification information (also called entity identification information) of the target entity unit. For example, the entity identification information of the target entity unit may include the number or identification code of the target entity unit. The memory control circuit 23 can determine the target entity unit based on this entity identification information.

[0049] In one embodiment, after receiving the first write instruction, the memory control circuit 23 can determine whether the first write instruction meets specific conditions (also known as preset conditions). If (or in response to) the first write instruction meets the preset conditions, the memory control circuit 23 can send back the entity identification information of at least one target entity unit mapped by the target logic unit to the host system 11. However, if (or in response to) the first write instruction does not meet the preset conditions, the memory control circuit 23 may not send back the entity identification information of any target entity unit to the host system 11.

[0050] In one embodiment, after obtaining the first write instruction, the memory control circuit 23 can determine whether the first write instruction conforms to a specific instruction format (also known as a preset instruction format) or whether the target data conforms to a specific data type (also known as a preset data type). If (or in response to) the first write instruction conforms to the preset instruction format or the target data conforms to the preset data type, the memory control circuit 23 can determine that the first write instruction meets the preset conditions. However, if (or in response to) the first write instruction does not conform to the preset instruction format and / or the target data does not conform to the preset data type, the memory control circuit 23 can determine that the first write instruction does not meet the preset conditions.

[0051] In one embodiment, after obtaining the first write instruction, the memory control circuit 23 can determine whether the first write instruction carries a preset flag. For example, after obtaining the first write instruction, the memory control circuit 23 can determine whether the target reserved bit in the first write instruction carries a preset flag. If (or in response to) the first write instruction carries this preset flag (e.g., the target reserved bit in the first write instruction is bit "1"), the memory control circuit 23 can determine that the first write instruction conforms to the preset instruction format. However, if (or in response to) the first write instruction does not carry this preset flag (e.g., the target reserved bit in the first write instruction is bit "0"), the memory control circuit 23 can determine that the first write instruction does not conform to the preset instruction format.

[0052] In one embodiment, after obtaining the first write instruction, the memory control circuit 23 can determine whether the target logic unit belongs to a specific logic range (also referred to as the target logic range). If (or in response to) the target logic unit belongs to the target logic range (for example, the logic identification information of the target logic unit is within the numerical range corresponding to the target logic range), the memory control circuit 23 can determine that the target data conforms to a preset data type (i.e., the target data belongs to the first type of data). However, if (or in response to) the target logic unit does not belong to the target logic range (for example, the logic identification information of the target logic unit is not within the numerical range corresponding to the target logic range), the memory control circuit 23 can determine that the target data does not conform to the preset data type (i.e., the target data does not belong to the first type of data).

[0053] In one embodiment, if (or in response to) the first write instruction meets preset conditions, the memory control circuit 23 can determine that the target data belongs to the first type of data. If (or in response to) the target data belongs to the first type of data, the memory control circuit 23 can send the entity identification information of the target entity unit back to the host system 11.

[0054] In one embodiment, if (or in response to) the first write instruction does not meet the preset conditions, the memory control circuit 23 may determine that the target data does not belong to the first type of data (i.e., the target data belongs to the second type of data). If (or in response to) the target data does not belong to the first type of data, the memory control circuit 23 may not send the entity identification information of the target entity unit back to the host system 11.

[0055] In one embodiment, the processor 111 may run an artificial intelligence model. For example, the artificial intelligence model may include a deep learning model, a large language model (LLM), a vision model, a vision language model (VLM), a multimodal model, a speech model, a generative artificial intelligence model, or another machine learning model. Furthermore, the type of artificial intelligence model may be adjusted according to practical needs.

[0056] In one embodiment, the first type of data may include any data available for use by the artificial intelligence model (or relevant data at the AI ​​application level). For example, the first type of data may include model weight data, inference intermediate data, embedding data, tokenizer data, cache data, and / or key-value (KV) cache data. In one embodiment, the second type of data may include any data not provided for use by the aforementioned artificial intelligence model, such as user data or system data unrelated to the operation of the artificial intelligence model.

[0057] In one embodiment, the first type of data can refer to various types of data suitable for accelerated access using entity recognition information. In one embodiment, compared to the second type of data, the first type of data has a higher access frequency, is more sensitive to access latency, has a higher reread frequency, and / or has a shorter lifespan.

[0058] In one embodiment, if (or in response to) a first write instruction that meets preset conditions, the memory control circuit 23 may include the entity identification information of the target entity unit in the response information corresponding to the first write instruction. The memory control circuit 23 may then send this response information back to the host system 11 in response to the first write instruction. For example, this response information may be used to notify the host system 11 of the execution result corresponding to the first write instruction (e.g., whether the execution of the first write instruction has been completed).

[0059] Figure 4 This is a schematic diagram illustrating how entity identification information is included in response information and sent back to the host system according to a first write instruction, as shown in an embodiment of the present invention. Please refer to... Figure 4 In one embodiment, the memory control circuit 23 may obtain a write instruction 41 (i.e., a first write instruction) from the host system 11. The memory control circuit 23 may, according to the write instruction 41, instruct the memory module 122 to perform a data write operation corresponding to a target logic unit. For example, in this data write operation, the memory module 122 may write target data to at least one target entity unit mapped to the target logic unit. After completing this data write operation, the memory control circuit 23 may generate a response message 42 corresponding to the write instruction 41.

[0060] In one embodiment, if (or in response to) the write instruction 41 meets preset conditions (e.g., the write instruction 41 meets a preset instruction format or the target data meets a preset data type), the memory control circuit 23 can include the entity identification information 43 of the target entity unit in the response information 42, and send the response information 42 carrying the entity identification information 43 back to the host system 11. Thus, the memory control circuit 23 can respond to the write instruction 41 through the response information 42, and simultaneously provide the entity identification information 43 to the host system 11 through the response information 42.

[0061] In one embodiment, the memory control circuit 23 may embed the entity identification information of the target entity unit into the response information as a mapping information pair. This mapping information pair may include the entity identification information of the target entity unit and the logic identification information of the target logic unit.

[0062] Figure 5 This is a schematic diagram illustrating the mapping information pairs according to an embodiment of the present invention. Please refer to... Figure 5 In one embodiment, it is assumed that the target data to be written by the first write instruction belongs to logic units LBA(0)-LBA(31) (i.e., target logic units), and logic units LBA(0)-LBA(31) are respectively mapped to entity units PCA(0)-PCA(31) (i.e., target entity units). Wherein, logic unit LBA(i) is mapped to entity unit PCA(i), i is between 0 and 31, and i is an integer.

[0063] In one embodiment, the memory control circuit 23 may include the mapping information 51 within the aforementioned response information, so as to send the mapping information 51 back to the host system 11 via the response information. Figure 5 For example, mapping information 51 includes 32 mapping information pairs. Each mapping information pair may contain the logical identification information of the logical unit LBA(i) and the entity identification information of the entity unit PCA(i) to reflect the mapping relationship between the logical unit LBA(i) and the entity unit PCA(i).

[0064] In one embodiment, the memory control circuit 23 can determine whether the first write instruction is a batch write instruction. If (or in response to) the first write instruction is a batch write instruction, the memory control circuit 23 can also include sub-information from the entity identification information in at least one Ready To Transfer (RTT) message corresponding to this batch write instruction. Then, the memory control circuit 23 can send this Ready To Transfer (RTT) message back to the host system 11. For example, this Ready To Transfer (RTT) message can be used to notify the host system 11 that it can begin batching or transferring the target data in stages.

[0065] Figure 6 This is a schematic diagram illustrating how entity identification information, along with transmission readiness information and response information, is transmitted back to the host system according to a first write instruction, based on an embodiment of the present invention. Please refer to... Figure 6 In one embodiment, it is assumed that write instruction 61 (i.e., the first write instruction) is a batch write instruction, and the total data size of the target data is 64KB. Furthermore, it is assumed that the unit of data transfer in a single transaction is a data chunk (also called a data block), and that a data chunk can carry 32KB of data. Therefore, after the write instruction 61 is provided to the storage device 12, the target data needs to be split into two data chunks (32KB + 32KB) and transmitted sequentially to the storage device 12.

[0066] In one embodiment, after receiving a write instruction 61 from the host system 11, the memory control circuit 23 may send back transmission readiness information 62(1) to the host system 11 according to the write instruction 61. According to the transmission readiness information 62(1), the processor 111 may send a data segment 63(1) to the storage device 12. For example, the data segment 63(1) contains a portion (also referred to as the first portion) of the target data.

[0067] In one embodiment, after acquiring data segment 63(1), the memory control circuit 23 can instruct the memory module 122 to perform a data write operation 64(1) to store the data segment 63(1) into the target entity unit (also referred to as the first target entity unit). At the same time, the memory control circuit 23 can map the logic unit (also referred to as the first target logic unit) to which the data segment 63(1) belongs to the first target entity unit.

[0068] In one embodiment, after completing the data write operation 64(1), the memory control circuit 23 may generate transfer ready information 62(2). Then, the memory control circuit 23 may include the entity identification information 65(1) of the first target entity unit (also referred to as the first entity identification information) in the transfer ready information 62(2) and transmit the transfer ready information 62(2) carrying the entity identification information 65(1) to the host system 11.

[0069] In one embodiment, processor 111 may transmit data segment 63(2) to storage device 12 based on transmission readiness information 62(2). For example, data segment 63(2) may contain another portion (also referred to as the second portion) of target data.

[0070] In one embodiment, after acquiring data segment 63(2), the memory control circuit 23 can instruct the memory module 122 to perform a data write operation 64(2) to store data segment 63(2) into a target entity unit (also referred to as a second target entity unit). At the same time, the memory control circuit 23 can map the logic unit (also referred to as the second target logic unit) to which data segment 63(2) belongs to the second target entity unit.

[0071] In one embodiment, after the data writing operation 64(2) is completed, in response to the target data being completely written to the memory module 122, the memory control circuit 23 may generate response information 66. Then, the memory control circuit 23 may include the entity identification information 65(2) of the second target entity unit (also referred to as the second entity identification information) in the response information 66, and transmit the response information 66 carrying the entity identification information 65(2) to the host system 11.

[0072] In one embodiment, entity identification information 65(1) and 65(2) are both embedded in the transmission readiness information 62(2) and the response information 66 respectively in the form of mapping information pairs. For example, the mapping information pair carried by the transmission readiness information 62(2) may include the logical identification information of the first target logic unit and the entity identification information of the first target entity unit, so as to reflect the mapping relationship between the first target logic unit and the first target entity unit. In addition, the mapping information pair carried by the response information 66 may include the logical identification information of the second target logic unit and the entity identification information of the second target entity unit, so as to reflect the mapping relationship between the second target logic unit and the second target entity unit.

[0073] It should be noted that, in Figure 6 In another embodiment, for batch write instructions (e.g., write instruction 61), additional transmission readiness information can also be used to transmit sub-information of entity identification information (such as the entity identification information of the first target entity unit and the entity identification information of the second target entity unit) to the host system 11. Furthermore, the total amount of target data and the amount of data that a single data segment can carry can be adjusted according to practical needs.

[0074] In one embodiment, after sending the first write instruction, the processor 111 can obtain entity identification information of the target entity unit from the storage device 12. Then, the processor 111 can store this entity identification information in the buffer memory 112.

[0075] In one embodiment, the processor 111 may store the entity identification information from the storage device 12 in the mapping table cache of the buffer memory 112 in the manner described above as mapping information pairs. As mentioned above, each mapping information pair may include the entity identification information of the target entity unit and the logical identification information of the target logic unit to reflect the mapping relationship between the target entity unit and the target logic unit. Then, by querying the information in the mapping table cache (i.e., the mapping information pairs), the processor 111 can quickly determine the target entity unit mapped by the target logic unit.

[0076] In one embodiment, the entity identification information of the target entity unit may be included in the response information corresponding to the first write instruction and sent back to the host system 11. In another embodiment, if (or in response to) the first write instruction is a batch write instruction, the entity identification information of the target entity unit may also be included in at least one transfer ready information corresponding to this batch write instruction and sent back to the host system 11. The relevant operational details have been described above and will not be repeated here. Then, the processor 111 may extract or separate the entity identification information of the target entity unit from the response information or the transfer ready information.

[0077] In one embodiment, after writing target data to storage device 12, when it is desired to read target data from storage device 12, processor 111 can obtain information about the target entity unit mapped to the target logic unit (e.g., entity identification information of the target entity unit) from buffer memory 112. Then, processor 111 can send a read instruction (also referred to as a first read instruction) to storage device 12 based on this entity identification information. The first read instruction can be used to instruct storage device 12 to read the target data. In particular, the first read instruction can carry entity identification information of the target entity unit. In addition, the first read instruction can also carry logic identification information of the target logic unit.

[0078] In one embodiment, after performing a data write operation on the target data, the memory control circuit 23 can obtain a first read instruction from the host system 11. In particular, in addition to the logical identification information of the target logic unit, the first read instruction also carries the entity identification information of the target entity unit.

[0079] In one embodiment, according to the first read instruction, without performing a mapping conversion operation corresponding to the target logical unit, the memory control circuit 23 can (directly) read the target data from the target entity unit and send the target data back to the host system 11. For example, according to the first read instruction, without performing a mapping conversion operation corresponding to the target logical unit, the memory control circuit 23 can (directly) instruct the memory module 122 to read the target data from the target entity unit based on the entity identification information carried by the first read instruction. Then, the memory control circuit 23 can send the target data back to the host system 11. Thus, compared to the general situation where a mapping conversion operation is required to determine the target entity unit mapped by the target logical unit, in one embodiment, by skipping the mapping conversion operation to accelerate the reading of the target data, the access performance of the storage device 12 (or data storage system 10) for the target data (or first type of data) can be effectively improved.

[0080] In one embodiment, the processor 111 may also send a configuration instruction. This configuration instruction can be used to instruct the storage device 12 to configure a target logical range. This target logical range can be dedicated to storing a first type of data. For example, the configuration instruction may include capacity information. This capacity information can be used to specify the capacity corresponding to the target logical range.

[0081] In one embodiment, the memory control circuit 23 can dynamically determine the target logical range based on the configuration instructions from the host system 11 and this capacity information. The capacity corresponding to the determined target logical range must be equal to (or not less than) the capacity specified by this capacity information.

[0082] In one embodiment, after configuring the target logic range, the processor 111 may also send a write instruction (also referred to as a second write instruction). The second write instruction can be used to instruct the storage device 12 to store the first type of data to at least one logic unit (also referred to as a candidate logic unit) belonging to the target logic range. The candidate logic unit may be mapped to at least one physical unit (also referred to as a candidate physical unit) in the memory module 122.

[0083] In one embodiment, according to a second write instruction from the host system 11, the memory control circuit 23 may perform a mapping conversion operation to determine at least one entity unit (also referred to as a candidate entity unit) in the memory module 122 that is mapped to a candidate logic unit. Then, the memory control circuit 23 may instruct the memory module 122 to store a first type of data into the candidate entity unit.

[0084] In one embodiment, after storing the first type of data into the memory module 122, the processor 111 may also send a query instruction. This query instruction is used to instruct the storage device 12 to provide mapping information (also known as initial mapping information) corresponding to the target logical range. This initial mapping information can reflect the mapping relationship between each candidate logic unit belonging to the target logical range and the candidate entity units in the memory module 122.

[0085] In one embodiment, based on a query instruction from the host system 11, the memory control circuit 23 may provide initial mapping information corresponding to the target logical range to the host system 11. For example, the memory control circuit 23 may query a logic-to-entity mapping table to obtain the initial mapping information corresponding to the target logical range. Then, the memory control circuit 23 may provide this initial mapping information to the host system 11.

[0086] In one embodiment, after obtaining the initial mapping information corresponding to the target logical range, the processor 111 may store this initial mapping information in the buffer memory 112. For example, the processor 111 may store the initial mapping information in the mapping table cache area of ​​the buffer memory 112 in the manner described above as mapping information pairs. For example, the initial mapping information may include multiple mapping information pairs. Each mapping information pair may include the logical identification information of a candidate logical unit and the entity identification information of a candidate entity unit, so as to reflect the mapping relationship between the candidate logical unit and the candidate entity unit.

[0087] Figure 7 This is a schematic diagram illustrating the acquisition of initial mapping information according to an embodiment of the present invention. Please refer to... Figure 7In one embodiment, according to configuration instructions, the memory control circuit 23 can determine the logic range between logic units LBA(0)-LBA(x) (i.e., candidate logic units) as the target logic range. After determining the target logic range, the memory control circuit 23 can store first-type data in logic units LBA(0)-LBA(x). It should be noted that data that does not belong to the first type of data (e.g., second-type data) cannot be stored in logic units LBA(0)-LBA(x) that belong to the target logic range. In addition, the memory control circuit 23 can store second-type data in logic units LBA(x+1)-LBA(y). Logic units LBA(x+1)-LBA(y) do not belong to the target logic range.

[0088] In one embodiment, it is assumed that logic units LBA(0)-LBA(x) are mapped to entity units PCA(0)-PCA(x) (i.e., candidate entity units). After storing the first type of data belonging to the target logic range into entity units PCA(0)-PCA(x), the memory control circuit 23 can dynamically generate mapping information 71 (i.e., initial mapping information) corresponding to the target logic range. The mapping information 71 can reflect the mapping relationship between logic units LBA(0)-LBA(x) and entity units PCA(0)-PCA(x). In one embodiment, according to a query instruction from the host system 11, the memory control circuit 23 can provide the mapping information 71 to the host system 11.

[0089] In one embodiment, after obtaining initial mapping information, the processor 111 can send a read instruction (also referred to as a second read instruction) based on this initial mapping information. The second read instruction can be used to instruct the storage device 12 to read at least a portion of the first type of data. Figure 7 For example, the second read instruction may carry entity identification information of at least one of the entity units PCA(0)-PCA(x). Based on the entity identification information in the second read instruction, the memory control circuit 23 can (directly) read at least a portion of the first type of data from at least one of the entity units PCA(0)-PCA(x) without performing a mapping conversion operation, and then send the read data back to the host system 11. This effectively improves the access performance of the storage device 12 (or data storage system 10) for the first type of data.

[0090] In one embodiment, the processor 111 may also monitor application operation information related to at least one application (also referred to as a target application). The target application may include one or more applications for operating or controlling an artificial intelligence model. This application operation information may reflect the target application's access to a first type of data. For example, this application operation information may reflect the time, frequency, or number of times the first type of data belonging to a candidate logic unit or a target logic unit is accessed or accessed.

[0091] In one embodiment, the processor 111 can determine expired data in the first type of data based on the application operation information. For example, the processor 111 can use the application operation information, along with a Least Recently Used (LRU) algorithm (or a similar algorithm), to filter out data that has been accessed or accessed relatively infrequently in the first type of data as expired data. Then, the processor 111 can send an invalidation instruction based on the determined expired data. This invalidation instruction can be used to instruct the storage device 12 to mark the determined expired data as invalid data.

[0092] In one embodiment, the invalidation instruction may include a Trim instruction or an instruction with similar functionality. This invalidation instruction may carry logical identification information of the logical unit to which the invalidated data belongs. Based on this invalidation instruction, the memory control circuit 23 can mark the logical unit to which the invalidated data belongs as not storing valid data (equivalent to marking the invalidated data as invalid data). In subsequent garbage collection operations or similar data defragmentation operations autonomously performed by the memory control circuit 23, the memory control circuit 23 does not need to move or copy the invalidated data and can directly erase the invalidated data. This improves the performance of garbage collection operations or similar data defragmentation operations and reduces write amplification of the memory module 122, thereby extending the lifespan of the memory module 122.

[0093] Figure 8 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 8 In step S801, a first write instruction is obtained from the host system, wherein the first write instruction is used to instruct the target data to be written to the target logic unit. In step S802, according to the first write instruction, a data write operation corresponding to the target logic unit is executed. In step S803, it is determined whether the first write instruction meets preset conditions.

[0094] If (or in response to) the first write instruction meets the preset conditions, in step S804, the entity identification information of at least one target entity unit mapped by the target logic unit is sent back to the host system. Furthermore, if (or in response to) the first write instruction does not meet the preset conditions, in step S805, the entity identification information is not sent back to the host system.

[0095] Figure 9 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 9 In step S901, a write command is sent according to the target data, wherein the write command instructs the target data to be written to the target logical unit. After sending the write command, in step S902, entity identification information of at least one target entity unit is obtained from the storage device, wherein the target entity unit is mapped to the target logical unit. In step S903, the entity identification information is stored in the buffer memory of the host system.

[0096] Figure 10 This is a flowchart illustrating a memory management method according to an embodiment of the present invention. Please refer to... Figure 10 In step S1001, a query instruction is obtained from the host system. In step S1002, based on the query instruction, initial mapping information corresponding to the target logical range is obtained, wherein the initial mapping information reflects the mapping relationship between at least one candidate logical unit belonging to the target logical range and at least one candidate entity unit in the memory module. In step S1003, the initial mapping information is provided to the host system.

[0097] However, Figures 8 to 10 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figures 8 to 10 Each step can be implemented as multiple program codes or circuits, and this invention is not limited thereto. Furthermore, Figures 8 to 10 The method can be used in conjunction with the above examples and embodiments, or it can be used alone. This invention does not impose any limitations.

[0098] In summary, the memory management method, storage device, and host system proposed in this invention can more effectively determine the entity unit to be accessed by writing and then returning entity identification information, querying to obtain initial mapping information, and caching and using the mapping information for subsequent data access by the host system. This reduces the mapping conversion overhead when reading the first type of data on the storage device. Therefore, the access performance of the data storage system for the first type of data can be effectively improved without significantly affecting the normal operation of the data storage system. Furthermore, this invention is compatible with existing storage system architectures and has good practicality and application value.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method, characterized in that, For use in a storage device, the storage device including a memory module, and the memory management method comprising: Obtain a first write instruction from the host system, wherein the first write instruction is used to instruct target data to be written to the target logic unit; According to the first write instruction, execute the data write operation corresponding to the target logic unit; In response to the first write instruction meeting preset conditions, entity identification information of at least one target entity unit mapped by the target logical unit is sent back to the host system; and If the first write instruction does not meet the preset conditions, the entity identification information will not be sent back to the host system.

2. The memory management method according to claim 1, characterized in that, The memory management method further includes: Determine whether the first write instruction conforms to a preset instruction format or whether the target data conforms to a preset data type; and In response to the first write instruction conforming to the preset instruction format or the target data conforming to the preset data type, it is determined that the first write instruction conforms to the preset conditions.

3. The memory management method according to claim 2, characterized in that, Determining whether the first write instruction conforms to the preset instruction format includes: Determine whether the first write instruction carries a preset flag; and In response to the first write instruction carrying the preset flag, it is determined that the first write instruction conforms to the preset instruction format.

4. The memory management method according to claim 2, characterized in that, Determining whether the target data conforms to the preset data type includes: Determine whether the target logic unit belongs to the target logic scope; and In response to the target logic unit belonging to the target logic range, the target data is determined to conform to the preset data type.

5. The memory management method according to claim 1, characterized in that, Returning the entity identification information of the at least one target entity unit mapped by the target logical unit to the host system includes: The entity identification information is included in the response information corresponding to the first write instruction, and the response information is sent back to the host system.

6. The memory management method according to claim 5, characterized in that, Including the entity identification information in the response information corresponding to the first write instruction includes: The entity identification information is included in the response information as a mapping information pair, wherein the mapping information pair includes the entity identification information and the logical identification information of the target logical unit.

7. The memory management method according to claim 5, characterized in that, The memory management method further includes: In response to the first write instruction being a batch write instruction, the sub-information in the entity identification information is included in at least one transmission ready information corresponding to the batch write instruction, and the at least one transmission ready information is sent back to the host system.

8. The memory management method according to claim 1, characterized in that, The memory management method further includes: After performing the data write operation, a first read instruction is obtained from the host system, wherein the first read instruction carries the entity identification information; and According to the first read instruction, without performing a mapping conversion operation corresponding to the target logical unit, the target data is read from the at least one target entity unit and the target data is sent back to the host system.

9. The memory management method according to claim 1, characterized in that, The target data belongs to the first type of data, and the memory management method further includes: A target logical scope is determined based on configuration instructions from the host system, wherein the target logical scope is dedicated to storing the first type of data; According to a second write instruction from the host system, the first type of data is stored in at least one candidate entity unit in the memory module, wherein the at least one candidate entity unit is mapped to at least one candidate logic unit belonging to the target logic range; and According to the query instruction from the host system, initial mapping information corresponding to the target logical range is provided to the host system, wherein the initial mapping information reflects the mapping relationship between the at least one candidate logical unit and the at least one candidate entity unit.

10. A storage device, characterized in that, include: Connection interface, used to connect to the host system; Memory module; as well as The memory controller is connected to the connection interface and the memory module. The memory controller is used to execute the memory management method according to any one of claims 1-9.

11. A memory management method, characterized in that, For a host system connected to a storage device, the memory management method includes: Based on the target data, a first write instruction is sent, wherein the first write instruction instructs the target data to be written to the target logic unit; After sending the first write instruction, entity identification information of at least one target entity unit is obtained from the storage device, wherein the at least one target entity unit is mapped to the target logical unit; and The entity identification information is stored in the buffer memory of the host system.

12. The memory management method according to claim 11, characterized in that, Storing the entity identification information in the buffer memory of the host system includes: The entity identification information is stored in the mapping table cache area of ​​the buffer memory as mapping information pairs, wherein the mapping information pairs include the entity identification information and the logical identification information of the target logic unit.

13. The memory management method according to claim 11, characterized in that, The entity identification information is included in the response information corresponding to the first write instruction and sent back to the host system.

14. The memory management method according to claim 13, characterized in that, The entity identification information is embedded in the response information in the form of mapping information pairs, wherein the mapping information pairs include the entity identification information and the logical identification information of the target logical unit.

15. The memory management method according to claim 13, characterized in that, In response to the first write instruction being a batch write instruction, the entity identification information is also included in at least one transmission ready information corresponding to the batch write instruction and transmitted back to the host system.

16. The memory management method according to claim 11, characterized in that, The memory management method further includes: Based on the entity identification information, a first read instruction is sent, wherein the first read instruction is used to instruct the reading of the target data, and the first read instruction carries the entity identification information.

17. The memory management method according to claim 11, characterized in that, The target data belongs to the first type of data, and the memory management method further includes: Send a configuration instruction, wherein the configuration instruction is used to instruct the storage device to configure a target logical range, and the target logical range is dedicated to storing the first type of data; Send a second write instruction, wherein the second write instruction is used to instruct the first type of data to be stored in at least one candidate logic unit belonging to the target logic range, and the at least one candidate logic unit is mapped to at least one candidate entity unit in the memory module; and Send a query instruction, wherein the query instruction is used to instruct the storage device to provide initial mapping information corresponding to the target logical range, and the initial mapping information reflects the mapping relationship between the at least one candidate logical unit and the at least one candidate entity unit.

18. The memory management method according to claim 17, characterized in that, The memory management method further includes: Based on the initial mapping information, a second read instruction is sent, wherein the second read instruction is used to instruct the reading of at least a portion of the first type of data.

19. The memory management method according to claim 11, characterized in that, The target data belongs to the first type of data, and the memory management method further includes: Based on application operation information, identify expired data in the first type of data; and Based on the expired data, an invalidation instruction is sent, wherein the invalidation instruction is used to instruct the storage device to mark the expired data as invalid data.

20. A host system, characterized in that, include: processor; as well as Buffer memory, connected to the processor, The processor is used to execute the memory management method according to any one of claims 11-19.

21. A memory management method, characterized in that, For use in a storage device, the storage device including a memory module, and the memory management method comprising: Retrieve query instructions from the host system; According to the query instruction, initial mapping information corresponding to the target logical range is obtained, wherein the initial mapping information reflects the mapping relationship between at least one candidate logical unit belonging to the target logical range and at least one candidate entity unit in the memory module; and The initial mapping information is provided to the host system.

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