Storage device, memory controller, and memory management method

Abstract

The present disclosure provides a storage device, a memory controller and a memory management method. The storage device comprises a non-volatile memory, an integrated volatile memory and a memory controller; the method maintains a complete mapping table comprising a plurality of mapping table pages in the integrated volatile memory, and maintains a cache mapping table for caching part of the mapping table pages in the memory controller; in response to an access command, it is determined whether the cache mapping table hits an access logical address of the access command; if the cache mapping table does not hit the access logical address, a mapping table page to which the access logical address belongs is loaded from the complete mapping table to the cache mapping table, and an access operation corresponding to the access command is executed based on the mapping table page. This scheme enables the memory controller to cope with large capacity mapping table with small cache.

Description

Technical Field

[0001] This disclosure relates to the field of memory management technology, and in particular to a memory device, memory controller, and memory management method that maintains a complete mapping table in an integrated volatile memory, has a cached mapping table maintained by a memory controller, and persists the mapping table pages in a low-power state. Background Technology

[0002] In the field of storage devices, as the capacity of non-volatile memory continues to increase, the size of the complete mapping table used to map logical addresses to physical addresses also increases. Existing memory controllers typically store only a portion of the complete mapping table in their internal cache, while storing the entire complete mapping table in non-volatile memory. When the host system initiates a read command and the internal cache misses the logical address carried by the read command, the memory controller needs to first read the corresponding mapping table page from non-volatile memory and load it into the internal cache, then use this information to find the target physical address before completing the corresponding data read. Therefore, using non-volatile memory as the carrier of the complete mapping table means that the mapping table page loading path when the internal cache misses involves non-volatile memory access.

[0003] On the other hand, while increasing the capacity of the internal cache of the memory controller can improve the hit rate, the capacity of the internal cache is difficult to expand synchronously with the capacity of the complete mapping table due to limitations in the area, cost, and power consumption of the controller chip. Furthermore, ensuring that the logical address to physical address mapping relationship recorded in the complete mapping table is not lost due to power loss of the volatile carrier when the memory device enters a low-power state or experiences an abnormal power failure, and that usable mapping lookup capabilities can still be reconstructed upon wake-up or recovery, also constitutes a practical consideration in memory management engineering. Summary of the Invention

[0004] In view of this, the present disclosure provides a storage device, a memory controller, and a memory management method. By integrating volatile memory within the storage device to carry a complete mapping table including multiple mapping table pages, and having the memory controller maintain a cached mapping table for caching a portion of the multiple mapping table pages, in response to an access command, the corresponding mapping table page is selectively loaded from the complete mapping table in the integrated volatile memory into the cached mapping table based on whether the cached mapping table hits the access logical address, and then the access operation corresponding to the access command is executed accordingly. This reduces the dependence of the memory controller's internal cache on the capacity of the complete mapping table, and reduces the latency and overhead caused by directly accessing non-volatile memory to query the mapping relationship when the cached mapping table misses.

[0005] According to a first aspect of this disclosure, a memory management method is provided, applicable to a storage device configured with a memory controller, integrated volatile memory, and non-volatile memory. The method includes: maintaining a complete mapping table including multiple mapping table pages in the integrated volatile memory, and maintaining a cache mapping table in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping table pages; in response to an access command, determining whether the cache mapping table hits the access logical address of the access command; and if the cache mapping table does not hit the access logical address, loading the mapping table page to which the access logical address belongs from the complete mapping table in the integrated volatile memory into the cache mapping table, and performing the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table.

[0006] According to a second aspect of this disclosure, a storage device is provided, comprising: a non-volatile memory; an integrated volatile memory; and a memory controller electrically connected to the non-volatile memory and the integrated volatile memory, wherein the memory controller includes: a non-volatile memory interface control circuit for being electrically connected to the non-volatile memory; an integrated volatile memory interface for being electrically connected to the integrated volatile memory; and a processor electrically connected to the non-volatile memory interface control circuit and the integrated volatile memory interface, wherein the processor is configured to: maintain a complete mapping table including multiple mapping table pages in the integrated volatile memory, and maintain a cache mapping table in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping table pages; in response to an access command, determine whether the cache mapping table hits the access logical address of the access command; and if the cache mapping table does not hit the access logical address, load the mapping table page to which the access logical address belongs from the complete mapping table in the integrated volatile memory into the cache mapping table, and execute the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table.

[0007] According to a third aspect of this disclosure, a memory controller is provided, suitable for a storage device configured with non-volatile memory and integrated volatile memory. The memory controller includes: a non-volatile memory interface control circuit for electrically connecting to the non-volatile memory; an integrated volatile memory interface for electrically connecting to the integrated volatile memory; and a processor electrically connected to the non-volatile memory interface control circuit and the integrated volatile memory interface, respectively. The processor is configured to: maintain a complete mapping table including multiple mapping table pages in the integrated volatile memory, and maintain a cache mapping table in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping table pages; in response to an access command, determine whether the cache mapping table hits the access logical address of the access command; and if the cache mapping table does not hit the access logical address, load the mapping table page to which the access logical address belongs from the complete mapping table in the integrated volatile memory into the cache mapping table, and execute the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table.

[0008] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided, on which a computer program is stored; the computer program is adapted to a storage device configured with a memory controller, integrated volatile memory, and non-volatile memory, and when the computer program is executed by a processor in the memory controller of the storage device, causes the processor to perform: maintaining a complete mapping table including multiple mapping table pages in the integrated volatile memory, and maintaining a cache mapping table in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping table pages; in response to an access command, determining whether the cache mapping table hits the access logical address of the access command; and if the cache mapping table does not hit the access logical address, loading the mapping table page to which the access logical address belongs from the complete mapping table in the integrated volatile memory into the cache mapping table, and performing the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table.

[0009] Based on the above, the storage device, memory controller, and memory management method provided in this disclosure maintain a complete mapping table including multiple mapping table pages in the integrated volatile memory, and maintains a cache mapping table in the memory controller for caching some of the multiple mapping table pages. This allows the logical address to physical address mapping lookup under an access command to be completed first through the cache mapping table. In response to an access command, if the cache mapping table matches the access logical address of the access command, the memory controller can execute the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table; if the cache mapping table does not match the access logical address, the memory controller can load the mapping table page to which the access logical address belongs from the complete mapping table in the integrated volatile memory into the cache mapping table, and then execute the access operation corresponding to the access command based on the loaded mapping table page. Therefore, compared to storing the complete mapping table primarily in non-volatile memory and reading the corresponding mapping table page from non-volatile memory when a cache miss occurs, this disclosure allows the loading path of the mapping table page when a cache miss occurs to be executed via integrated volatile memory, thereby reducing the dependence of the memory controller's internal cache on the capacity of the complete mapping table. Attached Figure Description

[0010] Figure 1 This is a block diagram illustrating the overall architecture of a storage device with integrated volatile memory according to an embodiment of the present disclosure.

[0011] Figure 2 This is a schematic diagram illustrating the hierarchical relationship between the complete mapping table, the cache mapping table, the complete copy, and the persistent copy according to embodiments of this disclosure.

[0012] Figure 3 This is a flowchart illustrating cache map hit and miss processing under access commands according to embodiments of the present disclosure;

[0013] Figure 4A This is a flowchart illustrating the processing when the access command is a read command according to an embodiment of the present disclosure;

[0014] Figure 4B This is a flowchart illustrating the cache mapping table update, first dirty mark setting, and first-stage flushing when the access command is a write command according to an embodiment of this disclosure;

[0015] Figure 5 A state diagram showing multiple power consumption levels and their correspondence with the states of the memory controller and integrated volatile memory, according to embodiments of this disclosure;

[0016] Figure 6 This is a flowchart illustrating the persistence of mapped pages under the first type of low power indication, the second type of low power indication, and the third type of low power indication according to embodiments of this disclosure;

[0017] Figure 7 This is a timing diagram of a hierarchical wake-up from self-refresh mode, as shown in an embodiment of the present disclosure.

[0018] Figure 8 This is a flowchart illustrating integrity checks and valid copy backfilling or metadata reconstruction according to embodiments of this disclosure;

[0019] Figure 9 This is a schematic diagram of the high-order address segment index, hash table, and content-addressable memory lookup structure shown in the embodiments of this disclosure;

[0020] Figure 10 This is a timing diagram illustrating the interaction of read commands according to embodiments of the present disclosure;

[0021] Figure 11 This is a timing diagram illustrating the write command interaction according to embodiments of the present disclosure;

[0022] Figure 12 This is a timing diagram of the second-stage brush interaction shown according to an embodiment of the present disclosure. Detailed Implementation

[0023] Reference will now be made in detail to exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0024] Figure 1 This is a block diagram illustrating the overall architecture of a storage device with integrated volatile memory according to embodiments of the present disclosure. Please refer to... Figure 1 The host system 10 is, for example, a personal computer, a laptop computer, or a server. The host system 10 includes a processor 110 (also called a second processor), host memory 120 (also called host RAM), and a data transfer interface circuit 130. In this embodiment, the processor 110 is electrically connected to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other via a system bus. In this embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be located on the motherboard of the host system 10.

[0025] The storage device 20 includes a non-volatile memory module 220 (also called a rewritable non-volatile memory module), an integrated volatile memory 240, a memory controller 210, and a connection interface circuit 230. The memory controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, a non-volatile memory interface control circuit 213, an integrated volatile memory interface 215, and a buffer memory 214.

[0026] In this embodiment, the host system 10 is electrically connected to the storage device 20 via a data transmission interface circuit 130 and a connection interface circuit 230 to perform data access operations. For example, the host system 10 can store data to or read data from the storage device 20 via the data transmission interface circuit 130.

[0027] In this embodiment, the number of data transmission interface circuits 130 can be one or more. Through the data transmission interface circuits 130, the motherboard can be electrically connected to the storage device 20 via wired or wireless means. The storage device 20 can be, for example, a Universal Flash Storage (UFS) device, an Embedded Multi-Media Card (eMMC) device, a Solid State Drive (SSD), a USB flash drive, a memory card, or a wireless storage device. The wireless storage device can be, for example, a Near Field Communication (NFC) storage device, a WiFi storage device, a Bluetooth storage device, or a Bluetooth Low Energy storage device (e.g., iBeacon), or other storage devices based on various wireless communication technologies. Furthermore, the motherboard can also be electrically connected via the system bus to various I / O devices such as a Global Positioning System (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, and a speaker.

[0028] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the UFS standard; and the data transmission interface circuit 130 and the connection interface circuit 230 transmit data using the command transmission and data transmission protocols defined in the UFS specification. In another embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 may also be compatible with interface circuits of interface standards such as eMMC, Peripheral Component Interconnect Express (PCI Express), or Non-Volatile Memory Express (NVMe).

[0029] In another embodiment, the connection interface circuit 230 may be packaged in a chip with the memory controller 210, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210.

[0030] In this embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. In this embodiment, the host memory 120 may be Dynamic Random Access Memory (DRAM), Static Random Access Memory (SRAM), etc. However, it should be understood that this disclosure is not limited to this, and the host memory 120 may also be other suitable memories.

[0031] The memory controller 210 is used to execute multiple logic gates or control instructions implemented in hardware or firmware, and to perform operations such as writing, reading and erasing data in the non-volatile memory module 220 according to the commands of the host system 10, and to execute the memory management method provided in this disclosure.

[0032] More specifically, the processor 211 in the memory controller 210 is hardware with computing capabilities, used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed with multiple control instructions / program codes, and these control instructions / program codes are executed when the storage device 20 is operating to perform operations such as writing, reading, and erasing data.

[0033] Furthermore, the processor 211 is configured to execute the memory management method provided in this disclosure. Specifically, the processor 211 maintains a complete mapping table including multiple mapping table pages in the integrated volatile memory 240, and maintains a cache mapping table in the memory controller 210, the cache mapping table being used to cache a portion of the multiple mapping table pages; in response to an access command initiated by the host system 10 via the data transmission interface circuit 130 and the connection interface circuit 230, the processor 211 determines whether the cache mapping table hits the access logical address of the access command; if the cache mapping table does not hit the access logical address, the processor 211 loads the mapping table page to which the access logical address belongs from the complete mapping table in the integrated volatile memory 240 into the cache mapping table via the integrated volatile memory interface 215; then, the processor 211 executes the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table.

[0034] It is worth mentioning that, in this embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar circuit components, and this disclosure is not limited thereto.

[0035] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212, a non-volatile memory interface control circuit 213, and an integrated volatile memory interface 215. It should be noted that the operations performed by each component of the memory controller 210 can also be considered as operations performed by the memory controller 210 itself.

[0036] The data management circuit 212 is electrically connected to the processor 211, the non-volatile memory interface control circuit 213, the integrated volatile memory interface 215, and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to perform data transfer. For example, it reads data from the host system 10 (e.g., host memory 120) via the connection interface circuit 230 and writes the read data to the non-volatile memory module 220 via the non-volatile memory interface control circuit 213. Alternatively, it performs a read operation according to a read command from the host system 10, reads data from one or more physical units of the non-volatile memory module 220 via the non-volatile memory interface control circuit 213, and transmits the read data to the host system 10 via the connection interface circuit 230. In one embodiment, when the cache mapping table does not match the read logical address of the read command, the data management circuit 212, in conjunction with the processor 211, reads the mapping table page to which the read logical address belongs from the complete mapping table in the integrated volatile memory 240 via the integrated volatile memory interface 215, and writes the mapping table page to the cache mapping table of the memory controller 210; the data management circuit 212 also, in conjunction with the processor 211, sends the read physical address obtained by the processor 211 from the cache mapping table to the non-volatile memory interface control circuit 213, so as to instruct the non-volatile memory interface control circuit 213 to read the target data from the non-volatile memory module 220.

[0037] In another embodiment, the data management circuit 212 may also be integrated into the processor 211. The non-volatile memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform write (also known as programming), read, or erase operations on the non-volatile memory module 220.

[0038] Furthermore, the data to be written to the non-volatile memory module 220 is converted into a format acceptable to the non-volatile memory module 220 via the non-volatile memory interface control circuit 213. Specifically, if the processor 211 needs to access the non-volatile memory module 220, the processor 211 will send a corresponding command sequence to the non-volatile memory interface control circuit 213 to instruct the non-volatile memory interface control circuit 213 to perform the corresponding operation. For example, these command sequences may include a write command sequence indicating the writing of data, a read command sequence indicating the reading of data, an erase command sequence indicating the erasure of data, and corresponding command sequences for indicating various memory operations. These command sequences may include one or more signals, or data on the bus. These signals or data may include command codes or program codes. For example, a read command sequence may include information such as the read identification code, memory address, and physical address.

[0039] The integrated volatile memory interface 215 is electrically connected to the processor 211 and also electrically connected to the integrated volatile memory 240. The integrated volatile memory interface 215 receives instructions from the processor 211 and, in conjunction with the data management circuit 212, performs operations such as accessing the complete mapping table, loading and writing back mapping table pages to the integrated volatile memory 240. In this embodiment, the integrated volatile memory interface 215 is an integrated volatile memory controller built into the memory controller 210, and includes a physical layer circuit (PHY) for driving the physical layer signals specified by the integrated volatile memory 240. In another embodiment, the physical layer circuit of the integrated volatile memory interface 215 may also be separately configured from the logic layer circuit of the memory controller 210. This disclosure is not limited to the specific circuit implementation of the integrated volatile memory interface 215.

[0040] In addition, the memory controller 210 establishes a logical to physical address mapping table (L2P mapping table) composed of a complete mapping table and a cache mapping table to record the mapping relationship between the logical addresses of logical units (e.g., logical blocks, logical pages) and the physical addresses of physical units (e.g., physical erase units / physical blocks, physical pages) configured for the non-volatile memory module 220. In this embodiment, the complete mapping table resides in the integrated volatile memory 240, and the cache mapping table resides in the memory controller 210 (e.g., in a designated segment of the buffer memory 214 or in the cache built into the memory controller 210). When a mapping entry corresponding to a logical address exists in the cache mapping table (also known as a hit), the memory controller 210 can directly obtain the physical address corresponding to the logical address without accessing the complete mapping table in the integrated volatile memory 240. When a mapping entry corresponding to a logical address does not exist in the cache mapping table (also known as a miss), the memory controller 210 loads the mapping table page to which the logical address belongs from the complete mapping table in the integrated volatile memory 240 to the cache mapping table via the integrated volatile memory interface 215, and then obtains the physical address corresponding to the logical address.

[0041] Buffer memory 214 is electrically connected to processor 211 and is used to temporarily store data and commands from host system 10, data from non-volatile memory module 220, and various system data for managing storage device 20. In this embodiment, processor 211 maintains cache mapping table 310 in buffer memory 214. Cache mapping table 310 is used to cache a portion of the multiple mapping table pages included in complete mapping table 300. Specifically, buffer memory 214 may store the index structure of cache mapping table 310, the contents of the cached partial mapping table pages, a first dirty flag indicating that the updated but not yet written back to complete mapping table 300 mapping table pages in cache mapping table 310 are dirty, a preset number threshold and a preset time interval threshold for triggering the writing back of mapping table pages with the first dirty flag in cache mapping table 310 to complete mapping table 300, a timer since the last first-stage flush, and the logical addresses and corresponding physical addresses carried by write commands and read commands from host system 10 that are not yet processed or are being processed.

[0042] The integrated volatile memory 240 is electrically connected to the memory controller 210. Specifically, the integrated volatile memory 240 is electrically connected to the integrated volatile memory interface 215 inside the memory controller 210 and is used to carry the complete mapping table 300. In this embodiment, the complete mapping table 300 includes multiple mapping table pages, which respectively record the mapping relationship between logical addresses and physical addresses. When the cache mapping table 310 misses a read or write logical address, the processor 211 can read the corresponding mapping table page from the complete mapping table 300 in the integrated volatile memory 240 via the integrated volatile memory interface 215 and load the read mapping table page into the cache mapping table 310. In some embodiments, the integrated volatile memory 240 can also temporarily store or maintain auxiliary information related to the complete mapping table 300, such as integrity check information of the mapping table pages, intermediate data during the mapping table page backfilling or recovery process, or data that the memory controller 210 needs to temporarily store in a volatile manner when executing the memory management method of this disclosure. This disclosure is not limited to the specific types of auxiliary information in the integrated volatile memory 240 other than the complete mapping table 300. In this embodiment, the integrated volatile memory 240 is a low-power double data rate synchronous dynamic random access memory (LPDDR); specifically, the integrated volatile memory 240 may be a low-power double data rate synchronous dynamic random access memory conforming to LPDDR4X, LPDDR5, or a newer generation standard, and this disclosure is not limited to the specific generation of the integrated volatile memory 240. In another embodiment, the integrated volatile memory 240 may also be other types of volatile memory such as synchronous dynamic random access memory (SDRAM) or static random access memory (SRAM), and this disclosure is not limited to the specific type of the integrated volatile memory 240.

[0043] The non-volatile memory module 220 is electrically connected to the memory controller 210 (specifically, electrically connected to the non-volatile memory interface control circuit 213) and is used to store user data sent by the host system 10. In this disclosure, the non-volatile memory module 220 is also used to pre-store a complete copy of the complete mapping table, and includes a mapping table backup area for storing the complete copy and a persistent copy of the mapping table pages with a second dirty mark in the complete mapping table; by integrating the complete copy and the persistent copy in the non-volatile memory module 220 with the resident complete mapping table in the volatile memory 240, the complete mapping table can still be restored in low-power state switching and abnormal recovery scenarios.

[0044] In one embodiment, the memory cell structure of the non-volatile memory module 220 can be understood as a multi-layered physical organization architecture. Specifically, the non-volatile memory module 220 includes multiple chips (also called dies), each chip has multiple planes, and each plane includes multiple physical blocks, each physical block consisting of multiple physical pages. In this embodiment, the non-volatile memory module 220 is a NAND flash memory; in another embodiment, the non-volatile memory module 220 may also be other types of non-volatile memory such as NOR flash memory, magnetoresistive random access memory (MRAM), phase change memory (PCM), etc. This disclosure is not limited to the specific type of the non-volatile memory module 220.

[0045] In this embodiment, as Figure 1 As shown, the memory controller 210 and the integrated volatile memory 240 are integrated within the same package 21. In some embodiments, the non-volatile memory module 220 may also be integrated with the memory controller 210 and the integrated volatile memory 240 within the same package 21 to form a multi-chip package within the same package 21 (e.g., a multi-chip package corresponding to a general-purpose flash memory device). In some embodiments, the same package 21 may include a package substrate, and the memory controller 210 and the integrated volatile memory 240 may be electrically connected via signal traces located within the package substrate. These signal traces may bypass the interposer or be routed through a printed circuit board outside the same package 21. In some embodiments, the signal traces may be microstrip lines or striplines.

[0046] In some embodiments, the package 21 may be a multi-chip package, the memory controller 210 may correspond to a controller die, and the integrated volatile memory 240 may correspond to a volatile memory die. The memory controller 210 and the integrated volatile memory 240 may be disposed on the same package substrate and electrically connected to each other through signal traces formed within the package substrate. In other words, the access path of the memory controller 210 to the integrated volatile memory 240 may be formed inside the package 21, without needing to pass through printed circuit board traces outside the package 21. Thus, the integrated volatile memory 240 can serve as a volatile storage space directly accessible to the memory controller 210, used to carry the complete mapping table of this disclosure.

[0047] Furthermore, the integrated volatile memory interface 215 can serve as an interface circuit within the memory controller 210 for accessing the integrated volatile memory 240. In some embodiments, the integrated volatile memory interface 215 may include control logic or physical layer circuitry for generating, receiving, or regulating signals required by the integrated volatile memory 240. The memory controller 210 can perform read, write, or refresh operations on the integrated volatile memory 240 via the integrated volatile memory interface 215, thereby maintaining a complete mapping table in the integrated volatile memory 240 and loading the corresponding mapping table page from the complete mapping table to the cached mapping table when the cached mapping table is not hit.

[0048] In some embodiments, the non-volatile memory module 220 may include one or more non-volatile memory dies, which are used to store user data, a complete copy of the complete mapping table, a persistent copy, or metadata for restoring mapping relationships. In this embodiment, as... Figure 1 As shown, the non-volatile memory module 220 can be integrated with the memory controller 210 and the integrated volatile memory 240 within the same package 21. In other embodiments, the non-volatile memory module 220 can also be disposed outside the same package 21, but co-located with the package 21 in the same storage device 20, and receive access control from the memory controller 210 via the non-volatile memory interface control circuit 213. This disclosure does not limit the specific package form of the non-volatile memory module 220.

[0049] In some alternative embodiments, the memory controller 210 may detect access anomalies in the integrated volatile memory 240 during operation. Access anomalies may include, for example, a timeout in the response to an access request initiated via the integrated volatile memory interface 215, the integrated volatile memory 240 returning an uncorrectable error message, or the control circuitry of the integrated volatile memory interface 215 reporting an abnormal state. When an access anomaly is detected, the memory controller 210 may enter a degraded service mode. In degraded service mode, the memory controller 210 may reduce or suspend reliance on the full mapping table in the integrated volatile memory 240, and instead maintain at least a portion of the logical address-to-physical address mapping lookup capability using a cached mapping table in the memory controller 210, a full copy in the non-volatile memory module 220, a persistent copy, or metadata.

[0050] Specifically, in degraded service mode, for logical address ranges already covered by the cache mapping table, the memory controller 210 can respond to read or write commands based on the cache mapping table; for logical address ranges not covered by the cache mapping table, the memory controller 210 can access the mapping table backup area in the non-volatile memory module 220 via the non-volatile memory interface control circuit 213 to read a valid copy of the corresponding mapping table page, or reconstruct the corresponding mapping relationship based on the metadata in the non-volatile memory module 220. Furthermore, the memory controller 210 can report access anomalies or the operational status of the degraded service mode of the integrated volatile memory 240 to the host system 10 via the connection interface circuit 230. Thus, even if the integrated volatile memory 240 is temporarily unavailable, the storage device 20 can still maintain predictable mapping query behavior under limited performance.

[0051] Based on the above Figure 1 The overall architecture of the storage device shown allows the memory controller 210 to access the integrated volatile memory 240 and the non-volatile memory module 220 via the processor 211, data management circuit 212, integrated volatile memory interface 215, non-volatile memory interface control circuit 213, and buffer memory 214. It maintains a complete mapping table including multiple mapping pages in the integrated volatile memory 240, and a cache mapping table for caching some mapping pages in the memory controller 210. Thus, Figure 1 The architecture shown provides a hardware foundation for cache mapping table hit determination under read commands, mapping table page loading when cache misses, and access to non-volatile memory module 220 based on the read physical address. At the same time, the co-package configuration of memory controller 210 and integrated volatile memory 240 in package 21 also provides a hardware connection foundation for memory controller 210 to access integrated volatile memory 240 carrying the complete mapping table.

[0052] Figure 2 This is a schematic diagram illustrating the hierarchical relationship between the complete mapping table 300, the cache mapping table 310, the complete copy 324, and the persistent copy 323 according to embodiments of this disclosure. Please refer to... Figure 2 In this embodiment, the memory controller 210, the integrated volatile memory 240, and the non-volatile memory module 220 are used to carry mapping table data at different levels to form a cache layer, a complete mapping table resident layer, and a persistent backup layer.

[0053] In memory controller 210, processor 211 maintains cache mapping table 310. Cache mapping table 310 may be at least partially stored in buffer memory 214 and used to cache partial mapping pages from the multiple mapping pages included in the full mapping table 300. Partial mapping pages may correspond to logical address ranges that have been recently accessed or are expected to be accessed. When a mapping page in cache mapping table 310 has been updated according to a write command but has not yet been written back to the full mapping table 300, processor 211 sets a first dirty flag for that mapping page; Figure 2 The shaded box in the middle indicates the mapping page with the first dirty mark.

[0054] In the integrated volatile memory 240, the processor 211 maintains a complete mapping table 300. The complete mapping table 300 includes multiple mapping table pages, which record the mapping relationship between logical addresses and physical addresses, and cover the logical address range corresponding to the non-volatile memory module 220. When a mapping table page in the complete mapping table 300 has been updated by the cache mapping table 310 but has not yet been persisted to the non-volatile memory module 220, the processor 211 sets a second dirty flag for that mapping table page; Figure 2 The shaded box in the middle indicates the mapping page with the second dirty mark.

[0055] In the non-volatile memory module 220, the mapping table backup area 222 is used to store a complete copy 324 and a persistent copy 323. The complete copy 324 is used to store the copy content that can restore the complete mapping table 300; the persistent copy 323 is used to store the copy content formed after at least some mapping table pages are written to the non-volatile memory module 220. In some embodiments, the persistent copy 323 may include the persistence result of mapping table pages with a second dirty mark in the complete mapping table 300, so as to provide a basis for the recovery of the complete mapping table 300 when the integrated volatile memory 240 loses power, malfunctions, or is powered on again.

[0056] As shown by arrow A21, when the cache mapping table 310 does not match the read logical address carried by the read command initiated by the host system 10, the memory controller 210 can load the mapping table page to which the read logical address belongs from the full mapping table 300 into the cache mapping table 310 via the integrated volatile memory interface 215. Arrow A21 points from the full mapping table 300 to the cache mapping table 310 to indicate that the loaded mapping table page is provided to the cache mapping table 310, so that the cache mapping table 310 can provide a mapping entry for the corresponding read logical address based on the loaded mapping table page. In some embodiments, the loaded mapping table page can be added to a portion of the mapping table pages cached by the cache mapping table 310, or can replace existing mapping table pages in the cache mapping table 310 according to the replacement strategy of the cache mapping table 310.

[0057] As shown by arrow A22, when the memory controller 210 determines that the first-stage flush trigger condition is met, the memory controller 210 can write the mapping table page with the first dirty mark in the cache mapping table 310 back to the corresponding position of the mapping table page in the complete mapping table 300 via the integrated volatile memory interface 215. In some embodiments, the first-stage flush trigger condition may include: the number of mapping table pages with the first dirty mark in the cache mapping table 310 reaches a preset number threshold, or the time elapsed since the last first-stage flush reaches a preset time interval threshold. After the write-back is completed, the memory controller 210 clears the first dirty mark of the mapping page in the cache mapping table 310 and sets a second dirty mark for the corresponding mapping page in the complete mapping table 300.

[0058] As indicated by arrow A23, when the storage device 20 responds to an indication to enter a low-power state, the memory controller 210 can write the mapping table page with the second dirty mark in the complete mapping table 300 to the mapping table backup area 222 via the non-volatile memory interface control circuit 213, so that the mapping relationship corresponding to the mapping table page with the second dirty mark is saved in the persistent copy 323. After the persistence is completed, the memory controller 210 can clear the second dirty mark of the mapping table page in the complete mapping table 300.

[0059] Through the aforementioned dual dirty tagging mechanism, the storage device 20 can distinguish between cached mapping table 310 and the complete mapping table 300 by using a first dirty tag to identify mapping table pages in the cached mapping table 310 that have been updated but not yet written back to the complete mapping table 300, and between the complete mapping table 300 and the mapping table backup area 222 by using a second dirty tag to distinguish between mapping table pages in the complete mapping table 300 that have been updated but not yet persisted to the mapping table backup area 222. Therefore, multiple updates to the same mapping table page by write commands can first be accumulated or merged in the cached mapping table 310, and then written back to the complete mapping table 300 in batches; multiple mapping table pages in the complete mapping table 300 with the second dirty tag can also first be accumulated or identified in the complete mapping table 300, and then persisted to the mapping table backup area 222 in batches. Compared to the method of immediately writing back the complete mapping table 300 or immediately persisting it to the mapping table backup area 222 after each mapping relationship update, the above-mentioned double dirty marking mechanism can reduce the frequency of write-back between the cached mapping table 310 and the complete mapping table 300, and reduce the frequency of persistence between the complete mapping table 300 and the mapping table backup area 222.

[0060] In this embodiment, when the complete mapping table 300 needs to be restored due to power failure or abnormality of the integrated volatile memory 240, the memory controller 210 can first restore the complete mapping table 300 to the copy state corresponding to the complete copy 324 based on the complete copy 324 in the mapping table backup area 222; then, the memory controller 210 can perform an overwrite update on the corresponding mapping table page in the complete mapping table 300 based on the update result of the mapping table page with the second dirty mark recorded in the persistent copy 323 in the mapping table backup area 222, so that the complete mapping table 300 is further restored to the corresponding state within the coverage of the persistent copy 323.

[0061] In this embodiment, the number of multiple mapping table pages included in the complete mapping table 300, the number of partial mapping table pages cached in the cached mapping table 310, the update frequency of the complete copy 324, and the upper limit of the accumulation of mapping table pages with the second dirty mark accumulated in the persistent copy 323 can all be configured according to the capacity of the storage device 20, the write characteristics of the non-volatile memory module 220, and the capacity of the integrated volatile memory 240. This disclosure is not limited to the specific values ​​of the above parameters.

[0062] Based on the above Figure 2The hierarchical relationship between the complete mapping table 300, cache mapping table 310, complete copy 324 and persistent copy 323 is shown. The memory controller 210 can maintain the complete mapping table 300 in the integrated volatile memory 240, maintain the cache mapping table 310 in the memory controller 210, and save the complete copy 324 and persistent copy 323 in the mapping table backup area 222 of the non-volatile memory module 220. As shown by arrow A21, the memory controller 210 can load the corresponding mapping table page from the complete mapping table 300 to the cache mapping table 310 when the cache mapping table 310 is missed; as shown by arrow A22, the memory controller 210 can write the mapping table page with the first dirty mark from the cache mapping table 310 back to the complete mapping table 300 when the first-stage flush trigger condition is met, and set the second dirty mark; as shown by arrow A23, the memory controller 210 can persist the mapping table page with the second dirty mark to the mapping table backup area 222 to form or update the persistent copy 323. Thus, the memory controller 210 can manage the synchronization status of the mapping table pages between the cache mapping table 310, the complete mapping table 300 and the mapping table backup area 222 based on the first dirty mark and the second dirty mark, and through the cooperation of the complete copy 324 and the persistent copy 323, the complete mapping table 300 can obtain a recovery basis when the integrated volatile memory 240 loses power or is abnormal.

[0063] Figure 3 This is a flowchart illustrating the cache map 310 hit and miss processing under access commands according to an embodiment of this disclosure. Please refer to... Figure 3 In this embodiment, the memory controller 210 executes a memory management method to process access commands from the host system 10. The access commands include read commands or write commands. The memory management method includes steps S310 to S360, wherein steps S310 and S320 are routine maintenance actions during the operation of the storage device 20, and steps S330 to S360 are processing actions performed by the memory controller 210 in response to each access command.

[0064] First, in step S310, the processor 211 of the memory controller 210 maintains a complete mapping table 300 in the integrated volatile memory 240, which includes multiple mapping table pages. The mapping relationship recorded in the complete mapping table 300 is the correspondence between the logical block address (LBA) and physical block address (PBA) of the non-volatile memory module 220. Next, in step S320, the processor 211 maintains a cache mapping table 310 in the memory controller 210. The cache mapping table 310 is used to cache a portion of the multiple mapping table pages. The maintenance of the complete mapping table 300 and the cache mapping table 310 is a normal operation during the operation of the storage device 20.

[0065] Furthermore, in step S330, in response to the access command initiated by the host system 10 via the data transmission interface circuit 130 and the connection interface circuit 230, the processor 211 obtains the access logical address from the access command, that is, the logical block address carried by the access command.

[0066] In step S340, the processor 211 determines whether the cache mapping table 310 has a hit on the access logical address of the access command. Specifically, the processor 211 searches the cache mapping table 310 for a mapping entry corresponding to the access logical address; if it exists, it is considered a hit, and the processor 211 causes the memory management method to continue processing in step S360; if it does not exist, it is considered a miss, and the processor 211 continues to process the miss in step S350.

[0067] In step S350, if the cache mapping table 310 misses an access logical address, the processor 211 loads the mapping table page corresponding to the access logical address from the complete mapping table 300 in the integrated volatile memory 240 into the cache mapping table 310 via the integrated volatile memory interface 215. Specifically, the processor 211 first locates the mapping table page containing the mapping entry for the corresponding access logical address in the complete mapping table 300, loads the mapping table page via the integrated volatile memory interface 215, and incorporates it into the existing partial mapping table pages of the cache mapping table 310, so that the partial mapping table pages included in the cache mapping table 310 are updated accordingly, rather than replacing the entire contents of the cache mapping table 310.

[0068] In step S360, the processor 211 executes the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table 310. In this embodiment, regardless of whether the judgment result of step S340 is a hit or a miss, step S360 always executes the access operation based on the mapping table page to which the access logical address belongs in the cache mapping table 310. The difference lies in the source of the mapping table page: when there is a hit, the mapping table page is a mapping table page that was originally cached in the cache mapping table 310; when there is a miss, the mapping page is the mapping page loaded into the cache mapping table 310 in step S350. When the access command is a read command, the access operation reads the target data from the non-volatile memory module 220 according to the read physical address provided by the mapping table page. The specific processing flow will be referred to later. Figure 4A The embodiments further illustrate that when the access command is a write command, the access operation involves writing the write data to the non-volatile memory module 220 and updating the mapping relationship recorded in the mapping table page. The specific processing flow will be described later. Figure 4B The embodiments are further illustrated.

[0069] Based on the above Figure 3 The access command cache mapping table 310 hit and miss processing flow shown is as follows: The memory controller 210 keeps the complete mapping table 300 resident in the integrated volatile memory 240 and keeps the cache mapping table 310 resident in the memory controller 210 itself. This allows each access command to obtain the mapping table page to which the access logical address belongs from the cache mapping table 310 during the mapping lookup phase when the cache mapping table 310 is hit, without having to access the complete mapping table 300. When the cache mapping table 310 is miss, the mapping table page to which the corresponding access logical address belongs can be loaded from the complete mapping table 300 into the cache mapping table 310, and the access operation corresponding to the access command can be executed accordingly, without having to directly access the non-volatile memory module 220 to query the mapping relationship during the mapping lookup phase.

[0070] Figure 4A This is a flowchart illustrating the processing when the access command is a read command according to an embodiment of this disclosure. Please refer to... Figure 4A This embodiment is Figure 3 The illustrated specification of the access master process when the access command is a read command includes steps S411 to S416 in the memory management method.

[0071] In step S411, processor 211 maintains a complete mapping table 300 comprising multiple mapping table pages in integrated volatile memory 240. In step S412, processor 211 maintains a cache mapping table 310 in memory controller 210 for caching portions of the multiple mapping table pages.

[0072] In step S413, in response to a read command initiated by the host system 10, the processor 211 obtains the read logical address from the read command. In step S414, the processor 211 determines whether the cache mapping table 310 hits the read logical address; if it does, the processor 211 causes the memory management method to continue processing in step S416; if it does not hit, the processor 211 continues processing in step S415.

[0073] In step S415, if the cache mapping table 310 does not hit the read logical address, the processor 211 loads the mapping table page to which the read logical address belongs from the complete mapping table 300 in the integrated volatile memory 240 to the cache mapping table 310 via the integrated volatile memory interface 215. The loaded mapping table page is merged into the original part of the mapping table page in the cache mapping table 310, rather than replacing all the contents of the cache mapping table 310.

[0074] In step S416, the processor 211 retrieves the physical address corresponding to the logical address from the cache mapping table 310, and reads the target data from the non-volatile memory module 220 according to the physical address via the non-volatile memory interface control circuit 213. After the target data is read, the processor 211 returns the target data to the host system 10 via the connection interface circuit 230 and the data transmission interface circuit 130 to complete the processing of this read command. In this embodiment, when a hit occurs, the physical address is read from the cache mapping table 310 that was already cached; when a miss occurs, the physical address is read from the mapping table page loaded into the cache mapping table 310 in step S415.

[0075] Figure 4B This is a flowchart illustrating the update of the cache mapping table 310, the setting of the first dirty mark, and the first-stage flushing when the access command is a write command according to an embodiment of this disclosure. Please refer to... Figure 4B This embodiment is Figure 3 The above describes the specification of the access master process when the access command is a write command. The memory management method includes steps S421 to S428, where steps S421 to S426 are foreground write processing actions performed by the memory controller 210 in response to the write command, and steps S427 and S428 are first-stage flushing actions performed by the memory controller 210 after the write command processing is completed or when the background conditions are met.

[0076] In step S421, in response to the write command initiated by the host system 10, the processor 211 obtains the write logical address from the write command and obtains the write data carried by the write command.

[0077] In step S422, the processor 211 writes the write data to the available physical location allocated by the non-volatile memory module 220 via the non-volatile memory interface control circuit 213 to obtain the write physical address of the corresponding write data.

[0078] In step S423, processor 211 determines whether cache mapping table 310 has hit the write logical address of the write command; if it has hit, processor 211 continues to perform hit branch processing in step S424; if it has not hit, processor 211 continues to perform miss branch processing in step S425.

[0079] In step S424, if the cache mapping table 310 hits a write logical address, the processor 211 updates the physical address recorded in the mapping entry corresponding to the write logical address in the cache mapping table 310 to the write physical address, and sets a first dirty flag for the mapping table page to which the mapping entry belongs. In this embodiment, in the case of an overwrite write where the mapping table page to which the write logical address belongs already exists in the cache mapping table 310, the processor 211 does not need to load the mapping table page from the complete mapping table 300, and can directly update the mapping entry corresponding to the write logical address in the cache mapping table 310.

[0080] In step S425, if the cache mapping table 310 misses the write logical address, the processor 211 loads the mapping table page to which the write logical address belongs from the complete mapping table 300 in the integrated volatile memory 240 to the cache mapping table 310 via the integrated volatile memory interface 215. In the loaded mapping table page, the physical address recorded in the mapping entry corresponding to the write logical address is updated to the write physical address, and the first dirty flag is set on the loaded mapping table page. The loaded mapping table page is merged into the original part of the mapping table page in the cache mapping table 310, rather than replacing all the contents of the cache mapping table 310.

[0081] In step S426, after the processor 211 completes the update of the cache mapping table 310 corresponding to step S424 or S425, it returns a write completion response to the host system 10 via the connection interface circuit 230 and the data transmission interface circuit 130. Through this phased synchronization method, the host system 10's foreground response to the write command can return after the non-volatile memory module 220 completes the writing of the data and the cache mapping table 310 completes the updating of the mapping entries, without waiting for the synchronization of the complete mapping table 300 or the mapping table backup area 222.

[0082] In step S427, the processor 211 determines whether the first-stage flush trigger condition is met. The first-stage flush trigger condition includes at least one of the following: the number of mapping table pages with the first dirty mark in the cache mapping table 310 reaches a preset number threshold, or the time elapsed since the last first-stage flush reaches a preset time interval threshold. If the first-stage flush trigger condition is met, the processor 211 continues to execute the first-stage flush in step S428; if it is not met, the processor 211 ends the foreground processing flow related to the current write command and ensures that the mapping table pages with the first dirty mark in the cache mapping table 310 continue to maintain their first dirty mark.

[0083] In step S428, the processor 211 writes the mapping page with the first dirty mark in the cache mapping table 310 back to the corresponding location of the mapping page in the complete mapping table 300 via the integrated volatile memory interface 215. After the write-back is completed, the processor 211 clears the first dirty mark of the mapping page in the cache mapping table 310 and sets the second dirty mark for the corresponding mapping page in the complete mapping table 300. The first-stage flush can be performed in batches on multiple mapping pages with the first dirty mark in the cache mapping table 310.

[0084] Based on the above Figure 4B The access command shown is a write command that updates the cache mapping table 310, sets the first dirty flag, and performs a first-stage flushing process. The memory controller 210 can first write the write data to the non-volatile memory module 220 to obtain the write physical address, and then update the mapping table page to which the write logical address belongs in the cache mapping table 310 with the write physical address and set the first dirty flag. Further, the memory controller 210 can trigger the first-stage flushing based on a preset quantity threshold or a preset time interval threshold, and write multiple mapping table pages with the first dirty flag in the cache mapping table 310 back to the complete mapping table 300 in batches, so that the foreground response path of the write command is separated from the write-back path of the complete mapping table 300.

[0085] Figure 5 This is a state diagram showing multiple power consumption levels of the storage device 20 according to embodiments of the present disclosure and their correspondence with the states of the memory controller 210 and the integrated volatile memory 240. Please refer to... Figure 5In this embodiment, the storage device 20 can switch between multiple power consumption levels. The multiple power consumption levels include at least a first power consumption level as shown in block B51 and a second power consumption level as shown in block B53, and the power consumption of the second power consumption level is lower than that of the first power consumption level. In addition, the storage device 20 may also include an idle level as shown in block B52, a sleep level as shown in block B54, and a power-off state as shown in block B55. The power consumption of the idle level is between the first power consumption level and the second power consumption level, the power consumption of the sleep level is lower than that of the second power consumption level, and the power consumption of the power-off state is lower than that of the sleep level.

[0086] As shown in block B51, at the first power level, the memory controller 210 is active, and the integrated volatile memory 240 is active. The active memory controller 210 can execute the memory management methods provided in this disclosure, such as performing cache map table 310 hit checks, miss loading, and access operations in response to read or write commands from the host system 10; the active integrated volatile memory 240 can respond to the memory controller 210's access to the complete map table 300. The first power level can be considered as the active power state of the storage device 20 during normal operation.

[0087] As shown in box B52, in the idle level, the memory controller 210 can enter a clock-gated state, and the integrated volatile memory 240 can enter a slightly idle state. In this embodiment, the memory controller 210 in the clock-gated state can turn off or reduce the clock of at least part of the internal circuitry to reduce dynamic power consumption while maintaining fast recovery capability; the integrated volatile memory 240 in the slightly idle state can maintain the data retention of the complete mapping table 300 and can quickly recover its response when the memory controller 210 re-initiates access. The idle level can be considered as a moderate power consumption state of the storage device 20 during brief periods of no command load.

[0088] As shown in box B53, at the second power level, the memory controller 210 enters a first low-power mode, and the integrated volatile memory 240 enters a self-refresh mode. In this embodiment, the first low-power mode can be the Hibern8 mode defined by the Universal Flash Storage (UFS) standard. In Hibern8 mode, the memory controller 210 can reduce the power supply or clock activity of at least some of its internal circuitry. The self-refresh mode can be the self-refresh mode defined by the Low-Power Double Data Rate Synchronous Dynamic Random Access Memory (LPDDR) standard. In self-refresh mode, the integrated volatile memory 240 can maintain the data of the complete mapping table 300 through its internal refresh mechanism. When the data is maintained normally in self-refresh mode, the complete mapping table 300 can continue to be maintained in the integrated volatile memory 240, reducing the need for the storage device 20 to recover the complete mapping table 300 from the non-volatile memory module 220 when returning from the second power level to the first power level.

[0089] As shown in box B54, in the sleep level, the memory controller 210 enters a second low-power mode, and the integrated volatile memory 240 enters a sleep state. In this embodiment, the integrated volatile memory 240 in the sleep state can further reduce power consumption compared to the self-refresh mode (e.g., shutting down more peripheral circuits or reducing the activity of the relevant clock domain), while maintaining the complete mapping table 300 with the minimum activity required to maintain data retention; thus, the integrated volatile memory 240 still retains the complete mapping table 300 in the sleep state, unlike in the power-off state where the complete mapping table 300 cannot be maintained, so that when the storage device 20 wakes up the integrated volatile memory 240 from the sleep level, it does not need to reload the complete mapping table 300 from the non-volatile memory module 220.

[0090] As shown in box B55, in the power-off state, the memory controller 210 enters the third low-power mode, and the integrated volatile memory 240 enters the power-off state. The power supply to the integrated volatile memory 240 in the power-off state can be cut off to further reduce standby power consumption. Since the integrated volatile memory 240 cannot maintain the complete mapping table 300 after power failure, before the storage device 20 switches to the power-off state, all mapping table pages with the second dirty mark in the complete mapping table 300 must first be persisted to the mapping table backup area 222 of the non-volatile memory module 220 for updating the pre-saved complete copy 324 in the non-volatile memory module 220. The specific actions regarding the persistence of mapping table pages with the second dirty mark from the complete mapping table 300 to the mapping table backup area 222 will be discussed later. Figure 6 The embodiments are further illustrated.

[0091] As shown by arrows A51 to A54, in this embodiment, the memory controller 210 can trigger the storage device 20 to switch between a first power level, an idle level, and a second power level based on at least one of the current command load and timing conditions. For example, when the memory controller 210 detects that the current command load has decreased or the time elapsed since the last command received from the host system 10 has reached a first timing threshold, the storage device 20 can be switched from the first power level to the idle level; when the idle state continues to reach a second timing threshold, the storage device 20 can be further switched from the idle level to the second power level; conversely, when the memory controller 210 receives a new command initiated by the host system 10 or detects a wake-up event, the storage device 20 can be returned from the second power level or the idle level to the first power level.

[0092] As shown by arrow A55, the memory controller 210 may, in response to a second type of low-power indication, switch the storage device 20 from a second power level to a sleep level. As shown by arrow A56, the memory controller 210 may, in response to a third type of low-power indication, switch the storage device 20 from a sleep level to a power-off state. In this embodiment, the second and third type of low-power indications may originate from the host system 10 or from upper-layer power management logic within the storage device 20. This disclosure is not limited to the specific source and form of the second and third type of low-power indications.

[0093] It should be noted that, Figure 5 The five states shown—the first power consumption level (block B51), the idle level (block B52), the second power consumption level (block B53), the sleep level (block B54), and the power-off state (block B55)—and the transition conditions between these states, are merely exemplary embodiments of this disclosure. In another embodiment, the storage device 20 may include more or fewer power consumption levels, and the method for determining command load, the specific threshold of timing conditions, and the specific forms of the second and third types of low-power indicators can also be adjusted according to the specific application scenario of the storage device 20. This disclosure is not limited to the specific number of power consumption levels or the specific definition of transition conditions.

[0094] Furthermore, an adaptive dynamic power consumption level may be included between the first power consumption level and the second power consumption level. When the memory controller 210 detects continuous large file read / write operations (such as loading AI training data), it prevents the integrated volatile memory 240 from entering a low-power state, ensuring that its bandwidth is fully utilized, i.e., maintaining Active Mode (full-speed operation); while if the host does not receive an IO request for a certain period of time (such as 50ms), the memory controller 210 can power off the integrated volatile memory 240.

[0095] Based on the above Figure 5 The storage device 20 is shown to have multiple power consumption levels and their correspondence with the memory controller 210 and the integrated volatile memory 240. The storage device 20 can switch between a first power consumption level, an idle level, a second power consumption level, a sleep level, and a power-off state according to the current command load, timing conditions, a second type of low power consumption indication, and a third type of low power consumption indication. In the second power consumption level and the sleep level, the integrated volatile memory 240 retains the complete mapping table 300 through self-refresh mode and sleep state, respectively, so that the storage device 20 can reduce the need to restore the complete mapping table 300 from the non-volatile memory module 220 when returning to the active state. In the power-off state, the complete copy 324 is updated by pre-persisting the mapping table page with the second dirty mark, providing a basis for recovery after power failure.

[0096] Figure 6 A flowchart illustrating how a storage device 20, according to an embodiment of this disclosure, performs map page persistence in response to a first type low-power indication, a second type low-power indication, and a third type low-power indication. Please refer to... Figure 6 In this embodiment, the memory controller 210 of the storage device 20 executes a memory management method to process an indication of entering a low-power state. The memory management method includes steps S610 and S620, as well as steps S630a and S640a, S630b and S640b, and S630c and S640c, respectively, which correspond to the first, second, and third types of low-power indications.

[0097] First, in step S610, the processor 211 of the memory controller 210 receives an indication to enter a low-power state. The indication to enter the low-power state may come from the host system 10 or from the upper-level power management logic inside the storage device 20.

[0098] Next, in step S620, the processor 211 determines the type of the indication to enter a low-power state. In this embodiment, the indication to enter a low-power state includes a first type of low-power indication, a second type of low-power indication, and a third type of low-power indication; the processor 211 then continues to execute the corresponding branch processing accordingly.

[0099] In step S630a, if the indication for entering a low-power state is a first type of low-power indication, the processor 211 determines a critical mapping page from the plurality of mapping pages included in the complete mapping table 300 in the integrated volatile memory 240, and writes the critical mapping page to the mapping table backup area 222 of the non-volatile memory module 220 via the non-volatile memory interface control circuit 213 to update the persistent copy 323. In this embodiment, the critical mapping page includes at least one of the following: a first subset consisting of mapping pages with a second dirty mark in the complete mapping table 300; or a second subset consisting of mapping pages whose access frequency exceeds a preset frequency threshold within a preset time window. In some embodiments, the processor 211 may determine the first subset and the second subset in parallel, and use the union of the first subset and the second subset as the critical mapping page; if a mapping page belongs to both the first subset and the second subset, the mapping page is retained only once in the critical mapping page to reduce repeated persistence and the resulting additional writes.

[0100] In step S640a, the processor 211 causes the memory controller 210 to enter a first low-power mode and the integrated volatile memory 240 to enter a self-refresh mode. In this embodiment, the first low-power mode can be the Hibern8 mode defined by the UFS standard, and the self-refresh mode can be the self-refresh mode defined by the LPDDR standard. In the first low-power mode and the self-refresh mode, the complete mapping table 300 can be maintained in the integrated volatile memory 240; when the self-refresh normally maintains the data, the storage device 20 does not need to reload the complete mapping table 300 from the non-volatile memory module 220 when returning to the active state from the low-power state corresponding to the first type of low-power indication.

[0101] In step S630b, if the indication for entering a low-power state is a second type of low-power indication, the processor 211 writes at least a portion of the mapping table pages of the complete mapping table 300 in the integrated volatile memory 240 to the mapping table backup area 222 of the non-volatile memory module 220 via the non-volatile memory interface control circuit 213, so as to retain a persistent copy 323 of at least a portion of the mapping table pages in the non-volatile memory module 220 before the integrated volatile memory 240 enters a sleep state.

[0102] In step S640b, the processor 211 causes the memory controller 210 to enter a second low-power mode and puts the integrated volatile memory 240 into a sleep state. In this embodiment, the integrated volatile memory 240 in the sleep state can further reduce power consumption compared to the self-refresh mode, while retaining the complete mapping table 300; thus, when the storage device 20 wakes up the integrated volatile memory 240 from the sleep state, it does not need to reload the complete mapping table 300 from the non-volatile memory module 220. In this embodiment, since the integrated volatile memory 240 retains the complete mapping table 300 in the sleep state, the persistent copy 323 of at least a portion of the mapping table pages written in step S630b can be used as the basis for restoring the complete mapping table 300 in abnormal situations, rather than for normal reloading after waking up from sleep.

[0103] In step S630c, if the indication for entering the low-power state is a third type of low-power indication, the processor 211 writes all the mapping table pages with the second dirty mark in the complete mapping table 300 in the integrated volatile memory 240 to the mapping table backup area 222 of the non-volatile memory module 220 via the non-volatile memory interface control circuit 213, so as to update the pre-saved complete copy 324 in the mapping table backup area 222, so that the mapping relationship corresponding to all the mapping table pages with the second dirty mark is persisted to the non-volatile memory module 220 before the integrated volatile memory 240 is powered off.

[0104] In step S640c, the processor 211 causes the memory controller 210 to enter a third low-power mode and controls the integrated volatile memory 240 to enter a power-off state. In this embodiment, the processor 211 can stop or disconnect the operating voltage supplied to the integrated volatile memory 240 through the power management logic inside the storage device 20, causing the integrated volatile memory 240 to enter a power-off state. In the power-off state, the complete mapping table 300 cannot continue to be maintained by the integrated volatile memory 240; therefore, upon subsequent wake-up from the power-off state, the processor 211 can rebuild the complete mapping table 300 in the integrated volatile memory 240 based on the complete copy 324 stored in the mapping table backup area 222. In some embodiments, if a persistent copy 323 is also stored in the mapping table backup area 222, the processor 211 can also update the rebuilt complete mapping table 300 accordingly based on the persistent copy 323.

[0105] Based on the above Figure 6The storage device 20 shown executes a mapping table page persistence process in response to a first type of low-power indication, a second type of low-power indication, and a third type of low-power indication. Under the first type of low-power indication, the memory controller 210 can determine and persist the union of mapping table pages with a second dirty mark and frequently accessed mapping table pages as critical mapping table pages, and then cause the integrated volatile memory 240 to enter a self-refresh mode to maintain the complete mapping table 300. Under the second type of low-power indication, after persisting at least some mapping table pages, the integrated volatile memory 240 can enter a sleep state to retain the complete mapping table 300. Under the third type of low-power indication, after persisting all mapping table pages with the second dirty mark in the complete mapping table 300 to update the complete copy 324, the integrated volatile memory 240 can enter a power-off state. Thus, the storage device 20 can select between three low-power strategies—self-refresh retention, sleep retention, and updating the complete copy 324 before power-off—depending on the type of indication for entering a low-power state.

[0106] First, in stage 1 wake-up, as shown in step S711, a wake-up event occurs to wake up from the self-refresh mode of the integrated volatile memory 240. The wake-up event may be, for example, the host system 10 releasing the low-power state request of the storage device 20, or the internal power management logic of the storage device 20 determining that the low-power state has ended. Next, as shown in step S712, in response to the wake-up event in step S711, the memory controller 210 restores power and clock, causing the processor 211 to re-enter the active state capable of executing the memory management method. Further, as shown in step S713, the processor 211 sends an instruction to the integrated volatile memory 240 to exit the self-refresh mode, requesting the integrated volatile memory 240 to begin exiting the self-refresh mode.

[0107] Next, during the exit self-refresh phase 2, as shown in step S721, the integrated volatile memory 240 responds to the exit self-refresh mode instruction sent in step S713 and begins to execute the internal program for exiting the self-refresh mode. Figure 7The process of exiting the self-refresh mode is represented by a continuously active segment on the lifeline of the integrated volatile memory 240, which can continue until the exit is completed as shown in step S731. In this embodiment, the time required for the integrated volatile memory 240 to exit the self-refresh mode and re-enter an active state that is responsive to access by the processor 211 can be, for example, on the order of tens of microseconds. During the exit time, as shown in step S722, the host system 10 can send a command to the storage device 20. The command can be a command that does not involve logical address to physical address mapping, or a command that carries a logical address and can perform cache hit determination. Further, as shown in step S723, the processor 211 receives the command, and when the command carries a logical address, the cache mapping table 310 carried in the buffer memory 214 queries whether the logical address carried by the command has been hit.

[0108] In this embodiment, Figure 7 During the second phase of exiting the self-refresh, processing branches under different command conditions are further represented by alternative blocks. In the first branch, if the command received by the processor 211 does not involve a mapping conversion from logical address to physical address, or if the logical address carried by the command hits the cache mapping table 310, then as shown in step S724a, the processor 211 executes the processing corresponding to the command based on the status information in the cache mapping table 310 or the processor 211, without waiting for the integrated volatile memory 240 to complete exiting the self-refresh mode before executing the processing corresponding to the command. In the second branch, if the command received by the processor 211 involves a mapping conversion from logical address to physical address, and the logical address carried by the command does not hit the cache mapping table 310, then as shown in step S724b, the processor 211 may temporarily store the command in the buffer memory 214 or make the command wait for the integrated volatile memory 240 to complete exiting the self-refresh mode. In some embodiments, the processor 211 may also return a busy response to the host system 10. This disclosure is not limited to the specific processing method of the cache miss branch during the exit from the self-refresh mode.

[0109] Finally, in the completion of stage 3, as shown in step S731, the integrated volatile memory 240 exits the self-refresh mode and re-enters an active state accessible by the processor 211. The integrated volatile memory 240 may return a self-refresh mode exit completion response to the processor 211. Figure 7The dashed line representing the exit completion response distinguishes it from the forward messages indicated by the solid arrows during Phase 1 wake-up and Phase 2 exit self-refresh. For the missed commands temporarily stored or waiting in step S724b, as shown in step S725, after the integrated volatile memory 240 completes the exit from self-refresh mode, the processor 211 can load the corresponding mapping table page from the complete mapping table 300 in the integrated volatile memory 240 to the cache mapping table 310 via the integrated volatile memory interface 215, and execute the missed command accordingly.

[0110] In this embodiment, the core of the tiered wake-up timing is as follows: In Phase 1, the power supply and clock of the memory controller 210 are restored first, so that the processor 211 can start receiving and judging the commands initiated by the host system 10 before the integrated volatile memory 240 has completed its self-refresh mode exit; During Phase 2, when the self-refresh mode exits, the processor 211 is allowed to execute commands that do not involve logical address to physical address mapping or commands that have been hit in the cache mapping table 310, using the portion of the mapping table pages already saved in the cache mapping table 310 or the state information kept inside the processor 211, without being blocked by the time consumption of the integrated volatile memory 240 exiting; For commands that involve logical address to physical address mapping and have not hit the cache mapping table 310, the corresponding mapping table page can be loaded from the complete mapping table 300 and the command executed after the integrated volatile memory 240 has completed its self-refresh mode exit. Therefore, storage device 20 can process commands that do not rely on access to the complete mapping table 300 or cache hits in advance while the integrated volatile memory 240 is exiting the self-refresh mode, thereby reducing the chance of such commands waiting for the integrated volatile memory 240 to complete exiting the self-refresh mode, while preserving the processing path for cache miss commands after exiting the self-refresh mode.

[0111] Based on the above Figure 7The illustrated storage device 20 is awakened from the self-refresh mode of the integrated volatile memory 240 in a hierarchical wake-up sequence. In response to the wake-up event from the self-refresh mode, the memory controller 210 restores its power supply and clock, and sends an instruction to the integrated volatile memory 240 to exit the self-refresh mode, causing the integrated volatile memory 240 to begin exiting the self-refresh mode. During the exit of the integrated volatile memory 240 from the self-refresh mode, if the command received by the memory controller 210 does not involve a logical address to physical address mapping, or if the logical address carried by the command hits the cache mapping table 310, then the processing corresponding to the command is executed based on the status information in the cache mapping table 310 or the memory controller 210, without waiting for the integrated volatile memory 240 to complete exiting the self-refresh mode before executing the processing corresponding to the command. If the command involves a logical address to physical address mapping and does not hit the cache mapping table 310, then after the integrated volatile memory 240 completes exiting the self-refresh mode, the corresponding mapping table page can be loaded from the complete mapping table 300 and the corresponding processing executed. Therefore, the perceived latency of the host system 10 for waking up the storage device 20 from the self-refresh mode can be decoupled from at least part of the time required for the integrated volatile memory 240 to exit the self-refresh mode, thereby enabling the storage device 20 to achieve a relative balance between low-power state switching and command response latency.

[0112] Figure 8 This is a flowchart illustrating how a storage device 20, according to an embodiment of the present disclosure, performs an integrity check on a complete mapping table 300 in integrated volatile memory 240 in response to a wake-up event, and performs valid copy backfilling or metadata reconstruction on mapping table pages that fail the integrity check. Please refer to... Figure 8 In this embodiment, the memory controller 210 of the storage device 20 executes a memory management method to handle the integrity check and recovery process. The memory management method includes steps S810 to S880.

[0113] First, in step S810, the processor 211 of the memory controller 210, in response to a wake-up event, initiates an integrity check and recovery process for the complete mapping table 300 in the integrated volatile memory 240. In this embodiment, the wake-up event may include a wake-up event from the self-refresh mode of the integrated volatile memory 240, a power-on wake-up event from the power-off state of the integrated volatile memory 240, or a recovery wake-up event after the storage device 20 has been powered on again following an abnormal power outage. In some embodiments, after the integrity check and recovery process is initiated, the processor 211 may perform the integrity check page-by-page in a background asynchronous manner to reduce the chance of the integrity check process blocking the host system 10 from accessing the storage device 20.

[0114] Next, in step S820, the processor 211 performs integrity checks on each of the multiple mapping table pages included in the complete mapping table 300 in the integrated volatile memory 240. In this embodiment, the processor 211 selects a mapping table page from the complete mapping table 300 as a target mapping table page and performs an integrity check on the target mapping table page; after completing the processing of the current target mapping table page, the processor 211 may continue to select the next unchecked mapping table page in the complete mapping table 300 as a new target mapping page, until all multiple mapping pages in the complete mapping table 300 have been processed.

[0115] Further, in step S830, the processor 211 calculates the Cyclic Redundancy Check (CRC) code for the currently selected target mapping page and compares the calculated CRC code with the pre-stored reference code corresponding to the target mapping page. In this embodiment, the pre-stored reference code can be calculated by the processor 211 and stored in a designated segment of the integrated volatile memory 240 or in the non-volatile memory module 220 when the target mapping page is written into the complete mapping table 300 or persisted to the mapping table backup area 222 of the non-volatile memory module 220, for comparison in step S830. The algorithm for calculating the CRC code can be, for example, the CRC-32 standard or other CRC algorithms, and this disclosure is not limited to the specific algorithm of the CRC code.

[0116] Furthermore, in step S840, processor 211 determines whether the comparison result of the cyclic redundancy check (CRC) code of the target mapping table page is consistent with the pre-stored reference code. If the comparison result is consistent, processor 211 continues to step S850 to select the next unchecked mapping table page in the complete mapping table 300 as the new target mapping table page, and returns to step S820 to perform an integrity check on the new target mapping table page. If the comparison result is inconsistent, processor 211 continues to step S860 to determine whether there is a valid copy of the corresponding target mapping table page.

[0117] In step S860, the processor 211 determines whether a valid copy of the corresponding target mapping table page exists in the mapping table backup area 222 of the non-volatile memory module 220. In this embodiment, a valid copy refers to the mapping table page content stored in the mapping table backup area 222 that corresponds to the logical address range covered by the target mapping table page and has been verified as trustworthy. The valid copy may come from the location of the corresponding target mapping table page in the complete copy 324, or from the mapping page content of the corresponding target mapping page in the persistent copy 323. If a valid copy exists in the mapping table backup area 222, the processor 211 continues to perform valid copy backfilling in step S870; if a valid copy does not exist in the mapping table backup area 222, the processor 211 continues to perform reconstruction of the marker to be rebuilt and metadata in step S880.

[0118] In step S870, if a valid copy of the corresponding target mapping table page exists in the mapping table backup area 222, the processor 211 reads the valid copy of the corresponding target mapping table page from the mapping table backup area 222 via the non-volatile memory interface control circuit 213, and overwrites the valid copy into the corresponding position of the complete mapping table 300 in the integrated volatile memory 240 via the integrated volatile memory interface 215, thereby replacing the target mapping table page. In some embodiments, after the valid copy replaces the target mapping table page, the processor 211 can re-perform cyclic redundancy check (CRC) calculation and comparison on the replaced target mapping table page to verify whether the replaced target mapping page is valid. If the verification passes, the processor 211 can continue to select the next mapping table page for checking.

[0119] In step S880, if there is no valid copy of the corresponding target mapping table page in the mapping table backup area 222, the processor 211 marks the target mapping table page as to be rebuilt. Upon receiving a command covering the logical address range of the target mapping table page, the processor reconstructs the mapping relationship of the target mapping table page based on the metadata in the non-volatile memory module 220. In this embodiment, the metadata may include the reverse mapping information from logical address to physical address recorded in the page header of the physical page or physical block in the non-volatile memory module 220. The processor 211 can reconstruct the mapping relationship of the target mapping table page and write it back to the complete mapping table 300 in the integrated volatile memory 240 by scanning the metadata in the non-volatile memory module 220 corresponding to the logical address range covered by the target mapping table page. Before the command corresponding to the logical address range covered by the target mapping page is received, the target mapping table page can temporarily maintain the state of being marked as to be rebuilt, so that the metadata reconstruction action is performed when the corresponding command arrives, thereby reducing the overhead of scanning metadata once during the wake-up phase.

[0120] In some embodiments, after completing the processing of the current target mapping page as shown in step S870 or step S880, the processor 211 may continue to perform integrity checks on other mapping pages in the complete mapping table 300 that have not yet been checked. Figure 8 For ease of explanation, the processing results after steps S870 and S880 are merged into the end node, but this disclosure is not limited to processing only a single target mapping page.

[0121] In another embodiment, after the storage device 20 is powered on again from a completely power-off state, the memory controller 210 can execute a cold boot recovery process of the complete mapping table 300. The completely power-off state may include corresponding... Figure 6 The power outage state caused by the third type of low power indicator, or the abnormal power outage state of storage device 20, is shown. The cold start recovery process may include stages such as writing back the first batch of critical mapping table pages, partially unblocking foreground commands, and writing back the remaining mapping table pages in the background.

[0122] During the initial critical mapping page write-back phase, the processor 211 can read the first batch of critical mapping pages of the complete mapping table 300 from the mapping table backup area 222 of the non-volatile memory module 220 via the non-volatile memory interface control circuit 213, and write them to the integrated volatile memory 240 via the integrated volatile memory interface 215, so that the first batch of critical mapping pages are written to the positions corresponding to the complete mapping table 300. In this embodiment, the first batch of critical mapping pages may include mapping pages corresponding to the recently active logical address range identified from the complete copy 324 and persistent copy 323 stored in the mapping table backup area 222; the number of the first batch of critical mapping pages can be determined according to the boot time target of the storage device 20 and the capacity of each mapping page, and this disclosure is not limited to the specific number of the first batch of critical mapping pages.

[0123] During the foreground command unblocking phase, after the first batch of critical mapping pages are ready in the integrated volatile memory 240, the processor 211 can unblock the memory controller 210 from processing some foreground commands. For the logical address range covered by the first batch of critical mapping pages, the processor 211 can use the cached mapping table 310 in conjunction with the complete mapping table 300 to serve read and write commands; for the logical address range not covered by the first batch of critical mapping pages, the processor 211 can temporarily respond to read commands by querying the physical address recorded in the corresponding mapping page from the mapping table backup area 222 via the non-volatile memory interface control circuit 213, and pull the corresponding mapping page into the corresponding position in the complete mapping table 300 in the integrated volatile memory 240 in the background.

[0124] During the background write-back phase of the remaining mapping table pages, the processor 211 can read the remaining mapping table pages in batches from the mapping table backup area 222 of the non-volatile memory module 220 according to priority in the background, and write them back to the corresponding positions of the complete mapping table 300 in the integrated volatile memory 240 via the integrated volatile memory interface 215, until multiple mapping table pages in the complete mapping table 300 are restored. Therefore, after the storage device 20 is powered on again from a completely power-off state, it can start serving some commands after the first batch of critical mapping table pages are ready, without waiting for all mapping table pages in the complete mapping table 300 to be written back from the mapping table backup area 222 to the integrated volatile memory 240 before starting service. In some embodiments, after the first batch of critical mapping table pages are written to the integrated volatile memory 240, the processor 211 can also execute the following on the first batch of critical mapping table pages: Figure 8 The main process performs an integrity check to verify the validity of the first batch of critical mapping pages.

[0125] Based on the above Figure 8 The integrity check and recovery process shown describes how the memory controller 210, in response to a wake-up event, performs a page-by-page comparison of the cyclic redundancy check (CRC) code with a pre-stored reference code on multiple mapping pages in the complete mapping table 300 to determine if a mapping page is suspected of being faulty or experiencing bit flips. For target mapping pages with inconsistent comparison results, the memory controller 210 prioritizes using a valid copy stored in the mapping table backup area 222 for backfilling. If no corresponding valid copy exists in the mapping table backup area 222, the target mapping page is marked as needing reconstruction. Upon receiving a command for the corresponding logical address range, the mapping relationship of the target mapping page is reconstructed based on the metadata in the non-volatile memory module 220. Therefore, after a wake-up event occurs, the storage device 20 can selectively recover suspected faulty mapping pages in the complete mapping table 300 without having to reload all mapping pages of the complete mapping table 300 at once during the wake-up phase, thereby reducing the recovery overhead during the wake-up phase and preserving the basis for mapping relationship recovery.

[0126] Figure 9 This is a schematic diagram illustrating the structure of the cache mapping table 310 according to an embodiment of the present disclosure, which establishes an index based on the high-order address segment of the access logical address and uses it to look up the corresponding mapping entry. Please refer to... Figure 9 In one embodiment, the index structure of the cache mapping table 310 is organized according to the high-order address segment of the access logical address, as shown in block B91. Therefore, the memory controller 210 can look up the mapping entry for the corresponding access logical address within the cache mapping table 310 based on the high-order address segment of the access logical address. Figure 9Two specific implementation methods for establishing an index based on the high-order address segment are shown in the examples: Example 1 is an index structure of cache mapping table 310 carried by a hash table as shown in box B94, and Example 2 is an index structure of cache mapping table 310 carried by content-addressable memory (CAM) as shown in box B97.

[0127] First, such as Figure 9 As shown at the top, the high-order address segment indicated by box B91 and the remaining access logical address shown to its right together constitute the overall structure of the access logical address. In this embodiment, when the processor 211 determines whether the cache mapping table 310 has a hit on the access logical address, it extracts the high-order address segment from the access logical address and searches the cache mapping table 310 for a mapping entry corresponding to the access logical address based on the high-order address segment. The bit width of the high-order address segment can be, for example, selected as a certain number of the high bits of the access logical address, such as 8 bits to 16 bits; the remaining access logical address is the remaining bits after deducting the high-order address segment from the access logical address. In this embodiment, the high-order address segment can be used to locate the mapping table page or index entry to which the access logical address belongs, and the remaining access logical address can be used to further locate the mapping entry corresponding to the access logical address within the corresponding mapping table page.

[0128] In Example 1, as Figure 9As shown in the upper part, the cache mapping table 310 can be organized as a hash table as shown in box B94. The hash table includes multiple hash buckets, which are storage groups in the hash table used to store one or more candidate mapping entries. Specifically, the processor 211 extracts the high-order address segment from the access logical address, as shown in box B92; as shown by arrow A91, the processor 211 provides the high-order address segment to the hash function shown in box B93. The hash function performs a hash operation on the high-order address segment to generate a hash result for locating the target hash bucket; as shown by arrow A92, the hash result is used to locate the target hash bucket among the multiple hash buckets in the hash table shown in box B94; as shown by arrow A93, the processor 211 searches for the mapping entry corresponding to the access logical address in the target hash bucket shown in box B95. In other words, in the hash table implementation, the processor 211 does not need to search through all the mapping entries cached in the cache mapping table 310 one by one, but first uses the high-order address segment to calculate the target hash bucket to be queried, and then only searches for candidate mapping entries in that target hash bucket. For example, in a specific example, if the high-order address segment of the accessed logical address is a value representing a logical address range, the processor 211 can perform a modulo operation or an XOR folding operation on the high-order address segment to obtain the target hash bucket number. Subsequently, the processor 211 searches only in the hash bucket corresponding to the target hash bucket number to see if there is a mapping entry that matches the accessed logical address. If a matching mapping entry is found, the processor 211 can obtain the corresponding physical address; if no matching mapping entry is found, the processor 211 can determine that the cache mapping table 310 has not hit the accessed logical address. In this embodiment, the hash function can employ modulo operation, XOR folding, or other hash algorithms, and this disclosure is not limited to the specific algorithm of the hash function.

[0129] In Example 2, as Figure 9As shown in the lower section, the index structure of the cache mapping table 310 can be implemented by the content-addressable memory (MAP) shown in box B97. Specifically, the processor 211 extracts the high-order address segment from the access logical address, as shown in box B96; as shown by arrow A94, the processor 211 sends the high-order address segment into the MAP; the MAP performs hardware parallel comparison on the multiple index entries stored therein; as shown by arrow A95, the MAP outputs the hit position or miss signal corresponding to the high-order address segment, as shown in box B98. In other words, in the MAP implementation, the processor 211 does not need to calculate the target hash bucket first, nor does it need to compare multiple index entries one by one by software. Instead, it sends the high-order address segment as the comparison content into the MAP, and the MAP simultaneously compares the multiple index entries stored therein. For example, in a specific example, the content-addressable memory (COM) can pre-store multiple index entries, each corresponding to the high-order address segment of a cached mapping table page. When the processor 211 sends the high-order address segment of the current access logical address to the COM, the COM can determine in parallel whether the high-order address segment matches any index entry. If a matching index entry exists, the COM outputs a hit location, which indicates the storage location of the corresponding mapping entry in the cache mapping table 310. If no matching index entry exists, the COM outputs a miss signal to inform the processor 211 that the cache mapping table 310 has not hit the access logical address. Compared to the method of comparing multiple index entries one by one by the processor 211, the COM can reduce the search burden of the processor 211 through hardware parallel comparison. Compared to the COM implementation method, the hash table implementation method can reduce the demand for hardware resources for parallel comparison. The actual choice of implementation method can be determined according to the specific requirements of the storage device 20 for query latency, hardware area, and power consumption.

[0130] Based on the hash table indexing method shown in Embodiment 1 and the content-addressable memory indexing method shown in Embodiment 2, the cache mapping table 310 can be indexed according to the high-order address segment of the access logical address. The commonality between the two implementations is that when the processor 211 determines whether the cache mapping table 310 hits an access logical address, it first extracts the high-order address segment from the access logical address, and then searches the cache mapping table 310 for a mapping entry corresponding to the access logical address based on the high-order address segment. The difference lies in that Embodiment 1 uses the hash function shown in block B93 and the hash table shown in block B94 to locate the target hash bucket shown in block B95, and then searches for the mapping entry in the target hash bucket; Embodiment 2 uses the content-addressable memory shown in block B97 to perform parallel comparisons on multiple index entries stored therein, and outputs the hit position or miss signal shown in block B98.

[0131] Based on the above Figure 9 The cache mapping table 310 shown is structured by indexing the high-order address segments of the access logical address and using this index to look up the corresponding mapping entries. The memory controller 210 can extract the high-order address segments from the access logical address and perform hash table indexing or content-addressable memory indexing based on these segments. Through hash table indexing, the processor 211 can narrow the search range to the target hash bucket without having to compare all mapping entries in the cache mapping table 310 one by one. Through content-addressable memory indexing, the processor 211 can use hardware parallel comparison to obtain the hit location or miss signal without having to compare multiple index entries one by one. Therefore, when determining whether the cache mapping table 310 hits an access logical address, the memory controller 210 can reduce the linear search of all mapping entries in the cache mapping table 310 and reduce the impact on the hit determination path when the number of cached pages in the cache mapping table 310 increases.

[0132] Figure 10 This is a timing diagram illustrating the interaction between the storage device 20 according to an embodiment of the present disclosure and the host system 10 in response to a read command, including hit query, miss load, and read return. Please refer to... Figure 10 In this embodiment, the read command interaction timing involves four participating units: the host system 10, the processor 211 of the memory controller 210, the buffer memory 214 of the memory controller 210, and the integrated volatile memory 240. The buffer memory 214 can hold at least a portion of the cache mapping table 310, and the integrated volatile memory 240 can hold the complete mapping table 300. The read command interaction timing includes three timing stages: stage 1 receiving a query, stage 2 loading if a miss occurs, and stage 3 reading back.

[0133] First, in Phase 1 of the query reception process, as shown in step S1011, the host system 10 sends a read command to the processor 211. The read command carries the read logical address, i.e., the logical block address carried by the read command. Next, as shown in step S1012, in response to the read command, the processor 211 determines whether the cache mapping table 310 carried in the buffer memory 214 matches the read logical address. Further, as shown in step S1013, if the cache mapping table 310 matches the read logical address, the processor 211 retrieves the corresponding read physical address from the cache mapping table 310. Figure 10 The dashed line representing the return response from buffer memory 214 to processor 211 indicates the return process of reading the physical address. In the case of a cache hit in cache mapping table 310, processor 211 can skip stage 2 (missed load) and directly continue the reading operation with the steps shown in stage 3 (read return).

[0134] On the other hand, during the miss loading in stage 2, if the cache mapping table 310 misses the read logical address, then as shown in step S1021, the processor 211 sends a load request to the integrated volatile memory 240 via the integrated volatile memory interface 215 to request that the mapping table page to which the read logical address belongs be loaded from the complete mapping table 300 in the integrated volatile memory 240 into the cache mapping table 310. Next, as shown in step S1022, in response to the load request, the integrated volatile memory 240 obtains the mapping table page to which the read logical address belongs from the complete mapping table 300, and returns the mapping table page to the processor 211 with a return response dotted line. Further, as shown in step S1023, the processor 211 loads the mapping table page obtained from the integrated volatile memory 240 into the cache mapping table 310, updating the cached portion of the mapping table pages accordingly, and obtains the read physical address corresponding to the read logical address from the loaded mapping table page. In some embodiments, mapping pages may be added to cache mapping table 310, or existing mapping pages in cache mapping table 310 may be replaced according to the replacement strategy of cache mapping table 310.

[0135] Finally, in stage 3 read return, as shown in step S1031, processor 211 reads the target data corresponding to the read physical address from non-volatile memory module 220 via non-volatile memory interface control circuit 213 according to the obtained read physical address. Figure 10 The processor 211 uses a loopback message on its own lifeline to indicate the target data reading action, and omits the lifelines of the non-volatile memory interface control circuit 213 and the non-volatile memory module 220. Next, as shown in step S1032, the processor 211 returns the target data to the host system 10 via the connection interface circuit 230 and the data transmission interface circuit 130 to complete the processing of this read command.

[0136] In this embodiment, the core of the read command interaction timing is as follows: Stage 1 receives the query and checks the read logical address carried by the read command through the cache mapping table 310. If a hit occurs, the processor 211 can skip Stage 2 (missed load) and directly enter Stage 3 (read return). This ensures that in the case of a cached map 310 hit, the host system 10's response path to the read command does not include loading the mapping table page from the integrated volatile memory 240. If a miss occurs, the processor 211 enters Stage 2 (missed load), retrieves the mapping table page corresponding to the read logical address from the complete mapping table 300 in the integrated volatile memory 240, merges it into the cache mapping table 310, and then enters Stage 3 (read return). Since the access latency of the integrated volatile memory 240 is usually lower than that of the non-volatile memory module 220, this embodiment can reduce the loading latency of the mapping table page when the cache mapping table 310 is missed, compared to reading the corresponding mapping table page from the non-volatile memory module 220 when the cache miss occurs.

[0137] Based on the above Figure 10 The storage device 20 shown responds to a read command initiated by the host system 10 by executing an interactive timing sequence of hit query, miss load, and read return. The processor 211 of the memory controller 210 responds to the read command by first determining whether the cache mapping table 310 hits the read logical address of the read command in stage 1 (receiving query). If the cache mapping table 310 misses the read logical address, then in stage 2 (miss load), the mapping table page to which the read logical address belongs is loaded from the complete mapping table 300 in the integrated volatile memory 240 into the cache mapping table 310. Then, in stage 3 (read return), the read physical address corresponding to the read logical address is obtained from the cache mapping table 310, and the target data is read from the non-volatile memory module 220 according to the read physical address and returned to the host system 10. Therefore, the processor 211 can omit the mapping table page loading action in the hit scenario, and can load the corresponding mapping table page via the integrated volatile memory 240 in the miss scenario, without having to read the corresponding mapping table page or the complete mapping table 300 from the non-volatile memory module 220 during the mapping lookup phase.

[0138] Figure 11 This is a timing diagram illustrating the interaction between the storage device 20, according to an embodiment of the present disclosure, executing a write response in response to a write command initiated by the host system 10, and the first-stage brush operation. Please refer to... Figure 11In this embodiment, the write command interaction timing involves five participating units: the host system 10, the processor 211 of the memory controller 210, the buffer memory 214 of the memory controller 210, the integrated volatile memory 240, and the non-volatile memory module 220. The buffer memory 214 can hold at least a portion of the cache mapping table 310, and the integrated volatile memory 240 can hold the complete mapping table 300. The write command interaction timing includes two timing stages: Stage 1 write response and Stage 2 first-stage flush.

[0139] First, in the Phase 1 write response, as shown in step S1111, the host system 10 sends a write command to the processor 211. The write command carries the write logical address, i.e., the logical block address carried by the write command, and the write data carried by the write command. Next, as shown in step S1112, in response to the write command, the processor 211 writes the write data to the available physical location allocated by the non-volatile memory module 220 via the non-volatile memory interface control circuit 213. Further, as shown in step S1113, after the write data is written, the processor 211 obtains the physical address corresponding to the available physical location as the write physical address. Figure 11 The dashed line representing the response from the non-volatile memory module 220 to the processor 211 illustrates the write physical address confirmation process after the write operation is completed. Further, as shown in step S1114, the processor 211 updates the write physical address corresponding to the write logical address in the cache mapping table 310 carried by the buffer memory 214. Specifically, it updates the physical address recorded in the mapping entry corresponding to the write logical address to the write physical address, and sets a first dirty flag on the mapping table page to which the mapping entry belongs, indicating that the mapping table page has been updated in the cache mapping table 310 but has not yet been written back to the complete mapping table 300. Finally, as shown in step S1115, the processor 211 returns a write completion response to the host system 10 via the connection interface circuit 230 and the data transmission interface circuit 130 to complete the foreground processing of this write command. Regarding the cache mapping table 310's hit detection of the written logical address, and the branching process where the complete mapping table 300 in the integrated volatile memory 240 loads the mapping table page to which the written logical address belongs to the cache mapping table 310 if the cache mapping table 310 misses the written logical address, please refer to [reference needed]. Figure 4B The write flowchart shown details the hit / miss branch judgment steps; Figure 11 The timing diagram shown is mainly used to illustrate the timing relationship between writing data, updating the cache mapping table, writing completion response, and the first-stage flush.

[0140] Next, in the first stage of stage 2, as shown in step S1121, the processor 211 determines whether the trigger condition for the first stage of stage 2 is met. Figure 11 The loopback message on the processor 211 lifeline indicates that the judgment action is mainly performed by the processor 211. In this embodiment, the first-stage flush trigger condition includes at least one of the following: the number of mapping table pages with the first dirty mark in the cache mapping table 310 reaches a preset number threshold, or the time elapsed since the last first-stage flush reaches a preset time interval threshold. If the first-stage flush trigger condition is met, the processor 211 continues to perform the first-stage flush in steps S1122 to S1126; if the first-stage flush trigger condition is not met, the processor 211 may not perform this first-stage flush and will keep the mapping table pages with the first dirty mark in the cache mapping table 310 waiting for subsequent triggers.

[0141] Further, as shown in step S1122, processor 211 reads the mapping table page with the first dirty mark from cache mapping table 310 from buffer memory 214; then, as shown in step S1123, buffer memory 214 returns the mapping table page with the first dirty mark to processor 211 with a return response dashed line. Further still, as shown in step S1124, processor 211 writes the mapping table page with the first dirty mark to the corresponding position of the mapping table page in complete mapping table 300 in integrated volatile memory 240 via integrated volatile memory interface 215. Moreover, as shown in step S1125, after the write-back is completed, processor 211 clears the first dirty mark of the mapping table page in cache mapping table 310 from buffer memory 214. Finally, as shown in step S1126, the processor 211 sets a second dirty flag for the corresponding mapping table page in the complete mapping table 300 in the integrated volatile memory 240, to indicate that the mapping table page has been updated in the complete mapping table 300 but has not yet been persisted to the non-volatile memory module 220.

[0142] Based on the above Figure 11The storage device 20, as shown, responds to a write command initiated by the host system 10 by executing a write response and a first-stage flushing interaction sequence. The processor 211 of the memory controller 210 can first, via the first-stage write response, write the write data carried by the write command to the non-volatile memory module 220 to obtain the write physical address, update the write physical address corresponding to the write logical address in the cache mapping table 310, and set a first dirty flag for the corresponding mapping table page. Then, it returns a write completion response to the host system 10. Afterwards, in the second-stage flushing, when the first-stage flushing trigger condition is met, the processor 211 can write the mapping table page with the first dirty flag in the cache mapping table 310 back to the corresponding location in the complete mapping table 300 in the integrated volatile memory 240, clear the first dirty flag in the cache mapping table 310, and set a second dirty flag for the corresponding mapping table page in the complete mapping table 300. Therefore, the foreground response of the write command can return after the written data is completed and the cached mapping table 310 is updated, while the write-back action of the complete mapping table 300 can be triggered by the first-stage flush trigger condition, thus separating the foreground response path of the write command from the write-back path of the complete mapping table 300 and reducing the chance that each write command will immediately trigger the write-back of the complete mapping table 300.

[0143] Figure 12 The timing diagram shows the interaction of the storage device 20 according to an embodiment of this disclosure performing a second-stage brush in response to an instruction to enter a low-power state. Please refer to... Figure 12 In this embodiment, the second-stage flushing interaction timing involves three participating units: the processor 211 of the memory controller 210, the integrated volatile memory 240, and the non-volatile memory module 220. The integrated volatile memory 240 carries the complete mapping table 300, and the non-volatile memory module 220 carries the mapping table backup area 222. The second-stage flushing interaction timing includes two timing stages: Stage 1 triggering and determining, and Stage 2 writing back and clearing the second dirty memory.

[0144] First, in the stage 1 triggering and determination, as shown in step S1211, the processor 211 receives the second stage brush trigger. Figure 12 The loopback message on the processor 211 lifeline indicates that the trigger reception action is mainly performed by the processor 211. In this embodiment, the second-stage flush trigger may include an indication to enter a low-power state from the host system 10, a request to enter a low-power state initiated by the upper-layer power management logic inside the storage device 20, or a trigger scenario related to the persistence of the mapping table. For the classification of indications to enter a low-power state and the specific actions of their corresponding branch processing, please refer to... Figure 6The process branches through the first type of low-power indication, the second type of low-power indication, and the third type of low-power indication. Next, as shown in step S1212, the processor 211 determines the mapping table pages with the second dirty mark within the complete mapping table 300 of the integrated volatile memory 240. Specifically, the processor 211 can filter out the mapping table pages currently with the second dirty mark from the multiple mapping table pages included in the complete mapping table 300, as the objects that need to be persisted in the write-back and second dirty clearing phase 2.

[0145] Next, in stage 2, writing back and clearing the second dirty page, as shown in step S1221, processor 211 sends a read request to integrated volatile memory 240 via integrated volatile memory interface 215 to read the mapping table page with the second dirty mark determined in step S1212. Further, as shown in step S1222, integrated volatile memory 240 responds to the read request by returning a dotted response line indicating that the mapping table page with the second dirty mark is returned to processor 211 via integrated volatile memory interface 215. Further still, as shown in step S1223, processor 211 writes the mapping table page with the second dirty mark to the mapping table backup area 222 in non-volatile memory module 220 via non-volatile memory interface control circuit 213. Specifically, in the second-stage flushing scenario corresponding to the first type of low-power indication, mapping table pages with the second dirty mark can be written to the persistent copy 323 in the mapping table backup area 222 to save the update result of the mapping table pages with the second dirty mark; in the second-stage flushing scenario corresponding to the third type of low-power indication, all mapping table pages with the second dirty mark can be written to the complete copy 324 in the mapping table backup area 222 to update the complete copy 324, and after the write is completed, the processor 211 controls the integrated volatile memory 240 to enter the power-off state. Finally, as shown in step S1224, after the write is completed, the processor 211 clears the second dirty mark of the corresponding mapping table page in the complete mapping table 300 in the integrated volatile memory 240 via the integrated volatile memory interface 215 to indicate that the mapping relationship corresponding to the mapping table page has been persisted to the mapping table backup area 222 of the non-volatile memory module 220.

[0146] In this embodiment, the core of the second-stage flushing interaction timing is as follows: Stage 1 triggers and determines the mapping page to be persisted in this second-stage flushing by filtering the second dirty mark status of multiple mapping page pages in the complete mapping table 300; Stage 2 writes back and clears the second dirty mark by writing the mapping page with the second dirty mark from the integrated volatile memory 240 to the mapping table backup area 222 of the non-volatile memory module 220 via the processor 211, so that the mapping relationship corresponding to the mapping page with the second dirty mark is persisted before the integrated volatile memory 240 enters the self-refresh related low-power state or power-off state. After persistence is completed, the second dirty mark of the corresponding mapping page in the complete mapping table 300 can be cleared, so that the number of mapping page pages with the second dirty mark accumulated in the complete mapping table 300 is reduced to zero or reduced after this second-stage flushing, so that the new round of second dirty mark mapping page pages generated by subsequent write commands can trigger the second-stage flushing again.

[0147] Based on the above Figure 12 The storage device 20, in response to an instruction to enter a low-power state, executes a second-stage flushing interaction sequence. The processor 211 of the memory controller 210 first triggers and confirms the receipt of the second-stage flushing trigger via stage 1, and identifies the mapping table pages with a second dirty mark in the complete mapping table 300 of the integrated volatile memory 240. Then, in stage 2 (write-back and clear second dirty), the mapping table pages with the second dirty mark are read from the integrated volatile memory 240 and written to the mapping table backup area 222 of the non-volatile memory module 220 via the processor 211, and the second dirty mark is cleared from the corresponding mapping table pages in the complete mapping table 300. Thus, the mapping relationships corresponding to the mapping table pages with the second dirty mark accumulated in the complete mapping table 300 of the integrated volatile memory 240 can be persisted to the mapping table backup area 222 of the non-volatile memory module 220 before the storage device 20 enters the corresponding low-power state, providing a basis for recovery of the complete mapping table 300 in low-power state switching or abnormal recovery scenarios.

[0148] In another embodiment, this disclosure also provides a computer-readable storage medium on which a computer program is stored. When the computer program is loaded and executed by a processor in the memory controller of a storage device, the processor performs the memory management method of this disclosure. Specifically, the processor performs the following steps: maintaining a complete mapping table including multiple mapping table pages in integrated volatile memory, and maintaining a cache mapping table in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping table pages; in response to an access command, determining whether the cache mapping table hits the access logical address of the access command; if the cache mapping table does not hit the access logical address, loading the mapping table page to which the access logical address belongs from the complete mapping table in integrated volatile memory into the cache mapping table; and performing the access operation corresponding to the access command based on the mapping table page to which the access logical address belongs in the cache mapping table. In some embodiments, the computer-readable storage medium may be a non-transitory computer-readable storage medium, such as a read-only memory, random access memory, flash memory, disk, optical disk, or other storage medium capable of storing a computer program. Thus, the memory management method of this disclosure can be implemented by a computer program stored in a computer-readable storage medium.

[0149] It should be noted that the numerical values, thresholds, parameter ranges, algorithm standards, interface standards, generational standards, and structural forms mentioned in the above embodiments are all examples, and this disclosure is not limited thereto. Specifically, the capacity of the cache mapping table, the capacity of the complete mapping table, the preset quantity threshold in the first-stage flush trigger condition, the preset time interval threshold in the first-stage flush trigger condition, the preset frequency threshold used for the key mapping table page, the preset time window used for the key mapping table page, the bit width of the high-order address segment, the algorithm standard used for the cyclic redundancy check code, the algorithm used for the hash function, the time consumed for the integrated volatile memory to exit the self-refresh mode, the number of the first batch of key mapping table pages read in the cold start recovery process, the generational standard conforming to the integrated volatile memory, the interface standard compatible with the connection interface circuit, the specific form of the signal routing in the package substrate, and the specific packaging form of the package can all be adjusted according to the application scenario requirements of the host system, the actual design requirements of the memory controller, the physical characteristics of the integrated volatile memory and non-volatile memory modules, and the operating conditions of the storage device. For example, the capacity of the cache mapping table can be 64KB to 256KB, the capacity of the complete mapping table can be approximately 1GB, corresponding to a storage device with a capacity of approximately 1TB, the bit width of the high-order address segment can be from the high 8 bits to the high 16 bits, the cyclic redundancy check code can adopt the CRC-32 standard or other cyclic redundancy check algorithms, the hash function can adopt modulo operation, XOR folding or other hash algorithms, the integrated volatile memory can conform to LPDDR4X, LPDDR5 or newer generation standards, the connection interface circuit can be compatible with UFS standard, eMMC standard, PCI Express standard or NVMe standard, the signal traces in the package substrate can be microstrip lines or striplines, and the package can be a multi-chip package.

[0150] Based on the above, the storage device, memory controller, and memory management method provided in this disclosure integrate volatile memory within the storage device to carry a complete mapping table including multiple mapping table pages, and the memory controller maintains a cached mapping table for caching some mapping table pages. This reduces the memory controller's dependence on the capacity of the complete mapping table when dealing with large-capacity complete mapping tables. In response to an access command, if the cached mapping table misses the access logical address, the memory controller can load the corresponding mapping table page from the complete mapping table in the integrated volatile memory, without directly accessing non-volatile memory to query the corresponding mapping table page during the mapping lookup phase. This reduces the loading latency and access overhead of mapping table pages when a cache miss occurs. Furthermore, in response to a write command, the write data is written to non-volatile memory to obtain the write physical address, which is then used to update the cache mapping table and set the first dirty flag for the corresponding mapping table page. When the first-stage flush trigger condition is met, the mapping table page with the first dirty flag is written back to the corresponding position of the complete mapping table and a second dirty flag is set. This separates the foreground response path of the write command from the write-back path of the complete mapping table and makes the write-back frequency of the complete mapping table constrained by the first-stage flush trigger condition. Furthermore, by persisting key mapping table pages in the complete mapping table to non-volatile memory and putting the integrated volatile memory into a self-refresh mode in response to a first type of low-power indication, persisting at least a portion of the mapping table pages to non-volatile memory and putting the integrated volatile memory into a sleep state that retains the complete mapping table in response to a second type of low-power indication, and writing all mapping table pages with a second dirty mark in the complete mapping table to non-volatile memory to update the complete copy and then controlling the integrated volatile memory to enter a power-off state in response to a third type of low-power indication, the storage device can select different mapping table page persistence strategies according to different low-power state requirements. In addition, by performing a comparison of the cyclic redundancy check (CRC) code with the pre-stored reference code on each of the multiple mapping table pages included in the complete mapping table in response to a wake-up event, and backfilling with a valid copy in the mapping table backup area or reconstructing based on metadata in the non-volatile memory, a recovery basis for the complete mapping table can be provided in wake-up or abnormal recovery scenarios. Thus, this disclosure achieves a relative balance between large-capacity mapping table carrying, runtime mapping queries, write responses, low-power state switching, and abnormal recovery.

[0151] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A memory management method applicable to a storage device configured with a memory controller, integrated volatile memory, and non-volatile memory, characterized in that, The method includes: A complete mapping table comprising multiple mapping pages is maintained in the integrated volatile memory, and a cache mapping table is maintained in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping pages; In response to an access command, determine whether the cache mapping table matches the access logic address of the access command; and If the cache mapping table does not match the access logical address, the mapping table page to which the access logical address belongs is loaded from the complete mapping table in the integrated volatile memory into the cache mapping table, and the access operation corresponding to the access command is executed based on the mapping table page to which the access logical address belongs in the cache mapping table.

2. The memory management method according to claim 1, characterized in that, The access command includes a read command, and the access logical address includes the read logical address of the read command; The execution of the access operation corresponding to the access command based on the mapping table page to which the access logical address in the cache mapping table belongs includes: The physical address corresponding to the read logical address is obtained from the cache mapping table, and the target data is read from the non-volatile memory according to the physical address.

3. The memory management method according to claim 1, characterized in that, The access command includes a write command, and the access logical address includes the write logical address of the write command; The execution of the access operation corresponding to the access command based on the mapping table page to which the access logical address in the cache mapping table belongs includes: Write the data to the non-volatile memory to obtain the physical address to write; In the cache mapping table, update the physical address corresponding to the logical address being written within the mapping table page to which the logical address being written belongs, and set a first dirty flag for the mapping table page; and Return a write completion response to the host system; The first dirty flag indicates that the mapping table page has been updated in the cached mapping table but has not yet been written back to the complete mapping table.

4. The memory management method according to claim 3, characterized in that, The method further includes: In response to the first-stage flush trigger condition being met, the mapping table page with the first dirty mark in the cache mapping table is written back to the corresponding position of the complete mapping table in the integrated volatile memory, the first dirty mark of the mapping table page is cleared, and the second dirty mark is set for the corresponding mapping table page in the complete mapping table. The first stage flush triggering conditions include: the number of mapping table pages with the first dirty mark in the cache mapping table reaches a preset number threshold, or the time elapsed since the last first stage flush reaches a preset time interval threshold. The second dirty tag indicates that the mapping page has been updated in the complete mapping table but has not yet been persisted to the non-volatile memory.

5. The memory management method according to claim 4, characterized in that, The method further includes: In response to an indication to enter a low-power state, at least a portion of the mapping table pages of the complete mapping table in the integrated volatile memory are written to the non-volatile memory to retain a persistent copy of the at least a portion of the mapping table pages in the non-volatile memory before the integrated volatile memory enters a low-power state.

6. The memory management method according to claim 5, characterized in that, The indication for entering a low-power state includes a first type of low-power indication, which is used to indicate that the memory controller enters a first low-power mode and to indicate that the integrated volatile memory enters a self-refresh mode. The at least partial mapping page includes a key mapping page; the key mapping page includes at least one of the following: The complete mapping table contains mapping table pages with a second dirty tag; or Mapped table pages that are accessed more frequently than a preset frequency threshold within a preset time window.

7. The memory management method according to claim 5, characterized in that, The indication for entering a low-power state includes a second type of low-power indication, which is used to indicate that the memory controller enters a second low-power mode and to indicate that the integrated volatile memory enters a sleep state. The integrated volatile memory retains the complete mapping table during the sleep state so that when the integrated volatile memory is woken from the sleep state, the complete mapping table does not need to be reloaded from the non-volatile memory.

8. The memory management method according to claim 5, characterized in that, The indication for entering a low-power state includes a third type of low-power indication, which is used to indicate that the memory controller enters a third low-power mode and to indicate that the integrated volatile memory enters a power-off state. The non-volatile memory therein holds a complete copy of the complete mapping table in advance; The method further includes: in response to the third type of low power indication, writing all mapping table pages with the second dirty mark in the complete mapping table of the integrated volatile memory to the non-volatile memory for updating the complete copy, and then controlling the integrated volatile memory to enter a power-off state.

9. The memory management method according to claim 1, characterized in that, The cache mapping table is indexed according to the high-order address segment of the logical address; The step of determining whether the cache mapping table hits the access logical address includes: extracting the high-order address segment from the access logical address, and searching the cache mapping table for a mapping entry corresponding to the access logical address based on the high-order address segment.

10. The memory management method according to claim 9, characterized in that, The cache mapping table is organized as a hash table, and the hash table includes multiple hash buckets; The step of searching the cache mapping table for a mapping entry corresponding to the access logical address based on the high-order address segment includes: performing a hash operation on the high-order address segment to obtain a target hash bucket among the plurality of hash buckets, and searching the target hash bucket for a mapping entry corresponding to the access logical address.

11. The memory management method according to claim 9, characterized in that, The index structure of the cache mapping table is implemented by content-addressable memory; The step of searching the cache mapping table for a mapping entry corresponding to the access logical address based on the high-order address segment includes: sending the high-order address segment into the content addressable memory, and comparing multiple index entries stored in the content addressable memory in parallel to output a hit position or miss signal corresponding to the access logical address.

12. The memory management method according to claim 1, characterized in that, The method further includes: Based on at least one of the current command load and timing conditions, the storage device is switched between multiple power levels, wherein the multiple power levels include at least a first power level and a second power level, and the power consumption of the second power level is lower than that of the first power level. At the first power consumption level, both the memory controller and the integrated volatile memory are kept active; and At the second power level, the memory controller is put into a first low-power mode, and the integrated volatile memory is put into a self-refresh mode.

13. The memory management method according to claim 12, characterized in that, The method further includes: In response to a wake-up event from the self-refresh mode, power supply and clock of the memory controller are restored, and an instruction to exit the self-refresh mode is sent to the integrated volatile memory so that the integrated volatile memory begins to exit the self-refresh mode; During the period when the integrated volatile memory exits the self-refresh mode, if the command received by the memory controller does not involve the mapping conversion from logical address to physical address, or if the logical address carried by the command hits the cache mapping table, then the processing corresponding to the command is executed based on the cache mapping table or the status information in the memory controller, without waiting for the integrated volatile memory to complete the exit from the self-refresh mode before executing the processing corresponding to the command.

14. The memory management method according to claim 4, characterized in that, The non-volatile memory includes a mapping table backup area, which is used to store a complete copy of the complete mapping table and a persistent copy of the mapping table pages in the complete mapping table that have a second dirty mark. The method further includes: In response to a wake-up event, an integrity check is performed page by page on the multiple mapping table pages of the complete mapping table in the integrated volatile memory, wherein the integrity check includes: calculating a cyclic redundancy check code for each mapping table page, and comparing the cyclic redundancy check code with a pre-stored reference code corresponding to the mapping table page; If the comparison results of the target mapping page among the plurality of mapping page pages are inconsistent, and a valid copy of the target mapping page exists in the mapping table backup area, then the valid copy is read from the mapping table backup area to replace the target mapping page in the integrated volatile memory; and If the comparison results of the target mapping page are inconsistent, and there is no valid copy of the target mapping page in the mapping table backup area, the target mapping page is marked as to be rebuilt. When a command corresponding to the logical address range covered by the target mapping page is received subsequently, the mapping relationship corresponding to the target mapping page is rebuilt based on the metadata in the non-volatile memory.

15. A storage device, characterized in that, include: Non-volatile memory; Integrated volatile memory; as well as A memory controller, electrically connected to the non-volatile memory and the integrated volatile memory, wherein the memory controller includes: A non-volatile memory interface control circuit is used for electrical connection to the non-volatile memory; An integrated volatile memory interface for electrical connection to the integrated volatile memory; and The processor is electrically connected to both the non-volatile memory interface control circuit and the integrated volatile memory interface, wherein the processor is configured to: A complete mapping table comprising multiple mapping pages is maintained in the integrated volatile memory, and a cache mapping table is maintained in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping pages; In response to an access command, determine whether the cache mapping table matches the access logic address of the access command; and If the cache mapping table does not match the access logical address, the mapping table page to which the access logical address belongs is loaded from the complete mapping table in the integrated volatile memory into the cache mapping table, and the access operation corresponding to the access command is executed based on the mapping table page to which the access logical address belongs in the cache mapping table.

16. The storage device according to claim 15, characterized in that, The memory controller and the integrated volatile memory are integrated into the same package.

17. The storage device according to claim 16, characterized in that, The same package includes a package substrate; the memory controller and the integrated volatile memory are electrically connected via signal traces located within the package substrate, and the signal traces are not routed through an interposer or through a printed circuit board outside the package.

18. The storage device according to claim 17, characterized in that, The signal traces are microstrip lines or striplines.

19. A memory controller suitable for a storage device configured with non-volatile memory and integrated volatile memory, characterized in that, The memory controller includes: A non-volatile memory interface control circuit is used for electrical connection to the non-volatile memory; An integrated volatile memory interface for electrical connection to the integrated volatile memory; and The processor is electrically connected to both the non-volatile memory interface control circuit and the integrated volatile memory interface, wherein the processor is configured to: A complete mapping table comprising multiple mapping pages is maintained in the integrated volatile memory, and a cache mapping table is maintained in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping pages; In response to an access command, determine whether the cache mapping table matches the access logic address of the access command; and If the cache mapping table does not match the access logical address, the mapping table page to which the access logical address belongs is loaded from the complete mapping table in the integrated volatile memory into the cache mapping table, and the access operation corresponding to the access command is executed based on the mapping table page to which the access logical address belongs in the cache mapping table.

20. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program is applicable to a storage device equipped with a memory controller, integrated volatile memory, and non-volatile memory. When the computer program is executed by a processor in the memory controller of the storage device, it causes the processor to execute: A complete mapping table comprising multiple mapping pages is maintained in the integrated volatile memory, and a cache mapping table is maintained in the memory controller, the cache mapping table being used to cache a portion of the multiple mapping pages; In response to an access command, determine whether the cache mapping table matches the access logic address of the access command; as well as If the cache mapping table does not match the access logical address, the mapping table page to which the access logical address belongs is loaded from the complete mapping table in the integrated volatile memory into the cache mapping table, and the access operation corresponding to the access command is executed based on the mapping table page to which the access logical address belongs in the cache mapping table.

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