A data type conversion method and apparatus

Abstract

The present application relates to the field of data processing, and in particular to a data type conversion method and device. The present application can complete bit field splitting and unified preprocessing of data based on the definition of different formats by obtaining input data, input data format and output data format, providing a basis for multi-type conversion. Through unified processing of sign bits, exponent values and mantissa values, a general expression form of floating point, integer and fixed point data is constructed, breaking through the limitation of only adapting to specific formats under a single conversion path. Based on the input-output format conversion relationship, the shift strategy is dynamically determined, different exponent and mantissa processing logic can be adapted to different conversion scenarios, and there is no need to design a special circuit for each conversion path. Finally, data combination is completed according to the output format, realizing flexible conversion between different data types and precision, effectively solving the problem of fixed and single conversion path in the prior art, and improving the universality and integration of the data conversion module.

Description

Technical Field

[0001] This invention relates to the field of data processing, and more specifically to a data type conversion method and apparatus. Background Technology

[0002] In digital signal processing, general computing, and embedded system applications, data type conversion is a key link connecting different arithmetic units, storage modules, and peripheral interfaces. It involves bidirectional or multidirectional conversion requirements between various data formats such as floating-point numbers, integers, and fixed-point numbers. However, existing data type conversion circuits only support a single conversion path from one type to another (or different precisions of the same type) in the mutual conversion between floating-point numbers, integers, and fixed-point numbers, lacking a unified adaptation architecture for multi-type and multi-precision conversion scenarios. Summary of the Invention

[0003] In view of this, embodiments of the present invention provide a data type conversion method and apparatus to solve the problem of lacking a unified architecture that supports conversion of multiple types and precisions of floating-point numbers, integers and fixed-point numbers, and the problem of fixed and single conversion paths.

[0004] In a first aspect, embodiments of the present invention provide a data type conversion method, the method comprising: Obtain the input data to be converted, the input data format, and the output data format; According to the input data format, the data of different data bits in the input data are processed to obtain intermediate data, the intermediate data including a first sign bit, a first exponent value and a first tail value; Based on the conversion relationship between the input data format and the output data format, a shift strategy is determined, and the first exponent value and the first tail value are processed according to the shift strategy to obtain the second exponent value and the second tail value. The first sign bit, the second exponent value, and the second tail value are combined according to the output data format to obtain the target output data.

[0005] Furthermore, the step of processing different data bits in the input data according to the input data format to obtain intermediate data includes: If the input data is in floating-point format, then identify whether the input data has a sign bit; If the sign bit exists, then the sign bit is used as the first sign bit; if the sign bit does not exist, then the preset sign bit is used as the first sign bit. Extract the exponent bit from the input data, pad the high bits of the exponent bit with zeros, and subtract the input bias value corresponding to the input data format from the extracted exponent value to obtain the first exponent value; Extract the mantissa from the input data and place the valid bits in the high-order bits to obtain the first mantissa value.

[0006] Furthermore, the step of processing different data bits in the input data according to the input data format to obtain intermediate data includes: If the input data format is integer, then identify whether the input data has a sign bit; If the sign bit exists, then the sign bit is used as the first sign bit; if the sign bit does not exist, then a preset sign bit is used as the first sign bit. Use the preset exponent as the first exponent value; All data bits of the input data are used as mantissa bits, and it is determined whether the mantissa bits are negative. If the mantissa bits are negative, they are converted into unsigned numbers to obtain the first mantissa value. Alternatively, if the mantissa bits are integers, they are used as the first mantissa value.

[0007] Furthermore, when the input data format is a normalized floating-point number format and the output data format is a normalized floating-point number format, the shift strategy is the first shift strategy; The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: Determine the output bias value based on the output data format, and set the number of leading zeros to zero; Calculate the corresponding intermediate index value based on the first index value, the number of leading zeros, and the output bias value; Determine whether the first exponent value is non-zero and whether the intermediate exponent value is greater than zero; When the first exponent value is non-zero and the intermediate exponent value is greater than zero, the intermediate exponent value is used as the second exponent value, and the first tail value is used as the second tail value.

[0008] Furthermore, when the input data format is a normalized floating-point number format and the output data format is an integer format, or when the input data format is a normalized floating-point number format and the output data format is a denormalized floating-point number format, the shift strategy is a second shift strategy. The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: Determine the output bias value based on the output data format, and set the number of leading zeros to zero; Calculate the corresponding intermediate index value based on the first index value, the number of leading zeros, and the output bias value; Determine whether the first exponent value is non-zero and whether the intermediate exponent value is less than or equal to zero; When the first exponent value is non-zero and the intermediate exponent value is less than or equal to zero, the second exponent value is set to zero, and the first tail value is padded with a hidden bit and then shifted to the right. The right shift amount is the absolute value of the intermediate exponent value, and the hidden position after the shift is zero, thus obtaining the second tail value.

[0009] Furthermore, when the input data format is an integer format and the output data format is a normalized floating-point format, or when the input data format is a denormalized floating-point format and the output data format is a normalized floating-point format, the shift strategy is a third shift strategy. The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: The output bias value is determined according to the output data format, and the number of leading zeros is obtained by counting the leading zeros of the first tail value. Calculate the corresponding intermediate index value based on the first index value, the number of leading zeros, and the output bias value; Determine whether the first exponent value is zero and whether the intermediate exponent value is greater than zero; When the first exponent value is zero and the intermediate exponent value is greater than zero, the intermediate exponent value is used as the second exponent value, and the first tail value is shifted left by the number of leading zeros to remove the leading zeros, and the highest bit is discarded to obtain the second tail value.

[0010] Furthermore, when the input data format is an integer format and the output data format is an integer format, or when the input data format is a denormalized floating-point format and the output data format is a denormalized floating-point format, the shift strategy is the fourth shift strategy. The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: Count the number of leading zeros by performing a leading zero count on the first tail value; set the first tail value to zero to obtain the second exponent value; The number of additional leading zeros is calculated based on the first exponent value and the output bias value corresponding to the output data format, wherein the number of additional leading zeros is the first exponent value plus the output bias value; When the number of extra leading zeros is greater than zero, the first tail value is shifted to the left according to the number of extra leading zeros, and the tail value obtained after the shift is used as the second tail value; or, when the number of extra leading zeros is less than zero, the first tail value is shifted to the right according to the absolute value of the number of extra leading zeros, and the tail value obtained after the shift is used as the second tail value.

[0011] Furthermore, after processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value, the method further includes: According to the output data format, a preset number of preset values ​​are padded into the high-order bits of the second tail value to obtain the extended tail value; Based on the length of the mantissa significant bits corresponding to the output data format, the extended mantissa value is shifted to the left so that the significant data bits are moved to the significant data bits, resulting in the left-shifted extended mantissa value. The significant data bits are the high-order part of the left-shifted extended mantissa value, and the length of the high-order part is the same as the length of the mantissa significant bits corresponding to the output data format. The rounding result is determined based on the extended tail value after left shift, wherein the rounding result includes a guard bit, a rounding bit, and a sticky bit; Based on the protection bit, rounding bit, and sticky bit in the rounding result, the second exponent value and the second tail value are adjusted to obtain the third tail value and the third exponent value.

[0012] Furthermore, after obtaining the third tail value and the third exponent value, the method further includes: Detect whether the input data exceeds the representation range of the output data format, and generate an overflow flag; Detect whether the input data is infinity or non-numerical, and generate an infinity flag and a non-numerical flag; When the overflow flag, the infinity flag, and the non-numerical flag are all invalid, the first sign bit, the third exponent value, and the third tail value are combined according to the output data format to obtain the target output data.

[0013] Secondly, embodiments of the present invention provide a data type conversion apparatus, the apparatus comprising: The acquisition module is used to acquire the input data to be converted, the input data format, and the output data format; The first processing module is used to process data of different data bits in the input data according to the input data format to obtain intermediate data, wherein the intermediate data includes a first sign bit, a first exponent value and a first tail value; The second processing module is used to determine a shift strategy based on the conversion relationship between the input data format and the output data format, and to process the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value. The combination module is used to combine the first sign bit, the second exponent value, and the second tail value according to the output data format to obtain the target output data.

[0014] Thirdly, embodiments of the present invention provide a computer device, including: a memory and a processor, the memory and the processor being communicatively connected to each other, the memory storing computer instructions, and the processor executing the computer instructions to perform the method described in the first aspect or any corresponding embodiment thereof.

[0015] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer instructions that cause a computer to perform the method described in the first aspect or any of its corresponding embodiments.

[0016] The method provided in this application has the following beneficial effects: This invention acquires input data, input data format, and output data format, enabling bit field splitting and unified preprocessing of data based on different format definitions, thus providing a foundation for multi-type conversion. Through unified processing of the sign bit, exponent value, and mantissa, it constructs a universal expression for floating-point, integer, and fixed-point data, overcoming the limitation of adapting only to specific formats under a single conversion path. Based on the dynamic determination of the shift strategy according to the input-output format conversion relationship, it can adapt different exponent and mantissa processing logics for different conversion scenarios, eliminating the need to design dedicated circuits for each conversion path. Finally, it completes data combination according to the output format, achieving flexible conversion between different data types and precisions, effectively solving the problem of fixed and single conversion paths in existing technologies, and improving the versatility and integration of the data conversion module. Attached Figure Description

[0017] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating a data type conversion method according to some embodiments of the present invention; Figure 2This is a flowchart illustrating another data type conversion method according to some embodiments of the present invention; Figure 3 This is a schematic diagram of the data format splitting and preprocessing process according to some embodiments of the present invention; Figure 4 This is a schematic diagram of the leading zero counting process according to some embodiments of the present invention. Figure 5 This is a schematic diagram of the exponent and mantissa shifting and adaptation process according to some embodiments of the present invention; Figure 6 This is a flowchart illustrating another data type conversion method according to some embodiments of the present invention; Figure 7 This is a schematic diagram of the rounding and exponent calibration process according to some embodiments of the present invention; Figure 8 This is a structural block diagram of a data type conversion device according to an embodiment of the present invention; Figure 9 This is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] According to embodiments of the present invention, a data type conversion method and apparatus are provided. It should be noted that the steps shown in the flowcharts in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowcharts, in some cases, the steps shown or described may be executed in a different order than that shown here.

[0021] This embodiment provides a data type conversion method. Figure 1 This is a flowchart of a data type conversion method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: Step S101: Obtain the input data to be converted, the input data format, and the output data format.

[0022] In this embodiment, the original binary input data to be formatted is read, and the original state of all bits of the original data is completely preserved without bit truncation, numerical correction, or bit field adjustment. The definition standard of the input data format is read and parsed simultaneously to distinguish between signed integer, unsigned integer, normalized floating-point number, and unnormalized floating-point number types, and to clarify the bit distribution position, bit width, and encoding rules of the sign bit, exponent bit, and mantissa bit under each type of format. At the same time, the specification parameters of the output data format are read to determine the bit width division, arrangement order, offset configuration, and normalization constraint requirements of the output sign field, exponent field, and mantissa field, and to completely retain the three types of basic information: the input data body, the input format definition parameters, and the output format definition parameters.

[0023] Step S102: Process the data of different data bits in the input data according to the input data format to obtain intermediate data. The intermediate data includes the first sign bit, the first exponent value, and the first tail value.

[0024] In this embodiment of the application, intermediate data is obtained by processing different data bits in the input data according to the input data format, including: Step A1: If the input data format is floating-point number format, then identify whether the input data has a sign bit.

[0025] First, based on the definition of the input data format, distinguish whether the data is in floating-point format or integer format. If it is in floating-point format, identify whether there is an independent sign bit field in the data bit stream according to the bit field division rules of the format. If it is in integer format, skip the sign bit identification step and handle the absolute value conversion of negative numbers by inverting and adding one, without needing to extract the sign bit separately.

[0026] Step A2: If a sign bit exists, the sign bit is used as the first sign bit; if no sign bit exists, the preset sign bit is used as the first sign bit.

[0027] If an independent sign bit is detected in the floating-point format, the level value of that bit position is directly extracted as the first sign bit, which directly reflects the positive or negative attribute of the original data. If it is an unsigned floating-point format or an integer format, there is no independent sign bit, so a preset low level value is used as the first sign bit to ensure that the sign output is always zero and does not affect subsequent operations. The sign bit of signed integer data has been processed in the absolute value conversion process of inversion and addition, so here we only need to output the sign bit result according to the definition of the input format.

[0028] Step A3: Extract the exponent from the input data and pad the high bits of the exponent with zeros. Subtract the input bias value corresponding to the input data format from the extracted exponent value to obtain the first exponent value.

[0029] Based on the exponent definition of the input data format, the bit segment corresponding to the exponent is extracted from the original data. To adapt to the subsequent operation bit width, zeros are padded to the high bits of the exponent to achieve the preset processing bit width. Then, the input bias value corresponding to the current input data format is retrieved, and the extracted and zero-padded exponent value is subtracted from the bias value to obtain the first exponent value after removing the bias. If the input data is in integer format, the first exponent value is directly set to zero. For signed integer data, since it has been converted to unsigned form by inversion and addition, the bias value standard of unsigned integers with the same bit width is used in the operation to ensure the consistency of exponent processing.

[0030] Step A4: Extract the mantissa from the input data and place the valid bits in the high-order bits to obtain the first mantissa value.

[0031] Based on the definition of the mantissa in the input data format, the bit segment corresponding to the mantissa is extracted from the original data; through logical shift operations, the valid bits in the mantissa are uniformly moved to the high-order position to obtain the normalized first mantissa value.

[0032] Step S103: Determine the shift strategy based on the conversion relationship between the input data format and the output data format, and process the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value.

[0033] In this embodiment of the application, when the input data format is normalized floating-point format and the output data format is normalized floating-point format, the shift strategy is the first shift strategy; In this embodiment of the application, the first exponent value and the first tail value are processed according to a shift strategy to obtain the second exponent value and the second tail value, including: Step B1: Determine the output bias value based on the output data format and set the number of leading zeros to zero.

[0034] Specifically, in conversion scenarios where both the input and output data formats are normalized floating-point numbers, the input data is a normalized floating-point number, whose mantissa implicitly contains a "1" (hidden bit). Since the mantissa's significant bits are already aligned to the most significant bit, there is no need to count leading zeros; therefore, the number of leading zeros is directly set to zero. The output bias value is determined based on the output data format's standard definition, extracting the corresponding bias constant from the preset format parameters.

[0035] Step B2: Calculate the corresponding intermediate exponent value based on the first exponent value, the number of leading zeros, and the output bias value.

[0036] Based on the standard definition of the output data format, the corresponding output bias value is extracted. The intermediate exponent value is calculated using a predetermined calculation formula. The calculation formula is: the intermediate exponent value equals the first exponent value minus the number of leading zeros plus the output bias value. The input bias value corresponding to integer data uses a fixed negative number for calculation. During the calculation process, the priority of numerical operations is strictly followed, and subtraction and addition operations are performed sequentially. The bias differences between the input and output formats and the numerical offset caused by leading zeros are all integrated into the calculation process to ensure that the obtained intermediate exponent value can adapt to the exponent encoding rules of the output data format, providing accurate calculation results for subsequent exponent judgment and assignment.

[0037] Step B3: Determine whether the first exponent value is non-zero and whether the intermediate exponent value is greater than zero.

[0038] A dual-condition parallel judgment logic is constructed. First, the numerical state of the first exponent value is checked to confirm whether it is a non-zero value. Simultaneously, the intermediate exponent value is checked to see if it is greater than zero. Both judgment conditions must be met at the same time. This logic is specifically adapted to application scenarios of floating-point to floating-point conversion and normalized number to normalized number conversion. Through double verification, valid data that meets the standard conversion conditions is filtered out, and abnormal data cases such as exponent of zero or intermediate exponent value of non-positive are excluded. This avoids exponent overflow, underflow or non-normalized data from interfering with the subsequent normal output process and ensures the accuracy of exponent and mantissa processing.

[0039] Step B4: When the first exponent value is non-zero and the intermediate exponent value is greater than zero, the intermediate exponent value is used as the second exponent value, and the first tail value is used as the second tail value.

[0040] When both conditions are met—the first exponent value is non-zero and the intermediate exponent value is greater than zero—the calculated intermediate exponent value is directly assigned as the second exponent value, which is used as the exponent part of the final output. At the same time, the mantissa data is kept unchanged without any shifting, truncation, or zero padding. The original first mantissa value is directly assigned as the second mantissa value, completing the final adaptation process between the exponent and the mantissa. This process strictly follows the rules of floating-point normalized number conversion, without the need to shift or adjust the mantissa, thus preserving the valid data of the original mantissa to the maximum extent.

[0041] Step S104: Combine the first sign bit, the second exponent value, and the second tail value according to the output data format to obtain the target output data.

[0042] In this embodiment, according to the preset bit field arrangement rules of the output data format, the first sign bit, the second exponent value, and the second mantissa value are concatenated bit by bit and combined with bit width adaptation to generate the final output data that conforms to the target format standard; the fixed bit positions, bit widths, and arrangement order specifications of the sign bit, exponent bit, and mantissa bit in the output data format are read to determine the arrangement logic of the sign bit occupying the highest fixed bit field, the exponent bit following the sign bit, and the mantissa bit occupying the remaining lower bit fields; the first sign bit is preferentially configured to the highest bit position of the output data, keeping the sign bit level state unchanged, and accurately representing the original The data is classified as positive or negative. The second exponent value, obtained through a shifting strategy, is adjusted according to the bit width requirement of the output exponent by padding high bits with zeros or truncating low bits, and then filled into the exponent-specific bit range of the output data. The second mantissa value is processed according to the bit width definition of the mantissa bits, retaining valid bits and discarding redundant bits, and then filled into the mantissa-specific bit range after aligning the low bits. After the three types of bit ranges are concatenated in sequence, the overall data is checked for bit width and format compliance to ensure that the combined bit arrangement, bit range division, and numerical specifications fully match the output data format requirements, and finally, standardized target output data is generated and output.

[0043] In another embodiment of this application, a data type conversion method is provided, the process of which includes the following steps: Step S201: Obtain the input data to be converted, the input data format, and the output data format.

[0044] In this embodiment, the original binary input data to be formatted is read, and the original state of all bits of the original data is completely preserved without bit truncation, numerical correction, or bit field adjustment. The definition standard of the input data format is read and parsed simultaneously to distinguish between signed integer, unsigned integer, normalized floating-point number, and unnormalized floating-point number types, and to clarify the bit distribution position, bit width, and encoding rules of the sign bit, exponent bit, and mantissa bit under each type of format. At the same time, the specification parameters of the output data format are read to determine the bit width division, arrangement order, offset configuration, and normalization constraint requirements of the output sign field, exponent field, and mantissa field, and to completely retain the three types of basic information: the input data body, the input format definition parameters, and the output format definition parameters.

[0045] Step S202: Process the data of different data bits in the input data according to the input data format to obtain intermediate data. The intermediate data includes the first sign bit, the first exponent value, the first tail value, and the number of leading zeros.

[0046] In this embodiment of the application, data from different data bits in the input data are processed according to the input data format to obtain intermediate data, such as... Figure 2 As shown, it includes: Step C1: If the input data format is integer, then identify whether the input data has a sign bit.

[0047] Based on the encoding standard of the input data format, the data is determined to belong to the integer format category. According to the bit definition rules of integer data, it is identified whether there is an independent sign bit position in the bit stream of the input data, distinguishing between signed integer and unsigned integer subtypes, and clarifying the fixed bit position where the sign bit is located. This provides a precise bit position basis for subsequent sign bit extraction and numerical conversion, ensuring that the sign attribute recognition is completely matched with the integer data format definition.

[0048] In step C2, if a sign bit exists, the sign bit is used as the first sign bit; if no sign bit exists, the default sign bit is used as the first sign bit.

[0049] Based on the identification result of whether the input data has a sign, the sign bit assignment operation is performed. If the input is determined to be a signed integer, the sign bit level value at the corresponding fixed bit position is directly extracted as the first sign bit, and the positive and negative attributes of the original data are completely preserved. If the input is determined to be an unsigned integer and there is no dedicated sign bit field, the preset zero level value is directly used as the first sign bit, and the sign output is stably set to zero.

[0050] Step C3: Use the preset exponent as the first exponent value.

[0051] Following the exponent processing rules for integer data, the preset all-zero bits are used as the first exponent value, and the first exponent value is directly set to zero. There is no need to extract the exponent, pad with zeros at high bits, or perform bias value calculations. Regardless of whether it is a signed or unsigned integer, the exponent value is uniformly fixed to zero. At the same time, after the signed integer is converted to an unsigned integer by inverting and adding one, the same bias value as the unsigned integer of the same bit width is used.

[0052] Step C4: Take all the data bits of the input data as the mantissa bits, and determine whether the mantissa bits are negative. If the mantissa bits are negative, convert the mantissa bits to an unsigned number to obtain the first mantissa value. Alternatively, if the mantissa bits are integers, use the mantissa bits as the first mantissa value.

[0053] All bits of the input integer data are included in the mantissa. All data bits, including the sign bit, are treated as mantissa. After the complete extraction of the mantissa, the positive or negative attribute of the value is determined. If it is determined to be negative, all mantissa bits, including the sign bit, are inverted and incremented by one to convert it into an unsigned number and obtain the first mantissa value, thus realizing the conversion of negative numbers by taking the absolute value. If it is determined to be positive, the completely extracted mantissa bits are directly used as the first mantissa value to ensure that the valid mantissa data is completely preserved.

[0054] Step S203: Determine the shift strategy based on the conversion relationship between the input data format and the output data format, and process the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value.

[0055] In this embodiment of the application, when the input data format is normalized floating-point format and the output data format is integer format, or when the input data format is normalized floating-point format and the output data format is denormalized floating-point format, the shift strategy is the second shift strategy. The first exponent value and the first tail value are processed according to the shift strategy to obtain the second exponent value and the second tail value, including: Step D1: Determine the output bias value based on the output data format and set the number of leading zeros to zero.

[0056] In conversion scenarios where the input is a normalized floating-point number and the output is an integer or denormalized floating-point number, since the input is a normalized floating-point number, its mantissa implicitly contains a "1" in the highest bit, the data is already aligned and has no leading zeros, so the number of leading zeros is directly set to zero. The output bias value is determined according to the output format. For example, when the output is an integer, the bias can be considered as a negative number (an integer can also be considered as a subnorm floating-point number with exp=0 and bias being negative). When the output is a denormalized floating-point number, the bias is extracted according to the format specification. After setting the leading zeros to zero, the offset term in the intermediate exponent value depends only on the input exponent, the input bias, and the output bias, accurately reflecting the state after exponent adaptation. This is used to subsequently determine whether it is necessary to right-shift the mantissa and set the exponent to zero to generate a denormalized or integer output.

[0057] Step D2: Calculate the corresponding intermediate exponent value based on the first exponent value, the number of leading zeros, and the output bias value.

[0058] The corresponding output bias value is determined according to the encoding specification of the output data format. The intermediate exponent value is calculated using a fixed formula. The formula is that the intermediate exponent value is equal to the first exponent value minus the number of leading zeros, and then added to the output bias value. The input bias value corresponding to integer data is a fixed negative number. The numerical operation rules are strictly followed during the calculation process. The original value of the input exponent, the offset caused by the leading zeros, and the bias standard of the output format are fully integrated into the calculation process to ensure that the obtained intermediate exponent value can accurately reflect the actual state after the exponent is adapted to the output format, providing accurate numerical basis for subsequent condition judgment and shift processing.

[0059] Step D2: Determine whether the first exponent value is non-zero and whether the intermediate exponent value is less than or equal to zero.

[0060] A dual-condition synchronous judgment logic is constructed. First, it checks whether the first exponent value is non-zero to confirm that the input data is in normalized form. At the same time, it checks whether the calculated intermediate exponent value is less than or equal to zero. Both conditions must be met simultaneously. This judgment logic is specifically adapted to conversion scenarios such as floating-point to integer conversion, high-precision floating-point to low-precision floating-point conversion, and conversions that exceed the normalized range and can only be represented by denormalized form. By filtering and locking the target data that needs to be denormalized through dual conditions, it distinguishes between normal normalization conversion and denormalization conversion processes, ensuring accurate matching of data processing paths.

[0061] Step D3: When the first exponent value is non-zero and the intermediate exponent value is less than or equal to zero, set the second exponent value to zero, and after filling the first tail value with the hidden position, shift it to the right by the absolute value of the intermediate exponent value. The hidden position after the shift is zero, thus obtaining the second tail value.

[0062] When all conditions are met, including a non-zero first exponent value and an intermediate exponent value less than or equal to zero, the second exponent value is directly fixed to zero, completing the denormalization assignment of the exponent part. Then, a hidden bit filling operation is performed on the first mantissa value. After filling with a standard hidden bit 1, a right shift operation is performed according to the absolute value of the intermediate exponent value as a fixed right shift amount. After the shift is completed, the hidden bit of the mantissa is forcibly set to zero. The mantissa is adjusted to a denormalized form through the right shift operation to make up for the numerical deviation caused by the exponent value returning to zero. Finally, the second mantissa value that meets the requirements of the denormalized format is obtained, completing the mantissa processing adapted to integer output or low-precision denormalized floating-point output.

[0063] Step S204: Combine the first sign bit, the second exponent value, and the second tail value according to the output data format to obtain the target output data.

[0064] In this embodiment, according to the preset bit field arrangement rules of the output data format, the first sign bit, the second exponent value, and the second mantissa value are concatenated bit by bit and combined with bit width adaptation to generate the final output data that conforms to the target format standard; the fixed bit positions, bit widths, and arrangement order specifications of the sign bit, exponent bit, and mantissa bit in the output data format are read to determine the arrangement logic of the sign bit occupying the highest fixed bit field, the exponent bit following the sign bit, and the mantissa bit occupying the remaining lower bit fields; the first sign bit is preferentially configured to the highest bit position of the output data, keeping the sign bit level state unchanged, and accurately representing the original The data is classified as positive or negative. The second exponent value, obtained through a shifting strategy, is adjusted according to the bit width requirement of the output exponent by padding high bits with zeros or truncating low bits, and then filled into the exponent-specific bit range of the output data. The second mantissa value is processed according to the bit width definition of the mantissa bits, retaining valid bits and discarding redundant bits, and then filled into the mantissa-specific bit range after aligning the low bits. After the three types of bit ranges are concatenated in sequence, the overall data is checked for bit width and format compliance to ensure that the combined bit arrangement, bit range division, and numerical specifications fully match the output data format requirements, and finally, standardized target output data is generated and output.

[0065] In this embodiment of the application, when the input data format is integer and the output data format is normalized floating-point number format, or when the input data format is denormalized floating-point number format and the output data format is normalized floating-point number format, the shift strategy is the third shift strategy. The first exponent value and the first tail value are processed according to the shift strategy to obtain the second exponent value and the second tail value, including: Step E1: Determine the output bias value according to the output data format, and count the number of leading zeros for the first tail value.

[0066] In conversion scenarios where the input is in integer or denormalized floating-point format and the output is in normalized floating-point format, the mantissa of the input data (integer or denormalized floating-point) may contain multiple leading zeros. A leading zero counter is needed to count these leading zeros. The specific counting method is as follows: the first mantissa value is grouped into fixed-width groups (e.g., 64 bits divided into 8 groups, each 8 bits). Each group is bitwise ORed to check for a "1". A priority encoder locates the first group containing a "1" and outputs the group index. A multiplexer then selects the data in that group and encodes it again to obtain the position of the first "1" within the group. The group index is then concatenated with the index within the group to obtain the number of leading zeros. The output bias value is extracted based on the output floating-point format and used for subsequent intermediate exponent value calculations to normalize the output.

[0067] Step E2: Calculate the corresponding intermediate exponent value based on the first exponent value, the number of leading zeros, and the output bias value.

[0068] The matching output bias value is determined based on the encoding standard of the output data format. The intermediate exponent value is calculated using a specified formula. The formula is: the intermediate exponent value equals the first exponent value minus the input bias value, minus the number of leading zeros, and finally added to the output bias value. The input bias value corresponding to integer data is a fixed negative number used in the calculation. The calculation process is strictly performed in the order of arithmetic operations, taking into account the input exponent, format bias difference, and leading zero offset. This ensures that the generated intermediate exponent value can accurately adapt to the conversion requirements of integer to floating point and low-precision non-normalized floating point to high-precision normalized floating point, providing a precise numerical basis for subsequent condition judgment and mantissa shifting.

[0069] Step E3: Determine whether the first exponent value is zero and whether the intermediate exponent value is greater than zero.

[0070] A dual-condition synchronous verification logic is established. First, it determines whether the first exponent value is zero to confirm whether the input is a denormalized floating-point number or an integer. At the same time, it determines whether the calculated intermediate exponent value is greater than zero. Both conditions must be met simultaneously. This judgment logic is specifically adapted to scenarios of converting integers to floating-point numbers and converting low-precision denormalized floating-point numbers to high-precision normalized floating-point numbers. By locking data that meets the requirements of normalized output through dual conditions, it distinguishes the processing paths of denormalized input and normalized output, and avoids numerical anomalies caused by mismatch between data types and conversion logic.

[0071] Step E4: When the first exponent value is zero and the intermediate exponent value is greater than zero, the intermediate exponent value is used as the second exponent value, and the first tail value is shifted to the left to remove the leading zeros by using the number of leading zeros, and the highest bit is discarded to obtain the second tail value.

[0072] When all conditions are met—the first exponent being zero and the intermediate exponent being greater than zero—the intermediate exponent is directly assigned to the second exponent as the exponent part of the normalized output. Simultaneously, the number of leading zeros obtained from the leading zero counting module is used as the left shift control parameter to perform a left shift operation on the corresponding number of bits of the first mantissa, completely removing all leading zeros at the front of the mantissa, aligning the significant bits of the mantissa to the most significant bit position, and then discarding the hidden bits of the most significant bit of the mantissa according to the format requirements of normalized floating-point numbers, thus completing the normalization and regularization of the mantissa, and finally obtaining the second mantissa that conforms to the output format standard.

[0073] In this embodiment of the application, when the input data format is integer and the output data format is integer, or when the input data format is denormalized floating-point number and the output data format is denormalized floating-point number, the shift strategy is the fourth shift strategy. The first exponent value and the first tail value are processed according to the shift strategy to obtain the second exponent value and the second tail value, including: Step F1: Count the number of leading zeros for the first tail value; set the first tail value to zero to obtain the second exponent value.

[0074] In conversion scenarios where the input is an integer and the output is an integer, or the input is a denormalized floating-point number and the output is a denormalized floating-point number, a leading zero counting operation is first performed on the first mantissa. This is done using a grouped bitwise OR method cascaded with a priority encoder (e.g., 64 bits divided into 8 groups, with each 8 bits detected and encoded) to obtain the number of leading zeros in the mantissa, which serves as an auxiliary parameter for subsequent shift control. Simultaneously, the first mantissa is cleared (i.e., all bits are set to zero), serving as the initial reference for the second mantissa; and the first exponent is set to zero to obtain the second exponent. This is because the output exponent is zero during integer-to-integer or denormalized-to-denormalized conversion (integer is considered exp=0, denormalized floating-point exp=0). This clearing operation provides a unified starting point for mantissa processing for subsequent left or right shifts based on the additional number of leading zeros, ensuring that the shift logic matches the conversion scenario.

[0075] Step F2: Calculate the number of extra leading zeros based on the first exponent value and the output bias value corresponding to the output data format, wherein the number of extra leading zeros is the first exponent value plus the output bias value.

[0076] Using the first exponent value as the basic calculation parameter and combining it with the fixed output bias value corresponding to the output data format, an addition operation is performed to obtain the number of extra leading zeros. The calculation formula is that the number of extra leading zeros is equal to the first exponent value and the output bias value directly added together. This calculation method relies on the numerical derivation rules of denormalization to denormalization, and integrates the offset of the input exponent and the bias standard of the output format into a unified shift control parameter. It does not require the introduction of the number of leading zeros to participate in the calculation, and directly generates a precise shift value that can be used for left or right shift of the mantissa, providing a unique and accurate control basis for the mantissa shift operation.

[0077] Step F3: When the number of extra leading zeros is greater than zero, shift the first tail value to the left according to the number of extra leading zeros, and use the tail value obtained after the shift as the second tail value; or, when the number of extra leading zeros is less than zero, shift the first tail value to the right according to the absolute value of the number of extra leading zeros, and use the tail value obtained after the shift as the second tail value.

[0078] When the number of extra leading zeros is greater than zero, a left shift operation is performed on the first mantissa value, using this value as the fixed shift number. Zeros are padded to the lower bits during the shift, and all valid bits are retained (without removing the most significant bit). The final shift result is assigned to the second mantissa value. When the number of extra leading zeros is less than zero, the absolute value of this value is used as the shift number, and a right shift operation is performed on the first mantissa value, padded to the higher bits during the shift. The final shift result is assigned to the second mantissa value. Through these differentiated shift operations, the system accurately adapts to integer to integer and denormalized floating-point number to denormalized floating-point number conversion scenarios, ensuring consistency between mantissa processing and shift control logic.

[0079] In the embodiments of this application, such as Figure 3 As shown, after data input, the sign bit, exponent bit, and mantissa bit are extracted separately according to the input format through a multiplexer: the sign bit is directly output as the first sign bit (unsigned numbers are set to zero); the exponent bit is padded with zeros at the high bits and then the input bias value is subtracted, and the exponent of integer data is directly set to zero; the mantissa bit is processed by inverting the whole number and adding one to process the absolute value of the negative number, and then the significant position is placed at the high bits to obtain the first mantissa value. At the same time, the logic judgment of whether the exponent is zero and whether the mantissa is zero is used to identify the non-normalized input. If it is non-normalized or integer data, the mantissa value is sent to the leading zero counter. Taking 64-bit data as an example, it is detected bitwise or grouped in groups of 8 bits. The first group containing 1 is located by the priority encoder, and then the group data is selected by the multiplexer and secondary priority encoding is performed. The number of leading zeros is obtained by concatenating the group position and the position within the group. For normalized floating-point numbers, the number of leading zeros is directly set to zero. Finally, all processing of the sign bit, exponent value, mantissa value, and number of leading zeros is completed.

[0080] As an example, such as Figure 4 As shown, taking a denormalized 64-bit floating-point number as an example, the process first identifies the presence of an independent sign bit based on the input format and extracts the sign bit level as the first sign bit. Next, the exponent is extracted and padded with zeros at the high bits, and the input bias value is subtracted to obtain the first exponent value. Then, the mantissa is extracted, and the significant bits are shifted to the high bits to obtain the first mantissa value. Since the floating-point number is denormalized, leading zeros need to be counted for the mantissa. The 64-bit mantissa is divided into 8 groups of 8 bits each. Each group is bitwise ORed to determine if it contains a 1. The first group containing a 1 is obtained through a priority encoder, which identifies the 4th group, and the output group_sel is "011". This group is then selected via a MUX, and secondary priority encoding is performed to obtain the first 1 in the group, which is "011". The number of leading zeros is then concatenated to obtain "011011". Finally, all processing of the sign bit, exponent value, mantissa value, and number of leading zeros is completed, providing complete intermediate data for subsequent shift strategies and format combinations.

[0081] The following are specific examples of shift strategies, such as Figure 5 As shown, ① Floating-point to floating-point: Normalized number to normalized number (E10>0, src_exp≠0).

[0082] The input exponent value is summed with the output bias value by an adder, and then the number of leading zeros is subtracted to obtain E10. Since the input is a normalized number, the number of leading zeros is 0, and the calculated result of E10 is greater than 0. The E10 complement is directly output as the exponent output through a multiplexer. The mantissa input does not enter the shift unit and is directly output through the data path without the need for left or right shift processing, thus completely preserving the original mantissa bits.

[0083] ② Floating-point to integer / high-precision to low-precision floating-point (denormalized output, E10≤0, src_exp≠0).

[0084] The input exponent value is summed with the output bias value by an adder, and then the number of leading zeros is subtracted to obtain E10. Since the output format cannot represent a normalized number, E10≤0, and the exponent part is output as 0 through a multiplexer. The mantissa input enters the right shift unit, and a right shift operation is performed with |E10| as the shift amount. The hidden bit 1 is added and the hidden bit is finally set to 0, adjusting the mantissa to a denormalized form. The shift result is output as the mantissa output through a multiplexer, completing the exponent zeroing and mantissa denormalization adaptation.

[0085] ③ Integer to floating point / Low precision to high precision floating point (normalized output, src_exp=0, E10>0).

[0086] The input exponent is 0. It is summed with the output bias value by the adder, and then the number of leading zeros is subtracted to obtain E10. Since the input is a denormalized number, the number of leading zeros is not 0, and the calculated result of E10 is greater than 0. The two's complement of E10 is directly output as the exponent output through the multiplexer. The mantissa input enters the left shift unit. The left shift operation is performed with the number of leading zeros as the shift amount. Leading zeros are removed and the highest hidden bit is discarded. The mantissa is adjusted to normalized form. The shift result is output as the mantissa output through the multiplexer, completing the conversion from denormalized input to normalized output.

[0087] ④ Integer to integer / denormalized to denormalized floating point (E10≤0, src_exp=0).

[0088] The input exponent value is summed with the output bias value by an adder to obtain the number of extra leading zeros (input exponent value + output bias value); the mantissa input selects the shift path according to the sign of the number of extra leading zeros: if it is positive, it enters the left shift unit to perform a left shift of the corresponding number of bits; if it is negative, it takes the absolute value and enters the right shift unit to perform a right shift of the corresponding number of bits. The shift process does not remove the highest bit; the exponent part is directly output as 0, and the mantissa output is the shifted denormalized form.

[0089] In this embodiment of the application, after processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value, as follows: Figure 6 As shown, the method also includes: Step S301: According to the output data format, a preset number of preset values ​​are padded into the high-order bits of the second tail value to obtain the extended tail value.

[0090] Based on the mantissa bit width and precision requirements specified in the output data format, a preset number of 1s are continuously padded before the highest bit of the second mantissa value. The mantissa bit width is expanded by padding the high bits with 1s, so that the overall bit width of the mantissa meets the standard bit length requirements of subsequent shift and rounding operations. This results in an expanded mantissa value with a regular bit width and uniform high-bit filling. The padding operation strictly matches the mantissa processing specifications of the output format, ensuring that the expanded mantissa can adapt to the subsequent left shift, rounding and carry accumulation process, providing a standard input carrier for mantissa precision processing.

[0091] Step S302: According to the length of the mantissa valid bits corresponding to the output data format, the extended mantissa value is shifted to the left so that the valid data bits are moved to the valid data bits, and the extended mantissa value after left shift is obtained. The valid data bits are the high-order part of the extended mantissa value after left shift, and the length of the high-order part is the same as the length of the mantissa valid bits corresponding to the output data format.

[0092] Based on the mantissa significant bit length parameter defined in the output data format, a left shift operation of a defined number of bits is performed on the extended mantissa value. During the left shift, all significant data bits in the original mantissa are progressively moved towards the higher bits until all significant data bits fall within the higher significant bit region specified by the output format. The length of this higher significant bit region is exactly equal to the mantissa significant bit length corresponding to the output data format. After the left shift is complete, the remaining lower bits outside this significant data bit region are automatically used as a dedicated bit segment for rounding processing, for subsequent rounding judgments. This left shift operation strictly follows the mantissa significant bit arrangement requirements of the output format, ensuring that significant data is completely preserved within the specified higher significant bit range, while providing accurate overflow and carry information for the rounding stage.

[0093] Step S303: Determine the rounding result based on the extended mantissa value after left shift, wherein the rounding result includes a protection bit, a rounding bit, and a sticky bit.

[0094] Three types of rounding flags are extracted from the extended mantissa after left shift according to fixed rules. The least significant bit of the valid data part is defined as the guard bit, the most significant bit of the rounding bit segment is defined as the rounding bit, and the result of performing a bitwise OR operation on all remaining bits below the rounding bit is defined as the sticky bit. The three types of bits together form the complete rounding result. The extraction process strictly follows the standard bit division rules for mantissa rounding, accurately locking the key bit state used for mantissa carry judgment, and providing a reliable rounding basis for subsequent mantissa and exponent adjustments.

[0095] Step S304: Based on the protection bit, rounding bit, and sticky bit in the rounding result, adjust the second exponent value and the second tail value to obtain the third tail value and the third exponent value.

[0096] The mantissa and exponent are calibrated and adjusted based on the combination of the guard bit, round bit, and sticky bit. The left-shifted high 32 bits of data are sent to the adder and the rounding result are added. The carry signal is accumulated and transmitted step by step by relying on the structural characteristic of padding the high bits with 1. If a carry signal is generated in the highest bit during the operation, the carry is directly superimposed on the second mantissa value to complete the correction and obtain the calibrated third mantissa value. At the same time, the second exponent value is adjusted synchronously according to the carry result and output format requirements, and finally the third exponent value that meets the accuracy specification is generated, completing the whole process of mantissa rounding and exponent calibration.

[0097] In this embodiment of the application, after obtaining the third tail value and the third exponent value, the method further includes: detecting whether the input data exceeds the representation range of the output data format and generating an overflow flag; detecting whether the input data is infinity or non-numerical and generating an infinity flag and a non-numerical flag; when the overflow flag, the infinity flag, and the non-numerical flag are all invalid, combining the first sign bit, the third exponent value, and the third tail value according to the output data format to obtain the target output data.

[0098] Specifically, the implementation process for detecting whether the input data is infinity or non-numerical, and generating infinity and non-numerical flags, is as follows: Based on the bit field definition of the input data format, the exponent and mantissa bits of the input data are traversed. When all exponent bits are 1 and all mantissa bits are 0, it is determined to be infinite data, and the infinity flag is set. When all exponent bits are 1 and not all mantissa bits are 0, it is determined to be non-numerical data, and the non-numerical flag is set. For integer data, if its value exceeds the maximum representation range of the output format, it also needs to be indirectly mapped to an overflow flag through the combination of exponent and mantissa. This process is strictly executed according to the encoding rules of infinity and non-numerical in the IEEE 754 standard. A valid flag is only generated when the exponent and mantissa simultaneously meet the corresponding encoding conditions, ensuring accurate identification and marking of abnormal data.

[0099] When the overflow flag, the infinity flag, and the non-numerical flag are all invalid, the specific implementation process of combining the first sign bit, the third exponent value, and the third mantissa value according to the output data format to obtain the target output data is as follows: Read the fixed bit positions and bit width definitions of the sign bit, exponent bit, and mantissa bit in the output data format, and concatenate the first sign bit, the third exponent value, and the third mantissa value in sequence according to the order that the sign bit occupies the highest bit, the exponent bit follows, and the mantissa bit occupies the lowest bit; the exponent value needs to be padded with zeros at the high bits or truncated at the low bits according to the output exponent bit width, and the mantissa value needs to be aligned with valid bits and rounded off according to the output mantissa bit width. After concatenation, verify the consistency between the overall bit width and the format definition to ensure that the combined bit arrangement completely matches the encoding specification of the output data format, and generate the final target output data. This process is only executed when there are no overflow, infinity, or non-numerical abnormal flags to ensure the format compliance and numerical accuracy of normal data.

[0100] As an example, such as Figure 7 As shown, the mantissa input is first padded with a preset number of 1s in the high bits, and then a left shift operation is performed according to the output mantissa bit width to shift the valid data to the high bits, splitting the valid mantissa, guard_bit (the lowest bit of the valid part), and round_bit (the highest bit of the rounding part), and the remaining bits of the rounding part are bitwise ORed to obtain sticky_bit; then, guard_bit, round_bit, and sticky_bit are sent to the rounding module to generate a 1-bit rounding result, which is added to the high 32 bits of the left-shifted valid mantissa. Due to the design of padding the high bits with 1s, the carry will be passed to the high bits. If the highest bit generates a carry, it will be added to the exponent at the same time. The exponent input also participates in the adder operation. Finally, the corrected mantissa is processed by two's complement and output together with the adjusted exponent through the multiplexer, completing the entire process of rounding and exponent calibration.

[0101] This embodiment also provides a data type conversion device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0102] This embodiment provides a data type conversion device, such as... Figure 8 As shown, it includes: The acquisition module 801 is used to acquire the input data to be converted, the input data format, and the output data format; The first processing module 802 is used to process the data of different data bits in the input data according to the input data format to obtain intermediate data, the intermediate data including the first sign bit, the first exponent value and the first tail value; The second processing module 803 is used to determine the shift strategy based on the conversion relationship between the input data format and the output data format, and process the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value. The combination module 804 is used to combine the first sign bit, the second exponent value, and the second tail value according to the output data format to obtain the target output data.

[0103] In this embodiment of the application, the first processing module 802 is used to: if the input data format is a floating-point number format, identify whether there is a sign bit in the input data; if there is a sign bit, use the sign bit as the first sign bit; if there is no sign bit, use a preset sign bit as the first sign bit; extract the exponent bit from the input data and pad the high bits of the exponent bit with zeros; subtract the input bias value corresponding to the input data format from the extracted exponent value to obtain the first exponent value; extract the mantissa bit from the input data and place the valid bits in the mantissa bit in the high bits to obtain the first mantissa value.

[0104] In this embodiment of the application, the first processing module 802 is used to identify whether there is a sign bit in the input data if the input data format is an integer format; if there is a sign bit, the sign bit is used as the first sign bit; if there is no sign bit, the preset sign bit is used as the first sign bit; the preset exponent bit is used as the first exponent value; all data bits of the input data are used as mantissa bits, and it is determined whether the mantissa bits are negative; if the mantissa bits are negative, the mantissa bits are converted into an unsigned number to obtain the first mantissa value; or, if the mantissa bits are integers, the mantissa bits are used as the first mantissa value.

[0105] In this embodiment of the application, when the input data format is normalized floating-point format and the output data format is normalized floating-point format, the shift strategy is the first shift strategy; The second processing module 803 is used to determine the output bias value according to the output data format and set the number of leading zeros to zero; calculate the corresponding intermediate exponent value according to the first exponent value, the number of leading zeros and the output bias value; determine whether the first exponent value is non-zero and whether the intermediate exponent value is greater than zero; when the first exponent value is non-zero and the intermediate exponent value is greater than zero, use the intermediate exponent value as the second exponent value and use the first tail value as the second tail value.

[0106] In this embodiment of the application, when the input data format is normalized floating-point format and the output data format is integer format, or when the input data format is normalized floating-point format and the output data format is denormalized floating-point format, the shift strategy is the second shift strategy. The second processing module 803 is used to determine the output bias value according to the output data format and set the number of leading zeros to zero; calculate the corresponding intermediate exponent value according to the first exponent value, the number of leading zeros and the output bias value; determine whether the first exponent value is non-zero and whether the intermediate exponent value is less than or equal to zero; when the first exponent value is non-zero and the intermediate exponent value is less than or equal to zero, set the second exponent value to zero, and after padding the first tail value with hidden bits, shift it to the right by the absolute value of the intermediate exponent value, and the hidden position after shifting is zero, thus obtaining the second tail value.

[0107] In this embodiment of the application, when the input data format is integer and the output data format is normalized floating-point number format, or when the input data format is denormalized floating-point number format and the output data format is normalized floating-point number format, the shift strategy is the third shift strategy. The second processing module 803 is used to determine the output bias value according to the output data format, count the number of leading zeros for the first tail value, calculate the corresponding intermediate exponent value according to the first exponent value, the number of leading zeros and the output bias value, determine whether the first exponent value is zero and whether the intermediate exponent value is greater than zero, and when the first exponent value is zero and the intermediate exponent value is greater than zero, take the intermediate exponent value as the second exponent value, and use the number of leading zeros to shift the first tail value to the left to remove the leading zeros, discard the highest bit, and obtain the second tail value.

[0108] In this embodiment of the application, when the input data format is integer and the output data format is integer, or when the input data format is denormalized floating-point number and the output data format is denormalized floating-point number, the shift strategy is the fourth shift strategy. The second processing module 803 is used to count leading zeros in the first tail value to obtain the number of leading zeros; set the first tail value to zero to obtain the second exponent value; calculate the number of additional leading zeros according to the first exponent value and the output bias value corresponding to the output data format, wherein the number of additional leading zeros is the first exponent value plus the output bias value; when the number of additional leading zeros is greater than zero, the first tail value is shifted to the left according to the number of additional leading zeros, and the tail value obtained after the shift is used as the second tail value; or, when the number of additional leading zeros is less than zero, the first tail value is shifted to the right according to the absolute value of the number of additional leading zeros, and the tail value obtained after the shift is used as the second tail value.

[0109] In this embodiment of the application, the device further includes: a processing module, configured to: pad a preset number of preset values ​​into the high-order bits of the second mantissa according to the output data format to obtain an extended mantissa; shift the extended mantissa to the left according to the length of the mantissa valid bits corresponding to the output data format, so that the valid data bits are moved to the valid data bits, to obtain a left-shifted extended mantissa, wherein the valid data bits are the high-order part of the left-shifted extended mantissa, and the length of the high-order part is consistent with the length of the mantissa valid bits corresponding to the output data format; determine a rounding result based on the left-shifted extended mantissa, wherein the rounding result includes a protection bit, a rounding bit, and a sticky bit; and adjust the second exponent value and the second mantissa based on the protection bit, rounding bit, and sticky bit in the rounding result to obtain a third mantissa value and a third exponent value.

[0110] In this embodiment of the application, the device further includes: a detection module, used to detect whether the input data exceeds the representation range of the output data format and generate an overflow flag; detect whether the input data is infinity or non-numerical and generate an infinity flag and a non-numerical flag; when the overflow flag, the infinity flag, and the non-numerical flag are all invalid, the first sign bit, the third exponent value, and the third tail value are combined according to the output data format to obtain the target output data.

[0111] Please see Figure 9 , Figure 9 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 9 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system).

[0112] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.

[0113] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.

[0114] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the computer device as shown by a landing page for an app. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, which can be connected to the computer device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0115] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.

[0116] The computer device also includes a communication interface 30 for communicating with other devices or communication networks.

[0117] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.

[0118] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A data type conversion method, characterized in that, The method includes: Obtain the input data to be converted, the input data format, and the output data format; According to the input data format, the data of different data bits in the input data are processed to obtain intermediate data, the intermediate data including a first sign bit, a first exponent value and a first tail value; Based on the conversion relationship between the input data format and the output data format, a shift strategy is determined, and the first exponent value and the first tail value are processed according to the shift strategy to obtain the second exponent value and the second tail value. The first sign bit, the second exponent value, and the second tail value are combined according to the output data format to obtain the target output data.

2. The method according to claim 1, characterized in that, The step of processing different data bits in the input data according to the input data format to obtain intermediate data includes: If the input data is in floating-point format, then identify whether the input data has a sign bit; If the sign bit exists, then the sign bit is used as the first sign bit; if the sign bit does not exist, then the preset sign bit is used as the first sign bit. Extract the exponent bit from the input data, pad the high bits of the exponent bit with zeros, and subtract the input bias value corresponding to the input data format from the extracted exponent value to obtain the first exponent value; Extract the mantissa from the input data and place the valid bits in the high-order bits to obtain the first mantissa value.

3. The method according to claim 1, characterized in that, The step of processing different data bits in the input data according to the input data format to obtain intermediate data includes: If the input data format is integer, then identify whether the input data has a sign bit; If the sign bit exists, then the sign bit is used as the first sign bit; if the sign bit does not exist, then a preset sign bit is used as the first sign bit. Use the preset exponent as the first exponent value; All data bits of the input data are used as mantissa bits, and it is determined whether the mantissa bits are negative. If the mantissa bits are negative, they are converted into unsigned numbers to obtain the first mantissa value. Alternatively, if the mantissa bits are integers, they are used as the first mantissa value.

4. The method according to claim 1, characterized in that, When the input data format is a normalized floating-point number format and the output data format is a normalized floating-point number format, the shift strategy is the first shift strategy; The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: Determine the output bias value based on the output data format, and set the number of leading zeros to zero; Calculate the corresponding intermediate index value based on the first index value, the number of leading zeros, and the output bias value; Determine whether the first exponent value is non-zero and whether the intermediate exponent value is greater than zero; When the first exponent value is non-zero and the intermediate exponent value is greater than zero, the intermediate exponent value is used as the second exponent value, and the first tail value is used as the second tail value.

5. The method according to claim 1, characterized in that, When the input data format is a normalized floating-point number format and the output data format is an integer format, or when the input data format is a normalized floating-point number format and the output data format is a denormalized floating-point number format, the shift strategy is the second shift strategy. The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: Determine the output bias value based on the output data format, and set the number of leading zeros to zero; Calculate the corresponding intermediate index value based on the first index value, the number of leading zeros, and the output bias value; Determine whether the first exponent value is non-zero and whether the intermediate exponent value is less than or equal to zero; When the first exponent value is non-zero and the intermediate exponent value is less than or equal to zero, the second exponent value is set to zero, and the first tail value is padded with a hidden bit and then shifted to the right. The right shift amount is the absolute value of the intermediate exponent value, and the hidden position after the shift is zero, thus obtaining the second tail value.

6. The method according to claim 1, characterized in that, When the input data format is an integer format and the output data format is a normalized floating-point format, or when the input data format is a denormalized floating-point format and the output data format is a normalized floating-point format, the shift strategy is the third shift strategy. The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: The output bias value is determined according to the output data format, and the number of leading zeros is obtained by counting the leading zeros of the first tail value. Calculate the corresponding intermediate index value based on the first index value, the number of leading zeros, and the output bias value; Determine whether the first exponent value is zero and whether the intermediate exponent value is greater than zero; When the first exponent value is zero and the intermediate exponent value is greater than zero, the intermediate exponent value is used as the second exponent value, and the first tail value is shifted left by the number of leading zeros to remove the leading zeros, and the highest bit is discarded to obtain the second tail value.

7. The method according to claim 1, characterized in that, When the input data format is an integer format and the output data format is an integer format, or when the input data format is a denormalized floating-point format and the output data format is a denormalized floating-point format, the shift strategy is the fourth shift strategy. The step of processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value includes: Count the number of leading zeros by performing a leading zero count on the first tail value; set the first tail value to zero to obtain the second exponent value; The number of additional leading zeros is calculated based on the first exponent value and the output bias value corresponding to the output data format, wherein the number of additional leading zeros is the first exponent value plus the output bias value; When the number of extra leading zeros is greater than zero, the first tail value is shifted to the left according to the number of extra leading zeros, and the tail value obtained after the shift is used as the second tail value; or, when the number of extra leading zeros is less than zero, the first tail value is shifted to the right according to the absolute value of the number of extra leading zeros, and the tail value obtained after the shift is used as the second tail value.

8. The method according to claim 1, characterized in that, After processing the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value, the method further includes: According to the output data format, a preset number of preset values ​​are padded into the high-order bits of the second tail value to obtain the extended tail value; Based on the length of the mantissa significant bits corresponding to the output data format, the extended mantissa value is shifted to the left so that the significant data bits are moved to the significant data bits, resulting in the left-shifted extended mantissa value. The significant data bits are the high-order part of the left-shifted extended mantissa value, and the length of the high-order part is the same as the length of the mantissa significant bits corresponding to the output data format. The rounding result is determined based on the extended tail value after left shift, wherein the rounding result includes a guard bit, a rounding bit, and a sticky bit; Based on the protection bit, rounding bit, and sticky bit in the rounding result, the second exponent value and the second tail value are adjusted to obtain the third tail value and the third exponent value.

9. The method according to claim 8, characterized in that, After obtaining the third tail value and the third exponent value, the method further includes: Detect whether the input data exceeds the representation range of the output data format and generate an overflow flag; Detect whether the input data is infinity or non-numerical, and generate an infinity flag and a non-numerical flag; When the overflow flag, the infinity flag, and the non-numerical flag are all invalid, the first sign bit, the third exponent value, and the third tail value are combined according to the output data format to obtain the target output data.

10. A data type conversion device, characterized in that, The device includes: The acquisition module is used to acquire the input data to be converted, the input data format, and the output data format; The first processing module is used to process data of different data bits in the input data according to the input data format to obtain intermediate data, wherein the intermediate data includes a first sign bit, a first exponent value and a first tail value; The second processing module is used to determine a shift strategy based on the conversion relationship between the input data format and the output data format, and to process the first exponent value and the first tail value according to the shift strategy to obtain the second exponent value and the second tail value. The combination module is used to combine the first sign bit, the second exponent value, and the second tail value according to the output data format to obtain the target output data.

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