Register configuration apparatus, method, electronic device, and storage medium

Abstract

The present disclosure provides a register configuration apparatus, method, electronic device and storage medium. The register configuration apparatus comprises a register group, and registers in the register group are configured to store configuration data for configuring an execution circuit based on a working mode; a decoding circuit is configured to receive a configuration access request, decode the configuration access request, determine a plurality of target registers in the register group based on register address sequences included in the decoded configuration access request, and write a plurality of configuration data corresponding to a plurality of register addresses in the register address sequences included in the configuration access request into the plurality of target registers respectively; and at least part of the plurality of register addresses included in the register address sequences are arranged continuously. Thus, the configuration efficiency of configuring a plurality of registers can be improved.

Description

Technical Field

[0001] This disclosure relates to register configuration techniques, and more particularly to a register configuration apparatus, method, electronic device, and storage medium. Background Technology

[0002] In order for a circuit in the hardware to perform a specific function, the registers corresponding to the circuit in the hardware need to be configured so that the registers store configuration data that supports the circuit to perform the specific function.

[0003] When configuring registers corresponding to circuits in hardware, multiple registers need to be configured. Related technologies require configuring each register separately, resulting in low register configuration efficiency. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a register configuration apparatus, method, electronic device, and storage medium.

[0005] A first aspect of this disclosure provides a register configuration apparatus, comprising: Register group, wherein the registers in the register group are configured as follows: Store configuration data for configuring the execution circuitry based on the operating mode; The decoding circuit is configured as follows: Receive configuration access requests; The configuration access request is decoded, and multiple target registers in the register group are determined based on the register address sequence included in the decoded configuration access request. The configuration data included in the configuration access request, corresponding to multiple register addresses in the register address sequence, are written into multiple target registers respectively; wherein, at least a portion of the multiple register addresses included in the register address sequence are arranged consecutively.

[0006] A second aspect of this disclosure provides a register configuration method, including: Receive configuration access requests via decoding circuitry; The configuration access request is decoded by the decoding circuit. Based on the register address sequence included in the decoded configuration access request, multiple target registers in the register group are determined. The registers in the register group are used to store configuration data for configuring the execution circuit based on the working mode. The decoding circuit writes the configuration data, which corresponds to multiple register addresses in the register address sequence, into multiple target registers, respectively, as included in the configuration access request; wherein at least a portion of the register addresses in the register address sequence are arranged consecutively.

[0007] A third aspect of this disclosure is to provide a computer-readable storage medium storing a computer program that, when executed, implements the register configuration method of any of the above embodiments.

[0008] A fourth aspect of this disclosure provides a computer program product that, when executed by an instruction processor, implements the register configuration method of any of the above embodiments.

[0009] A fifth aspect of this disclosure provides an electronic device, including: Memory, used to store computer programs; A processor is configured to execute a computer program stored in the memory, wherein when the computer program is executed by the processor, it implements the register configuration method of any of the above embodiments.

[0010] A sixth aspect of this disclosure provides a neural network processor, comprising: The register configuration device provided in the first embodiment described above.

[0011] In this embodiment, the decoding circuit decodes the received configuration access request to obtain a register address sequence. Based on the multiple register addresses included in the register address sequence, multiple target registers are determined. Then, the configuration data corresponding to each of the multiple register addresses included in the configuration access request is written into the multiple target registers, completing the configuration of the multiple target registers. Notably, at least some of the register addresses in the register address sequence are arranged consecutively. Therefore, continuous configuration of multiple registers can be achieved based on consecutive register addresses. Furthermore, because the addresses of the multiple registers to be written are consecutive, address gaps during batch configuration can be reduced, thus improving register configuration efficiency. Attached Figure Description

[0012] Figure 1 This is a system architecture diagram of a system to which some exemplary embodiments of this disclosure apply.

[0013] Figure 2 This is a schematic diagram of the structure of a register configuration device provided in an exemplary embodiment of the present disclosure.

[0014] Figure 3 This is a schematic diagram of the structure of a register configuration apparatus provided in some other exemplary embodiments of this disclosure.

[0015] Figure 4 This is a schematic diagram of the structure of a register configuration apparatus provided in some exemplary embodiments of the present disclosure.

[0016] Figure 5 This is a schematic diagram of the structure of a register configuration apparatus provided by some exemplary embodiments of the present disclosure.

[0017] Figure 6 This is a flowchart illustrating a register configuration method provided by some exemplary embodiments of this disclosure.

[0018] Figure 7 This is a flowchart illustrating a register configuration method provided by some other exemplary embodiments of this disclosure.

[0019] Figure 8 This is a flowchart illustrating the process of determining multiple target registers via a decoding circuit, provided by some exemplary embodiments of this disclosure.

[0020] Figure 9 This is a schematic diagram of a process for transmitting a configuration access request to a decoding circuit, provided by some exemplary embodiments of this disclosure.

[0021] Figure 10 This is a schematic diagram of a process for transmitting configuration transmission transactions to a decoding circuit, provided by some exemplary embodiments of this disclosure.

[0022] Figure 11 This is a schematic diagram of the process of generating configuration transfer transactions through a controller, provided by some exemplary embodiments of this disclosure.

[0023] Figure 12 This is a schematic diagram of the process of decoding configuration transmission transactions through a decoding circuit, provided by some exemplary embodiments of this disclosure.

[0024] Figure 13 This is a schematic diagram of a process for transmitting a configuration access request to a decoding circuit, provided by some other exemplary embodiments of this disclosure.

[0025] Figure 14 This is a structural diagram of an electronic device provided in an exemplary embodiment of this disclosure. Detailed Implementation

[0026] To explain this disclosure, exemplary embodiments of the disclosure will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the disclosure, and not all of them. It should be understood that the disclosure is not limited to exemplary embodiments.

[0027] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0028] Application Overview To enable a circuit in hardware to perform a specific function, multiple registers corresponding to the circuit need to be configured. In related technologies, each register needs to be configured individually. Alternatively, a batch configuration method using a configuration bus can be employed.

[0029] When configuring registers in batches via the configuration bus, invalid addresses (called address holes, indicating addresses that do not need to be written) exist in consecutively configured register addresses. These invalid addresses must be marked using a strobe signal. When configuring multiple registers, the dispersed register addresses result in numerous address holes due to the batch configuration method, leading to low register configuration efficiency.

[0030] Exemplary System Figure 1 This is a system architecture diagram of a system to which some exemplary embodiments of this disclosure apply. For example... Figure 1 As shown, the system includes a register group 10, a decoding circuit 20, and an execution circuit 30. The register group 10 includes registers 101, which can be electrically connected to the decoding circuit 20 and the execution circuit 30, respectively.

[0031] The decoding circuit 20 can write the configuration data for configuring the execution circuit 30 into the corresponding register 101 in the register group 10 according to the configuration access request. The execution circuit 30 can implement specific functions based on the configuration data stored in the configured register 101. For example, the execution circuit 30 can implement the corresponding calculation function in a specific working mode based on the configuration data stored in the configured register 101.

[0032] In some alternative implementations, register group 10 may be a plurality of registers within execution circuitry 30. Alternatively, register group 10 may be a plurality of registers independent of execution circuitry 30.

[0033] In some alternative implementations, the decoding circuit 20 may be a local circuit within the execution circuit 30. Alternatively, the decoding circuit 20 may be a circuit independent of the execution circuit 30.

[0034] Exemplary device Figure 2 This is a schematic diagram of a register configuration apparatus provided in an exemplary embodiment of this disclosure. On one hand, the register configuration apparatus can be applied to a neural network processor, chip, or electronic device; on the other hand, the register configuration apparatus can itself be a neural network processor, chip, or electronic device. Figure 2 As shown, the register configuration apparatus of this disclosure includes: Register group 10, register 101 in register group 10 is configured to store configuration data for configuring execution circuit 30 based on operating mode.

[0035] The decoding circuit 20 is configured to receive a configuration access request, decode the configuration access request, determine multiple target registers in the register group 10 based on the register address sequence included in the decoded configuration access request, and write multiple configuration data corresponding to the multiple register addresses in the register address sequence included in the configuration access request into the multiple target registers respectively; wherein, at least a portion of the multiple register addresses included in the register address sequence are arranged consecutively.

[0036] Each register 101 in register group 10 is electrically connected to the decoding circuit 20.

[0037] For example, register group 10 includes multiple registers 101, each storing different configuration data. This register group supports writing batch configuration data for the execution circuit under multiple operating modes (hereinafter referred to as modes). Different operating modes correspond to different configuration data. After confirming any operating mode, the multiple configuration data corresponding to that operating mode can be written in batches into the corresponding registers in register group 10, and the execution circuit 30 corresponding to those registers can be controlled to complete the functional operation corresponding to that operating mode. That is, configuration data is written to different registers in register group 10 under different operating modes, so that the configured registers can support the execution circuit 30 to run in the corresponding operating mode. The configuration data represents the execution parameters of the execution circuit 30, and may include parameter configuration data, mode configuration data, precision type, etc.

[0038] The operating mode refers to the data calculation mode performed by the execution circuit 30. The operating mode is used to indicate the operation method of the execution circuit 30 in processing data, or to indicate the data processing function that the execution circuit 30 needs to perform. Different operating modes correspond to different data operation methods or different data processing functions.

[0039] The execution circuit 30 can be a circuit with execution functions. The same execution circuit 30 can support one operating mode or different operating modes. In one operating mode, it is usually necessary to control one or more execution circuits to perform the function corresponding to that operating mode. If multiple execution circuits need to be controlled to perform the function corresponding to that operating mode in one operating mode, configuration data needs to be written to multiple registers respectively. The configuration data written to the multiple registers then controls the corresponding multiple execution circuits to complete the corresponding operations. The execution circuit 30 includes, but is not limited to, circuits of the types such as arithmetic circuits, control execution circuits, auxiliary arithmetic circuits, loading circuits, selection circuits, and shift circuits. Furthermore, the arithmetic circuit includes, but is not limited to, multipliers, adder tree circuits, accumulator registers, tensor calculation circuits, and vector calculation circuits.

[0040] The decoding circuit 20 is used to decode the configuration access request. Optionally, the decoding circuit 20 may include an address decoding circuit. By decoding the configuration access request through the decoding circuit 20, the register address sequence and corresponding configuration data included in the decoded configuration access request can be obtained. The register address sequence includes multiple register addresses. Then, the configuration data is written into the corresponding register 101 in the register group 10.

[0041] A configuration access request is used to configure a target register in the register bank. The register address sequence in the configuration access request includes the register address of the target register and the configuration data corresponding to each register address. The register address indicates the write address of the corresponding configuration data. The register address can be the physical offset address of the register in memory. The target register can be a register that needs to be configured when configuring the execution circuit 30 in a certain operating mode. After configuring the target register by writing configuration data based on the configuration access request, the execution circuit 30 corresponding to the target register can perform the corresponding operation in the corresponding operating mode based on the configuration data stored in the target register.

[0042] For example, the configuration access request may include a sequence of register addresses corresponding to multiple configuration data, or the configuration access request may include address information indicating the register address sequence. The decoding circuit 20 decodes the configuration access request to obtain the register address sequence corresponding to the configuration access request.

[0043] The register address sequence includes multiple register addresses, each corresponding to a write address for a specific configuration data item included in the configuration access request. At least a portion of the register addresses in the register address sequence are arranged consecutively. Consecutive register address arrangement means that the registers are physically located adjacently in memory. For example, consecutive register addresses could be 0x000, 0x001, 0x002, 0x003…

[0044] For example, the register address sequence may include multiple register addresses that are all consecutively arranged, or some register addresses that are consecutively arranged. The consecutively arranged partial register addresses may include one or more partial register addresses. For instance, the consecutively arranged partial register addresses may include a first portion of consecutively arranged register addresses, such as 0x000 and 0x001, and a second portion of consecutively arranged register addresses, such as 0x006 and 0x007.

[0045] For example, a configuration access request may include one or more configuration access sub-requests. That is, multiple target registers can be configured in batches using a single configuration access request. Alternatively, multiple target registers can be configured in batches using multiple configuration access sub-requests. It should be noted that at least some register addresses in the register address sequence corresponding to each configuration access request are consecutive.

[0046] In cases involving multiple configuration access sub-requests, the decoding circuit 20 can decode all configuration access requests after receiving them, and determine multiple target registers in register group 10 to write the corresponding configuration data into the target registers respectively. Alternatively, the decoding circuit 20 can receive configuration access sub-requests separately, decode them sequentially, and in each decoding process, determine the target register corresponding to the register address indicated by the configuration access sub-request, and write the configuration data corresponding to the register address into the target register.

[0047] In this embodiment, the decoding circuit decodes the received configuration access request to obtain a register address sequence. Based on the multiple register addresses included in the register address sequence, multiple target registers are determined. Then, the configuration data corresponding to each of the multiple register addresses included in the configuration access request is written into the multiple target registers, completing the configuration of the multiple target registers. Notably, at least some of the register addresses in the register address sequence are arranged consecutively. Therefore, continuous configuration of multiple registers can be achieved based on consecutive register addresses. Furthermore, because the addresses of the multiple registers to be written are consecutive, address gaps during batch configuration can be reduced, thus improving register configuration efficiency.

[0048] In some alternative implementations, such as Figure 3 As shown, the registers in register group 10 include special register 1011 and shared register 1013.

[0049] Optionally, the number of shared registers 1013 may include one or more. Shared register 1013 represents a register allocated for configuration data storage in all operating modes across multiple operating modes. That is, the register configuration device can support register configuration for multiple operating modes, and shared register 1013 refers to a register that can support write configuration to the execution circuit 30 for all operating modes. For example, if the register configuration device can support register configuration for 10 operating modes, then shared register 1013 refers to a register that can support write configuration to the execution circuit 30 for all 10 operating modes. Correspondingly, the register address includes the shared register address corresponding to shared register 1013. When there are multiple shared registers 1013, the multiple shared register addresses corresponding to the multiple shared registers 1013 are at least partially contiguous. For example, if working mode A requires writing configuration data to 5 shared registers, then at least some of the shared register addresses among the 5 shared register addresses must be arranged consecutively. The number of shared register addresses arranged consecutively can be 2, 3, 4 or 5. If the number of shared register addresses arranged consecutively is 5, the corresponding consecutively arranged shared register addresses can be, for example, 0x001, 0x002, 0x003, 0x004 and 0x005.

[0050] Optionally, the number of special-purpose registers 1011 may include one or more. Special-purpose register 1011 represents a register allocated to a portion of the aforementioned multiple operating modes for configuration data storage. That is, special-purpose register 1011 is a register that can only support writing configuration to the execution circuit 30 in a portion of the operating modes. For example, if the register configuration device can support register configuration for 10 operating modes, then special-purpose register 1011 refers to a register that can only support writing configuration to the execution circuit 30 for fewer than 10 operating modes, such as special-purpose register 1011 supporting only 1, 3, 5, 7, or 9 operating modes. Correspondingly, the register address includes the special-purpose register address corresponding to special-purpose register 1011. When special-purpose register 1011 includes multiple registers, at least some of the special-purpose register addresses corresponding to the multiple special-purpose registers 1011 are arranged consecutively. For example, if operating mode C requires writing configuration data to four special-purpose registers, then at least some of the shared register addresses among the four special-purpose register addresses are arranged consecutively. The number of shared register addresses arranged consecutively can be two, three, or four. If the number of shared register addresses arranged consecutively is four, the corresponding consecutively arranged shared register addresses could be, for example, 0x010, 0x011, 0x012, and 0x013.

[0051] Optionally, registers can be pre-allocated according to the configuration data required for different operating modes of the execution circuit 30, dividing the multiple registers included in the register group 10 into shared register 1013 and dedicated register 1011.

[0052] Optionally, the operating modes include at least one of pooling mode, convolution mode, activation mode, concatenation mode, pruning mode, and data slicing mode. For example, in pooling mode, one or more execution circuits 30 perform pooling processing on the data based on configuration data in the corresponding registers. In convolution mode, one or more execution circuits 30 perform convolution processing on the data based on configuration data in the corresponding registers. In activation mode, one or more execution circuits 30 perform activation processing on the data based on configuration data in the corresponding registers. In concatenation mode, one or more execution circuits 30 perform concatenation processing on the data based on configuration data in the corresponding registers. In pruning mode, one or more execution circuits 30 perform pruning processing on the data based on configuration data in the corresponding registers. In data slicing mode, one or more execution circuits 30 slice the data into chunks based on configuration data in the corresponding registers.

[0053] Optionally, the configuration data for configuring the execution circuit 30 may include, but is not limited to, at least one of the following: interrupt enable signal, input address parameter, output address parameter, input size parameter, output size parameter, constant, padding parameter, convolution kernel size parameter, activation type parameter, and shared configuration parameter.

[0054] The different operating modes each correspond to multiple configuration data sets. These configuration data sets are not entirely identical across different operating modes. For example, each operating mode may include one or more identical configuration data sets, as well as configuration data only present in certain operating modes. That is, the configuration data includes shared configuration data (also called first configuration data) that needs to be configured in all operating modes and dedicated configuration data (also called second configuration data) that needs to be configured in certain operating modes. For example, input size parameters, output size parameters, input address parameters, output address parameters, and shared constants are shared configuration data that needs to be configured in all operating modes. Specific input size parameters and specific output size parameters are dedicated configuration data that needs to be configured in certain operating modes. For multiple different shared configuration data sets, shared registers 1013 can be allocated for storage. For multiple different dedicated configuration data sets, dedicated registers 1011 can be allocated for storage, thus dividing the multiple registers included in register group 10 into multiple shared registers 1013 and / or multiple dedicated registers 1011.

[0055] In some alternative implementations, consecutively arranged shared register addresses and / or multiple dedicated register addresses can be allocated to shared register 1013 and dedicated register 1011 respectively, for the purpose of consecutively configuring multiple shared registers 1013 and / or multiple dedicated registers 1011.

[0056] The decoding circuit 20 is further configured to: decode the configuration access request; determine multiple target special-purpose registers and / or multiple target shared registers based on the consecutively arranged addresses of multiple special-purpose registers and / or consecutively arranged addresses of multiple shared registers in the register address sequence included in the decoded configuration access request; write first configuration data corresponding to the multiple shared register addresses into the multiple target shared registers respectively; and / or write multiple second configuration data corresponding to the consecutively arranged addresses of multiple special-purpose registers into the multiple target special-purpose registers respectively.

[0057] Optionally, the register address sequence obtained after decoding the configuration access request by the decoding circuit 20 includes multiple consecutively arranged special purpose register addresses and / or multiple consecutively arranged shared register addresses. The consecutively arranged special purpose register addresses correspond to multiple different special purpose registers 1011, and the consecutively arranged shared register addresses correspond to multiple different shared registers 1013. The decoding circuit 20 can determine multiple target special purpose registers based on the consecutively arranged special purpose register addresses, and / or can determine multiple target shared registers based on the consecutively arranged shared register addresses.

[0058] The configuration data in the configuration access request may include first configuration data and / or second configuration data. The first configuration data may be the aforementioned shared configuration data, and the second configuration data may be the aforementioned dedicated configuration data. When the decoding circuit 20 obtains multiple consecutively arranged shared register addresses through decoding, it can determine the first configuration data corresponding to each shared register address and write each piece of first configuration data into the target shared register corresponding to that shared register address. When the decoding circuit 20 obtains multiple consecutively arranged dedicated register addresses through decoding, it can determine the second configuration data corresponding to each dedicated register address and write each piece of second configuration data into the target dedicated register corresponding to that dedicated register address.

[0059] In this embodiment, the registers can be divided into dedicated registers 1011 and shared registers 1013 according to the configuration data requirements of the execution circuit under different operating modes. The register addresses corresponding to the multiple dedicated registers 1011 include at least a partially contiguous arrangement of multiple dedicated register addresses, and the register addresses corresponding to the multiple shared registers 1013 include at least a partially contiguous arrangement of multiple shared register addresses. Configuration access requests for configuring multiple target dedicated registers and / or multiple target shared registers can be generated based on the at least partially contiguous arrangement of multiple dedicated register addresses and / or at least a partially contiguous arrangement of multiple shared register addresses and sent to the decoding circuit 20. The decoding circuit 20 can continuously configure the multiple target dedicated registers and / or multiple target shared registers according to the configuration access requests, thereby helping to reduce configuration time and improve register configuration efficiency.

[0060] Furthermore, register group 10 is divided into dedicated register 1011 and shared register 1013. Shared register 1013 is allocated to all operating modes, allowing configuration data to be written to the execution circuit in all operating modes. Dedicated register 1011 is allocated to some operating modes, allowing configuration data to be written to the execution circuit in some operating modes. Thus, it is not necessary to allocate multiple separate registers for different operating modes, which reduces the need for a large number of registers and effectively reduces register hardware overhead.

[0061] In some alternative implementations, register group 10 can be divided according to the operating mode to obtain dedicated register 1011 that can support write configuration for execution circuit 30 only in some operating modes, and shared register 1013 that can support write configuration for execution circuit in all operating modes.

[0062] Optionally, among the multiple dedicated register addresses of the multiple dedicated registers 1011 corresponding to each operating mode, at least some of the dedicated register addresses are arranged consecutively. Among the multiple shared register addresses of the multiple shared registers 1013 that require write configuration in all operating modes, at least some of the shared register addresses are arranged consecutively.

[0063] Table 1 illustrates the partitioning of multiple registers 101 in register group 10 provided in some exemplary embodiments of this disclosure. The following example illustrates the operation modes supported by the register configuration device, including Mode A, Mode B, and Mode C. The configuration information, including input 0 size dim0, output size dim0, mode selection, address start position, address end position, and constant 2, is required for all three operation modes. The corresponding configuration data is written to the shared register 1013. The addresses of the multiple shared registers 1013 are consecutively arranged (0x000-0x005). The configuration information, including constant 0, splicing direction, input 0 size dim1, output size dim1, and constant 1, is required for Mode A. The corresponding configuration data is written to the dedicated register 1011 for Mode A. The addresses of the multiple dedicated registers 1011 for Mode A are consecutively arranged (0x006-0x00A). As shown in Table 1, the addresses of the multiple special-purpose registers 1011 corresponding to Mode B and Mode C are also arranged consecutively, which will not be elaborated here.

[0064] Table 1

[0065] Based on the mapping relationship configured above, in a working mode, the target register to be configured in that working mode can be configured continuously based on the addresses of multiple shared registers arranged in succession and the addresses of multiple dedicated registers arranged in succession corresponding to that mode.

[0066] Optionally, the configuration data included in the configuration access request may be configuration data configured for the execution circuit 30 in the same operating mode. For example, referring to the example in Table 1, in mode A, the configuration data included in the configuration access request may include configuration data corresponding to input 0 size dim0, output size dim0, mode selection, address start position, address end position, and constant 2, as well as configuration data corresponding to constant 0, splicing direction, input 0 size dim1, output size dim1, and constant 1.

[0067] The decoding circuit 20, based on the consecutively arranged addresses of multiple dedicated registers and / or multiple shared registers in the decoded register address sequence, can determine multiple target dedicated registers and / or multiple target shared registers. These target dedicated registers and / or multiple target shared registers are registers for configuration writes to the execution circuit within the same operating mode. For example, referring to the example in Table 1, in mode A, the consecutively arranged addresses of multiple dedicated registers included in the configuration access request could be 0x006-0x00A, and the corresponding dedicated register 1011 is a dedicated register for mode A. The consecutively arranged addresses of multiple shared registers could be 0x000-0x005, and the corresponding shared register 1013 also belongs to the registers that need to be configured in mode A.

[0068] In this embodiment, the decoding circuit 20 can decode the configuration access request to obtain the configuration data to be configured in the same working mode, as well as the addresses of multiple dedicated registers and / or multiple shared registers arranged consecutively. This enables the continuous configuration of the dedicated register 1011 and / or shared register 1013 corresponding to the working mode in the same working mode, which helps to improve the configuration efficiency of registers in each working mode.

[0069] In some optional implementations, the decoding circuit 20 decodes the configuration access request and determines multiple target registers by decoding the configuration access request based on a pre-configured address mapping relationship, thereby determining the register address sequence included in the decoded configuration access request; and determining multiple target registers corresponding to the multiple register addresses based on the multiple register addresses in the register address sequence.

[0070] The address mapping relationship represents the correspondence between register addresses and corresponding registers. As shown in Table 1, address 0x000 corresponds to the register where configuration data of size dim0 (configuration information input 0) is written. After decoding the configuration access request, the decoding circuit 20 obtains a register address sequence. Then, based on the address mapping relationship, it can determine the registers corresponding to the multiple register addresses included in the register address sequence, thus determining multiple target registers. For example, after decoding the register address sequence, if the register address sequence includes register address 0x000, the decoding circuit 20 can determine the register corresponding to 0x000 (e.g., reg000) according to the address mapping relationship, and determine reg000 as the target register. Optionally, when the configuration access request includes a register address sequence corresponding to multiple configuration data, the decoding circuit 20 can directly obtain the register address sequence by decoding the configuration access request.

[0071] When the configuration access request includes address information indicating the register address sequence, the decoding circuit 20 can decode the configuration access request to obtain the address information and determine the register address sequence indicated by the configuration access request based on the address information.

[0072] In this embodiment, the decoding circuit 20 determines multiple target registers corresponding to the register address sequence included in the configuration access request based on the pre-configured address mapping relationship, so as to accurately write the configuration data into the corresponding registers.

[0073] Optionally, the register includes special purpose register 1011. The register address includes the special purpose register address corresponding to special purpose register 1011. The address mapping relationship includes the correspondence between the same special purpose register 1011 and at least two different special purpose register addresses.

[0074] That is, the same special register 1011 can be configured with at least two different special register addresses. For example, the same special register 1011 (represented as reg001) can be configured with special register address 0x00D and special register address 0x008.

[0075] When the decoding circuit 20 decodes at least two different special purpose register addresses configured in the same special purpose register 1011, it can write the corresponding configuration data into the same special purpose register 1011. For example, in conjunction with the above example, the decoding circuit 20 can perform the following operations: If (addr == 0x00D || addr == 0x008) {reg001 = data}. This means that if the decoded register address is 0x008 or 0x00D, the configuration data data can be written into the corresponding special register reg001.

[0076] In this embodiment, the address mapping relationship includes the correspondence between the same special purpose register 1011 and at least two different special purpose register addresses, so that the configuration data corresponding to at least two different special purpose register addresses can be written into the same special purpose register 1011, thereby reducing the hardware overhead of the register.

[0077] When pre-configuring the address mapping relationship, you can configure consecutive register addresses for multiple shared registers 1013, and consecutive register addresses for multiple dedicated registers 1011 corresponding to different working modes.

[0078] The same special purpose register 1011 can be assigned to two or more operating modes for configuration data storage. To ensure that the special purpose register addresses of special purpose registers 1011 corresponding to each operating mode are arranged consecutively, different special purpose register addresses can be preset for special purpose registers 1011 assigned to at least two operating modes for configuration data storage. For example, the special purpose register address corresponding to mode B (represented as 0x00D) and the special purpose register address corresponding to mode A (represented as 0x008) are configured to be mapped to the same special purpose register 1011 (represented as reg001).

[0079] That is, at least two different special purpose register addresses corresponding to the same special purpose register 1011 are respectively assigned to at least two different operating modes, so that in a first target operating mode among the at least two different operating modes, at least a portion of the special purpose register addresses corresponding to the first target operating mode are arranged consecutively. The first target operating mode can be any of the at least two different operating modes. In other words, the at least two different special purpose register addresses belong to the consecutively arranged special purpose register addresses corresponding to the at least two operating modes to which the special purpose register 1011 is assigned.

[0080] As shown in Table 1, the configuration information input 0, size dim1, is the configuration information that needs to be configured in both Mode A and Mode B. The dedicated register 1011 to which the configuration data corresponding to this configuration information is written is allocated to Mode A and Mode B respectively, and can be used as dedicated register 1011 for Mode A and dedicated register 1011 for Mode B respectively. In order to make the multiple dedicated register addresses of multiple dedicated registers 1011 in Mode A and Mode B consecutively arranged, different dedicated register addresses can be preset for each dedicated register, such as 0x008 for Mode A and 0x00D for Mode B. That is, dedicated register addresses 0x008 and 0x00D are mapped to the same dedicated register. If the register address sequence obtained by decoding the configuration access request by the decoding circuit 20 includes 0x008 or 0x00D, the corresponding configuration data can be written into the corresponding same dedicated register.

[0081] In this embodiment, instead of allocating a separate dedicated register corresponding to a dedicated register address for each working mode in order to arrange multiple dedicated register addresses corresponding to the same working mode consecutively, the same dedicated register 1011 can be allocated to at least two working modes. The same dedicated register 1011 is preset with different dedicated register addresses in different working modes. In the corresponding working mode, any dedicated register address can be set to be arranged consecutively with other dedicated register addresses corresponding to that working mode. This setting method can not only ensure that multiple dedicated register addresses corresponding to any working mode are arranged consecutively, but also effectively reduce the hardware overhead of dedicated registers.

[0082] In some alternative implementations, Figure 4 A schematic diagram of the structure of a register configuration apparatus provided in some exemplary embodiments of the present disclosure is shown. Figure 2 Based on the embodiments, such as Figure 4 As shown, the register configuration device also includes a controller 40 and a configuration bus 50. The controller 40 is electrically connected to the configuration bus 50, and the configuration bus 50 is electrically connected to the decoding circuit 20.

[0083] The controller 40 is used to control the configuration of multiple registers 101 in the register group 10. Specifically, the controller 40 can generate a corresponding configuration access request based on the configuration information required for the operating mode, and transmit the configuration access request to the decoding circuit 20 via the configuration bus 50.

[0084] Optionally, the controller 40 may include a central processing unit (CPU), a direct memory access (DMA) controller, or a microcontroller unit (MCU), etc.

[0085] In some optional implementations, the controller 40 is configured to: determine multiple configuration information based on a second target operating mode; acquire each register address and each configuration data corresponding to each configuration information; generate first register address information based on each register address corresponding to each configuration information; wherein the first register address information represents at least a portion of the register addresses in a continuous arrangement; generate a configuration access request based on the first register address information and each configuration data corresponding to each register address; and transmit the configuration access request to the decoding circuit 20 via the configuration bus 50.

[0086] The second target operating mode can be any of multiple operating modes. When the execution circuit 30 needs to be configured based on the second target operating mode, the controller 40 can determine the corresponding multiple configuration information based on the second target operating mode. Optionally, the controller 40 can determine the multiple configuration information corresponding to the second target operating mode based on the mapping relationship between multiple operating modes and multiple configuration information. For example, referring to the example shown in Table 1, if the second target operating mode is mode A, the corresponding multiple configuration information may include input 0 size dim0, output size dim0, mode selection, address start position, address end position, constant 2, constant 0, splicing direction, input 0 size dim1, output size dim1, and constant 1.

[0087] After determining the multiple configuration information corresponding to the second target operating mode, the controller 40 can obtain the register addresses and configuration data corresponding to each configuration information. The register addresses corresponding to each configuration information can be determined according to a pre-set address mapping relationship, as shown in Table 1. After determining the register addresses corresponding to each configuration information, first register address information can be generated. This first register address information indicates the multiple register addresses corresponding to the multiple configuration information, where at least some register addresses are arranged consecutively. Optionally, the first register address information may include the multiple register addresses corresponding to the multiple configuration information. Alternatively, the first register address information may include the starting register address of each consecutively arranged register address.

[0088] In some alternative implementations, such as Figure 5As shown, the register configuration device also includes a memory 60, which is electrically connected to the controller 40. The memory 60 is used to store configuration information for the execution circuit 30. Optionally, the memory 60 may be a dynamic random-access memory (DRAM), a static random-access memory (SRAM), a double data rate synchronous dynamic random-access memory (DDR SDRAM), or the like.

[0089] After determining the multiple configuration information corresponding to the second target operating mode, the controller 40 can retrieve the configuration data corresponding to the multiple configuration information from the memory 60. Optionally, the multiple configuration information corresponding to the second target operating mode can be stored continuously in the memory 60. During the process of reading the configuration data, the controller 40 can determine the storage start address information and data length information of the configuration data corresponding to each of the multiple configuration information in the memory 60, and read the configuration data corresponding to the multiple configuration information from the memory 60 based on the storage start address information and data length information. Optionally, the configuration data of the multiple configuration information corresponding to the second target operating mode can also be stored separately in different storage areas of the memory 60. The controller 40 can determine the storage start address information and data length information of the configuration data of each configuration information separately, and read the configuration data corresponding to each configuration information separately.

[0090] After generating first register address information based on multiple register addresses and reading the configuration data corresponding to each configuration information, controller 40 can generate a configuration access request. The configuration access request includes the first register address information and the configuration data corresponding to each configuration information. Then, the configuration access request is transmitted to decoding circuit 20 via configuration bus 50. Optionally, when transmitting the configuration access request to decoding circuit 20 via configuration bus 50, controller 40 can transmit based on the bus protocol of configuration bus 50. For example, the bus protocol may include Advanced Dextensible Interface (AXI) protocol or Advanced High-performance Bus (AHB) protocol.

[0091] In one example, referring to the example in Table 1, when the second target working mode is mode A, multiple configuration information of mode A (including input 0 size dim0, output size dim0, mode selection, address start position, address end position, constant 2, constant 0, splicing direction, input 0 size dim1, output size dim1, constant 1) correspond to multiple configuration data (represented as data0, data1, data2, data3, data4, data5, data6, data7, data8, data9, data10 respectively). Multiple configuration data can be stored continuously in memory 60. Controller 40 can obtain the starting storage address information and data length information of multiple configuration data (including data0-data10) corresponding to mode A, and then read the multiple configuration data corresponding to mode A from memory 60.

[0092] In this embodiment, the controller 40 can determine multiple configuration information of the second target working mode, and generate a configuration access request based on multiple register addresses and configuration data corresponding to the multiple configuration information. Among the multiple register addresses corresponding to the multiple configuration information, at least some register addresses are arranged continuously. After the configuration access request is transmitted to the decoding circuit 20 via the configuration bus 50, the decoding circuit 20 can decode the multiple register addresses included in the configuration access request and the configuration data corresponding to each register address. Since at least some register addresses are arranged continuously, the decoding circuit 20 can configure registers continuously based on the continuously arranged register addresses. Therefore, the address gap phenomenon caused by including invalid register addresses can be reduced during the batch configuration of registers via the configuration bus, and the configuration efficiency of multiple registers in any working mode can be improved.

[0093] In some optional implementations, during the process of the controller 40 transmitting a configuration access request to the decoding circuit 20 via the configuration bus 50, the controller 40 is further configured to: divide the configuration access request into multiple configuration transmission transactions based on the data channel bit width corresponding to the configuration bus and the register bit width corresponding to the register; wherein at least one configuration transmission transaction includes second register address information, the second register address information indicating that multiple register addresses are arranged consecutively; and transmit the multiple configuration transmission transactions sequentially to the decoding circuit 20 via the configuration bus 50.

[0094] Due to the limitation of the configuration bus data channel width, multiple configuration data corresponding to the second target operating mode may not be able to be transmitted to the decoding circuit 20 in one go. The controller 40 can divide the configuration access request into multiple configuration transmission transactions according to the configuration bus data channel width and the corresponding register width, and transmit the configuration access request through multiple configuration transmission transactions. The configuration transmission transaction can also be called a configuration access sub-request.

[0095] The data channel width of configuration bus 50 refers to the number of bits of configuration data that configuration bus 50 can transmit in parallel within a single clock cycle. For example, the data channel width of configuration bus can be 64 bits, 128 bits, 256 bits, etc. The register width refers to the maximum number of bits of binary data that register 101 can store. For example, the register width can be 16 bits, 32 bits, 64 bits, etc.

[0096] The controller 40 divides the configuration access request into each configuration transmission transaction, which includes partial configuration data and second register address information indicating the partial register address corresponding to each partial configuration data. The data bit width of the partial configuration data included in each configuration transmission transaction is less than or equal to the data channel bit width of the configuration bus 50.

[0097] Optionally, the data channel width of the configuration bus 50 is greater than the register width, allowing at least two configuration data corresponding to at least two register addresses to be transmitted in parallel via the configuration bus 50. At least one configuration transmission transaction includes at least two configuration data corresponding to at least two register addresses transmitted in parallel, along with the corresponding register address information.

[0098] In this embodiment, the controller 40 can divide the configuration access request into multiple configuration transmission transactions based on the data channel width corresponding to the configuration bus 50 and the register width corresponding to the register 101. This is to prevent the data width of the configuration data included in the configuration access request from exceeding the data channel width corresponding to the configuration bus, thus ensuring the normal transmission of configuration data. Furthermore, the register addresses corresponding to at least one configuration transmission transaction in the multiple configuration transmission transactions are arranged consecutively. That is, in the process of configuring multiple target registers in batches based on multiple configuration transmission transactions, multiple registers can be configured continuously, which helps to improve configuration efficiency.

[0099] After the controller 40 divides the configuration transmission transactions into multiple transactions, it sequentially sends each configuration transmission transaction to the decoding circuit 20 via the configuration bus 50. The decoding circuit 20 is further configured to: sequentially receive multiple configuration transmission transactions via the configuration bus 50, and decode the received configuration transmission transactions.

[0100] For any configuration transmission transaction, the decoding circuit 20 can decode the configuration transmission transaction to obtain the register addresses included in the configuration transmission transaction, determine the target register corresponding to the register address, and write the configuration data corresponding to the register address into the corresponding target register. Specifically, after the decoding circuit 20 obtains the register addresses included in the configuration transmission transaction, it can determine the target register corresponding to the register address according to the pre-configured address mapping relationship.

[0101] The decoding circuit 20, by decoding multiple configuration transmission transactions, can write the configuration data from multiple configuration transmission transaction repositories into their respective target registers, thus enabling the configuration of multiple target registers based on these transactions. Optionally, the decoding circuit 20 can decode at least one configuration transmission transaction to obtain second register address information, determine consecutively arranged register addresses based on this information, and write configuration data based on these consecutively arranged register addresses, thereby achieving continuous register configuration.

[0102] In this embodiment, the decoding circuit 20 can write multiple configuration data corresponding to the second target working mode into the corresponding target registers in batches based on configuration transmission transactions. In the process of configuring multiple target registers in batches based on multiple configuration transmission transactions, multiple registers can be configured continuously, which helps to improve configuration efficiency.

[0103] In some optional implementations, when the controller 40 divides the configuration access request into multiple configuration transmission transactions based on the data channel width corresponding to the configuration bus 50 and the register width corresponding to the register 101, it is further configured to divide the configuration access request into multiple configuration transmission transactions based on the data channel width and the register width, according to the rule of aggregating consecutively arranged register addresses into the same configuration transmission transaction.

[0104] The rule of aggregating consecutively arranged register addresses into the same configuration transfer transaction means that consecutively arranged register addresses corresponding to the second target operating mode are preferentially aggregated into the same configuration transfer transaction. For example, referring to the example in Table 1, if the second target operating mode is mode A, then the register addresses corresponding to the second target operating mode are 0x000-0x00A, including 0x000, 0x001, 0x002, 0x003, 0x004, 0x005, 0x006, 0x007, 0x008, 0x009, and 0x00A. Therefore, consecutively arranged register addresses 0x000-0x00A should be preferentially aggregated into the same configuration transfer transaction.

[0105] When aggregating consecutive register addresses into the same configuration transfer transaction, if the total bit width of the configuration data corresponding to multiple consecutive register addresses exceeds the data channel bit width, the consecutive register addresses can be further aggregated in batches into two or more configuration transfer transactions by combining the data channel bit width and the register bit width. Specifically, the number of consecutive addresses allowed to be aggregated in a configuration transfer transaction can be determined based on the data channel bit width and the register bit width, and then the consecutive register addresses can be aggregated in batches into two or more configuration transfer transactions based on the number of consecutive addresses.

[0106] For example, with a data channel width of 128 bits and a register width of 32 bits, the configuration bus 50 can transmit configuration data from four registers in parallel at one time. That is, a configuration transmission transaction can aggregate a maximum of 4 consecutively arranged register addresses. In units of 4, the consecutively arranged register addresses 0x000-0x00A are aggregated in 3 configuration transmission transactions. Each configuration transmission transaction includes first register address information representing the consecutive arrangement of multiple register addresses. That is, the first register address information in the first configuration transmission transaction represents consecutively arranged register addresses 0x000, 0x001, 0x002, and 0x003; the first register address information in the second configuration transmission transaction represents consecutively arranged register addresses 0x004, 0x005, 0x006, and 0x007; and the first register address information in the third configuration transmission transaction represents consecutively arranged register addresses 0x008, 0x009, and 0x00A.

[0107] In this embodiment, based on the data channel bit width and register bit width, and according to the rule of aggregating consecutively arranged register addresses into the same configuration transmission transaction, multiple consecutively arranged register addresses corresponding to the second target working mode can be aggregated in batches into multiple configuration transmission transactions, so that the multiple register addresses included in the multiple configuration transmission transactions are arranged consecutively, which helps to improve the configuration efficiency of configuring multiple registers in the second target working mode.

[0108] In some optional implementations, during the process of dividing the configuration access request into multiple configuration transmission transactions, the controller 40 is further configured to: determine a first number of configuration data carried by a single configuration transmission transaction based on the data channel bit width and the register bit width; determine the starting register address of a second number of consecutively arranged register addresses; wherein the starting register address represents the first register address in the second number of consecutively arranged register addresses; the second number is a positive integer greater than 1 and less than or equal to the first number; and generate a configuration transmission transaction based on the configuration data and the starting register address corresponding to the second number of consecutively arranged register addresses.

[0109] The first quantity refers to the maximum amount of configuration data that can be carried in a single configuration transfer transaction. For example, if the data channel width is 128 bits and the register width is 32 bits, the first quantity of configuration data carried in a single configuration transfer transaction is 4.

[0110] Optionally, the configuration transfer transaction can be a burst transaction. A configuration transfer transaction can continuously transfer a first quantity of configuration data, with the multiple register addresses corresponding to the first quantity of configuration data arranged consecutively. For the continuously transferred configuration data, the starting register address can be carried among the multiple register addresses corresponding to the continuously transferred configuration data. The starting register address can indicate the register address corresponding to each of the first quantity of configuration data in the continuous transfer.

[0111] Optionally, configuration transfer transactions can be generated in units of a second quantity less than or equal to the first quantity, with each generated transaction including the second quantity of configuration data. During the generation of configuration transfer transactions in units of the second quantity, the starting register address of the second quantity of consecutively arranged register addresses can be determined. Specifically, the starting register address of a configuration transfer transaction can be aligned with the maximum quantity carried by a single configuration transfer transaction; that is, the integer represented by the binary data corresponding to the starting register address must be divisible by the first quantity, and the integer represented by the binary data corresponding to the starting register address of the determined second quantity of consecutively arranged register addresses must be divisible by the first quantity. For example, in the above example, with a data channel width of 128 bits and a register width of 32 bits, the integer represented by the binary data corresponding to the starting register address must be divisible by 4.

[0112] Optionally, to reduce the number of configuration data transmissions for a working mode, it can be preset that the integer represented by the binary data corresponding to the starting register address among multiple consecutive register addresses corresponding to a working mode is divisible by a first quantity. For example, combined with Figure 1 For example, when the first quantity is 4, after configuring the addresses of the dedicated registers arranged consecutively for the dedicated registers corresponding to mode A, the last register address is 0x00A, and the next register address is 0x00B. The integer represented by 0x00B is 11, which is not divisible by 4. To improve the efficiency of register configuration in working mode B, the register address corresponding to the next integer divisible by 4 after 0x00B can be used as the starting register address of the consecutive register addresses of the dedicated registers corresponding to mode B. For example, the integer represented by 0x00C is 12, which is divisible by 4, so 0x00C can be used as the starting register address of the consecutive register addresses of the dedicated registers corresponding to mode B.

[0113] After determining the starting register address of the second number of consecutively arranged register addresses, a configuration transfer transaction can be generated based on the starting register address and the corresponding configuration data.

[0114] In one example, the second quantity equals the first quantity, which is the maximum amount of configuration data transferred per configuration transfer transaction. Combined Figure 1 As shown, with a first quantity of 4 and a second target working mode of Mode A, the starting register addresses for each configuration transfer transaction can be determined as 0x000, 0x004, and 0x008, respectively. That is, the configuration access request can be divided into three configuration transfer transactions: a first configuration transfer transaction, a second configuration transfer transaction, and a third configuration transfer transaction. The first configuration transfer transaction includes the starting register address 0x000 and the configuration data corresponding to each register address from 0x000 to 0x003. The second configuration transfer transaction includes the starting register address 0x004 and the configuration data corresponding to each register address from 0x004 to 0x007. The third configuration transfer transaction includes the starting register address 0x008 and the configuration data corresponding to each register address from 0x008 to 0x00A.

[0115] In this embodiment, the controller 40 determines the first quantity of configuration data that a configuration transmission transaction can carry based on the data channel bit width and the register bit width, and generates each configuration transmission transaction based on the first quantity. Thus, when multiple register addresses that are continuously arranged according to the second target working mode are aggregated in batches into multiple configuration transmission transactions, abnormal transmission problems caused by the configuration data allocated to each configuration transmission transaction exceeding the first quantity can be avoided, ensuring the normal transmission of configuration data.

[0116] In addition, by indicating the starting register address, the configuration transfer transaction corresponds to multiple consecutively arranged register addresses, so that multiple configuration data corresponding to these consecutively arranged register addresses can be transferred through the same configuration transfer transaction, thereby reducing the number of configuration transactions, reducing bus handshake overhead, and helping to improve register configuration efficiency.

[0117] Optionally, the decoding circuit 20 can be further configured to: decode the configuration transmission transaction to obtain the starting register address included in the configuration transmission transaction; and determine the addresses of a second number of consecutively arranged registers based on the starting register address.

[0118] Optionally, the decoding circuit 20 decodes the configuration transmission transaction to obtain the starting register address included in the configuration transmission transaction. Then, based on the starting register address and the first quantity of configuration data carried by the configuration transmission transaction, it determines the addresses of multiple consecutively arranged registers. The decoding circuit 20 can determine the first quantity based on the data channel bit width and the register bit width. For example, if the starting register address is determined to be 0x000, and the first quantity is determined to be 4, then the addresses of the multiple consecutively arranged registers are determined to be 0x000-0x003.

[0119] In the configuration transmission transaction generated by controller 40, there may be cases where the first quantity of configuration data is not transmitted. Optionally, controller 40 can determine the register addresses that do not need to be written from the first quantity of consecutively arranged register addresses based on the configuration data and the starting register address, and mark them with the Storbe signal, i.e., the configuration transmission transaction carries the Storbe signal. For example, referring to the above example, the third configuration transmission transaction includes the starting register address 0x008. The first quantity of consecutive register addresses determined based on the starting register address 0x008 is 0x008-0x00B. The configuration data included in the third configuration transmission transaction is the configuration data corresponding to each register address in 0x008-0x00A. 0x00B needs to be marked as an invalid register address by the Storbe signal, and no data needs to be written. For example, when the first quantity is 4, the Storbe signal can indicate whether each register address is valid through 4 bits of data.

[0120] When decoding a configuration transmission transaction, the decoding circuit 20 determines a first number of consecutively arranged register addresses based on the starting register address, and then determines the valid addresses among the first number of consecutively arranged register addresses based on the Storbe signal included in the configuration transmission transaction, thus obtaining a second number of register addresses. For example, in conjunction with the above example, after decoding the third configuration transmission transaction, the decoding circuit 20 can obtain consecutive register addresses 0x008-0x00B, and determine 0x00B as an invalid address and 0x008-0x00A as a valid address based on the Storbe signal. The first three 32-bit configuration data in the 128-bit data width of the data channel can be written into the register addresses corresponding to 0x008-0x00A respectively.

[0121] In this embodiment, the decoding circuit 20 decodes the configuration transmission transaction to obtain the starting register address. Based on the starting register address, the addresses of multiple consecutively arranged registers can be determined, and the registers can be configured consecutively, thereby improving the register configuration efficiency.

[0122] In some alternative implementations, the controller 40 is further configured to: Multiple configuration information is determined based on the second target working mode; Obtain the addresses of dedicated registers and the first configuration data corresponding to each first configuration information in multiple configuration information, and / or obtain the addresses of shared registers and the second configuration data corresponding to each second configuration information in multiple configuration information; According to the rule of aggregating register addresses that are at least partially consecutive among multiple dedicated register addresses into the same configuration transfer transaction, generate dedicated register address sub-information, and / or, according to the rule of aggregating shared register addresses that are at least partially consecutive among multiple shared register addresses into the same configuration transfer transaction, generate shared register address sub-information; A configuration access request is generated based on the dedicated register address sub-information and the first configuration data corresponding to each dedicated register address, and / or based on the shared register address sub-information and the second configuration data corresponding to each shared register address; The configuration access request is transmitted to the decoding circuit 20 via the configuration bus 50.

[0123] Optionally, a configuration access request can be divided into a configuration transfer transaction for configuring special-purpose register 1011 and / or a configuration transfer transaction for configuring shared register 1013. The configuration transfer transaction for configuring special-purpose register 1011 can be used for consecutive configuration of multiple target special-purpose registers. The configuration access transaction for configuring shared register 1013 can be used for consecutive configuration of multiple target shared registers.

[0124] Specifically, the configuration information determined by the controller 40 based on the second target operating mode includes first configuration information and / or second configuration information. The first configuration information is dedicated configuration information that needs to be configured in some operating modes, and the second configuration information is shared configuration information that needs to be configured in all operating modes.

[0125] For the first configuration information, the controller 40 can obtain the dedicated register address of each first configuration information based on the address mapping relationship, and read the first configuration data corresponding to each first configuration information from the memory 60. For the second configuration information, the controller 40 can obtain the shared register address of each second configuration information based on the address mapping relationship, and read the second configuration data corresponding to each second configuration information from the memory 60.

[0126] Optionally, among the dedicated register addresses corresponding to each of the first configuration information, there are consecutive dedicated register addresses. The controller 40 can generate dedicated register address sub-information according to the rule of aggregating at least some consecutively arranged register addresses into the same configuration transmission transaction. The dedicated register address sub-information can be information used in the configuration transmission transaction to indicate consecutively arranged dedicated register addresses. During this process, the controller 40 can generate dedicated register address sub-information based on the data channel bit width and register bit width, according to the rule of aggregating at least some consecutively arranged register addresses into the same configuration transmission transaction. After generating each dedicated register address sub-information, the controller 40 can determine the corresponding first configuration data based on the consecutively arranged dedicated register addresses indicated by each dedicated register address sub-information, and generate multiple configuration transmission transactions for configuring dedicated registers based on each dedicated register address sub-information and its corresponding first configuration data.

[0127] The shared register addresses corresponding to each of the second configuration information are arranged consecutively. The controller 40 can generate shared register address sub-information according to the rule of aggregating at least some consecutively arranged register addresses into the same configuration transfer transaction. The shared register address sub-information can be information used in the configuration transfer transaction to indicate the consecutively arranged shared register addresses. During this process, the controller 40 can generate shared register address sub-information based on the data channel bit width and register bit width, according to the rule of aggregating at least some consecutively arranged register addresses into the same configuration transfer transaction. After generating each shared register address sub-information, the controller 40 can determine the second configuration data corresponding to each of the consecutively arranged shared register addresses indicated by each shared register address sub-information, and generate one or more configuration transfer transactions for configuring the shared registers based on each shared register address sub-information and the corresponding second configuration data.

[0128] The controller 40 can generate a configuration access request based on multiple configuration transfer transactions for configuring dedicated registers and / or multiple configuration transfer transactions for configuring shared registers. Specific implementation methods for generating multiple configuration transfer transactions for configuring dedicated registers and multiple configuration transfer transactions for configuring shared registers can be found in the above embodiments and will not be repeated here.

[0129] In some optional implementations, when the configuration information includes first configuration information and second configuration information, if the multiple dedicated register addresses corresponding to the first configuration information and the multiple shared register addresses corresponding to the second configuration information are consecutive, the multiple dedicated register addresses and the multiple shared register addresses can be combined into a total of multiple consecutively arranged register addresses. Based on the data channel bit width and register bit width, register address sub-information corresponding to each configuration transmission transaction is generated by aggregating the multiple consecutively arranged register addresses into the same configuration transmission transaction according to the rules.

[0130] Referring to the example in Table 1, when the second target operating mode is mode A, since the addresses of multiple dedicated registers and multiple shared registers in mode A are consecutive, register address sub-information corresponding to each configuration transfer transaction can be generated based on the consecutive register addresses (0x000-0x00A) formed by the multiple dedicated register addresses and multiple shared register addresses. In conjunction with the method described in the above embodiments, the register address sub-information can be a starting register address, including 0x000, 0x004, and 0x008. Then, the configuration data corresponding to each register address sub-information is determined, generating multiple configuration transfer transactions for configuring multiple shared registers and multiple dedicated registers.

[0131] In some optional implementations, if the addresses of multiple dedicated registers corresponding to the first configuration information and the addresses of multiple shared registers corresponding to the second configuration information are not consecutive, a configuration transfer transaction for configuring multiple dedicated registers can be generated based on the addresses of multiple dedicated registers corresponding to the first configuration information and the corresponding first configuration data, and a configuration transfer transaction for configuring multiple shared registers can be generated based on the addresses of multiple shared registers corresponding to the second configuration information and the corresponding second configuration data.

[0132] Referring to the example in Table 1, when the second target operating mode is mode B, since the addresses of multiple dedicated registers and multiple shared registers of mode B are not contiguous, configuration transfer transactions for configuring mode B dedicated registers and configuration transfer transactions for configuring shared registers need to be generated separately. Specifically, for the multiple dedicated register addresses corresponding to mode B, in accordance with the method described in the above embodiments, the dedicated register address sub-information can be the starting register address. When the first quantity is 4, the determined dedicated register address sub-information is 0x00C, indicating that the consecutively arranged multiple dedicated register addresses are 0x00C-0x00F. Based on the first configuration data corresponding to each dedicated register address, a configuration transfer transaction for configuring mode B dedicated registers is generated. For multiple shared register addresses (0x000-0x005), in accordance with the method in the above embodiments, the shared register address sub-information can be the starting register address. When the first quantity is 4, the determined shared register address sub-information is 0x000, 0x004, and 0x000 is used to indicate multiple consecutively arranged shared register addresses 0x000-0x003. Combined with the second configuration data corresponding to each address in the multiple shared register addresses 0x000-0x003, a configuration transmission transaction is generated. 0x004 is used to indicate multiple consecutive addresses 0x004-0x007, where addresses 0x004-0x005 are shared register addresses, and addresses 0x006-0x007 are invalid. The configuration data corresponding to addresses 0x004-0x005 can be combined to generate a corresponding configuration transfer transaction. The Storbe signal carried in the configuration transfer transaction can indicate that the last two register addresses out of the four consecutive register addresses are invalid (i.e., indicating that addresses 0x006-0x007 are invalid). The second configuration data included in this configuration transfer transaction is the configuration data corresponding to addresses 0x004-0x005.

[0133] In this embodiment, the controller 40 can determine the corresponding multiple dedicated register addresses and first configuration data based on the first configuration information among the multiple configuration information of the second target working mode, and / or determine the corresponding multiple shared register addresses and second configuration data based on the second configuration information. Specifically, for the multiple dedicated register addresses corresponding to the multiple dedicated registers and / or the multiple shared register addresses corresponding to the multiple shared register addresses, a corresponding configuration transmission transaction is generated according to the rule of aggregating consecutively arranged register addresses into the same configuration transmission transaction. This allows multiple first configuration data corresponding to consecutively arranged dedicated register addresses to be transmitted through a single configuration transmission transaction, and / or multiple second configuration data corresponding to consecutively arranged shared register addresses to be transmitted through a single configuration transmission transaction. This helps reduce the number of configuration transactions, thereby reducing bus handshake overhead and improving register configuration efficiency.

[0134] The decoding circuit 20 can configure registers continuously based on the consecutively arranged addresses of dedicated registers and / or shared registers. This reduces address gaps caused by including invalid register addresses during batch configuration of registers via the configuration bus and improves the configuration efficiency of multiple dedicated registers and / or shared registers in any operating mode.

[0135] Exemplary methods This disclosure also provides a register configuration method. Figure 6 This is a flowchart illustrating a register configuration method provided by some exemplary embodiments of this disclosure. For example... Figure 6 As shown, the method includes the following steps: S610 receives configuration access requests via a decoding circuit.

[0136] S620 decodes the configuration access request through a decoding circuit and determines multiple target registers in the register group based on the register address sequence included in the decoded configuration access request.

[0137] The registers in the register group are used to store configuration data for configuring the execution circuitry based on the operating mode.

[0138] S630 uses a decoding circuit to write multiple configuration data, which correspond to multiple register addresses in the register address sequence included in the configuration access request, into multiple target registers respectively.

[0139] The register address sequence includes at least a portion of the register addresses arranged consecutively.

[0140] In some optional implementations, the registers include dedicated registers and shared registers, and the register address includes the dedicated register address corresponding to the dedicated register and the shared register address corresponding to the shared register; the dedicated registers represent registers allocated to a portion of the multiple operating modes for configuration data storage; the shared registers represent registers allocated to all of the multiple operating modes for configuration data storage.

[0141] exist Figure 6 Based on the embodiments, such as Figure 7 As shown, step S620 above includes: S710 decodes the configuration access request through a decoding circuit, and determines multiple target special-purpose registers and / or multiple target shared registers based on the multiple dedicated register addresses and / or multiple shared register addresses arranged consecutively in the register address sequence included in the decoded configuration access request.

[0142] The above step S630 includes: S720 writes first configuration data corresponding to multiple shared register addresses into multiple target shared registers, and / or writes multiple second configuration data corresponding to multiple consecutively arranged special purpose register addresses into multiple target special purpose registers.

[0143] The configuration data includes first configuration data and / or second configuration data.

[0144] In some alternative implementations, multiple target dedicated registers and / or multiple target shared registers are registers that are written to the execution circuitry in the same operating mode.

[0145] In some alternative implementations, in Figure 6 Based on the embodiments, such as Figure 8 As shown, step S620 above includes: The S810 decodes the configuration access request based on a pre-configured address mapping relationship through a decoding circuit, and determines the register address sequence included in the decoded configuration access request.

[0146] The S820 uses a decoding circuit to determine multiple target registers corresponding to multiple register addresses based on multiple register addresses in a register address sequence.

[0147] The address mapping relationship represents the correspondence between register addresses and corresponding registers.

[0148] In some alternative implementations, the registers include special purpose registers, and the register addresses include the special purpose register addresses corresponding to the special purpose registers; the address mapping relationship includes the correspondence between the same special purpose register and at least two different special purpose register addresses.

[0149] In some alternative implementations, at least two different dedicated register addresses corresponding to the same dedicated register are respectively assigned to at least two different operating modes, so that in a first target operating mode among the at least two different operating modes, at least a portion of the dedicated register addresses corresponding to the first target operating mode are arranged consecutively.

[0150] In some optional implementations, the working modes include at least one of pooling mode, convolution mode, activation mode, splicing mode, pruning mode, and data dicing mode.

[0151] In some alternative implementations, the configuration data includes at least one of the following: interrupt enable signal, input address parameter, output address parameter, input size parameter, output size parameter, constant, padding parameter, kernel size parameter, activation type parameter, and shared configuration parameter.

[0152] In some alternative implementations, such as Figure 9 As shown, the register configuration method also includes the following steps: The S910 determines multiple configuration information based on the second target operating mode through the controller.

[0153] The S920 obtains the register addresses and configuration data corresponding to each configuration information through the controller.

[0154] S930 generates first register address information based on the register addresses corresponding to each configuration information, using the controller. The first register address information indicates that at least a portion of the register addresses are arranged consecutively. S940 generates a configuration access request based on the first register address information and the configuration data corresponding to each register address.

[0155] The S950 transmits configuration access requests to the decoding circuit via the configuration bus through the controller.

[0156] In some alternative implementations, such as Figure 10 As shown, step S950 above includes the following steps: S1010 divides configuration access requests into multiple configuration transmission transactions based on the data channel width corresponding to the configuration bus and the register width corresponding to the register.

[0157] In one of the configuration transmission transactions, at least one second register address information is included, which indicates that multiple register addresses are arranged consecutively.

[0158] S1020 transmits multiple configuration transfer transactions sequentially to the decoding circuit via the configuration bus through the controller.

[0159] In some optional implementations, after step S1020, the decoding circuit sequentially receives multiple configuration transmission transactions through the configuration bus and decodes the received configuration transmission transactions.

[0160] In some optional implementations, step S1010 may include the following steps: S1010a divides configuration access requests into multiple configuration transmission transactions based on the data channel bit width and register bit width, according to the rule of aggregating consecutively arranged register addresses into the same configuration transmission transaction.

[0161] In some alternative implementations, such as Figure 11 As shown, step S1010a above includes the following steps: S1110 determines the first quantity of configuration data carried by a single configuration transmission transaction based on the data channel bit width and register bit width by the controller.

[0162] S1120, the controller determines the starting register address of the second number of consecutively arranged register addresses. The starting register address represents the first register address in the second number of consecutively arranged register addresses, and the second number is a positive integer greater than 1 and less than or equal to the first number.

[0163] S1130 generates a configuration transfer transaction based on the configuration data and the starting register address corresponding to the second number of consecutively arranged register addresses.

[0164] In some alternative implementations, such as Figure 12 As shown, the above-mentioned decoding of the received configuration transmission transaction via the decoding circuit includes the following steps: S1210 decodes the configuration transmission transaction through the decoding circuit to obtain the starting register address included in the configuration transmission transaction.

[0165] S1220 determines the addresses of the second number of consecutively arranged registers based on the starting register address using the decoding circuit.

[0166] In some alternative implementations, such as Figure 13 As shown, the register configuration method also includes the following steps: S1310 determines multiple configuration information based on the second target operating mode through the controller.

[0167] S1320: Obtain the address of each dedicated register and the first configuration data corresponding to each first configuration information in the multiple configuration information through the controller, and / or obtain the address of each shared register and the second configuration data corresponding to each second configuration information in the multiple configuration information.

[0168] S1330 generates dedicated register address sub-information according to the rule that register addresses arranged in at least some consecutive arrangement among multiple dedicated register addresses are aggregated into the same configuration transfer transaction by the controller, and / or generates shared register address sub-information according to the rule that shared register addresses arranged in at least some consecutive arrangement among multiple shared register addresses are aggregated into the same configuration transfer transaction.

[0169] S1340, the controller generates a configuration access request based on the dedicated register address sub-information and the first configuration data corresponding to each dedicated register address, and / or based on the shared register address sub-information and the second configuration data corresponding to each shared register address.

[0170] The S1350 transmits configuration access requests to the decoding circuit via the configuration bus through the controller.

[0171] It should be noted that the register configuration device and register configuration method of the embodiments of this disclosure correspond to each other in terms of technical implementation and implementation method, and can be referenced and cited in the content of the embodiments; the register configuration device and register configuration method of the embodiments of this disclosure also correspond to each other in terms of technical effect, and can also refer to the relevant records of the corresponding technical effect. In order to reduce redundancy, they will not be repeated here.

[0172] Exemplary neural network processor This disclosure also provides a neural network processor, which may include: the register configuration device provided in any of the above embodiments.

[0173] Exemplary electronic devices Figure 14 A structural diagram of an electronic device provided in an embodiment of this disclosure includes at least one processor 1410 and a memory 1420.

[0174] The processor 1410 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0175] The memory 1420 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1410 may execute one or more computer program instructions to implement the register configuration methods and / or other desired functions of the various embodiments of this disclosure described above.

[0176] In one example, the electronic device may also include an input device 1430 and an output device 1440, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0177] The input device 1430 may also include, for example, a keyboard, a mouse, etc.

[0178] The output device 1440 can output various information to the outside, including, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0179] Of course, for the sake of simplicity, Figure 14 Only some of the components of the electronic device relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device may include any other suitable components depending on the specific application.

[0180] Exemplary computer program products and computer-readable storage media In addition to the methods and apparatus described above, embodiments of this disclosure may also provide a computer program product, including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the register configuration methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0181] Computer program products can be written in any combination of one or more programming languages ​​to perform the operations of embodiments of this disclosure. These programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0182] Furthermore, embodiments of this disclosure may also be computer-readable storage media storing computer program instructions that, when executed by a processor, cause the processor to perform the steps of the register configuration methods of the various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0183] Computer-readable storage media may take the form of any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may include, but is not limited to, systems, apparatuses, or devices that are electrical, magnetic, optical, electromagnetic, infrared, or semiconductor, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0184] The basic principles of this disclosure have been described above with reference to specific embodiments. However, the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0185] Various modifications and variations can be made to this disclosure without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, this disclosure is also intended to include such modifications and variations.

Claims

1. A register configuration device, comprising: Register group, wherein the registers in the register group are configured as follows: Store configuration data for configuring the execution circuitry based on the operating mode; The decoding circuit is configured as follows: Receive configuration access requests; The configuration access request is decoded, and multiple target registers in the register group are determined based on the register address sequence included in the decoded configuration access request. The configuration data included in the configuration access request, corresponding to multiple register addresses in the register address sequence, are written into multiple target registers respectively; wherein, at least a portion of the multiple register addresses included in the register address sequence are arranged consecutively.

2. The apparatus according to claim 1, wherein, The registers include dedicated registers and shared registers. The register addresses include dedicated register addresses corresponding to the dedicated registers and shared register addresses corresponding to the shared registers. The dedicated registers represent registers allocated to a portion of the multiple operating modes for storing the configuration data. The shared registers represent registers allocated to all of the multiple operating modes for storing the configuration data. The decoding circuit is further configured as follows: The configuration access request is decoded, and multiple target dedicated registers and / or multiple target shared registers are determined based on the multiple dedicated register addresses and / or multiple shared register addresses that are consecutively arranged in the register address sequence included in the decoded configuration access request. First configuration data corresponding to the addresses of the multiple shared registers are written to the multiple target shared registers respectively, and / or, second configuration data corresponding to the addresses of the multiple consecutively arranged dedicated registers are written to the multiple target dedicated registers respectively; wherein, the configuration data includes first configuration data and / or second configuration data.

3. The apparatus according to claim 2, wherein, The multiple target dedicated registers and / or multiple target shared registers are registers that are written to the execution circuitry in the same operating mode.

4. The apparatus according to claim 1, wherein, The decoding circuit is further configured as follows: The configuration access request is decoded based on a pre-configured address mapping relationship to determine the register address sequence included in the decoded configuration access request; Based on the multiple register addresses in the register address sequence, a plurality of target registers corresponding to the multiple register addresses are determined; wherein, the address mapping relationship represents the correspondence between the register address and the corresponding register.

5. The apparatus according to claim 4, wherein, The register includes a special purpose register, and the register address includes the special purpose register address corresponding to the special purpose register; the address mapping relationship includes the correspondence between the same special purpose register and at least two different special purpose register addresses.

6. The apparatus according to claim 5, wherein, At least two different dedicated register addresses corresponding to the same dedicated register are respectively assigned to at least two different operating modes, so that in a first target operating mode among the at least two different operating modes, at least a portion of the dedicated register addresses corresponding to the first target operating mode are arranged consecutively.

7. The apparatus according to claim 1, wherein, The working modes include at least one of the following: pooling mode, convolution mode, activation mode, splicing mode, pruning mode, and data slicing mode.

8. The apparatus according to claim 1, wherein, The configuration data includes at least one of the following: interrupt enable signal, input address parameters, output address parameters, input size parameters, output size parameters, constants, padding parameters, convolution kernel size parameters, activation type parameters, and shared configuration parameters.

9. The apparatus according to any one of claims 1 to 8, wherein, The register configuration device further includes a controller, which is configured to: Multiple configuration information is determined based on the second target working mode; Obtain the register address and configuration data corresponding to each of the configuration information; Based on the register addresses corresponding to each of the configuration information, a first register address information is generated; wherein, the first register address information represents at least a portion of the register addresses being arranged consecutively. Based on the first register address information and the configuration data corresponding to each register address, the configuration access request is generated; The configuration access request is transmitted to the decoding circuit via the configuration bus.

10. The apparatus according to claim 9, wherein, The controller is further configured to: Based on the data channel width corresponding to the configuration bus and the register width corresponding to the register, the configuration access request is divided into multiple configuration transmission transactions; wherein, at least one of the configuration transmission transactions includes second register address information, and the second register address information indicates that multiple register addresses are arranged consecutively; Multiple configuration transfer transactions are sequentially transmitted to the decoding circuit via the configuration bus.

11. The apparatus according to claim 10, wherein, The decoding circuit is further configured as follows: Multiple configuration transmission transactions are received sequentially through the configuration bus; The received configuration transmission transaction is decoded.

12. The apparatus according to claim 11, wherein, The controller is further configured to: Based on the data channel bit width and the register bit width, and according to the rule of aggregating consecutively arranged register addresses into the same configuration transmission transaction, the configuration access request is divided into multiple configuration transmission transactions.

13. The apparatus according to claim 12, wherein, The controller is further configured to: Based on the data channel bit width and the register bit width, determine a first quantity of the configuration data carried by a single configuration transmission transaction; Determine the starting register address of a second number of consecutively arranged register addresses, wherein the starting register address represents the first register address in the second number of consecutively arranged register addresses; the second number is a positive integer greater than 1 and less than or equal to the first number; The configuration transfer transaction is generated based on the configuration data corresponding to the second number of consecutively arranged register addresses and the starting register address.

14. The apparatus according to claim 13, wherein, The decoding circuit is further configured as follows: The configuration transmission transaction is decoded to obtain the starting register address included in the configuration transmission transaction; Based on the starting register address, determine the addresses of the second number of consecutively arranged registers.

15. The apparatus according to any one of claims 9 to 14, wherein, The controller is further configured to: Multiple configuration information is determined based on the second target working mode; Obtain the addresses of dedicated registers and the first configuration data corresponding to each first configuration information in the plurality of configuration information, and / or obtain the addresses of shared registers and the second configuration data corresponding to each second configuration information in the plurality of configuration information; Special register address sub-information is generated according to the rule that register addresses arranged in at least a partial consecutive arrangement among multiple special register addresses are aggregated into the same configuration transport transaction, and / or shared register address sub-information is generated according to the rule that shared register addresses arranged in at least a partial consecutive arrangement among multiple shared register addresses are aggregated into the same configuration transport transaction; Based on the dedicated register address sub-information and the first configuration data corresponding to each dedicated register address, and / or based on the shared register address sub-information and the second configuration data corresponding to each shared register address, the configuration access request is generated; The configuration access request is transmitted to the decoding circuit via the configuration bus.

16. A register configuration method, comprising: Receive configuration access requests via decoding circuitry; The configuration access request is decoded by the decoding circuit. Based on the register address sequence included in the decoded configuration access request, multiple target registers in the register group are determined. The registers in the register group are used to store configuration data for configuring the execution circuit based on the working mode. The decoding circuit writes the configuration data, which corresponds to multiple register addresses in the register address sequence, into multiple target registers, respectively, as included in the configuration access request; wherein at least a portion of the register addresses in the register address sequence are arranged consecutively.

17. A computer-readable storage medium storing a computer program, which, when executed, implements the register configuration method of claim 16.

18. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the register configuration method of claim 16.

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