A method for RISC-V machine clock degradation processing, a processor, a medium and an equipment
Patent Information
- Application Number
- CN202610964846.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-30
- Publication Date
- 2026-09-25
AI Technical Summary
用以解决上述背景技术中提出的定时器中断处理权限与操作系统运行权限不匹配、早期RISC-V处理器缺乏中断委托机制导致操作系统无法直接响应定时器中断、以及异常处理过程中上下文保存不完整的技术问题
一种RISC-V机器时钟降级处理方法，通过步骤A至步骤E的完整流程设计，形成了机器模式中断响应、中断状态降级传递—监管者模式中断触发—定时器重装请求、系统服务与循环建立的协作闭环。该方法无需依赖硬件中断委托机制，即可实现定时器中断从机器模式到监管者模式的可靠传递，同时与操作系统的调度循环有机衔接，解决了中断处理权限与操作系统运行权限不匹配的技术问题，显著提高了系统的兼容性和时钟中断处理的整体效率。
Smart Images
Figure CN122816799A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of computer architecture technology, and specifically relates to a RISC-V machine clock degradation processing method, processor, medium and device. Background Technology
[0002] In the RISC-V architecture, timer interrupts are a fundamental mechanism for the operating system to implement core functions such as task scheduling and time management. However, existing RISC-V architectures default to hardware-level direct reporting of timer interrupts to the highest privilege machine mode, while mainstream operating systems typically run in supervisor mode, resulting in a mismatch between interrupt handling permissions and operating system execution permissions. Although some processors provide interrupt delegation mechanisms, these mechanisms rely on hardware implementation, and different vendors implement them differently. Some early RISC-V versions even completely do not support timer interrupt delegation.
[0003] In the absence of hardware delegation support, existing technologies use pure software simulation to achieve cross-mode transmission of timer interrupts, but this has the following problems: First, the temporary storage area of the supervisor mode may be modified during the exception entry period, resulting in incomplete context saving and affecting system stability; Second, frequent mode switching and register operations increase system overhead and processing latency; Third, existing methods lack effective connection with the operating system scheduling loop, making it difficult to form a stable clock interrupt handling closed loop.
[0004] Therefore, how to achieve efficient and reliable transmission of timer interrupts from machine mode to supervisor mode without relying on hardware interrupt delegation mechanisms, and how to organically connect it with the operating system scheduling loop, is a technical problem that urgently needs to be solved in this field. Summary of the Invention
[0005] The purpose of this application is to provide a RISC-V machine clock degradation processing method, processor, medium, and device. This addresses the technical problems mentioned in the background art, such as the mismatch between timer interrupt handling permissions and operating system execution permissions, the lack of interrupt delegation mechanisms in early RISC-V processors leading to the operating system's inability to directly respond to timer interrupts, and incomplete context saving during exception handling.
[0006] To achieve the above objectives, this application adopts the following technical solution: In a first aspect, this application provides a method for degrading the machine clock on a RISC-V processor platform, comprising the following steps: Step A: After the timer generates an interrupt, it reports to the machine mode. In machine mode, the timer interrupt signal is received and responded to, and the machine mode timer interrupt handler is executed. Step B: In the machine mode timer interrupt handler, the timer interrupt wait state in machine mode is cleared through an atomic register write operation sequence, and the timer interrupt wait state in supervisor mode is set at the same time, thus completing the downgraded transmission of the interrupt event from machine mode to supervisor mode. Step C: Return from machine mode to supervisor mode via software exception return instruction. Since the timer interrupt wait state of supervisor mode has been set, the processor automatically triggers and executes the supervisor mode timer interrupt service routine. Step D: In the timer interrupt service routine in the supervisor mode, the system re-enters machine mode by making a privilege escalation call from supervisor mode to machine mode. In machine mode, the timer comparison value is reset and the next timer interrupt is configured. Then, the system returns to supervisor mode. Step E: Continue executing the timer interrupt service routine in the supervisor mode, including updating the system time counter and performing system scheduling processing, and finally execute the supervisor mode interrupt return to complete this clock interrupt processing cycle.
[0007] In one possible implementation, the atomic register write operation sequence in step B includes: Clear the timer interrupt enable bit in the machine mode interrupt enable register; The timer interrupt wait bit in the machine mode interrupt wait register is cleared by performing a write operation on the timer compare register. Set the supervisor timer interrupt enable bit in the machine mode interrupt enable register; Set the supervisor timer interrupt wait bit in the machine mode interrupt wait register.
[0008] In one possible implementation, the software exception return instruction in step C is a machine mode exception return instruction, which causes the processor to recover the program address from the machine mode exception program counter register and restore the previous privilege level to supervisor mode according to the machine mode status register.
[0009] In one possible implementation, resetting the timer comparison value in step D further includes: Get the current cycle count of the processor core since startup; The target number of cycles for the next interrupt trigger point is obtained by adding a preset time interval value to the current cycle count. Write the target number of cycles into the memory-mapped machine-mode timer compare register.
[0010] In one possible implementation, step B, before clearing the timer interrupt wait state in machine mode, further includes: The machine mode timer interrupt is temporarily disabled by a write operation to prevent additional interrupt interference during state transitions.
[0011] In one possible implementation, the method does not rely on the interrupt delegation mechanism of the RISC-V architecture and is applicable to RISC-V processor platforms that do not support timer interrupt delegation or where the interrupt delegation mechanism is unavailable.
[0012] In one possible implementation, when the supervisor mode timer interrupt service routine is executed, it first disables the current clock interrupt source and clears the supervisor mode timer interrupt wait state to avoid repeatedly triggering the interrupt before the timer reload is complete.
[0013] Secondly, this application also protects a RISC-V processor configured to perform the RISC-V processor platform machine clock degradation processing method described in any of the first aspects above.
[0014] Thirdly, this application also protects a computer-readable storage medium having a computer program stored thereon, which, when executed by a RISC-V processor, implements the RISC-V processor platform machine clock degradation processing method described in any of the first aspects above.
[0015] Fourthly, this application also protects an electronic device, comprising: A RISC-V processor that supports machine mode and regulator mode; A timer, connected to the RISC-V processor, is used to generate timer interrupts; The memory, connected to the RISC-V processor, stores the operating system kernel and machine-mode firmware. The RISC-V processor is configured to execute the machine-mode firmware and operating system kernel to implement the RISC-V processor platform machine clock degradation processing method described in any of the first aspects above.
[0016] Compared with the prior art, this application has the following beneficial effects: A RISC-V machine clock degradation handling method, through a complete process design from steps A to E, forms a collaborative closed loop of machine mode interrupt response, interrupt status degradation propagation, supervisor mode interrupt triggering, timer reload request, and system service and loop establishment. This method achieves reliable propagation of timer interrupts from machine mode to supervisor mode without relying on hardware interrupt delegation mechanisms. Simultaneously, it organically integrates with the operating system's scheduling loop, resolving the technical problem of mismatch between interrupt handling permissions and operating system execution permissions, significantly improving system compatibility and overall clock interrupt handling efficiency.
[0017] In one possible implementation, the specific content of the atomic register write operation sequence is further defined, including clearing the machine mode timer interrupt enable bit, writing to the compare register to clear the interrupt wait bit, and setting the supervisor timer interrupt enable bit and the interrupt wait bit. This operation sequence ensures the integrity and atomicity of the interrupt state transition from machine mode to supervisor mode, avoiding data inconsistency or interrupt loss during the state transition process, and providing a low-level hardware operation layer technical guarantee for the reliable degradation propagation of interrupt events.
[0018] In one possible implementation, the privilege switch from machine mode to supervisor mode is achieved through a machine mode exception return instruction (mret). This instruction restores the program address from the machine mode exception program counter register and restores the previous privilege level according to the machine mode status register. This technique utilizes the standard exception return mechanism of the RISC-V architecture to trigger a supervisor mode timer interrupt, avoiding unreliable access to the supervisor mode temporary storage area during exception entry, ensuring the integrity of the saved context, and thus significantly improving the stability of the system during interrupt handling.
[0019] In one possible implementation, the method for resetting the timer comparison value is further defined, including obtaining the current cycle count, adding a preset time interval to obtain the target cycle number, and writing it to the timer comparison register. This technical solution enables dynamic configurability of the timer interrupt cycle, allowing the operating system to flexibly adjust the frequency of the clock interrupt according to actual needs, providing a precise time base for multi-task scheduling, while ensuring the accuracy and reliability of the timer reload operation.
[0020] In one possible implementation, the machine-mode timer interrupt is temporarily disabled via a write operation before clearing the machine-mode timer interrupt wait state. This technique effectively prevents state confusion or repeated triggering caused by additional interrupt interference during interrupt state transitions, ensuring the smooth execution of the atomic register operation sequence and further enhancing the robustness and reliability of the interrupt degradation process.
[0021] In one possible implementation, the method is explicitly defined as not relying on the interrupt delegation mechanism of the RISC-V architecture, and is applicable to RISC-V processor platforms that do not support timer interrupt delegation or whose interrupt delegation mechanism is unavailable. This technical solution solves the compatibility problem of early RISC-V processors, which lacked hardware delegation support and could not allow the operating system to directly respond to timer interrupts. This makes the invention widely applicable to different versions and implementations of RISC-V processors, exhibiting broad applicability and portability.
[0022] In one possible implementation, when the timer interrupt service routine in supervisor mode is executed, the current clock interrupt source is first disabled, and the supervisor mode timer interrupt wait state is cleared. This technique avoids the problem of repeated triggering caused by the interrupt wait state not being cleared before the timer reload is complete, ensuring that each timer interrupt cycle triggers only one valid service process, thus improving the accuracy of interrupt handling and the efficiency of system resource utilization.
[0023] A RISC-V processor is configured to perform the method described in the first aspect. Through hardware and firmware collaboration, this processor achieves reliable degradation and periodic processing of timer interrupts from machine mode to supervisor mode without requiring additional hardware interrupt delegation mechanisms. This provides stable and efficient clock interrupt support for running mainstream operating systems and offers advantages such as simple structure and strong compatibility.
[0024] A computer-readable storage medium storing a computer program thereon, which, when executed by a RISC-V processor, implements the method described in the first aspect. This storage medium can be programmed into or installed in various RISC-V devices, enabling the devices to obtain reliable clock interrupt handling capabilities without relying on hardware interrupt delegation mechanisms. This facilitates software distribution and product deployment, and has significant industrial application value.
[0025] An electronic device includes a RISC-V processor, a timer, and a memory. The processor is configured to execute machine-mode firmware and an operating system kernel to implement the methods described above. This electronic device can be an embedded device, an IoT device, an industrial controller, or an autonomous driving system, etc. By applying the technical solution of this application, the device can achieve stable and predictable timed interrupts on various RISC-V processor platforms, providing a reliable time base for operating system scheduling and significantly improving the system stability and multitasking capabilities of the device. Attached Figure Description
[0026] Figure 1 The timing interaction diagram of the RISC-V machine clock degradation processing method provided in this application illustrates the interrupt propagation and processing interaction relationship between the timer, machine mode, supervisor mode and user program; Figure 2 The overall flowchart of a RISC-V machine clock degradation processing method provided in this application shows the complete processing cycle from step A to step E. Detailed Implementation
[0027] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.
[0028] In the description of this application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc., indicating the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.
[0029] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.
[0030] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0031] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.
[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0033] Example 1 This embodiment provides a RISC-V machine clock degradation processing method, such as... Figure 1 and Figure 2 As shown, the method includes the following steps: After the RISC-V processor boots up, the system initially runs in machine mode, the highest privilege level. In this mode, the timer interrupt system is initialized and configured. First, the machine mode interrupt enable register (MIE) is configured via a write operation, setting the timer interrupt enable bit (MTIE) to allow the processor to respond to timer interrupts in machine mode. Then, the processor core's cycle count (mcycle) since startup is obtained, and a preset time interval value (e.g., the number of clock cycles corresponding to 10ms) is added to this count to calculate the trigger point for the first timer interrupt. Finally, this target cycle count is written to the memory-mapped machine mode timer compare register (mtimecmp), completing the initial timer configuration.
[0034] When the system time reaches the set comparison value, a timer interrupt event is automatically generated by the hardware and directly reported to machine mode. The processor hardware automatically performs the following operations: saves the current program counter to the machine mode exception program counter register (mepc), saves the current privilege level to the machine mode status register (mstatus), switches the processor privilege level to machine mode, and jumps to the machine mode timer interrupt entry address.
[0035] After entering the machine mode interrupt handler, the following key operations are performed to achieve interrupt degradation propagation: (1) Clear the timer interrupt enable bit (mie.MTIE) in the machine mode interrupt enable register to temporarily disable the interrupt source in order to prevent additional interrupt interference during state transition.
[0036] (2) Perform a write operation (write the current value or any value) on the memory-mapped timer compare register (mtimecmp), which will automatically clear the timer interrupt wait bit (MTIP) in the machine mode interrupt wait register (mip).
[0037] (3) Set the supervisor timer interrupt enable bit (mie.STIE) in the machine mode interrupt enable register to provide conditions for subsequent interrupt propagation.
[0038] (4) Set the supervisor timer interrupt wait bit (mip.STIP) in the machine mode interrupt wait register to artificially create a supervisor mode timer interrupt event to be processed.
[0039] After completing the above state transition, the machine mode exception return instruction (mret) is executed. This instruction causes the processor to restore the program address from the mepc register and restore the previous privilege level (i.e., supervisor mode) according to the mstatus register. At the same time, the processor hardware automatically clears the mip.STIP bit.
[0040] Since the timer interrupt wait bit (mip.STIP) was set before returning to the controller mode, the processor will immediately execute the timer interrupt handling process in the controller mode.
[0041] In the regulator mode service interrupt procedure, the operating system performs the following operations: (1) Timer reload: First, a system call (such as SBI_SET_TIMER) is initiated through the Supervisor Binary Interface (SBI) to re-enter machine mode. In machine mode, the firmware recalculates and sets the timer comparison value (current cycle count + time interval) for the next interrupt point according to the operating system's requirements, completing the periodic reload of the timer. Then, the firmware returns to supervisor mode.
[0042] (2) System core services: After the timer is reset, the operating system updates the global and core local runtime counts it maintains. Then, it calls the system scheduler to execute core scheduling logic such as time-slice-based task switching and timeout management.
[0043] (3) Interrupt return: After all services are completed, the supervisor mode interrupt return instruction (sret) is executed to resume the execution of the user program. At this time, since the timer has been reset, the hardware will generate the next interrupt at the new time point, thus forming a stable and periodic clock interrupt handling loop.
[0044] Example 2 This embodiment provides another RISC-V machine clock degradation processing method. The main difference from Embodiment 1 is that in step B, clearing the machine mode timer interrupt wait state and setting the supervisor mode timer interrupt wait state are completed through a single atomic operation sequence. This ensures that the machine mode interrupt wait state is cleared before returning to supervisor mode, preventing the same interrupt event from being processed repeatedly. Specifically, the above operation sequence disables local interrupts during execution, ensuring that the entire operation process is not interrupted by other interrupts, thereby guaranteeing the atomicity and integrity of state transitions.
[0045] This embodiment provides a RISC-V processor configured to execute the RISC-V machine clock degradation processing method described in any of the above method embodiments. Specifically, the processor includes at least: a processing core, a timer interface, and a register set (including the MIE register, MIP register, MEPC register, and MSTAUS register). When running machine-mode firmware and an operating system kernel, the processor processes timer interrupts according to the above method flow.
[0046] This embodiment provides a computer-readable storage medium storing a computer program that, when executed by a RISC-V processor, implements the RISC-V machine clock degradation processing method described in any of the above method embodiments. The storage medium includes, but is not limited to, ROM, RAM, hard disk, flash memory, EEPROM, etc.
[0047] This embodiment provides an electronic device, including: a RISC-V processor (supporting machine mode and supervisor mode), a timer (connected to the processor for generating timer interrupts), and a memory (connected to the processor and storing an operating system kernel and machine mode firmware). This electronic device can be an embedded device, an IoT device, an industrial controller, or an autonomous driving system, etc. The processor is configured to execute the machine mode firmware and operating system kernel to implement the methods described in any of the above method embodiments.
[0048] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications to the technical solutions described in the foregoing embodiments, or equivalent substitutions for some or all of the technical features, do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.
Claims
1. A method for degrading the machine clock on a RISC-V processor platform, characterized in that, Includes the following steps: Step A: After the timer generates an interrupt, it reports to the machine mode. In machine mode, the timer interrupt signal is received and responded to, and the machine mode timer interrupt handler is executed. Step B: In the machine mode timer interrupt handler, the timer interrupt wait state in machine mode is cleared through an atomic register write operation sequence, and the timer interrupt wait state in supervisor mode is set at the same time, thus completing the downgraded transmission of the interrupt event from machine mode to supervisor mode. Step C: Return from machine mode to supervisor mode via software exception return instruction. Since the timer interrupt wait state of supervisor mode has been set, the processor automatically triggers and executes the supervisor mode timer interrupt service routine. Step D: In the timer interrupt service routine in the supervisor mode, the system re-enters machine mode by making a privilege escalation call from supervisor mode to machine mode. In machine mode, the timer comparison value is reset and the next timer interrupt is configured. Then, the system returns to supervisor mode. Step E: Continue executing the timer interrupt service routine in the supervisor mode, including updating the system time counter and performing system scheduling processing, and finally execute the supervisor mode interrupt return to complete this clock interrupt processing cycle.
2. The RISC-V processor platform machine clock degradation processing method according to claim 1, characterized in that, The atomic register write operation sequence in step B includes: Clear the timer interrupt enable bit in the machine mode interrupt enable register; The timer interrupt wait bit in the machine mode interrupt wait register is cleared by performing a write operation on the timer compare register. Set the supervisor timer interrupt enable bit in the machine mode interrupt enable register; Set the supervisor timer interrupt wait bit in the machine mode interrupt wait register.
3. The RISC-V processor platform machine clock degradation processing method according to claim 1, characterized in that, The software exception return instruction in step C is a machine mode exception return instruction. This instruction causes the processor to recover the program address from the machine mode exception program counter register and restore the previous privilege level to supervisor mode according to the machine mode status register.
4. The RISC-V processor platform machine clock degradation processing method according to claim 1, characterized in that, Step D, resetting the timer comparison value, further includes: Get the current cycle count of the processor core since startup; The target number of cycles for the next interrupt trigger point is obtained by adding a preset time interval value to the current cycle count. Write the target number of cycles into the memory-mapped machine-mode timer compare register.
5. The RISC-V processor platform machine clock degradation processing method according to claim 1, characterized in that, In step B, before clearing the timer interrupt wait state in machine mode, the following is also included: The machine mode timer interrupt is temporarily disabled by a write operation to prevent additional interrupt interference during state transitions.
6. The RISC-V processor platform machine clock degradation processing method according to claim 1, characterized in that, The method does not rely on the interrupt delegation mechanism of the RISC-V architecture and is applicable to RISC-V processor platforms that do not support timer interrupt delegation or where the interrupt delegation mechanism is unavailable.
7. The RISC-V processor platform machine clock degradation processing method according to claim 1, characterized in that, When the timer interrupt service routine in the regulator mode is executed, it first disables the current clock interrupt source and clears the timer interrupt waiting state in the regulator mode to avoid triggering the interrupt repeatedly before the timer is reloaded.
8. A RISC-V processor, characterized in that, The RISC-V processor is configured to perform the RISC-V processor platform machine clock degradation processing method as described in any one of claims 1 to 7.
9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the RISC-V processor, it implements the RISC-V processor platform machine clock degradation processing method as described in any one of claims 1 to 7.
10. An electronic device, characterized in that, include: A RISC-V processor that supports machine mode and regulator mode; A timer, connected to the RISC-V processor, is used to generate timer interrupts; The memory, connected to the RISC-V processor, stores the operating system kernel and machine-mode firmware. The RISC-V processor is configured to execute the machine-mode firmware and operating system kernel to implement the RISC-V processor platform machine clock degradation processing method according to any one of claims 1 to 7.