Continuous health monitoring for volatile memory systems

Abstract

This application relates to persistent health monitoring for volatile memory systems. A memory device can determine that an operating condition associated with an array of memory cells on the device, such as temperature, current, voltage, or other measure of health state, is outside of a range associated with a risk of degradation of the device. The memory device can monitor a duration for which the operating condition is outside of the range, and can determine whether the duration satisfies a threshold. In some cases, the memory device can store an indication when (e.g., each time) the duration satisfies the threshold. The memory device can store the one or more indications in one or more non-volatile storage elements, such as fuses, which can enable the memory device to maintain a persistent indication of a cumulative duration for which the memory device has operated with operating conditions outside of the range.

Description

[0001] Information related to divisional application This application is a divisional application of the invention patent application filed on May 21, 2020, with application number "202080047463.7" and invention title "Continuous Health Monitoring for Volatile Memory Systems". Cross-reference

[0002] This patent application claims priority to PCT application No. PCT / US2020 / 034045, filed May 21, 2020, entitled "Persistent Health Monitoring for Volatile Memory Systems," filed by Bell et al., which claims priority to U.S. Patent Application No. 16 / 433,820, filed June 6, 2019, entitled "Persistent Health Monitoring for Volatile Memory Systems," each of which is assigned to its assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field relates to continuous health monitoring for volatile memory systems. Background Technology

[0004] The following text generally relates to systems comprising at least one memory device, and more specifically, to continuous health monitoring of volatile memory devices.

[0005] Memory devices are widely used to store information in various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming different states of the memory device. For example, binary devices often store one of two states typically indicated by logic 1 or logic 0. In other devices, more than two states can be stored. To access the stored information, components of the device can read or sense at least one stored state in the memory device. To store information, components of the device can write to or program the states in the memory device.

[0006] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), and others. Memory devices can be volatile or non-volatile. For example, non-volatile FeRAM can store its logic state for extended periods, even without external power. Volatile DRAM, on the other hand, may lose its stored state when disconnected from external power.

[0007] In some cases, memory devices may be used within systems configured or designated for high reliability. Such systems may include, for example, automotive or other safety-related systems. However, the health of a memory device can degrade over time, potentially leading to memory errors. Summary of the Invention

[0008] A method is described. In some instances, the method may include: determining that an operating condition associated with a memory cell array exceeds a range; monitoring the duration for which the operating condition exceeds the range, at least in part based on the determination that the operating condition exceeds the range; determining that the duration satisfies the threshold, at least in part based on the monitoring of the duration; and storing an indication that the duration satisfies the threshold in a memory element, at least in part based on the determination that the duration satisfies the threshold.

[0009] A memory device is described. In some instances, the memory device may include: a volatile memory cell array; and a controller coupled to the volatile memory cell array and operable such that the memory device: determines that an operating condition associated with the volatile memory cell array exceeds a range; monitors the duration for which the operating condition exceeds the range, at least in part based on the determination; determines that the duration satisfies a threshold, at least in part based on the monitoring of the duration; and stores an indication that the duration satisfies the threshold in a non-volatile memory element, at least in part based on the determination that the duration satisfies the threshold.

[0010] An apparatus is described. In some instances, the apparatus may include: an array of volatile memory cells; a sensor configured to sense operating conditions associated with the volatile memory cell array and output a first signal based on the operating conditions; a comparator configured to determine whether the operating conditions exceed a range and output a second signal at least partially based on the comparison; a timer coupled to the comparator and configured to start timing at least partially based on the second signal and output a third signal after a threshold duration; and a logic circuit system coupled to a set of non-volatile memory elements and configured to receive an indication of the third signal and program one or more of the set of non-volatile memory elements at least partially based on the indication of the third signal. Attached Figure Description

[0011] Figure 1 Examples of systems for continuous health monitoring of volatile memory devices are provided, based on the examples disclosed herein.

[0012] Figure 2 This document describes examples of memory dies used for continuous health monitoring of volatile memory devices, based on the examples disclosed herein.

[0013] Figure 3 This document describes an example of a system 300 for continuous health monitoring of volatile memory devices, based on the examples disclosed herein.

[0014] Figure 4 A block diagram illustrating a memory array supporting continuous health monitoring of a volatile memory device according to aspects of this disclosure.

[0015] Figure 5 The flowchart illustrates one or more methods for continuous health monitoring of volatile memory devices, based on the examples disclosed herein. Detailed Implementation

[0016] In some cases, memory devices may be used within systems configured for or designated for high reliability. Such systems may include, for example, automotive or other systems where security is a significant concern. Memory devices can degrade over time due to various factors. This degradation can introduce errors into the memory device, which is particularly problematic for these systems. Therefore, in some cases, it may be necessary to monitor the health of the memory device to identify or predict such degradation before it reaches a significant or dangerous level.

[0017] In some cases, memory devices may degrade more quickly when operated under relatively harsh or severe operating conditions, such as higher temperatures, higher voltages, higher workloads, etc. Such operating conditions can be considered higher-risk operating conditions because memory devices degrade faster under harsh conditions than under less harsh conditions. In some cases, even operating a memory device at the upper end of its rated operating range can be considered as operating under harsh conditions and can lead to faster degradation over time than operating a memory device at a more moderate end of its rated operating range. Therefore, in some cases, it is possible to identify or determine lower-risk operating condition ranges for memory devices associated with slower device degradation and higher-risk operating condition ranges (possibly encompassing portions of the rated operating range) associated with faster device degradation.

[0018] In some cases, degradation of a memory device can be predicted by monitoring the amount of time the device operates under harsh operating conditions during its operation; for example, when the device operates under operating conditions that exceed a low-risk range. For instance, the memory device may include: one or more sensors, such as temperature or voltage sensors, for detecting when the memory device operates under harsh operating conditions (e.g., one or more operating conditions exceed a low-risk range); and a timer for determining the duration of the memory device's operation under harsh operating conditions.

[0019] In some cases, recording the cumulative duration of a storage memory device's operation under harsh operating conditions can be useful. However, volatile memory devices, such as DRAM-based memory devices, lose their status information whenever they are powered off. Such memory devices may lack a mechanism to periodically track the cumulative amount of time the memory device operates under harsh operating conditions during periods of power loss. For example, if a memory device operates under harsh conditions for a certain number of minutes during each activity but loses this information when it is powered off, then the cumulative duration of the memory device's operation under harsh conditions is unknown. Over time, such as months or years, the cumulative duration can become significant and may indicate that the memory device may have begun (or may have already begun) to degrade.

[0020] To address this issue, in some cases, the memory device can monitor the duration of operation under harsh conditions, and if the duration reaches or exceeds (e.g., satisfies) a threshold, the memory device can store an indication that the device has operated under harsh conditions for the threshold duration in a non-volatile memory element. The memory device can store the indication, for example, by blowing a fuse or by writing the indication to external non-volatile memory. This method allows the memory device to maintain a continuous indicator of its health status across periods of power loss.

[0021] In some cases, the memory device may store, in addition to storing an indication that it has operated under harsh conditions for a threshold duration in non-volatile memory, or instead of storing the indication in non-volatile memory, in on-die volatile memory (e.g., in a register). In this case, an external device, such as a host processor, may be configured to poll (e.g., read) the volatile memory at various times. The external device may then determine how to respond to the information retrieved from the volatile memory. For example, the external processor may be configured to retrieve information from the volatile memory and store it in non-volatile memory (e.g., non-volatile memory outside the memory die), or adjust the operating characteristics associated with the memory die (e.g., reduce the clock speed), or switch to another memory device, or alert the user or take some other action based on the indication. The external device itself may maintain (or cause to maintain) a continuous record of the cumulative duration for which the memory device has operated under harsh conditions and may perform various actions based on the cumulative duration.

[0022] In some cases, the memory device may store an indication in non-volatile memory whenever a duration exceeds a threshold. In other cases, the memory device may use a timer to determine whether a duration has been reached or exceeded a threshold, and may restart the timer after storing the indication in non-volatile memory. For example, whenever the timer indicates that the memory device has been operating under harsh conditions for a period of time (e.g., 5 minutes, 10 minutes, 15 minutes, 20 minutes, 25 minutes, or 30 minutes), the memory device may blow fuses in an array of fuses on the die, and may restart the timer after each fuse is blown.

[0023] In this way, non-volatile memory elements can maintain a continuous record of the cumulative duration across periods of device power failure. In some cases, the threshold duration can be relatively short compared to the frequency with which the memory device is typically powered off. For example, if the memory device is used in a system in which the memory device is typically powered on for about an hour before power failure, then the threshold duration could be, for example, 5 minutes, 10 minutes, 30 minutes, etc., making it more likely that the device will capture information about the duration of its operation under harsh conditions.

[0024] In some cases, the memory device may store indications in consecutive non-volatile memory elements within an array of non-volatile memory elements. Returning to the previous example, the memory device may include an array of fuses, capable of blowing a first fuse after the device has operated under harsh operating conditions for 30 minutes, a second fuse after another 30 minutes, a third fuse after yet another 30 minutes, and so on. In this way, each non-volatile memory element can be associated with a specific cumulative duration of operation of the memory device under harsh operating conditions.

[0025] In some cases, a specific non-volatile memory element can be associated with an alarm so that if the memory device indicates that the information is stored in that specific non-volatile memory element, the memory device can transmit an alarm to an external device (e.g., a host processor) to notify the external device that the memory device has reached the duration associated with that specific non-volatile memory element. The alarm can inform the external device that the memory device may be degrading, allowing the external device to adjust various operating characteristics of the memory device or the entire system, or to notify the user or take some other action.

[0026] Returning to the previous example, if the memory device blows a third fuse associated with a cumulative duration of 90 minutes of operation under harsh conditions, and that fuse is associated with an alarm, then the memory device can transmit the alarm to an external device.

[0027] Therefore, the techniques described herein enable volatile memory devices to maintain a continuous indication of their own health across periods of power loss and to send alarms to external devices as needed to indicate critical operating thresholds that can be associated with degradation of the memory device. The techniques further allow external devices to monitor the health of the memory device, for example, by polling registers that may contain indications of the duration under severe operating conditions for which the memory device has been operating.

[0028] Although the techniques described herein are discussed primarily in the context of volatile memory devices, such techniques can also be used in non-volatile memory devices without departing from the scope of this disclosure. For example, using a single non-volatile memory element (e.g., a fuse) to retain an indication that a non-volatile memory device has operated for a threshold duration under one or more operating conditions beyond a range (e.g., a low-risk range) can provide a continuous record of the device's operating conditions following a catastrophic failure of the non-volatile memory device.

[0029] Firstly, in reference Figure 1 and 2 The features of this disclosure are described in the context of the memory system and memory die described herein. (The reference includes...) Figure 3The features of this disclosure are described in the context of a system containing the memory device. These and other features of this disclosure are illustrated in conjunction with reference to [reference needed]. Figures 4 to 5 The device diagrams and flowcharts related to continuous health monitoring of the described volatile memory device are further illustrated and described with reference to the device diagrams and flowcharts.

[0030] Figure 1 This document describes an example of a system 100 utilizing one or more memory devices, based on the examples disclosed herein. System 100 may include an external memory controller 105, a memory device 110, and multiple channels 115 coupling the external memory controller 105 and the memory device 110. System 100 may include one or more memory devices, but for ease of description, one or more memory devices may be described as a single memory device 110.

[0031] System 100 may include electronic device components, such as computing devices, mobile computing devices, wireless devices, or graphics processing devices. System 100 may be an example of a portable electronic device. System 100 may be an example of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, Internet-connected device, etc. Memory device 110 may be a component of the system configured to store data of one or more other components of system 100. In some instances, system 100 is capable of machine-type communication (MTC), machine-to-machine (M2M) communication, or device-to-device (D2D) communication.

[0032] At least a portion of system 100 may be an example of a host device. This host device may be an example of a device that uses memory to execute processes, such as a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, some other fixed or portable electronic device, etc. In some cases, host device may refer to the hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 105. In some cases, external memory controller 105 may be called a host or host device. In some instances, system 100 is a graphics card.

[0033] In some cases, memory device 110 may transmit an alarm to the host device indicating that the memory device has been operating under severe conditions for a certain threshold duration, based on an indication that the memory device has been operating under severe conditions (e.g., operating beyond a range of operating conditions) for a specific threshold duration. In this case, the host device may determine whether to change the characteristics of each system, for example, by switching to a different memory device, reducing the number or frequency of memory accesses, reducing the clock speed, or issuing an alarm to another system.

[0034] In some cases, the host device may poll volatile memory elements on memory device 110 to determine whether memory device 110 has operated for a threshold duration under one or more operating conditions exceeding a range. In some cases, the host device may poll volatile memory elements by synchronously or asynchronously reading them. In some cases, the host device may then store the indication in non-volatile memory elements, for example, outside memory device 110 (e.g., outside the die). In some cases, the volatile memory elements may be registers on memory device 110 or other types of volatile memory elements, such as volatile memory cells, flip-flops, or latches.

[0035] In some cases, memory device 110 may be a separate device or component configured to communicate with other components of system 100 and provide physical memory address / space that may be used or referenced by system 100. In some instances, memory device 110 may be configurable to work with at least one or more different types of system 100. Signaling between components of system 100 and memory device 110 is operable to support modulation schemes for modulating signals, different pin designs for transmitting signals, dissimilar packages of system 100 and memory device 110, clock signaling and synchronization between system 100 and memory device 110, timing conventions and / or other factors.

[0036] Memory device 110 may be configured to store data of components of system 100. In some cases, memory device 110 may be used as a slave device of system 100 (e.g., responding to and executing commands provided by system 100 via external memory controller 105). Such commands may include access commands for access operations, such as write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands. In some cases, memory device 110 may comprise a single memory die 160. In some cases, memory device 110 may comprise two or more memory dies 160 (e.g., memory chips) supporting a desired or specified data storage capacity. A memory device 110 comprising two or more memory dies 160 may be referred to as a multi-die memory or package (also known as a multi-chip memory or package).

[0037] System 100 may further include processor 120, basic input / output system (BIOS) component 125, one or more peripheral components 130, and input / output (I / O) controller 135. The components of system 100 may communicate electronically with each other via bus 140.

[0038] Processor 120 may be configured to control at least a portion of system 100. Processor 120 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware component, or a combination of these types of components. In such cases, processor 120 may be an instance of central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances thereof.

[0039] BIOS component 125 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100. BIOS component 125 may also manage the data flow between processor 120 and various components of system 100 (e.g., peripheral components 130, I / O controller 135, etc.). BIOS component 125 may contain programs or software stored in read-only memory (ROM), flash memory, or any other non-volatile memory.

[0040] Peripheral component 130 may be any input or output device that can be integrated into or integrated with system 100, or an interface for such a device. Examples may include disk controllers, sound controllers, graphics controllers, Ethernet controllers, modems, universal serial bus (USB) controllers, serial or parallel ports, or peripheral card slots such as Peripheral Component Interconnect (PCI) or dedicated graphics ports. Peripheral component 130 may be other components that are understood by those skilled in the art to be peripheral devices.

[0041] I / O controller 135 manages data communication between processor 120 and peripheral components 130, input devices 145, or output devices 150. I / O controller 135 can manage peripheral devices that are not integrated into system 100 or are not integrated with system 100. In some cases, I / O controller 135 may represent a physical connection or port to an external peripheral component.

[0042] Input 145 may represent a device or signal outside of system 100 that provides information, signals, or data to system 100 or its components. This may include a user interface or interface with or between other devices. In some cases, input 145 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0043] Output 150 may represent a device or signal external to system 100 configured to receive output from system 100 or any of its components. Examples of output 150 may include a display, audio speaker, printing device, or another processor on a printed circuit board, etc. In some cases, output 150 may be a peripheral device that interfaces with system 100 via one or more peripheral components 130, or may be managed by I / O controller 135.

[0044] The components of system 100 may consist of general-purpose or special-purpose circuit systems designed to perform their functions. This may include various circuit elements configured to perform the functions described herein, such as conductive lines, transistors, capacitors, inductors, resistors, amplifiers, or other active or passive components.

[0045] Memory device 110 may include a device memory controller 155 and one or more memory dies 160. In some cases, the memory dies 160 may be manufactured using semiconductor manufacturing processes associated with volatile memory cells. For example, the memory dies 160 may be manufactured using a stacked DRAM process, a trench DRAM process, a fin DRAM process, or another process. In some cases, the semiconductor processes associated with the manufacture of volatile memory cells may not support features of non-volatile memory cells, such as EEPROM or flash memory cells. For example, volatile memory manufacturing processes may not support the construction of tunneling diodes, devices capable of hot electron injection for storage or floating gate discharge, and the like. Additionally, DRAM processes may not support high-voltage transistors (e.g., voltages greater than the inherent voltage of a given process) for internal boosting used by EEPROM, flash memory, and other non-volatile memories. Therefore, in some cases, it is impractical or infeasible to manufacture non-volatile memory cells on memory dies 160 manufactured using processes favorable for high-density volatile memory cells.

[0046] Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, and / or local memory controller 165-...). N ) and memory array 170 (e.g., memory array 170-a, memory array 170-b, and / or memory array 170- N The memory array 170 may be a collection of memory cells (e.g., a grid), wherein each memory cell is configured to store at least one bit of digital data. A feature reference is provided for the memory array 170 and / or the memory cells. Figure 2 To describe in more detail.

[0047] In some cases, the memory die 160 may include one or more sensors that detect when the operating conditions of the memory device 110 exceed a range, thereby indicating that the memory device 110 may be operating under harsh conditions. For example, the memory die 160 may include one or more temperature sensors, voltage sensors, etc., that can be configured to detect corresponding operating conditions of the memory device 110.

[0048] In some cases, memory die 160 may include one or more timers to monitor (e.g., measure) the duration for which memory device 110 has operated outside a range (e.g., a low-risk range). For example, memory die 160 may include a timer coupled to a sensor on memory die 160. When the sensor detects that the operating conditions of memory die 160 are outside a range, the sensor may transmit a signal that can start timing to the timer. If the timer reaches a threshold duration before the sensor indicates that the operating conditions have returned to the normal range, the timer may transmit a signal causing memory die 160 or memory device 110 to retain an indication that the threshold duration has been met (e.g., met or exceeded) in a non-volatile memory component, for example, by blowing a fuse. In some cases, the timer is then resettable.

[0049] In some cases, the memory die 160 or memory device 110 may include an array of one or more indicated non-volatile memory elements, such as fuses, that can be used to store that the memory device 110 has operated for a threshold duration under one or more operating conditions beyond a range.

[0050] In some cases, the values ​​of the range and / or threshold range may be programmed into the memory device 110 and / or received from an external device, such as a host processor (e.g., configured by the external device). For example, the memory device 110 may have registers that hold values ​​for ranges of voltage, power, temperature, or current, and may have registers for duration. The registers may have default values ​​that can be overwritten by the device memory controller 155 or the external memory controller 105.

[0051] The memory device 110 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. For example, a 2D memory device may include a single memory die 160. A 3D memory device may include two or more memory dies 160 (e.g., memory die 160-a, memory die 160-b, and / or any number of memory dies 160-). N In 3D memory devices, multiple memory dies 160- N They can be stacked on top of each other or stacked side by side. In some cases, the memory dies in 3D memory devices are 160-N It can be referred to as a layer, hierarchy, stack, or die. A 3D memory device can contain any number of stacked memory dies. N (For example, two highs, three highs, four highs, five highs, six highs, seven highs, eight highs). This can increase the number of memory cells that can be positioned on the substrate compared to a single 2D memory device, which can reduce manufacturing costs or improve the performance of the memory array, or both. In some 3D memory devices, different layers can share at least one common access line, such that some layers can share at least one of word lines, digital lines, and / or plate lines.

[0052] The device memory controller 155 may include circuitry or components configured to control the operation of the memory device 110. Therefore, the device memory controller 155 may include hardware, firmware, and software that enables the memory device 110 to execute commands, and may be configured to receive, transmit, or execute commands, data, or control information associated with the memory device 110. The device memory controller 155 may be configured to communicate with an external memory controller 105, one or more memory dies 160, or a processor 120. In some cases, the memory device 110 may receive data and / or commands from the external memory controller 105. For example, the memory device 110 may receive a write command instructing the memory device 110 to store certain data on behalf of a component of system 100 (e.g., processor 120) or a read command instructing the memory device 110 to provide certain data stored in the memory die 160 to a component of system 100 (e.g., processor 120). In some cases, the device memory controller 155 may control the operation of the memory device 110 described herein in conjunction with the local memory controller 165 of the memory die 160. Examples of components included in the device memory controller 155 and / or the local memory controller 165 may include a receiver for demodulating signals received from the external memory controller 105, a decoder for modulating signals and transmitting signals to the external memory controller 105, logic, amplifiers, filters, etc.

[0053] A local memory controller 165 (e.g., local to memory die 160) may be configured to control the operation of memory die 160. Furthermore, the local memory controller 165 may be configured to communicate with device memory controller 155 (e.g., to receive and transmit data and / or commands). The local memory controller 165 may support device memory controller 155 in controlling the operation of memory device 110 as described herein. In some cases, memory device 110 may not include device memory controller 155, and either local memory controller 165 or external memory controller 105 may perform the various functions described herein. Therefore, the local memory controller 165 may be configured to communicate with device memory controller 155, communicate with other local memory controllers 165, or communicate directly with external memory controller 105 or processor 120.

[0054] External memory controller 105 may be configured to facilitate the exchange of information, data, and / or commands between components of system 100 (e.g., processor 120) and memory device 110. External memory controller 105 may act as a liaison between components of system 100 and memory device 110, allowing components of system 100 to potentially operate without needing to know the details of memory device operation. Components of system 100 may submit requests (e.g., read or write commands) to external memory controller 105 that external memory controller 105 may fulfill. External memory controller 105 may translate or interpret communications exchanged between components of system 100 and memory device 110. In some cases, external memory controller 105 may include a system clock that generates a common (source) system clock signal. In some cases, external memory controller 105 may include a common data clock that generates a common (source) data clock signal.

[0055] In some cases, the external memory controller 105 or other components of system 100, or its functionality as described herein, may be implemented by processor 120. For example, external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by processor 120 or other components of system 100. Although external memory controller 105 is depicted as being external to memory device 110, in some cases, external memory controller 105, or its functionality as described herein, may be implemented by memory device 110. For example, external memory controller 105 may be hardware, firmware, or software, or some combination thereof, implemented by device memory controller 155 or one or more local memory controllers 165. In some cases, external memory controller 105 may be distributed across processor 120 and memory device 110 such that portions of external memory controller 105 are implemented by processor 120, and other portions are implemented by device memory controller 155 or local memory controller 165. Similarly, in some cases, one or more functions attributed herein to the device memory controller 155 or the local memory controller 165 may be performed by the external memory controller 105 (separate from or included in the processor 120).

[0056] Components of system 100 may exchange information with memory device 110 using multiple channels 115. In some instances, channel 115 may enable communication between external memory controller 105 and memory device 110. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between terminals associated with components of system 100. For example, channel 115 may include a first terminal comprising one or more pins or pads at external memory controller 105 and one or more pins or pads at memory device 110. Pins may be instances of conductive input or output points of devices of system 100, and pins may be configured to serve as part of a channel.

[0057] In some cases, the pins or pads of a terminal may be part of the signal path of channel 115. Additional signal paths may be coupled to terminals of channels used for routing signals within components of system 100. For example, memory device 110 may include signal paths (e.g., signal paths within memory device 110 or its components, such as within memory die 160) that route signals from the terminals of channel 115 to various components of memory device 110 (e.g., device memory controller 155, memory die 160, local memory controller 165, memory array 170).

[0058] Channel 115 (and associated signal paths and terminals) can be dedicated to transmitting a specific type of information. In some cases, channel 115 can be an aggregated channel and therefore can contain multiple individual channels. For example, data channel 190 can be x4 (e.g., containing 4 signal paths), x8 (e.g., containing 8 signal paths), x16 (containing 16 signal paths), and so on. Signals transmitted via the channel can use double data rate (DDR) signaling. For example, some symbols of the signal can be registered to the rising edge of the clock signal, and other symbols of the signal can be registered to the falling edge of the clock signal. Signals transmitted via the channel can use single data rate (SDR) signaling. For example, one symbol of the signal can be registered for each clock cycle.

[0059] In some cases, channel 115 may include one or more command and address (CA) channels 186. CA channels 186 may be configured to transmit commands between external memory controller 105 and memory device 110, containing control information (e.g., address information) associated with the command. For example, CA channel 186 may contain a read command with an address containing desired data. In some cases, CA channel 186 may be registered on rising and / or falling clock edges. In some cases, CA channel 186 may contain any number of signal paths (e.g., eight or nine signal paths) for decoding address and command data.

[0060] In some cases, channel 115 may include one or more clock signal (CK) channels 188. CK channels 188 may be configured to transmit one or more common clock signals between external memory controller 105 and memory device 110. Each clock signal may be configured to oscillate between high and low states and coordinate the operation of external memory controller 105 and memory device 110. In some cases, the clock signals may be differential outputs (e.g., CK_t and CK_c signals), and the signal paths of CK channel 188 may be configured accordingly. In some cases, the clock signals may be single-ended. CK channel 188 may include any number of signal paths. In some cases, clock signals CK (e.g., CK_t and CK_c signals) may provide a timing reference for command and addressing operations of memory device 110 or for other system-wide operations of memory device 110. Clock signals CK may therefore be referred to differently as control clock signal CK, command clock signal CK, or system clock signal CK. The system clock signal CK can be generated by the system clock, which may contain one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0061] In some cases, the external memory controller 105 may synchronously poll the volatile memory elements of the memory device 100 to check for indications that the memory device 110 has operated under operating conditions exceeding a range for a threshold duration. That is, the external memory controller 105 may read the contents of the volatile memory elements at a time based on timing associated with one or more clock signals. In some cases, the external memory controller 105 may asynchronously read the volatile memory elements of the memory device 100 to check for indications that the memory device 110 has operated under operating conditions exceeding a range for a threshold duration. That is, the external memory controller 105 may read the contents of the volatile memory elements at a time not based on one or more clock signals.

[0062] In some cases, channel 115 may include one or more data (DQ) channels 190. Data channels 190 may be configured to transfer data and / or control information between external memory controller 105 and memory device 110. For example, data channels 190 may transfer information to be written to memory device 110 (e.g., bidirectional) or information to be read from memory device 110.

[0063] In some cases, channel 115 may include one or more other channels 192 that may be dedicated to other purposes. These other channels 192 may contain any number of signal paths.

[0064] In some cases, other channels 192 may include one or more write clock (WCK) channels. While the 'W' in WCK may nominally stand for "write," the write clock signals WCK (e.g., WCK_t and WCK_c signals) provide a timing reference typically used for access operations of memory device 110 (e.g., a timing reference for both read and write operations). Therefore, the write clock signal WCK may also be referred to as the data clock signal WCK. The WCK channels may be configured to transmit a common data clock signal between the external memory controller 105 and the memory device 110. The data clock signal may be configured to coordinate access operations (e.g., write or read operations) of the external memory controller 105 and the memory device 110. In some cases, the write clock signal may be a differential output (e.g., WCK_t and WCK_c signals), and the signal paths of the WCK channels may be configured accordingly. The WCK channels may contain any number of signal paths. The data clock signal WCK can be generated by a data clock, which may contain one or more hardware components (e.g., oscillator, crystal, logic gate, transistor, etc.).

[0065] In some cases, other channels 192 may include one or more Error Detection Code (EDC) channels. EDC channels can be configured to deliver error detection signals, such as checksums, to improve system reliability. EDC channels can contain any number of signal paths.

[0066] In some cases, one or more channels, such as CA channel 186 or other channels 192, may be configured to transmit an indication (e.g., transmitted to an external device) that the duration of an operating condition exceeding a range meets (e.g., meets or exceeds) a threshold duration.

[0067] Channel 115 can couple external memory controller 105 to memory device 110 using a variety of different architectures. Examples of various architectures may include buses, point-to-point connections, cross switches, high-density interposers such as silicon interposers, or channels formed in an organic substrate, or some combination thereof. For example, in some cases, the signal path may at least partially include a high-density interposer, such as a silicon interposer or a glass interposer.

[0068] Signals transmitted via channel 115 can be modulated using a variety of different modulation schemes. In some cases, binary symbol (or binary level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. A binary symbol modulation scheme can be an example of an M-ary modulation scheme, where M equals 2. Each symbol of a binary symbol modulation scheme can be configured to represent a digital data bit (e.g., a symbol can represent logic 1 or logic 0). Examples of binary symbol modulation schemes include (but are not limited to) non-return-to-zero (NRZ), single-pole coding, bipolar coding, Manchester coding, pulse amplitude modulation (PAM) with two symbols (e.g., PAM2), and / or other modulation schemes.

[0069] In some cases, multi-symbol (or multi-level) modulation schemes can be used to modulate signals transmitted between external memory controller 105 and memory device 110. The multi-symbol modulation scheme may be an example of an M-ary modulation scheme, where M is greater than or equal to 3. Each symbol of the multi-symbol modulation scheme may be configured to represent more than one digital data bit (e.g., the symbol may represent logic 00, logic 01, logic 10, or logic 11). Examples of multi-symbol modulation schemes include (but are not limited to) PAM3, PAM4, PAM8, quadrature amplitude modulation (QAM), quadrature phase shift keying (QPSK), and / or other modulation schemes. A multi-symbol signal (e.g., a PAM3 signal or a PAM4 signal) may be a signal modulated using a modulation scheme comprising at least three levels for encoding more than one information bit. Multi-symbol modulation schemes and symbols may alternatively be referred to as non-binary, multi-bit, or higher-order modulation schemes and symbols.

[0070] Figure 2 This document describes an example of a memory die 200 based on the examples disclosed herein. The memory die 200 may be used as a reference. Figure 1 An example of the described memory die 160. In some cases, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205 programmable to store different logic states. Each memory cell 205 may be programmable to store two or more states. For example, the memory cell 205 may be configured to store one digital logic bit at a time (e.g., logic 0 and logic 1). In some cases, a single memory cell 205 (e.g., a multi-level memory cell) may be configured to store more than one digital logic bit at a time (e.g., logic 00, logic 01, logic 10, or logic 11).

[0071] Memory cell 205 can store charge representing a programmable state in a capacitor. A DRAM architecture may include a capacitor comprising a dielectric material for storing charge representing a programmable state. In other memory architectures, other memory devices and components are feasible. For example, a nonlinear dielectric material may be used.

[0072] Operations such as reading and writing can be performed on memory cell 205 by activating or selecting access lines, such as word line 210 and / or digital line 215. In some cases, digital line 215 may also be referred to as bit line. References to access lines, word lines, and digital lines or the like are interchangeable without loss of understanding or operation. Activating or selecting word line 210 or digital line 215 may involve applying voltage to the respective line.

[0073] The memory die 200 may include access lines (e.g., word lines 210 and digital lines 215) arranged in a grid-like pattern. Memory cells 205 may be located at the intersection of word lines 210 and digital lines 215. A single memory cell 205 at its intersection can be accessed by biasing word lines 210 and digital lines 215 (e.g., by applying a voltage to word lines 210 or digital lines 215).

[0074] Access to memory cell 205 can be controlled by row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate word lines 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate digital lines 215 based on the received column addresses. For example, memory die 200 may include multiple word lines 210 labeled WL_1 to WL_M and multiple digital lines 215 labeled DL_1 to DL_N, where M and N depend on the size of the memory array. Therefore, by activating word lines 210 and digital lines 215, such as WL_1 and DL_3, memory cell 205 at their intersection can be accessed. In a two-dimensional or three-dimensional configuration, the intersection of word lines 210 and digital lines 215 may be referred to as the address of memory cell 205.

[0075] Memory cell 205 may include logic storage components, such as capacitor 230 and switching component 235. Capacitor 230 may be an example of a dielectric capacitor or a ferroelectric capacitor. A first node of capacitor 230 may be coupled to switching component 235, and a second node of capacitor 230 may be coupled to voltage source 240. In some cases, voltage source 240 may be a cell board reference voltage, such as Vpl, or may be ground, such as Vss. In some cases, voltage source 240 may be an example of a plate line coupled to a plate line driver. Switching component 235 may be an example of a transistor or any other type of switching device that selectively establishes or de-establishes electronic communication between two components.

[0076] Selecting or deselecting memory cell 205 can be accomplished by activating or deactivating switch assembly 235. Capacitor 230 can communicate electronically with digital line 215 using switch assembly 235. For example, capacitor 230 can be isolated from digital line 215 when switch assembly 235 is deactivated, and capacitor 230 can be coupled to digital line 215 when switch assembly 235 is activated. In some cases, switch assembly 235 is a transistor, and its operation can be controlled by applying a voltage to the transistor gate, wherein the voltage difference between the transistor gate and the transistor source can be greater than or less than the transistor's threshold voltage. In some cases, switch assembly 235 can be a p-type transistor or an n-type transistor. Word line 210 can communicate electronically with the gate of switch assembly 235 and can be activated / deactivated based on a voltage applied to word line 210.

[0077] Word line 210 may be a conductive line for performing access operations on memory cell 205 in electronic communication with memory cell 205. In some architectures, word line 210 may be in electronic communication with the gate of switching component 235 of memory cell 205 and may be configured to control the switching component 235 of memory cell 205. In some architectures, word line 210 may be in electronic communication with the node of capacitor of memory cell 205, and memory cell 205 may not include a switching component.

[0078] Digital line 215 may be a conductive line connecting memory cell 205 and sensing component 245. In some architectures, memory cell 205 may be selectively coupled to digital line 215 during portions of an access operation. For example, word line 210 and switching component 235 of memory cell 205 may be configured to couple and / or isolate capacitor 230 of memory cell 205 from digital line 215. In some architectures, memory cell 205 may be in electronic communication (e.g., constant) with digital line 215.

[0079] Sensing component 245 may be configured to detect the state (e.g., charge) stored on capacitor 230 of memory cell 205 and determine the logic state of memory cell 205 based on the stored state. In some cases, the charge stored by memory cell 205 may be very small. Therefore, sensing component 245 may be used to include one or more sensing amplifiers that amplify the signal output from memory cell 205. The sensing amplifiers may detect small changes in charge on digital line 215 during a read operation and may generate a signal corresponding to logic state 0 or logic state 1 based on the detected charge. During a read operation, capacitor 230 of memory cell 205 may output a signal (e.g., release charge) to its corresponding digital line 215. The signal may cause a change in voltage on digital line 215. Sensing component 245 may be configured to compare the signal received from memory cell 205 across digital line 215 with a reference signal 250 (e.g., a reference voltage). Sensing component 245 may determine the stored state of memory cell 205 based on the comparison. For example, in binary signaling, if digital line 215 has a higher voltage than reference signal 250, then sensing component 245 can determine that the stored state of memory cell 205 is logic 1, and if digital line 215 has a lower voltage than reference signal 250, then sensing component 245 can determine that the stored state of memory cell 205 is logic 0. Sensing component 245 may include various transistors or amplifiers for detecting and amplifying differences in signals. The detected logic state of memory cell 205 may be provided as an output of sensing component 245 (e.g., provided to input / output 255) and may be indicated to another component of memory device 110 including memory die 200 (e.g., device memory controller 155) (e.g., directly or using local memory controller 260).

[0080] The local memory controller 260 can control the operation of the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, and sensing component 245). The local memory controller 260 may be used as a reference. Figure 1 An example of a local memory controller 165 is described. In some cases, one or more of the row decoder 220, column decoder 225, and sensing component 245 may co-locate with the local memory controller 260. The local memory controller 260 may be configured to receive data from an external memory controller 105 (or refer to...). Figure 1The described device memory controller 155 receives commands and / or data, translates the commands and / or data into information usable by the memory die 200, performs one or more operations on the memory die 200, and, in response to performing the one or more operations, transfers data from the memory die 200 to the external memory controller 105 (or the device memory controller 155). The local memory controller 260 can generate row and column address signals to activate target word lines 210 and target digital lines 215. The local memory controller 260 can also generate and control various voltages or currents used during operation of the memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current described herein can be adjusted or varied and may differ for various operations discussed during operation of the memory die 200.

[0081] In some cases, the local memory controller 260 may be configured to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 may be programmed to store a desired logical state. In some cases, multiple memory cells 205 may be programmed during a single write operation. The local memory controller 260 may identify the target memory cell 205 to which a write operation is performed. The local memory controller 260 may identify the target word line 210 and target digital line 215 (e.g., the address of the target memory cell 205) that are in electronic communication with the target memory cell 205. The local memory controller 260 may activate the target word line 210 and target digital line 215 (e.g., by applying voltage to the word line 210 or digital line 215) to access the target memory cell 205. The local memory controller 260 may apply a specific signal (e.g., voltage) to the digital line 215 during a write operation to store a specific state (e.g., charge) in the capacitor 230 of the memory cell 205, the specific state (e.g., charge) indicating a desired logic state.

[0082] In some cases, the local memory controller 260 may be configured to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During a read operation, the logical state stored in the memory cells 205 of the memory die 200 may be determined. In some cases, multiple memory cells 205 may be sensed during a single read operation. The local memory controller 260 may identify the target memory cell 205 on which the read operation is performed. The local memory controller 260 may identify the target word line 210 and target digital line 215 (e.g., the address of the target memory cell 205) that are electronically communicating with the target memory cell 205. The local memory controller 260 may activate the target word line 210 and target digital line 215 (e.g., apply voltage to the word line 210 or digital line 215) to access the target memory cell 205. The target memory cell 205 may transmit a signal to the sensing component 245 in response to a bias access line. The sensing component 245 may amplify the signal. The local memory controller 260 can trigger a sensing component 245 (e.g., a latching sensing component) and thereby compare a signal received from memory cell 205 with a reference signal 250. Based on the comparison, the sensing component 245 can determine a logical state stored in memory cell 205. The local memory controller 260 can then transmit the logical state stored in memory cell 205 to external memory controller 105 (or device memory controller 155) as part of a read operation.

[0083] In some memory architectures, accessing memory cell 205 can degrade or destroy the logic state stored in memory cell 205. For example, activation of a word line in a DRAM architecture can partially or completely discharge the capacitor of the target memory cell. Sensing component 245 can restore the voltage on digital line 215 based on the sensed logic state, which can restore the voltage on memory cell 205 to the same or similar voltage used in a write operation. Therefore, as long as there is a sufficient level in sensing component 245 to distinguish the stored logic state, a read operation performed in a DRAM architecture can restore the logic state of memory cell 205.

[0084] In some memory architectures based on volatile memory cells, such as DRAM, the state of memory cell 205 may need to be periodically refreshed to maintain its state when memory cell 205 has not been accessed for a period of time (and therefore will not be recovered as part of a read or write operation). Therefore, memory die 200 may include a logic circuitry configured to periodically perform a refresh procedure on one or more rows 275 of memory cells 205 by reading and recovering the state of memory cell 205 (e.g., triggering sensing component 245 to amplify the voltage on memory cell 205 back to the initially written voltage level). In some cases, this logic circuitry may be part of a local memory controller 260, or it may be a separate circuitry. In some cases, memory die 200 may perform a refresh procedure on one or more rows 275 of memory cells 205 in response to receiving a refresh command from an external host device or based on internal timing specifying the frequency at which the refreshable memory cells 205 are to be refreshed.

[0085] In some cases, the memory die 200 may include one or more sensors 265 configured to sense one or more operating conditions associated with the memory die 200, such as temperature, voltage, power, etc. In some cases, the sensor 265 may include one or more temperature sensors, one or more voltage sensors, one or more power sensors, or other types of sensors or circuitry configured to detect values ​​of the operating conditions. The sensor 265 may be positioned at various physical locations on the memory die 200 so that the sensor 265 can detect the operating conditions at those locations.

[0086] In some cases, operating conditions may include one or more metrics based on the number of bit errors associated with the memory device, which can provide an indication of the health status of the memory device. For example, memory die 200 may be configured to monitor (e.g., determine, detect) the value of the number of bit errors in the memory array of memory die 200 over time by executing an error detection program, such as an error correction code (ECC) procedure (rather than by sensing values ​​using sensor 320). In some cases, the health status of the device may be determined based on the number of detected bit errors or changes in the number of bit errors. In some instances, memory die 200 may indicate its health status to an external memory controller.

[0087] In some cases, memory die 200 may be configured to determine that an operating condition associated with an array of memory cells (e.g., memory cell 205, which may be within memory array 170 and reside on memory die 200) exceeds a range, and monitor the duration for which the operating condition exceeds the range based on the determination that the operating condition exceeds the range. Memory die 200 may be configured to determine whether the duration meets (e.g., meets or exceeds) a threshold duration, and store an indication that the duration meets the threshold duration in one or more memory elements 270 associated with the threshold duration. The memory elements 270 may be, for example, on memory die 200, and may be or may contain non-volatile or volatile memory elements.

[0088] In some cases, storage element 270 may comprise a one-time programmable storage element, such as a fuse or non-volatile memory cell that can only be written to once. In some cases, the fuse may comprise an electrical element, such as a polysilicon wire, that "melts" by applying a relatively large current to the element, thereby causing a change in the electrical properties of the element, such as an increase in the resistance across the element. In some cases, melting the electrical element may cause the element to behave as an open circuit, which can be detected by a current or voltage sensing circuit system.

[0089] In some cases, memory element 270 may include reprogrammable non-volatile memory elements, such as non-volatile memory cells that can be rewritten multiple times. However, non-volatile memory elements can be manufactured using different manufacturing processes than volatile memory elements, and therefore, manufacturing both types of memory elements on a single die can be challenging.

[0090] In some cases, storage element 270 may include volatile storage elements, such as volatile memory cells, registers, counters, etc.

[0091] Figure 3 This document describes an example of a system 300 for continuous health monitoring of volatile memory devices, based on the examples disclosed herein.

[0092] System 300 includes a memory device 305, which can be configured to store memory devices 305, ... Figure 1 and 2 Examples of memory device 110 or memory die 200 depicted herein. Memory device 305 includes memory cell array 310, which may include, for reference... Figure 1 and 2 The memory cell 205 is a portion of the memory array 170 discussed. The memory cell array 310 may include volatile memory cells such as DRAM memory cells or non-volatile memory cells such as FeRAM or flash memory cells.

[0093] The memory device 305 may include a group of one or more storage elements 345 to maintain a continuous recording of the cumulative amount of time the memory device 305 operates under harsh operating conditions, such as when one or more operating conditions of the memory device 305 exceed a corresponding range.

[0094] The memory device 305 may include one or more sensors 320. Sensors 320 may be configured to sense (e.g., determine) values ​​of operating conditions associated with the memory cell array 310. In some cases, sensors 320 may be located on the same die as the memory cell array 310. Sensors 320 may be, for example, temperature sensors, voltage sensors (e.g., for sensing the internal voltage of the memory device, such as VDD voltage), current sensors, power sensors, vibration sensors, acceleration sensors, radiation sensors, or other types of sensors.

[0095] In some cases, the memory device 305 may include multiple sensors 320, which may be the same or different types of sensors. For example, the memory device 305 may include multiple temperature sensors at different locations on the memory device 305 to enable the memory device 305 to monitor the temperature associated with the memory cell array 310 at multiple locations. For example, the memory device 305 may include both temperature sensors and voltage sensors to monitor both the temperature and voltage associated with the memory cell array 310.

[0096] In some cases, for example, sensor 320 may be configured to output a signal indicating a value of the sensed operating conditions.

[0097] Memory device 305 may include a comparator element 325. Comparator element 325 may be coupled to sensor 320 and configured to receive a signal from sensor 320 indicating a value of a sensed operating condition. In some cases, comparator element 325 may be located on a memory die having memory cell array 310. In some cases, comparator element 325 may be included in local memory controller 165, 260, or in device memory controller 155 or sensor 320, or may be a separate circuit system.

[0098] In some cases, the comparator element 325 may be configured to determine, based on a signal received from the sensor 320, that an operating condition associated with the memory cell array 310 exceeds a range, and output a signal indicating that the operating condition exceeds the range. For example, the comparator element 325 may determine that the operating condition exceeds the range when a sensed value of the operating condition (e.g., as received in the signal from the sensor 320) is higher than an upper threshold or lower than a lower threshold of the operating condition. In some cases, the comparator element 325 may include a comparator configured to compare the signal received from the sensor 320 with one or more thresholds (e.g., stored in the comparator) and output a signal based on the comparison. For example, the comparator may output a signal indicating that the operating condition exceeds the range, a signal indicating that the comparison is within the range, or no signal, depending on the comparison.

[0099] In some cases, the comparator element 325 (or other components of the memory die 200) may include an amount capable of determining that the operating conditions exceed the range, for example, it may quantify the severity of the operating conditions. In some cases, the comparator element may be configured to output a signal indicating that the operating conditions exceed the range (e.g., output to timer 330 or logic circuit system 340 or another component).

[0100] Memory device 305 may include timer 330. Timer 330 may be coupled to and configured to receive from comparator element 325 a signal indicating that operating conditions are outside the operating range. In some cases, when comparator element 325 outputs a signal indicating that operating conditions of memory device 305 are outside the operating range, timer 330 may begin measuring (monitoring) the elapsed time of the operating conditions being outside the operating range based on the signal received from comparator element 325. In some cases, timer 330 may be started (e.g., initiated) based on a signal received from comparator element 325, and may continue timing the duration (e.g., elapsed time) as long as timer 330 continues to receive signals indicating that operating conditions are outside the range. In some cases, if timer 330 stops receiving signals from comparator element 325, then timer 330 may stop timing the duration. In some cases, if timer 330 subsequently receives a signal indicating that operating conditions are outside the operating range again, then timer 330 may continue timing the duration from a previous time value, or may be reset and start timing the duration again from an initial time of zero.

[0101] In some cases, if timer 330 determines, based on a signal received from comparator 325, that the duration for which the operating conditions exceed the operating range meets (e.g., meets or exceeds) a threshold, then timer 330 may output a signal indicating that the duration meets the threshold. Timer 330 can then be reset, and if comparator 325 continues to output signals indicating that the operating conditions exceed a range, then timer 330 restarts timing for the duration of operation exceeding the range based on a signal received from comparator 325. In some cases, timer 330 may output a signal indicating that the duration meets the threshold whenever (e.g., every time) timer 330 determines that the duration meets the threshold.

[0102] In some cases, timer 330 may be configured to begin timing a duration if any of a plurality of operating conditions exceeds a range. For example, memory device 305 may include a plurality of sensors 320, and in some cases, a plurality of comparator elements 325 configured to determine whether any of the sensed operating conditions exceeds a corresponding range. In some cases, timer 330 may be configured (e.g., from comparator elements 325 or from a multiplexer) to receive a single signal indicating when any of the plurality of operating conditions exceeds its corresponding range. In some cases, timer 330 may be configured (e.g., from comparator elements 325) to receive a separate signal indicating when each operating condition exceeds its corresponding range.

[0103] In some cases, the threshold duration can be determined by various factors or combinations of factors related to the likelihood of device degradation (e.g., depending on various factors or combinations of factors). For example, in some cases, each sensor 320 or each type of sensor 320 may be associated with a different threshold duration; that is, the threshold duration may depend on the specific operating condition being sensed. For example, the threshold duration for temperature may differ from the threshold duration for voltage.

[0104] In some cases, the threshold duration may be based on the amount by which the operating conditions exceed the range. For example, the threshold duration may be shorter when the operating conditions are significantly beyond the range than when the operating conditions are slightly beyond the range. The timer 330 may, for example, integrate the amount by which the operating conditions exceed the range and compare the integrated value with one or more thresholds.

[0105] In some cases, the threshold duration can be based on the state of multiple operating conditions. For example, the threshold duration may be shorter when both temperature and voltage are outside their respective ranges, compared to when only temperature or voltage is outside their respective ranges.

[0106] In some cases, the threshold duration may be based on a weighted combination of factors, which may include, for example, the number of operating conditions exceeding their respective ranges and / or the amount of various operating conditions exceeding their respective ranges, or various other combinations of factors.

[0107] In some cases, one or more threshold durations may be stored on memory device 305, such as in a register, and accessed by timer 330 to determine whether the duration meets the threshold. In some cases, the threshold duration may be configured by an external controller.

[0108] In some cases, timer 330 may output a signal indicating that the duration meets a threshold to logic circuitry 340 on memory device 305. In some cases, logic circuitry 340 may be configured to store an indication that the duration meets the threshold in one or more of a set of storage elements 345-a, 345-b, 345-c, 345-d, 345-e, 345-f that may be included on memory device 305.

[0109] In some cases, a set of storage elements 345 may include a set of one-time programmable storage elements, such as a set of fuses or one-time programmable memory cells. In some cases, a set of storage elements 345 may include a set of volatile storage elements, such as volatile memory cells. Although a set of storage elements 345 in Figure 3 The memory is depicted as being contained within the memory device 305, but in some cases, a set of memory elements 345 may be external to the memory device 305 (e.g., outside the chip or die). In some cases, a set of memory elements 345 may be coupled to the memory device 305 and / or may be coupled to an external device.

[0110] In some cases, the logic circuit system 340 can identify a specific storage element from a set of storage elements 345 used for storing an indication. In some cases, each storage element 345 in the set of storage elements 345 can be associated with a specific threshold duration, and the logic circuit system 340 can select the storage element 345 associated with the specific threshold duration based on a signal indicating that the indication duration has met the specific threshold duration. For example, one storage element 345 may be associated with a threshold duration of 10 minutes, and another storage element 345 may be associated with a threshold duration of 30 minutes.

[0111] In some cases, the logic circuit system 340 may select memory elements sequentially from left to right or from top to bottom in an array (group) of memory elements. For example, the logic circuit system 340 may receive a signal indicating that a duration meets a threshold, and may select the next consecutive unused memory element in a group of memory elements 345 to store the indication that the duration meets the threshold. In some cases, the number of consecutive memory elements containing the indication that the duration meets the threshold can provide an indication of one or more cumulative durations for which an operating condition exceeds a range.

[0112] In some cases, the logic system 340 may select memory elements discontinuously, for example, by skipping consecutive memory elements. For instance, skipping memory elements may indicate that a threshold duration has been met by 5 or 10 times, or based on some other multiplier or exponential function. In some cases, skipping consecutive memory elements can save memory elements and reduce the power used to store the indication that the duration has met the threshold. In some cases, when the logic system 340 is provided with a time to store the indication during a power-down cycle, it may select discontinuous memory elements.

[0113] Therefore, in some cases, the number and / or location of the storage elements in a set of storage elements 345 used to indicate that the duration of storage meets a threshold can provide an indication of the cumulative amount of time that the memory device 305 has been operating under one or more operating conditions beyond a range, such as by detection by sensor 320 and measurement by timer 330.

[0114] In some cases, memory device 305 may include a counter 335 coupled to timer 330. Counter 335 may be configured to count the number of times a duration threshold is met based on the number of instances of signals received from timer 330 by counter 335. In some cases, counter 335 may be configured to output a signal indicating the number of times the duration threshold is met to logic circuit system 340. In some cases, logic circuit system 340 may select one or more storage elements 345 based on signals received from counter 335. For example, if counter 335 outputs a signal indicating that the duration threshold is met three (3) times (or indicating an equivalent duration), then logic circuit system 340 may select three (3) storage elements 345 and store the indication that the duration threshold is met in each of the selected storage elements 345. In some cases, logic circuit system 340 may store the indication in the selected storage element 345 whenever the duration threshold is met, and may also store the indication in the selected storage element 345 at a later time (e.g., during a power-down procedure). However, the number of storage elements 345 need not match the number of times the duration meets the threshold. In some cases, different storage elements 345 may be associated with different thresholds. For example, the logic circuit system 340 may select a single storage element 345 corresponding to the total duration indicated by the number of times the duration meets the threshold.

[0115] In some cases, a set of storage elements 345 may include a set of fuses to store an indication that a duration has met a threshold. However, blowing a fuse on the memory device 305 can consume a significant amount of power, which could disrupt or degrade the normal operation of the memory device 305. Therefore, in some cases, the memory device 305 may wait for the fuse to blow (or store the indication in another type of storage element) until the memory device 305 is idle or otherwise operates under suitable conditions.

[0116] For example, the logic circuit system 340 may receive a signal from the timer 330 or the counter 335 indicating that the duration meets a threshold, and may wait for a subsequent storage opportunity to store the indication in one or more storage elements 345. A storage opportunity may be a period during which the memory device 305 is idle or performing an operation consuming less than the threshold power.

[0117] In some cases, the logic circuit system 340 can identify memory opportunities based on signals received from the controller 350. For example, the controller 350 can provide a signal indicating that the memory device 305 is operating in an idle state to the logic circuit system 340 so that the logic circuit system 340 can identify memory opportunities. The controller 350 may be (or may be included in) a reference. Figure 1 and 2The described local memory controllers 165, 260, device memory controller 155, or external memory controller 105. In some cases, the logic circuitry system 340 may be included in the controller 350.

[0118] In some cases, one or more storage elements 345 may be associated with an alarm, such that when an indication is stored in storage element 345, an alarm is transmitted to an external device 355, such as a host processor or other device. For example, in some cases, blowing a specific fuse in a set of fuses may cause an alarm to be transmitted to the external device 355. Such alarms may be associated with the memory device 305 approaching or reaching a critical or significant duration of operation under conditions exceeding its operating range, and may enable the memory device 305 to notify the external device 355 that the memory device 305 is degrading. In some cases, multiple storage elements 345 may be associated with an alarm, such that the memory device 305 may transmit consecutive alarms to the external device indicating an increased likelihood that the memory device 305 may be degrading.

[0119] In some cases, a set of storage elements 345 may include one or more registers, which may include volatile storage elements. In some cases, the memory device 305 may track the number of times a duration meets a threshold and may store an indication of the number of times in a register. In some cases, an external device may read the registers to determine the health status of the memory device 305. In some cases, the memory device 305 may clear the registers when reading them, or modify the values ​​in individual status registers (e.g., registers that can be co-polled to read other status information) to indicate when the number of times stored in the registers has been updated.

[0120] In some cases, for example, memory device 305 may provide an indication to an external device (e.g., via a pin) whenever a threshold is met, so that the external device does not have to continue reading the register to determine whether the value has changed.

[0121] In some cases, one or more sensors 320 may be located outside the die or outside the memory device, for example, at another location within a system that includes the memory device and the host processor. In some cases, the host processor may determine that operating conditions associated with the system and / or with the memory cell array on the memory device exceed a range, and monitor the duration for which the operating conditions exceed the range based on the determination that the operating conditions exceed the range. The host processor may determine a duration that meets a threshold based on the monitored duration, and may store an indication that the duration meets the threshold in a memory element based on the determination that the duration meets the threshold. For example, the memory element may be on the memory device or the memory die.

[0122] Figure 4A block diagram 400 illustrates a memory device 405 supporting continuous health monitoring for volatile memory devices, based on examples disclosed herein. Memory device 405 may be used as a reference. Figures 1 to 3 Examples of aspects of the described memory device or memory die. Memory device 405 may include a determination component 410, a duration monitoring component 415, a threshold component 420, a storage component 425, a storage opportunity identification component 430, an alarm determination component 435, and an interface component 440. Each of these modules may communicate directly or indirectly with each other (e.g., via one or more buses).

[0123] The determining component 410 may determine that an operating condition associated with the memory cell array exceeds a range. In some instances, the determining component 410 may determine that a second operating condition associated with the memory cell array exceeds a second range. In some instances, the determining component 410 may determine the amount by which the operating condition exceeds the range. In some cases, the operating condition includes one or more of temperature, power, voltage, current, or health status determined based on the detection of a memory error in the memory cell array.

[0124] The duration monitoring component 415 can monitor the duration for which the operating conditions exceed the range based on a determination that the operating conditions exceed the range. In some instances, the duration monitoring component 415 can start a timer based on a determination that the operating conditions exceed the range, wherein the duration is monitored based on the time elapsed since the timer was started. In some instances, the duration monitoring component 415 can restart the timer when the duration meets a threshold.

[0125] Threshold component 420 can determine whether a duration meets a threshold based on the monitoring duration. In some instances, threshold component 420 can determine the threshold based on the determination that an operating condition exceeds the range and the determination that a second operating condition exceeds a second range. In some instances, threshold component 420 can determine the threshold based on the amount by which the operating condition exceeds the range.

[0126] Storage component 425 may store an indication that a duration meets a threshold in a storage element based on a determined duration threshold. In some instances, storage component 425 may select a storage element from a set of storage elements based on a threshold, wherein each storage element in the set of storage elements is associated with a corresponding threshold.

[0127] In some instances, storage component 425 may store the indication in a volatile storage element.

[0128] In some instances, storage component 425 may store the indication in a non-volatile storage element. In some instances, the indication may be stored in a storage element that includes a programmable, one-time programmable storage element.

[0129] In some instances, storage component 425 may store a second indication in a second non-volatile memory element based on determining that a threshold is met after a timeout following a timer restart. In some instances, storing the indication in a non-volatile memory element includes programming a first one-time programmable memory element, and storing the second indication in a second non-volatile memory element includes programming a second one-time programmable memory element. In some cases, the first and second one-time programmable memory elements are consecutive one-time programmable memory elements within an array of one-time programmable memory elements.

[0130] In some cases, a non-volatile memory element includes one or more programmable non-volatile memory cells, and the non-volatile memory element will indicate that the value stored in the one or more programmable non-volatile memory cells is adjusted.

[0131] In some cases, the storage opportunity identification component 430 can identify a storage opportunity after an indication has been stored in a volatile storage element, wherein storing the indication in a non-volatile storage element includes reading the indication from the volatile storage element and storing the indication in the non-volatile storage element during the storage opportunity. The storage opportunity identification component 430 can identify storage opportunities by identifying periods during which the memory cell array is idle.

[0132] Alarm determination component 435 can determine whether a non-volatile storage element is associated with an alarm. In some instances, alarm determination component 435 can transmit an alarm to an external device based on the determination that a non-volatile storage element is associated with an alarm.

[0133] Interface component 440 can receive requests for indications from an external device. In some instances, interface component 440 can transmit indications from storage elements to the external device based on the request.

[0134] Figure 5 The illustration shows a flowchart of one or more methods 500 for continuous health monitoring of a volatile memory device, illustrating aspects of this disclosure. Operation of method 500 may be implemented by the memory device or its components described herein. For example, operation of method 500 may be performed by reference to... Figure 4 The described memory device performs the functions described. In some instances, the memory device may execute a set of instructions to control the functional elements of the memory device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0135] At 505, the memory device may determine that the operating conditions associated with the memory cell array exceed a range. Operation 505 may be performed according to the methods described herein. In some instances, aspects of operation 505 may be derived from references... Figure 3The described sensor, comparator, and / or logic circuit system performs this operation. In some instances, aspects of operation 505 may be described in reference to... Figure 4 The described component is executed.

[0136] At 510, the memory device can monitor the duration of the operating conditions exceeding the range based on determining that the operating conditions exceed the range. Operation 510 can be performed according to the methods described herein. In some instances, aspects of operation 510 may be derived from references... Figure 3 The described timer is executed. In some instances, aspects of operation 510 can be found in the reference. Figure 4 The duration monitoring component described is executed.

[0137] In operation 515, the memory device can determine whether a duration meets a threshold based on the monitored duration. Operation 515 can be performed according to the method described herein. In some instances, aspects of operation 515 may be derived from references. Figure 3 The described timer and / or logic circuit system performs this operation. In some instances, aspects of operation 515 can be found in the reference... Figure 4 The described threshold component is executed.

[0138] At 520, the memory device may store an indication that a duration meets a threshold in a memory element based on determining that the duration meets the threshold. Operation 520 may be performed according to the method described herein. In some instances, aspects of operation 520 may be derived from references. Figure 3 The described controller, logic circuit system, and / or set of storage elements perform this action. In some instances, aspects of operation 520 may be described in reference. Figure 4 The described storage component is executed.

[0139] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: determining that an operating condition associated with a memory cell array exceeds a range; monitoring the duration for which the operating condition exceeds the range based on the determination; determining that the duration satisfies a threshold based on the monitoring; and storing, in a storage element, an indication that the duration satisfies the threshold.

[0140] In some examples of the method 500 and apparatus described herein, the memory cell array may be a volatile memory cell array, and the storage element may be a non-volatile storage element.

[0141] In some instances of the method 500 and apparatus described herein, the operation, feature, component, or instruction indicating storage in a non-volatile memory element may include the operation, feature, component, or instruction for selecting a non-volatile memory element from a set of non-volatile memory elements based on a threshold, wherein each non-volatile memory element in the set of non-volatile memory elements may be associated with a corresponding threshold.

[0142] In some instances of the method 500 and apparatus described herein, the means of indicating an operation, feature, component, or instruction stored in a non-volatile storage element may include an operation, feature, component, or instruction for programming a one-time programmable storage element.

[0143] Some examples of the method 500 and apparatus described herein may further include operations, features, components, or instructions for: storing an indication in a volatile storage element; and identifying a storage opportunity after storing the indication in a volatile storage element, wherein storing the indication in a non-volatile storage element includes reading the indication from the volatile storage element and storing the indication in the non-volatile storage element during the storage opportunity.

[0144] In some instances of the method 500 and apparatus described herein, the operations, features, components, or instructions for identifying storage opportunities may include operations, features, components, or instructions for identifying periods during which a volatile memory cell array may be idle.

[0145] In some instances of the method 500 and apparatus described herein, the non-volatile storage element includes one or more programmable non-volatile memory cells, and the value stored in the non-volatile storage element is indicated to adjust the value stored in the one or more programmable non-volatile memory cells.

[0146] Some examples of the method 500 and device described herein may further include operations, features, components, or instructions for: determining that a non-volatile storage element can be associated with an alarm; and transmitting the alarm to an external device based on the determination that a non-volatile storage element can be associated with an alarm.

[0147] Some examples of the method 500 and apparatus described herein may further include operations, features, components, or instructions for: determining that a second operating condition associated with the volatile memory cell array may exceed a second range; and determining a threshold based on determining that the operating condition may exceed the range and determining that the second operating condition may exceed the second range.

[0148] Some examples of the methods 500 and devices described herein may further include operations, features, components, or instructions for: determining an amount by which operating conditions may exceed the range; and determining a threshold based on the amount by which operating conditions may exceed the range.

[0149] In some instances of the method 500 and apparatus described herein, the operation, feature, component, or instruction for monitoring duration may include an operation, feature, component, or instruction for initiating a timer based on determining that operating conditions may exceed the range, wherein the duration may be monitored based on the time elapsed since the timer was started.

[0150] Some examples of the method 500 and apparatus described herein may further include operations, features, components, or instructions for: restarting a timer when a duration satisfies a threshold; and storing a second indication in a second non-volatile storage element based on determining that the time elapsed after restarting the timer satisfies the threshold.

[0151] In some instances of the method 500 and apparatus described herein, the instruction stored in a non-volatile storage element may include operations, features, components, or instructions for: programming a first one-time programmable storage element; and storing a second instruction in a second non-volatile storage element.

[0152] In some examples of the method 500 and apparatus described herein, the first one-time programmable storage element and the second one-time programmable storage element may be consecutive one-time programmable storage elements within an array of one-time programmable storage elements.

[0153] In some instances of the method 500 and apparatus described herein, the operating conditions include one or more of temperature, power, voltage, current, or health status determined based on the detection of a memory error in the volatile memory cell array.

[0154] Some examples of the method 500 and apparatus described herein may further include operations, features, components, or instructions for: receiving a request for an instruction from an external device; and transmitting the instruction from a storage element to the external device based on the request.

[0155] It should be noted that the methods described above are subject to possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are feasible. Furthermore, portions from two or more of the methods can be combined.

[0156] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips referenced throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have multiple bit widths.

[0157] As used herein, the term "virtual ground" refers to a node of a circuit that is maintained at approximately zero volts (0 V) but is not directly coupled to ground. Therefore, the voltage of a virtual ground may fluctuate temporarily and return to approximately 0 V in steady state. Virtual grounding can be implemented using various electronic circuit elements, such as a voltage divider consisting of operational amplifiers and resistors. Other implementations are also possible. "Virtual ground" or "virtual ground connection" implies a connection to approximately 0 V.

[0158] The terms "electronic communication," "conductive contact," "connection," and "coupling" refer to the relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if any conductive path exists between them that can support the flow of signals between them at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) may be either an open or closed circuit based on the operation of the device containing the connected component. The conductive path between connected components may be a direct conductive path between the components, or it may be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some cases, the flow of signals between connected components may be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0159] The term "coupling" refers to a shift from an open-circuit relationship between components (where signals cannot currently travel between components via conductive paths) to a closed-circuit relationship between components (where signals may be able to travel between components via conductive paths). When a component, such as a controller, couples other components together, the component initially allows signals to flow between other components via conductive paths that were previously not permitted.

[0160] The term "isolation" refers to a relationship between components where signals cannot currently flow between them. Components are isolated from each other if there is an open circuit between them. For example, when a switch is open, two components separated by a switch positioned between them are isolated from each other. When a controller isolates two components, the controller introduces a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0161] As used in this article, the term “substantially” means that the modified characteristic (e.g., a verb or adjective modified by the term “substantially”) does not need to be absolute but close enough to achieve the advantage of the characteristic.

[0162] As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can serve as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise a trace, wire, conductive line, conductive layer, or the like that providing a conductive path between elements or components of the memory array.

[0163] The devices discussed herein, including memory arrays, can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In others, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0164] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, drain, and gate. The terminals may be connected to other electronic components via a conductive material (e.g., a metal). The source and drain may be conductive and may include heavily doped (e.g., degraded) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., the majority carriers are signals), then the FET may be called an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0165] The descriptions herein, together with the accompanying drawings, depict exemplary configurations and do not represent all instances that may be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description," not "preferred" or "superior to other instances." The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0166] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash followed by a second reference numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral, regardless of the second reference numeral.

[0167] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, the data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0168] The various illustrative blocks and modules described in connection with the disclosure herein may be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, a processor may be any processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0169] The functions described herein can be implemented in hardware or software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented in software executed by a processor, hardware, firmware, firmware, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distributed implementations such that portions of the functions are implemented in different physical locations. Moreover, as used herein, the word "or" in the list of items (e.g., a list of items beginning with phrases such as "at least one of..." or "one or more of...") encompasses the claims and indicates a list of inclusions, such that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as a reference to a set of closing conditions. For example, an exemplary step described as "based on condition A" may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0170] Computer-readable media includes non-transitory computer storage media and communication media, with communication media including any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example and without limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then the media definition includes coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave). As used herein, disks and optical discs include CDs, laser discs, optical discs, DVDs, floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0171] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand that various modifications to this disclosure are possible, and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method executed by a host system, comprising: Read one or more volatile memory elements of a memory device, wherein the memory device operates according to operating conditions associated with an operating range; At least in part, based on reading the one or more volatile memory elements, information is stored in one or more non-volatile memory elements, the information indicating whether the duration for which the operating conditions exceed the operating range exceeds a threshold duration, wherein the threshold duration is determined at least in part based on the type of the operating conditions; as well as Whether to modify one or more system features associated with the memory device is determined, at least in part based on information indicating whether the duration of the operating conditions exceeding the operating range exceeds the threshold duration.

2. The method according to claim 1, further comprising: At least in part based on determining that one or more system features associated with the memory device need to be modified, the system switches from one or more first commands for exchanging operations of the memory device to one or more second commands for exchanging operations of a second memory device.

3. The method according to claim 1, further comprising: At least in part, based on determining that one or more system features associated with the memory device need to be modified to reduce the number of memory accesses, the memory access frequency, or both at the memory device, wherein the one or more system features include the number of memory accesses, the memory access frequency, or both.

4. The method of claim 1, further comprising: At least in part, based on determining that one or more system characteristics associated with the memory device need to be modified, the clock frequency associated with the memory device is reduced, wherein the one or more system characteristics include the clock frequency.

5. The method of claim 1, further comprising: At least in part based on determining that one or more system features associated with the memory device need to be modified, an alarm is transmitted to a system different from the host system and the memory device, wherein the alarm indicates that the duration of the operating conditions exceeding the operating range exceeds the threshold duration, and wherein the one or more system features include the alarm.

6. The method of claim 1, further comprising: An alarm is received from the memory device indicating that the duration of the operating condition being outside the operating range exceeds the threshold duration, wherein storing the information includes storing, at least in part, the information indicating that the duration exceeds the threshold duration based on the alarm.

7. The method of claim 1, wherein reading the one or more volatile memory elements comprises: Detecting one or more memory errors in the one or more volatile memory elements, wherein the operating conditions are determined at least in part based on the detection of the one or more memory errors.

8. The method of claim 1, wherein determining whether to modify the one or more system features comprises: Based at least in part on the information indicating that the duration exceeds the threshold duration, it is determined that one or more system features need to be modified; or Based at least in part on the information indicating that the duration has not exceeded the threshold duration, it is determined that modification of one or more system features should be avoided.

9. The method of claim 1, wherein storing the information comprises: The information is stored in one or more non-volatile memory elements located outside the memory device.

10. The method of claim 1, wherein the one or more volatile memory elements comprise one or more registers on the memory device.

11. The method of claim 1, wherein the operating conditions include one or more of temperature, power, voltage, current, and health status, or any combination thereof.

12. A method comprising: The memory device is operated with operating conditions associated with the operating range, wherein the operating conditions are one of a plurality of operating conditions supported by the memory device. Based at least in part on operating the memory device, detecting that the duration for which the operating conditions exceed the operating range exceeds a threshold duration, wherein the duration is determined at least in part based on the type of the operating conditions; and Based at least in part on the detection, an indication is stored that the duration for which the operating conditions exceed the operating range exceeds the threshold duration.

13. The method of claim 12, further comprising: At least in part based on the storage, an alarm is transmitted to an external device, the alarm indicating that the duration for which the operating conditions are outside the operating range exceeds the threshold duration.

14. The method of claim 12, further comprising: At least in part, based on operating the memory device, the detection that the operating conditions of the memory device exceed the operating range is made; and A timer is started at least in part based on detecting that the operating conditions exceed the operating range, wherein the timer is started at least in part based on detecting that the duration for which the operating conditions exceed the operating range exceeds the threshold duration.

15. The method of claim 12, further comprising: Based at least in part on the detection, a storage element is identified from a plurality of storage elements that is associated with the duration during which the operating conditions exceed the operating range, wherein each of the plurality of storage elements is associated with a corresponding threshold duration, and wherein the storage further includes storing the indication in the identified storage element.

16. The method of claim 12, further comprising: The operating conditions of the memory device are monitored, at least in part based on the operation of the memory device, wherein the detection is performed at least in part based on the monitoring.

17. The method of claim 12, further comprising: The threshold duration is identified at least in part based on the operating conditions, the amount by which the operating conditions exceed the operating range, the number of operating conditions of the memory device that exceed the corresponding operating range, or a combination thereof, wherein the detection is performed at least in part based on the identification of the threshold duration.

18. The method of claim 12, wherein storing the indication further comprises: The instruction is stored in a one-time programmable storage element.

19. The method of claim 12, wherein the operating conditions include one or more of temperature, power, voltage, current, and health status, the health status being determined at least in part based on the detection of memory errors in one or more volatile memory cell arrays of the memory device.

20. A host system comprising: One or more interfaces, said one or more interfaces including one or more signal paths operable for communicating with one or more memory systems; and A processing circuitry system, coupled to the one or more interfaces and configured to cause the host system to perform the following operations: Read one or more volatile memory elements of a memory device, wherein the memory device operates according to operating conditions associated with an operating range; At least in part, based on reading the one or more volatile memory elements, information is stored in one or more non-volatile memory elements, the information indicating whether the duration for which the operating conditions exceed the operating range exceeds a threshold duration, wherein the threshold duration is determined at least in part based on the type of the operating conditions; as well as Whether to modify one or more system features associated with the memory device is determined, at least in part based on information indicating whether the duration of the operating conditions exceeding the operating range exceeds the threshold duration.

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