A server memory read-write timing adaptive calibration method based on dynamic delay lock

Abstract

The application relates to the field of computer and auxiliary equipment repair technology, and is a server memory read-write timing adaptive calibration method based on dynamic delay locking. The specific method comprises the following steps: synchronously collecting key electric signals of a memory controller and environmental states to generate a timing offset feature set; establishing a dynamic delay locking reference path, analyzing real-time phase differences between a clock and data, and forming a dynamic phase deviation result; determining a compensation amount, performing dynamic compensation, adaptively adjusting loop gain, and generating a phase calibration result; reextracting local phase deviation intensity, dynamically adjusting a sampling window center and reconstructing a data sampling boundary, and generating a sampling window result; automatically switching delay locking parameter groups, recursively updating compensation strategies, and outputting stable read-write timing control results. The application solves the problem that, in the prior art, in the face of high-load burst access, long-term read-write reliability of a server memory cannot be ensured under the conditions of high-frequency switching and wide-temperature power supply fluctuation.

Description

Technical Field

[0001] This invention belongs to the field of computer and auxiliary equipment repair technology, and more specifically, relates to a server memory read / write timing adaptive calibration method based on dynamic delay locking. Background Technology

[0002] In high-speed parallel interfaces for server memory, as the operating frequency of memory such as DDR5 jumps to several gigahertz, the effective clock and data windows narrow dramatically. Multi-dimensional environmental disturbances such as temperature, voltage fluctuations, and dynamic frequency switching easily cause timing offsets, leading to a drastic deterioration in the bit error rate. Most existing delay-locking technologies rely on fixed delay parameters or simple phase comparisons, lacking high-precision synchronous acquisition of clock, data gating signals, and environmental conditions. This prevents the extraction of sampling point offsets, offset change rates, and window compression evaluation values ​​under the coupling effects of multiple factors, resulting in a lack of timing offset characteristics. When establishing a locking reference path, traditional methods select the path based solely on a single delay value, failing to comprehensively consider the overall propagation path delay, jitter margin, and window compression risks. Furthermore, they cannot dynamically update the optimal reference path during frequency or read / write mode switching, resulting in a coarse evaluation of the real-time phase difference between the reference clock and data, and a lack of offset trend prediction capabilities. The compensation stage typically employs fixed-granularity delay units and constant loop gain, failing to flexibly select different granularity delay lines based on phase deviation levels. It also lacks adaptive adjustment of the loop gain based on the rate of temperature change, voltage fluctuation amplitude, and delay change slope under frequency switching. This results in lag response during rapid temperature drift and overcompensation leading to oscillations during severe voltage fluctuations. After calibration, existing technologies lack continuous closed-loop monitoring of read / write error status and sampling stability, making it impossible to determine whether the effective window width after calibration truly meets the margin, or to dynamically adjust the sampling window center and reconstruct data boundaries. This leads to short-term error-free illusions masking long-term drift risks. Furthermore, separate adjustment of read / write paths lacks a mechanism for unified constraint to the same window center, and inconsistencies between read gating and write data path deviations easily cause timing conflicts. Faced with high-load burst access, traditional methods converge slowly and lack the ability to learn drift trends across temperature domains and recursively update compensation strategies, failing to guarantee long-term read / write reliability of server memory under high-frequency switching and wide-temperature power supply fluctuation conditions. Summary of the Invention

[0003] To address the shortcomings of existing technologies, the present invention aims to resolve the aforementioned deficiencies and propose a server memory read / write timing adaptive calibration method based on dynamic latency locking.

[0004] The present invention adopts the following technical solution;

[0005] The first aspect of this invention discloses a server memory read / write timing adaptive calibration method based on dynamic latency locking, as follows:

[0006] S1: Synchronously collect key electrical signals and environmental status of the memory controller, and extract sampling point offset, offset change rate and window compression evaluation value through read and write timing window and dynamic offset analysis to generate timing offset feature set;

[0007] S2: Based on the timing offset feature set, by establishing a dynamic delay-locked reference path, the real-time phase difference between the clock and data is analyzed, and combined with the sampling window center deviation and offset trend prediction, dynamic phase deviation results are synthesized.

[0008] S3: Based on the dynamic phase deviation results, delay units of different granularities are selected according to the deviation level and the compensation amount is determined. Dynamic compensation is performed on the clock path and data path. At the same time, the loop gain is adaptively adjusted according to the delay change slope, temperature change rate and voltage fluctuation amplitude to generate the phase calibration result after delay compensation.

[0009] S4: Based on the phase calibration results, continuously detect the read / write error status and sampling stability after calibration, re-extract the local phase deviation intensity, dynamically adjust the sampling window center and reconstruct the data sampling boundary accordingly, and generate the sampling window result after closed-loop stabilization.

[0010] S5: Based on the sampling window results, the read and write paths are uniformly constrained to the same window center. The delay locking parameter group is automatically switched according to the frequency and window margin. The wide temperature range drift trend is continuously learned and the compensation strategy is recursively updated. The sampling window boundary is quickly converged during high-load burst access, and finally a stable read and write timing control result is output.

[0011] Furthermore, S1 includes:

[0012] S11: A high-speed sampling unit is set on the memory controller side to synchronously acquire the clock signal, data signal and data strobe signal under the same time base, and record the clock edge arrival time, data flip time and data strobe signal effective edge time of each channel to form the original timing signal set.

[0013] S12: Based on the original timing signal set, extract the stable start time, stable end time, sampling point time and clock edge time for read and write operations respectively, and perform a real and usable sampling margin analysis to obtain the effective sampling window width, which is output as the read and write timing monitoring result;

[0014] S13: Synchronously collect memory chip temperature status, memory controller temperature status, power supply voltage status, operating frequency status and frequency switching status, and then bind them to the corresponding read and write timing monitoring results according to the sampling timestamp, generating a set of read and write timing states with environmental tags for each set of timing states, each carrying temperature, voltage and frequency conditions.

[0015] S14: Based on the read / write timing state set, analyze the offset of the actual sampling point relative to the center of the sampling window, analyze the offset change rate between adjacent detection cycles, and analyze the window compression degree in combination with the temperature, voltage and frequency deviations based on the initial calibration window to obtain a unified sampling window compression evaluation value. Then, the three together constitute the timing offset feature set.

[0016] Furthermore, S2 includes:

[0017] S21: Classify the timing offset feature set according to memory channel number, read / write direction, current operating frequency and sampling window compression evaluation value, record the clock propagation time, data propagation time and data gating signal propagation time of each channel respectively, and combine jitter margin and window compression calculation to obtain the comprehensive delay evaluation value of propagation path, and form the memory channel propagation path mapping result of channel-frequency-read / write mode-propagation path;

[0018] S22: Based on the memory channel propagation path mapping results, and according to the current operating frequency and read / write mode, the stability of the path is evaluated by comprehensively considering the latency evaluation value, sampling point offset, offset change trend and jitter margin. The path with the best stability is selected as the dynamic latency locking reference path, and is dynamically updated when the frequency, window compression or read / write mode changes.

[0019] S23: After the dynamic delay lock reference path is determined, the clock arrival time, data arrival time and data strobe signal arrival time under the path are read. Based on the clock edge, the time difference between the data and the clock is corrected by the strobe signal and converted into real-time phase deviation according to the current operating frequency.

[0020] S24: Determine the center of the sampling window based on the start and end times of data stability, and combine the deviation between the actual sampling point and the center of the sampling window with the offset change trend, and integrate them with the real-time phase deviation to generate a dynamic phase deviation result.

[0021] S25: Encapsulate the dynamic phase deviation results according to the memory channel number, read / write mode, current operating frequency, reference path number, phase deviation magnitude, deviation direction, sampling window width, and window compression evaluation value. Based on the relationship between the absolute value of the dynamic phase deviation results and the preset stability threshold and safety threshold, mark them as slight deviation state, compensable deviation state, or forced calibration deviation state, respectively, to form a packaged dynamic phase deviation result with deviation level marking.

[0022] Furthermore, S3 includes:

[0023] S31: Read the phase deviation magnitude, deviation direction, current operating frequency, read / write mode, and sampling window compression evaluation value from the dynamic phase deviation results, and convert the deviation angle into the number of delay units according to the frequency and the selected delay unit step size;

[0024] Simultaneously, based on the comparison between the phase deviation magnitude and the preset stability threshold and safety threshold, fine-grained, medium-grained, or coarse-grained delay units are activated in stages to form a graded control result for delay units;

[0025] S32: Based on the phase deviation direction in the dynamic phase deviation result and the hierarchical control result of the delay unit, the total delay compensation is allocated to the clock path and the data path to obtain the clock path delay compensation and the data path delay compensation.

[0026] Simultaneously, the delay on the strobe signal side or the controller output side is adjusted preferentially according to the read / write mode.

[0027] Furthermore, S3 also includes:

[0028] S33: When the memory frequency changes, continuously record the change in total delay compensation and the frequency change amplitude before and after the change. Combined with the detection period interval, evaluate the sensitivity of the delay compensation to the frequency change, i.e. the delay change slope, and form a delay compensation change sequence.

[0029] S34: Adaptively adjust the loop gain based on the rate of temperature change, the amplitude of voltage fluctuation, and the slope of the delay change.

[0030] S35: Based on the adaptive loop gain, the clock path delay compensation and data path delay compensation are actually applied, and the phase residual after compensation is re-estimated.

[0031] Simultaneously, the loaded path delay, loop gain, and delay compensation change sequence are encapsulated together as a phase calibration result.

[0032] Furthermore, S4 includes:

[0033] S41: Read the phase residual, path delay and loop gain in the phase calibration result, continuously perform read and write monitoring in the current memory channel, and count the number of bit errors, read and write accesses, residual offset of sampling points and data holding time within a unit detection cycle. The ratio of erroneous data bits to total detection data bits reflects the true read and write reliability after calibration, and generates read and write status detection results after calibration.

[0034] S42: Based on the read / write status detection results after calibration, combined with the start and end times of data stabilization, the amount of clock and data jitter, and the compensated phase residual, the setup and hold time, jitter, and the time occupied by the remaining phase deviation are deducted from the data stabilization duration to obtain the actual usable sampling window width after calibration, and at the same time, it is determined whether there is still continuous drift at the clock edge.

[0035] Furthermore, S4 also includes:

[0036] S43: When the effective sampling window width after calibration is lower than the preset window lower limit, or when it shows a downward trend for multiple consecutive detection cycles, the stable start and end times, actual sampling point times and phase residuals of the data are re-extracted from the corresponding memory channel. The amplitude of the remaining phase deviation, the degree of deviation of the sampling point from the center of the window and the reduction ratio of the window relative to the initial calibration are combined into a local phase deviation intensity to determine whether the sampling window center needs to be readjusted.

[0037] S44: Determine the correction amount for the center of the sampling window based on the intensity of the local phase deviation.

[0038] If the actual sampling point is biased towards the leading edge of the window, the center will be moved backward;

[0039] If the actual sampling point is biased towards the rear edge of the window, then the center will be moved forward;

[0040] Subsequently, the data sampling front and back boundaries were redefined based on the center time of the reconstructed sampling window, forming the reconstructed data sampling boundary.

[0041] S45: Encapsulate the reconstructed sampling window center, data sampling boundary, calibrated effective window width, bit error rate, local phase deviation intensity, and corresponding channel number, and simultaneously perform state marking to obtain the sampling window result after closed-loop stabilization.

[0042] Furthermore, S5 includes:

[0043] S51: Read the sampling window center, data sampling boundary, bit error rate, and local phase deviation intensity from the sampling window results after closed-loop stabilization. For the read operation path, focus on aligning the gating signal with the controller sampling point. For the write operation path, focus on aligning the controller output edge with the particle receiving window. Constrain the read and write paths to the vicinity of the same window center. Then, fuse the degree of sampling point deviation from the window center, the ratio of bit error rate to the allowable threshold, and the ratio of local deviation intensity to the allowable threshold to form a unified timing deviation evaluation value for read and write operations.

[0044] S52: Based on the unified timing deviation evaluation value for read and write, combined with the current memory operating frequency, loop gain, and the margin of the effective window width relative to the initial calibration window, the parameter group switching judgment value is obtained to determine whether the target delay locking parameter group needs to be switched.

[0045] S53: After selecting the target delay locking parameter group, continuously record the changes in window center, bit error rate and delay compensation amount under different temperature, voltage and frequency conditions, and recursively update the historical compensation results to obtain the updated delay compensation strategy value, and simultaneously form a dynamically updated delay compensation strategy.

[0046] S54: When a sudden increase in the number of read and write accesses, a rise in the bit error rate, or a sampling window boundary approaching the lower limit is detected in a short period of time, the fast convergence adjustment is initiated by rapidly converging the compensation amount under high load, so that the compensation response under high load is accelerated but no oscillation is generated.

[0047] If the sampling point returns to the center area of ​​the effective window, the normal compensation strategy will be gradually restored.

[0048] If convergence is still not achieved, the corresponding memory channel will be marked as a forced calibration state and fed back to S2 to re-establish the reference path, and finally output a stable read and write timing control result.

[0049] A second aspect of the present invention discloses a terminal, including a processor and a storage medium; characterized in that:

[0050] The storage medium is used to store instructions;

[0051] The processor is configured to operate according to the instructions to execute the steps of the server memory read / write timing adaptive calibration method based on dynamic latency locking as described in the first aspect.

[0052] The third aspect of the present invention discloses a computer-readable storage medium having a computer program stored thereon, characterized in that, when the program is executed by a processor, it implements the steps of the server memory read / write timing adaptive calibration method based on dynamic delay locking described in the first aspect.

[0053] The beneficial effects of the present invention are as follows: Compared with the prior art, the present invention has the following advantages:

[0054] 1. This technical solution synchronously acquires clock signals, data gating signals, and multi-dimensional states such as temperature and voltage. It extracts the sampling point offset, offset change rate, and sampling window compression evaluation value, establishes a comprehensive delay evaluation system for the propagation path, and dynamically selects the optimal locking reference path. It integrates offset trend prediction to generate high-precision dynamic phase deviation. In the delay compensation stage, coarse, medium, and fine-grained delay units are activated according to the phase deviation level. The temperature change rate, voltage fluctuation amplitude, and delay change slope induced by frequency switching are acquired in real time. The loop gain is adaptively adjusted. When the temperature drifts rapidly, the gain is automatically increased to accelerate the tracking response. When the voltage fluctuates drastically or the delay is highly sensitive to the frequency, the gain is actively suppressed to suppress overshoot oscillation. This achieves a dynamic balance between compensation speed and stability under all operating conditions.

[0055] 2. This technical solution adaptively moves the sampling window center and reconstructs the data boundary by assessing the intensity of local phase deviation. At the same time, it forces the read and write operation paths to be uniformly constrained to the same window center, eliminating the timing conflict caused by the asynchronous adjustment of the read gating path and the write data path. Relying on the recursive learning of the drift trend over a wide temperature range and the fast convergence compensation mechanism under high load burst access, the sampling window always maintains sufficient margin under frequency switching, large temperature and voltage fluctuations and heavy load conditions, keeping the bit error rate at an extremely low level for a long time and improving the high reliability of server memory read and write. Attached Figure Description

[0056] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0057] Figure 1 This is a flowchart illustrating an adaptive calibration method for server memory read / write timing based on dynamic latency locking according to the present invention. Detailed Implementation

[0058] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0059] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0060] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0061] Example 1:

[0062] like Figure 1 As shown in the figure, an adaptive calibration method for server memory read / write timing based on dynamic latency locking according to an embodiment of the present invention includes the following:

[0063] S1: Synchronously collect key electrical signals and environmental status of the memory controller, and extract sampling point offset, offset change rate and window compression evaluation value through read and write timing window and dynamic offset analysis to generate timing offset feature set;

[0064] S1 includes:

[0065] S11: A high-speed sampling unit is set on the memory controller side to synchronously acquire the clock signal, data signal and data strobe signal under the same time base at a sampling frequency higher than the memory operating frequency. The clock edge arrival time, data flip time and data strobe signal effective edge time of each channel are recorded to form the original timing signal set.

[0066] For example, in this embodiment, when the memory operating frequency is 3200 MHz, the sampling frequency is set to 25.6 to 46.5 samples per second;

[0067] S12: Based on the original timing signal set, extract the stable start time, stable end time, sampling point time and clock edge time for read and write operations respectively, and perform a real and usable sampling margin analysis to obtain the effective sampling window width, which is output as the read and write timing monitoring result;

[0068] For example, in this embodiment, the effective sampling window width depends on factors such as the data stabilization start time, data stabilization end time, setup time requirement, hold time requirement, clock jitter, and data jitter. Generally, it is the remaining portion after deducting the setup time requirement, hold time requirement, clock jitter, and data jitter from the total duration of data stabilization. The total duration of data stabilization is determined by subtracting the start time from the data stabilization end time; setup and hold times are usually small, fixed amounts, and the more they are used, the smaller the remaining width; the greater the clock jitter and data jitter, or the more severe their combined effect, the narrower the final effective width. In short, this width reflects the actual time margin available for reliable reading during actual sampling.

[0069] S13: Synchronously collect memory chip temperature status, memory controller temperature status, power supply voltage status, operating frequency status and frequency switching status, and then bind them to the corresponding read and write timing monitoring results according to the sampling timestamp, generating a set of read and write timing states with environmental tags for each set of timing states, each carrying temperature, voltage and frequency conditions.

[0070] It should be noted that, in this embodiment, the temperature status of the memory chip is obtained from the onboard temperature sensor; the temperature status of the memory controller is obtained from the memory module temperature register; the power supply voltage status is obtained from the power management chip; and the operating frequency status is read from the memory controller configuration register.

[0071] S14: Based on the read / write timing state set, analyze the offset of the actual sampling point relative to the center of the sampling window to describe the current deviation direction and magnitude, analyze the offset change rate between adjacent detection cycles to describe the timing drift speed, and analyze the window compression degree in combination with the temperature, voltage and frequency deviation based on the initial calibration window to obtain a unified sampling window compression evaluation value. Then, the three together constitute the timing offset feature set.

[0072] For example, in this embodiment, the offset of the sampling window center represents the degree of deviation of the actual sampling time from the center position of the sampling window. The center position of the window is determined by both the start and end times of data stabilization, and is approximately located in the middle of the two. If the actual sampling time is later than this center, the offset is positive, indicating that the sampling point is biased towards the rear edge of the window; if the actual sampling time is earlier than the center, the offset is negative, indicating that the sampling point is biased towards the front edge of the window. The larger the absolute value of the offset, the farther the sampling point is from the window center, and the worse the sampling reliability.

[0073] The offset change rate describes how quickly the sampling point offset changes over time. It depends on the magnitude of the offset change between two adjacent detection cycles and the time interval between the end times of these two cycles. Generally, the greater the change in offset measured in the current cycle compared to the previous cycle, and the closer the end times of the two cycles are, the higher the change rate; conversely, the smaller the change or the longer the time interval, the lower the change rate.

[0074] The sampling window compression evaluation value comprehensively reflects the degree of reduction in the sampling window width and the impact of environmental disturbances. The level of the sampling window compression evaluation value is determined by two aspects, as follows: The first aspect is the reduction range of the window itself. Generally speaking, taking the sampling window width in the initial calibration state as a reference, the larger the reduction ratio, the tighter the available margin, and the higher the basic level of compression risk.

[0075] The second level is the degree to which the operating environment deviates from the nominal operating conditions, which amplifies the aforementioned basic risks. Specifically, the greater the temperature deviation from the rated temperature, the greater the proportion of voltage deviation from the rated voltage, or the greater the proportion of operating frequency deviation from the rated frequency, the higher the risk amplification factor. Each of the three environmental factors has a sensitivity coefficient: the temperature coefficient determines the contribution of each degree Celsius deviation to the risk, the voltage coefficient determines the weight of the impact of the voltage deviation proportion, and the frequency coefficient determines the intensity of the effect of the frequency deviation proportion.

[0076] Taken together, the sampling window compression evaluation value essentially correlates the physical reduction of the sampling window with environmental disturbances in three dimensions: temperature, voltage, and frequency. This transforms a single indicator that originally only reflected changes in the sampling window width into a feature quantity that can comprehensively express temporal risk. A higher sampling window compression evaluation value means that, under the current environmental conditions, the degree of strain on the sampling window and the temporal risk are greater.

[0077] S2: Based on the timing offset feature set, by establishing a dynamic delay-locked reference path, the real-time phase difference between the clock and data is analyzed, and combined with the sampling window center deviation and offset trend prediction, dynamic phase deviation results are synthesized.

[0078] S2 includes:

[0079] S21: Classify the timing offset feature set according to memory channel number, read / write direction, current operating frequency and sampling window compression evaluation value, record the clock propagation time, data propagation time and data gating signal propagation time of each channel respectively, and combine jitter margin and window compression calculation to obtain the comprehensive delay evaluation value of propagation path, and form the memory channel propagation path mapping result of channel-frequency-read / write mode-propagation path;

[0080] It should be noted that, in this embodiment, for read operations within the same channel, the data propagation path is based on the direction from the memory chip to the memory controller; for write operations, the data propagation path is based on the direction from the memory controller to the memory chip.

[0081] For example, in this embodiment, the propagation path comprehensive delay evaluation value is used to measure the total delay experienced by the signal along the entire propagation path. It mainly comes from the following aspects: the time required for the clock signal to travel from the starting point to the ending point (the slower the clock or the longer the path, the greater this time); the transmission time of the data signal itself (the later the data arrives, the greater this factor); the propagation time of the data strobe signal, which also contributes to the delay; and the maximum edge jitter margin within the same channel (the more severe the jitter, the greater the time margin). In addition, the previously calculated sampling window compression evaluation value also affects this total delay—the more severely the window is compressed, the higher the compression evaluation value, and according to a fixed conversion relationship, it adds an extra component to the total delay.

[0082] In summary, in this embodiment, the propagation path comprehensive delay evaluation value integrates the effects of clock path, data path, gating path, and window compression to determine whether the current channel needs to initiate stronger dynamic locking constraints.

[0083] S22: Based on the memory channel propagation path mapping results, and according to the current operating frequency and read / write mode, the stability of the path is evaluated by comprehensively considering the latency evaluation value, sampling point offset, offset change trend and jitter margin. The path with the best stability is selected as the dynamic latency locking reference path, and is dynamically updated when the frequency, window compression or read / write mode changes.

[0084] It should be noted that in this embodiment, when the operating frequency increases, the constraint on the stability of the clock edge is increased; when the sampling window compression evaluation value increases, the constraint on the data gating signal and the location of the data center is increased; when the read / write mode is switched, the data propagation path in the corresponding direction is reselected.

[0085] The path with optimal stability is determined by evaluating the reference path selection score of each reference path, comparing the reference path selection scores of each reference path, and then selecting the path with the lowest reference path selection score as the optimal path.

[0086] For example, in this embodiment, the reference path selection score is determined by four factors of varying importance. The first factor is the comprehensive delay evaluation value of the propagation path, which reflects the basic delay characteristics of the path; this factor typically carries the highest weight. The second factor is the offset of the sampling point, i.e., how far the actual sampling time deviates from the center of the window. For example, the greater the deviation, the greater the adverse impact on the score; this factor carries a medium weight. The third factor is the effect of the temporal offset change rate combined with the detection period duration. For example, the faster the offset change rate and the longer the detection period, the greater the cumulative offset change within a period, and the higher the impact on the score; this factor carries a lower weight. The fourth factor is the maximum edge jitter margin; the more severe the jitter, the worse the score; this factor also carries a medium weight. Combining these four factors according to their respective weights yields the final score for each reference path; the path with the better score is more suitable as a locking reference.

[0087] S23: After the dynamic delay lock reference path is determined, the clock arrival time, data arrival time and data strobe signal arrival time under the path are read. Based on the clock edge, the time difference between the data and the clock is corrected by the strobe signal and converted into real-time phase deviation according to the current operating frequency.

[0088] For example, in this embodiment, the real-time phase deviation is used to measure the angular deviation in time between the clock signal and the data signal. The real-time phase deviation is mainly determined by the following two time differences, and is ultimately converted into angles according to the current operating frequency, specifically:

[0089] The first time difference is the difference between the arrival time of the data signal and the arrival time of the clock signal. Generally speaking, if the data arrives later than the clock, a positive phase difference will occur; the later the arrival, the larger the phase difference. Conversely, if the data arrives earlier than the clock, the phase difference will be negative.

[0090] The second time difference is the arrival time of the data strobe signal. Generally, the data strobe signal usually accompanies the data signal and is used to indicate the valid window of the data. In practice, the arrival time of the data strobe signal often has an offset relative to the arrival time of the data signal; for example, sometimes the strobe signal arrives earlier, and sometimes later. This offset is adjusted according to a fixed correction factor (preferably ranging from 0.2 to 0.8) to adjust the aforementioned basic time difference. Specifically, if the strobe signal arrives later than the data signal, the phase difference will be increased on top of the basic difference; if it arrives earlier, part of the basic difference will be canceled out.

[0091] Combining these two time differences as described above yields a corrected total time difference. Finally, based on the current memory operating frequency, this total time difference is converted into an angle: the higher the frequency, the larger the angle corresponding to the same time difference (for example, a 1-nanosecond time difference corresponds to 360 degrees at 1 gigahertz and 720 degrees at 2 gigahertz). This converted angle is the real-time phase difference, which directly tells the system clock how many degrees it has deviated from the data, allowing the delay-locked loop to make precise adjustments.

[0092] S24: The sampling window center is determined by the start and end times of data stabilization. The deviation between the actual sampling point and the sampling window center, along with the offset change trend, is fused with the real-time phase deviation to generate a dynamic phase deviation result, which describes the offset direction and magnitude of the sampling point relative to the window center.

[0093] For example, in this embodiment, the dynamic phase deviation result is a more comprehensive dynamic phase deviation, which combines deviations from three different sources. The first source is the real-time phase difference, which represents the static or instantaneous angular difference between the clock and data. The second source is the phase amount caused by the current sampling point deviating from the window center: the farther the actual sampling time is from the window center, and the higher the current operating frequency, the larger the angle corresponding to this deviation. The third source is the prediction of future trends. For example, the faster the rate of change of timing offset and the longer the detection period, the more additional change will accumulate within one period. This change is multiplied by a correction factor and converted to angle according to frequency to obtain the estimated value of future deviation. Combining these three parts forms a dynamic phase deviation that can be used for delay adjustment, which reflects the actual sampling situation more accurately than the real-time phase difference.

[0094] S25: Encapsulate the dynamic phase deviation results according to the memory channel number, read / write mode, current operating frequency, reference path number, phase deviation magnitude, deviation direction, sampling window width, and window compression evaluation value. Based on the relationship between the absolute value of the dynamic phase deviation results and the preset stability threshold and safety threshold, mark them as slight deviation state, compensable deviation state, or forced calibration deviation state, respectively, to form a packaged dynamic phase deviation result with deviation level marking.

[0095] S3: Based on the dynamic phase deviation results, delay units of different granularities are selected according to the deviation level and the compensation amount is determined. Dynamic compensation is performed on the clock path and data path. At the same time, the loop gain is adaptively adjusted according to the delay change slope, temperature change rate and voltage fluctuation amplitude to generate the phase calibration result after delay compensation.

[0096] S3 includes:

[0097] S31: Read the phase deviation magnitude, deviation direction, current operating frequency, read / write mode, and sampling window compression evaluation value from the dynamic phase deviation result, and convert the deviation angle into the number of delay units to be called according to the frequency and the selected delay unit step size;

[0098] Simultaneously, based on the comparison between the phase deviation magnitude and the preset stability threshold and safety threshold, fine-grained, medium-grained, or coarse-grained delay units are activated in stages to form a graded control result for delay units;

[0099] The larger the phase deviation, the more units are required; the higher the operating frequency and the larger the delay unit step size, the fewer units are required.

[0100] For example, in this embodiment, the number of delay units depends on the magnitude of the phase deviation angle, the current operating frequency, and the coarseness of the selected delay unit step size. Generally speaking, the larger the phase deviation angle, the more units are required; the higher the operating frequency, the shorter the time corresponding to a single cycle, and the less time is needed to compensate for the same deviation angle, thus reducing the number of units required; the coarser the delay unit step size, the fewer units are required.

[0101] S32: Based on the phase deviation direction in the dynamic phase deviation result and the hierarchical control result of the delay unit, the total delay compensation is allocated to the clock path and the data path to obtain the clock path delay compensation and the data path delay compensation.

[0102] Simultaneously, the delay on the strobe signal side or the controller output side is adjusted preferentially according to the read / write mode.

[0103] For example, in this embodiment, the priority adjustment of the delay on the strobe signal side or the controller output side specifically means: for read operations, priority adjustment of the delay related to the data strobe signal; for write operations, priority adjustment of the data path delay on the memory controller output side.

[0104] It should be noted that the compensation amount is not applied all at once in this embodiment, but is gradually loaded according to the hierarchical control results of the delay unit, so as to better avoid the phase suddenly crossing the center of the sampling window;

[0105] For example, in this embodiment, the total delay compensation is determined by both the deviation angle and the current operating frequency. Generally, the larger the deviation angle, the more time needs to be compensated; the lower the operating frequency, the longer the time corresponding to each degree of deviation, and the greater the total compensation. Both factors together convert the angle deviation into the actual amount of time compensation that needs to be applied.

[0106] The amount of delay compensation required for the clock path depends primarily on the clock path's inherent allocation tendency, which reflects the system's dependence on clock path adjustments under normal conditions. Furthermore, the larger the total compensation amount, the greater the compensation received by the clock path. However, the degree of window compression and the rate of offset change inversely adjust this allocation result: more severe window compression means tighter sampling margins, causing the system to be more cautious in increasing clock path delays, tending to allocate more compensation tasks to the data path, thus significantly reducing the compensation received by the clock path; more drastic offset changes indicate more active data-side drift, similarly shifting the compensation focus towards the data path, further reducing the clock path's share of compensation. In other words, the clock path compensation amount is obtained by positively pulling on the total demand based on its inherent allocation share, and negatively suppressing it by window compression and the rate of offset change.

[0107] The amount of delay compensation required for the data path starts from the basic allocation tendency of the data path and increases positively with the expansion of the total compensation scale. It should be noted that, unlike the clock path, the rate of offset change has a positive driving effect on the amount of compensation for the data path—the more drastic the offset change, the heavier the compensation responsibility the data path bears, and the greater the compensation it receives. While the degree of window compression also participates in the adjustment, its effect is bidirectional: on the one hand, window compression also increases the dependence on data path adjustment; on the other hand, because the total compensation is generally limited when compression is severe, the amount of compensation for the data path will not grow uncontrollably, but will reach a dynamic equilibrium under the pull of the offset change rate and the constraint of window compression. Overall, the amount of data path compensation is set by the basic tendency and total demand, pulled upwards by the offset change rate, and then constrained by window compression, thus forming the actual amount applied.

[0108] S3 further includes:

[0109] S33: When the memory frequency changes, continuously record the change in total delay compensation and the frequency change amplitude before and after the change. Combined with the detection period interval, evaluate the sensitivity of the delay compensation to the frequency change, i.e. the delay change slope, and form a delay compensation change sequence.

[0110] For example, in this embodiment, the latency change slope is used to measure how quickly the latency compensation adjusts when the memory operating frequency changes. This can be understood as the system's sensitivity to frequency changes. The level of sensitivity depends primarily on the difference in the total latency compensation between two consecutive detection cycles. Specifically, the greater the difference, the more severe the latency fluctuations caused by frequency changes, and the higher the sensitivity. On the other hand, this sensitivity is also influenced by the combined effects of the detection cycle length and the magnitude of the frequency change: the longer the detection cycle or the larger the frequency change, the lower the system's sensitivity to each frequency change; conversely, the shorter the detection cycle and the more minute the frequency change, the higher the sensitivity. A very small fixed baseline value is preset to ensure that the sensitivity calculation remains stable, avoiding unreasonable extreme judgments when the frequency change is extremely small and the detection cycle is extremely short. In summary, a high value indicates that even small frequency changes will cause significant fluctuations in latency compensation, requiring a faster response from subsequent loop adjustments; a low value indicates that the system is less sensitive to frequency changes, allowing for relatively gentle adjustments.

[0111] If the delay compensation continues to increase unidirectionally after the frequency switch, it indicates that the current reference path is not well adapted to the new frequency, and the compensation tracking intensity needs to be strengthened.

[0112] If the delay compensation amount oscillates between positive and negative over multiple cycles, it indicates that there is overshoot in the adjustment, and a convergence basis needs to be provided for subsequent loop gain adjustment.

[0113] It should be noted that this step can identify the delay change pattern at the moment of frequency switching, avoiding the system from blindly compensating based on only one detection point, thereby reducing the risk of read and write errors in high-frequency switching scenarios.

[0114] S34: Adaptively adjust the loop gain based on the rate of temperature change, the amplitude of voltage fluctuation, and the slope of the delay change.

[0115] For example, in this embodiment, the more drastic the temperature change, the higher the loop gain is to accelerate the tracking response; the greater the voltage fluctuation or the more sensitive the delay compensation is to frequency changes, the lower the loop gain is to suppress oscillations and enable the loop to maintain stable convergence under temperature and voltage disturbances without overcompensation.

[0116] For example, in this embodiment, the loop gain determines the intensity of the loop's adjustment to timing deviations. It automatically amplifies or reduces the value based on current environmental changes, starting from a base value. Specifically, the faster the temperature changes—that is, the greater the rate of change of the difference between the current temperature and the previous detection cycle per unit time—the higher the gain will be on top of the base value, allowing the loop to track the effects of temperature drift more quickly. Conversely, the further the supply voltage deviates from the calibration value, the more the gain will be suppressed; simultaneously, the greater the slope of the delay change during frequency switching, the more the gain will be suppressed. The voltage deviation and excessive slope combine; either excessively large factor will weaken the final gain, making the loop adjustment more conservative and gradual, avoiding oscillations caused by over-adjustment.

[0117] S35: Based on the adaptive loop gain, the clock path delay compensation and data path delay compensation are actually applied, and the phase residual after compensation is re-estimated.

[0118] Simultaneously, the loaded path delay, loop gain, and delay compensation change sequence are encapsulated together as a phase calibration result.

[0119] It should be noted that in this embodiment, the actual loading process adopts a segmented update method, and the maximum compensation amount in a single detection cycle does not exceed 30% to 60% of the total delay compensation amount; when the phase residual decreases for several consecutive cycles, the current gain is maintained; when the phase residual increases in the opposite direction, the gain is immediately reduced and the compensation amount of the previous stage is rolled back.

[0120] For example, in this embodiment, the compensated phase residual represents the phase deviation that remains after compensation. It is calculated by first subtracting the phase correction portion corresponding to the total compensation amount actually applied to the clock and data paths from the original dynamic phase deviation. Specifically, the delay compensation amounts for the clock and data paths are first combined into a total time compensation value. This time compensation value is then converted into a corresponding angle according to the current operating frequency; for example, the higher the frequency, the larger the angle corresponding to the same time compensation amount. Furthermore, the adaptive loop gain is considered during the conversion process; the larger the gain, the stronger the correction effect of the same compensation amount. After removing the converted angle correction amount from the original deviation, what remains is the phase residual that was not completely eliminated after compensation.

[0121] It should be noted that the smaller the phase residual after compensation, the more accurate the current compensation strategy is.

[0122] S4: Based on the phase calibration results, continuously detect the read / write error status and sampling stability after calibration, re-extract the local phase deviation intensity, dynamically adjust the sampling window center and reconstruct the data sampling boundary accordingly, and generate the sampling window result after closed-loop stabilization.

[0123] S4 includes:

[0124] S41: Read the phase residual, path delay and loop gain in the phase calibration result, continuously perform read and write monitoring in the current memory channel, and count the number of bit errors, read and write accesses, residual offset of sampling points and data holding time within a unit detection cycle. The ratio of erroneous data bits to total detection data bits reflects the true read and write reliability after calibration, and generates read and write status detection results after calibration.

[0125] It should be noted that in this embodiment, the detection period is 0.001 seconds to 0.1 seconds; for high-load servers, the detection period is 0.001 seconds to 0.01 milliseconds to improve the response speed to sudden bit errors.

[0126] The proportion of erroneous data bits to the total detected data bits is defined as the bit error rate in this embodiment.

[0127] For example, in this embodiment, the bit error rate is determined by the number of erroneous data bits during the detection period and the total number of data bits involved in the verification. Generally speaking, the more erroneous data bits there are, the higher the bit error rate; the larger the total number of detected data bits, the more representative the statistical results are. The ratio of the two reflects the correctness of data transmission under the current calibration state.

[0128] S42: Based on the read / write status detection results after calibration, combined with the start and end times of data stabilization, the amount of clock and data jitter, and the compensated phase residual, the setup and hold time, jitter, and the time occupied by the remaining phase deviation are deducted from the data stabilization duration to obtain the actual usable sampling window width after calibration, and at the same time, it is determined whether there is still continuous drift at the clock edge.

[0129] For example, in this embodiment, the actual usable sampling window width after calibration is the portion remaining after deducting the setup time requirement, hold time requirement, clock jitter, data jitter, and the time occupied by the compensated phase residual, based on the original data stabilization duration. Generally, the larger the phase residual or the lower the operating frequency, the more time the residual occupies, and the narrower the usable window.

[0130] It should be noted that the width of this window reflects the actual situation of the sampling margin after calibration.

[0131] It should also be noted that if the bit error rate decreases but the window continues to shrink, it indicates that the calibration is only effective for a short time; if the window width is stable and the residual continues to decrease, it indicates that the delay compensation has entered a stable state.

[0132] It should also be noted that this step does not only check whether the bit error rate has decreased, but also checks whether the sampling window has widened and whether the clock edge is stable, in order to prevent the system from mistakenly judging a short-term error-free state as a long-term stable state.

[0133] S4 further includes:

[0134] S43: When the effective sampling window width after calibration is lower than the preset window lower limit, or when it shows a downward trend for multiple consecutive detection cycles, the stable start and end times, actual sampling point times and phase residuals of the data are re-extracted from the corresponding memory channel. The amplitude of the remaining phase deviation, the degree of deviation of the sampling point from the center of the window and the reduction ratio of the window relative to the initial calibration are combined into a local phase deviation intensity to determine whether the sampling window center needs to be readjusted.

[0135] For example, in this embodiment, the lower limit of the window is set to 40% to 60% of the width of the initial calibration sampling window; and the number of consecutive detection cycles is set to 3 to 8.

[0136] For example, in this embodiment, the magnitude of the local phase deviation intensity is closely related to three factors: First, the remaining phase error after compensation; the larger the error value, the greater the deviation intensity. Second, the actual sampling time depends on how far it deviates from the center of the data stability interval, and also on the memory operating frequency. For example, the greater the deviation and the higher the frequency, the more obvious the deviation. This can be understood as the phase impact being more pronounced at higher frequencies due to temporal deviations. Third, the variation in the sampling window width also plays a role: the greater the difference between the initially calibrated window width and the actual effective window width after calibration, and the larger the proportion of this difference to the initial width, the greater the deviation intensity. The magnitude of this effect is also limited by an empirical coefficient, which in this embodiment is between 0.2 and 0.8. In summary, these three factors jointly determine the final deviation intensity value.

[0137] S44: Determine the correction amount for the center of the sampling window based on the intensity of the local phase deviation.

[0138] If the actual sampling point is biased towards the leading edge of the window, the center will be moved backward;

[0139] If the actual sampling point is biased towards the rear edge of the window, then the center will be moved forward;

[0140] Subsequently, the data sampling front and back boundaries were redefined based on the center time of the reconstructed sampling window, forming the reconstructed data sampling boundary.

[0141] It should be noted that, in this embodiment, the adjustment range does not exceed 20% to 40% of the current effective window width;

[0142] For example, in this embodiment, the center of the reconstructed sampling window is mainly determined by three factors, as follows: First, the center position of the original window (i.e., the midpoint between the start and end times of data stabilization). The larger this base value, the further back the reconstructed center is usually. Second, the remaining phase residual after compensation and the current memory operating frequency. For example, the larger the residual or the lower the frequency, the further forward the reconstructed center will move; conversely, the smaller the residual and the higher the frequency, the closer the center will be to the original position. Third, the deviation of the actual sampling point from the center of the original window: if the sampling point is biased behind the original center, coupled with a pullback coefficient between 0.3 and 0.7, the reconstructed center will move further forward; conversely, if the sampling point is biased in front of the original center, the reconstructed center will move backward. In other words, the final center is the result of being pulled in different directions by both the phase residual and the sampling point offset, based on the original center.

[0143] S45: Encapsulate the reconstructed sampling window center, data sampling boundary, calibrated effective window width, bit error rate, local phase deviation intensity, and corresponding channel number, and simultaneously perform state marking to obtain the sampling window result after closed-loop stabilization.

[0144] It should be noted that, in this embodiment, the state marking specifically means: marking a closed-loop stable state when the bit error rate is lower than a preset bit error threshold, the effective sampling window width is higher than the lower limit of the window, and the local phase deviation intensity is lower than the forced reconstruction threshold; otherwise, marking it as a state to be recalibrated.

[0145] It should be noted that the bit error rate threshold is set according to the server reliability level, and in this embodiment, it is no higher than [the threshold value is missing from the original text]. to ;

[0146] S5: Based on the sampling window results, the read and write paths are uniformly constrained to the same window center. The delay locking parameter group is automatically switched according to the frequency and window margin. The wide temperature range drift trend is continuously learned and the compensation strategy is recursively updated. The sampling window boundary is quickly converged during high-load burst access, and finally a stable read and write timing control result is output.

[0147] S5 includes:

[0148] S51: Read the sampling window center, data sampling boundary, bit error rate, and local phase deviation intensity from the sampling window results after closed-loop stabilization. For the read operation path, focus on aligning the gating signal with the controller sampling point. For the write operation path, focus on aligning the controller output edge with the particle receiving window. Constrain the read and write paths to the vicinity of the same window center. Then, fuse the degree of sampling point deviation from the window center, the ratio of bit error rate to the allowable threshold, and the ratio of local deviation intensity to the allowable threshold to form a unified timing deviation evaluation value for read and write operations.

[0149] For example, in this embodiment, the unified timing deviation evaluation value for read and write comprehensively reflects the quality of the current timing control from three dimensions: the first dimension is the degree of deviation between the actual position of the sampling point and the center of the reconstructed window. The greater the deviation and the narrower the effective window, the greater the contribution of this item to the evaluation value; the second dimension is the ratio of the current bit error rate to the system's allowed bit error threshold. The more severe the bit error, the higher the evaluation value; the third dimension is the ratio of the intensity of the local phase deviation to its allowed threshold. The more prominent the local deviation, the higher the evaluation value.

[0150] By combining these three factors, a unified control evaluation index is provided, with a higher value indicating that the timing control state needs more attention.

[0151] S52: Based on the unified timing deviation evaluation value for read and write, combined with the current memory operating frequency, loop gain, and the margin of the effective window width relative to the initial calibration window, the parameter group switching judgment value is obtained to determine whether the target delay locking parameter group needs to be switched.

[0152] It should be noted that, in this embodiment, the target delay locking parameter group is selected from the preset parameter group;

[0153] The parameter set includes at least clock path delay, data path delay, data strobe signal delay, loop gain, and maximum single-cycle compensation limit.

[0154] When the frequency is higher, the deviation is greater, and the window margin is smaller, it is more inclined to choose a parameter group with a smaller fine-grained delay step. When the frequency decreases, it is permissible to use a parameter group with a larger compensation step to speed up convergence, thereby avoiding the use of the same set of parameters for all frequencies, which would lead to insufficient high-frequency compensation or excessive low-frequency adjustment.

[0155] The parameter group switching decision value is jointly determined by the loop gain, the read / write timing deviation evaluation value, the current operating frequency, and the ratio of the effective window width to the initial calibration window. Generally speaking, the higher the loop gain, the larger the deviation evaluation value, and the higher the operating frequency, the larger the decision value, meaning that the current operating condition requires switching to a parameter group with stronger constraints. The margin of the effective window width relative to the initial window acts as a suppression factor; the more sufficient the margin, the lower the decision value, and the more the system tends to maintain the current parameter group unchanged.

[0156] It should be noted that this mechanism enables the automatic upward movement of stronger parameter groups when the frequency is high, the window is tight, and the deviation is large, while maintaining stability and avoiding frequent switching when the window is wide.

[0157] S53: After selecting the target delay locking parameter group, continuously record the changes in window center, bit error rate and delay compensation amount under different temperature, voltage and frequency conditions, and recursively update the historical compensation results to obtain the updated delay compensation strategy value, and simultaneously form a dynamically updated delay compensation strategy.

[0158] It should be noted that in this embodiment, the temperature detection period is set to 1 to 10 seconds; the voltage detection period is set to 0.1 to 0.001 seconds; it should be noted that the temperature and voltage detection periods can be appropriately shortened for high-load servers.

[0159] If drift in the same direction occurs multiple times within a certain temperature range, the delay pre-compensation amount in the corresponding direction should be increased in advance.

[0160] In this embodiment, a recursive smoothing method is used to update the delay compensation strategy value. This recursive mechanism allows the strategy value to accumulate long-term trends while remaining sensitive to environmental changes.

[0161] For example, in this embodiment, the updated delay compensation strategy value mainly depends on the old strategy value before the update, the total delay compensation amount obtained this time, and the degree of deviation of the current temperature and voltage from the calibration value. Generally speaking, the old strategy value accounts for the majority of the influence in the new value, while the current compensation amount only contributes a small share; at the same time, the further the temperature deviates from the normal value or the further the voltage deviates from the calibration value, the greater the contribution of the current compensation amount will be. In other words, the new strategy value retains the stable foundation accumulated over time, and can automatically adjust according to the magnitude of changes in the current environment. For example, the more drastic the environmental changes, the more significantly the strategy value is adjusted upwards.

[0162] S54: When a sudden increase in the number of read and write accesses, a rise in the bit error rate, or a sampling window boundary approaching the lower limit is detected in a short period of time, the fast convergence adjustment is initiated by rapidly converging the compensation amount under high load, so that the compensation response under high load is accelerated but no oscillation is generated.

[0163] If the sampling point returns to the center area of ​​the effective window, the normal compensation strategy will be gradually restored.

[0164] If convergence is still not achieved, the corresponding memory channel will be marked as a forced calibration state and fed back to S2 to re-establish the reference path, and finally output a stable read and write timing control result.

[0165] For example, in this embodiment, the high-load fast convergence compensation amount is based on the updated latency compensation strategy value, and then amplified or reduced according to the load level and sampling deviation. Generally speaking, regarding load: the higher the ratio of the current read / write access count to the calibration count, the larger the compensation amount will be; the heavier the load, the faster the response. Regarding sampling deviation: the larger the time difference between the actual sampling time and the center of the reconstructed window relative to the calibrated window width, the smaller the compensation amount will be.

[0166] It should be noted that compensation is accelerated under high load, but when the sampling point deviates too far from the center of the window, the convergence compensation intensity is appropriately reduced to prevent system oscillation. The combined effect of load pull and deviation suppression makes the compensation amount respond quickly under high load and maintain stable convergence when the sampling point deviates.

[0167] Example 2:

[0168] This embodiment provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program that can be called by the processor;

[0169] The processor executes the aforementioned adaptive calibration method for server memory read / write timing based on dynamic latency locking by calling computer programs stored in memory.

[0170] This electronic device can vary considerably depending on its configuration or performance. It may include one or more Central Processing Units (CPUs) and one or more memories, wherein the memories store at least one computer program, which is loaded and executed by the processor to implement the server memory read / write timing adaptive calibration method based on dynamic latency locking provided in the above-described embodiment. The electronic device may also include other components for implementing its functions; for example, it may have wired or wireless network interfaces and input / output interfaces for data input and output. Details will not be elaborated upon in this embodiment.

[0171] Example 3:

[0172] This embodiment proposes a computer-readable storage medium on which an erasable and rewritable computer program is stored.

[0173] When a computer program runs on a computer device, it causes the computer device to perform the aforementioned adaptive calibration method for server memory read / write timing based on dynamic delay locking.

[0174] For example, computer-readable storage media can be read-only memory (ROM), random access memory (RAM), compact disc read-only memory (CD-ROM), magnetic tape, floppy disk, and optical data storage devices.

[0175] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0176] It should be understood that determining B based on A does not mean determining B solely based on A; it also means determining B based on A and / or other information.

[0177] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, as some steps may be performed in other orders or simultaneously according to this application. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this application.

[0178] It should be further noted that although the steps in the flowchart are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0179] It should be understood that the above-described device embodiments are merely illustrative, and the device of this application can also be implemented in other ways. For example, the division of units / modules in the above embodiments is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units, modules, or components may be combined, or integrated into another system, or some features may be ignored or not executed.

[0180] Furthermore, unless otherwise specified, the functional units / modules in the various embodiments of this application can be integrated into one unit / module, or each unit / module can exist physically separately, or two or more units / modules can be integrated together. The integrated units / modules described above can be implemented in hardware or as software program modules.

[0181] In the above embodiments, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0182] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0183] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope.

Claims

1. A server memory read / write timing adaptive calibration method based on dynamic latency locking, characterized in that, The method includes the following: S1: Synchronously collect key electrical signals and environmental status of the memory controller, and extract sampling point offset, offset change rate and window compression evaluation value through read and write timing window and dynamic offset analysis to generate timing offset feature set; S2: Based on the timing offset feature set, by establishing a dynamic delay-locked reference path, the real-time phase difference between the clock and data is analyzed, and combined with the sampling window center deviation and offset trend prediction, dynamic phase deviation results are synthesized. S3: Based on the dynamic phase deviation results, delay units of different granularities are selected according to the deviation level and the compensation amount is determined. Dynamic compensation is performed on the clock path and data path. At the same time, the loop gain is adaptively adjusted according to the delay change slope, temperature change rate and voltage fluctuation amplitude to generate the phase calibration result after delay compensation. S4: Based on the phase calibration results, continuously detect the read / write error status and sampling stability after calibration, re-extract the local phase deviation intensity, dynamically adjust the sampling window center and reconstruct the data sampling boundary accordingly, and generate the sampling window result after closed-loop stabilization. S5: Based on the sampling window results, the read and write paths are uniformly constrained to the same window center. The delay locking parameter group is automatically switched according to the frequency and window margin. The wide temperature range drift trend is continuously learned and the compensation strategy is recursively updated. The sampling window boundary is quickly converged during high-load burst access, and finally a stable read and write timing control result is output.

2. The server memory read / write timing adaptive calibration method based on dynamic latency locking according to claim 1, characterized in that, S1 includes: S11: A high-speed sampling unit is set on the memory controller side to synchronously acquire the clock signal, data signal and data strobe signal under the same time base, and record the clock edge arrival time, data flip time and data strobe signal effective edge time of each channel to form the original timing signal set. S12: Based on the original timing signal set, extract the stable start time, stable end time, sampling point time and clock edge time for read and write operations respectively, and perform a real and usable sampling margin analysis to obtain the effective sampling window width, which is output as the read and write timing monitoring result; S13: Synchronously collect memory chip temperature status, memory controller temperature status, power supply voltage status, operating frequency status and frequency switching status, and then bind them to the corresponding read and write timing monitoring results according to the sampling timestamp, generating a set of read and write timing states with environmental tags for each set of timing states, each carrying temperature, voltage and frequency conditions. S14: Based on the read / write timing state set, analyze the offset of the actual sampling point relative to the center of the sampling window, analyze the offset change rate between adjacent detection cycles, and analyze the window compression degree in combination with the temperature, voltage and frequency deviations based on the initial calibration window to obtain a unified sampling window compression evaluation value. Then, the three together constitute the timing offset feature set.

3. The server memory read / write timing adaptive calibration method based on dynamic latency locking according to claim 2, characterized in that, S2 include: S21: Classify the timing offset feature set according to memory channel number, read / write direction, current operating frequency and sampling window compression evaluation value, record the clock propagation time, data propagation time and data gating signal propagation time of each channel respectively, and combine jitter margin and window compression calculation to obtain the comprehensive delay evaluation value of propagation path, and form the memory channel propagation path mapping result of channel-frequency-read / write mode-propagation path; S22: Based on the memory channel propagation path mapping results, and according to the current operating frequency and read / write mode, the stability of the path is evaluated by comprehensively considering the latency evaluation value, sampling point offset, offset change trend and jitter margin. The path with the best stability is selected as the dynamic latency locking reference path, and is dynamically updated when the frequency, window compression or read / write mode changes. S23: After the dynamic delay lock reference path is determined, the clock arrival time, data arrival time and data strobe signal arrival time under the path are read. Based on the clock edge, the time difference between the data and the clock is corrected by the strobe signal and converted into real-time phase deviation according to the current operating frequency. S24: Determine the center of the sampling window based on the start and end times of data stability, and combine the deviation between the actual sampling point and the center of the sampling window with the offset change trend, and integrate them with the real-time phase deviation to generate a dynamic phase deviation result. S25: Encapsulate the dynamic phase deviation results according to the memory channel number, read / write mode, current operating frequency, reference path number, phase deviation magnitude, deviation direction, sampling window width, and window compression evaluation value. Based on the relationship between the absolute value of the dynamic phase deviation results and the preset stability threshold and safety threshold, mark them as slight deviation state, compensable deviation state, or forced calibration deviation state, respectively, to form a packaged dynamic phase deviation result with deviation level marking.

4. The server memory read / write timing adaptive calibration method based on dynamic latency locking according to claim 3, characterized in that, S3 include: S31: Read the phase deviation magnitude, deviation direction, current operating frequency, read / write mode, and sampling window compression evaluation value from the dynamic phase deviation results, and convert the deviation angle into the number of delay units according to the frequency and the selected delay unit step size; Simultaneously, based on the comparison between the phase deviation magnitude and the preset stability threshold and safety threshold, fine-grained, medium-grained, or coarse-grained delay units are activated in stages to form a graded control result for delay units; S32: Based on the phase deviation direction in the dynamic phase deviation result and the hierarchical control result of the delay unit, the total delay compensation is allocated to the clock path and the data path to obtain the clock path delay compensation and the data path delay compensation. Simultaneously, the delay on the strobe signal side or the controller output side is adjusted preferentially according to the read / write mode.

5. The server memory read / write timing adaptive calibration method based on dynamic latency locking according to claim 4, characterized in that, S3 also includes: S33: When the memory frequency changes, continuously record the change in total delay compensation and the frequency change amplitude before and after the change. Combined with the detection period interval, evaluate the sensitivity of the delay compensation to the frequency change, i.e. the delay change slope, and form a delay compensation change sequence. S34: Adaptively adjust the loop gain based on the rate of temperature change, the amplitude of voltage fluctuation, and the slope of the delay change. S35: Based on the adaptive loop gain, the clock path delay compensation and data path delay compensation are actually applied, and the phase residual after compensation is re-estimated. Simultaneously, the loaded path delay, loop gain, and delay compensation change sequence are encapsulated together as a phase calibration result.

6. The server memory read / write timing adaptive calibration method based on dynamic latency locking according to claim 5, characterized in that, S4 includes: S41: Read the phase residual, path delay and loop gain in the phase calibration result, continuously perform read and write monitoring in the current memory channel, and count the number of bit errors, read and write accesses, residual offset of sampling points and data holding time within a unit detection cycle. The ratio of erroneous data bits to total detection data bits reflects the true read and write reliability after calibration, and generates read and write status detection results after calibration. S42: Based on the read / write status detection results after calibration, combined with the start and end times of data stabilization, the amount of clock and data jitter, and the compensated phase residual, the setup and hold time, jitter, and the time occupied by the remaining phase deviation are deducted from the data stabilization duration to obtain the actual usable sampling window width after calibration, and at the same time, it is determined whether there is still continuous drift at the clock edge.

7. The server memory read / write timing adaptive calibration method based on dynamic latency locking according to claim 6, characterized in that, S4 also includes: S43: When the effective sampling window width after calibration is lower than the preset window lower limit, or when it shows a downward trend for multiple consecutive detection cycles, the stable start and end times, actual sampling point times and phase residuals of the data are re-extracted from the corresponding memory channel. The amplitude of the remaining phase deviation, the degree of deviation of the sampling point from the center of the window and the reduction ratio of the window relative to the initial calibration are combined into a local phase deviation intensity to determine whether the sampling window center needs to be readjusted. S44: Determine the correction amount for the center of the sampling window based on the intensity of the local phase deviation. If the actual sampling point is biased towards the leading edge of the window, the center will be moved backward; If the actual sampling point is biased towards the rear edge of the window, then the center will be moved forward; Subsequently, the data sampling front and back boundaries were redefined based on the center time of the reconstructed sampling window, forming the reconstructed data sampling boundary. S45: Encapsulate the reconstructed sampling window center, data sampling boundary, calibrated effective window width, bit error rate, local phase deviation intensity, and corresponding channel number, and simultaneously perform state marking to obtain the sampling window result after closed-loop stabilization.

8. The server memory read / write timing adaptive calibration method based on dynamic latency locking according to claim 7, characterized in that, S5 include: S51: Read the sampling window center, data sampling boundary, bit error rate, and local phase deviation intensity from the sampling window results after closed-loop stabilization. For the read operation path, focus on aligning the gating signal with the controller sampling point. For the write operation path, focus on aligning the controller output edge with the particle receiving window. Constrain the read and write paths to the vicinity of the same window center. Then, fuse the degree of sampling point deviation from the window center, the ratio of bit error rate to the allowable threshold, and the ratio of local deviation intensity to the allowable threshold to form a unified timing deviation evaluation value for read and write operations. S52: Based on the unified timing deviation evaluation value for read and write, combined with the current memory operating frequency, loop gain, and the margin of the effective window width relative to the initial calibration window, the parameter group switching judgment value is obtained to determine whether the target delay locking parameter group needs to be switched. S53: After selecting the target delay locking parameter group, continuously record the changes in window center, bit error rate and delay compensation amount under different temperature, voltage and frequency conditions, and recursively update the historical compensation results to obtain the updated delay compensation strategy value, and simultaneously form a dynamically updated delay compensation strategy. S54: When a sudden increase in the number of read and write accesses, a rise in the bit error rate, or a sampling window boundary approaching the lower limit is detected in a short period of time, the fast convergence adjustment is initiated by rapidly converging the compensation amount under high load, so that the compensation response under high load is accelerated but no oscillation is generated. If the sampling point returns to the center area of ​​the effective window, the normal compensation strategy will be gradually restored. If convergence is still not achieved, the corresponding memory channel will be marked as a forced calibration state and fed back to S2 to re-establish the reference path, and finally output a stable read and write timing control result.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements a server memory read / write timing adaptive calibration method based on dynamic delay locking as described in any one of claims 1-8.

10. An electronic device, characterized in that, include: Memory, used to store instructions; A processor is configured to execute the instructions, causing the device to perform operations implementing the server memory read / write timing adaptive calibration method based on dynamic latency locking as described in any one of claims 1-8.

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