An analysis processing platform for server running parameters

Abstract

The application relates to the computer technical field and discloses an analysis and processing platform for server running parameters, which comprises a resource topology construction module, a sensor effectiveness flag bit and a reliability weight factor are generated; a state and load collection module, node identification is extracted and bottom layer load data sequences are collected; a residual error calculation module, physical temperature after time delay compensation is generated by compensating thermal response delay, and standardized residual error sequences are extracted; a matrix evaluation and judgment module, a maximum lag similarity is calculated by flattening a matrix, and an effective abnormal state is output; a sampling and analysis output module, a dynamic context snapshot is spliced, and a cross-node page residence correlation call link diagram is output. The application eliminates time lag deviation caused by physical thermal capacity through time sequence alignment processing, accurately identifies an effective abnormal state by combining bottom layer state checking to exclude interference, triggers state machine switching, completes context snapshot splicing without locking, and outputs a call link diagram to realize reverse tracing.

Description

Technical Field

[0001] This invention relates to the field of computer technology, specifically to a platform for analyzing and processing server operating parameters. Background Technology

[0002] With the increasing computing density of servers, non-uniform memory access architectures are widely used in various data centers. Monitoring and analyzing server operating parameters is crucial for ensuring system stability. Existing server monitoring solutions collect temperature sensor data and software-level load data independently and perform simple correlation analysis. However, due to the thermal capacity of physical components such as chip packaging materials and heat sinks, changes in physical temperature objectively lag behind sudden increases in software execution load. Current technologies lack compensation mechanisms for this thermal response delay and do not perform timing alignment processing, resulting in the inability to establish an accurate timing correspondence between software execution load and the underlying physical thermal response, thus leading to low accuracy in extracting thermal response residuals.

[0003] In complex, non-uniform memory access architectures, cross-node resource allocation and scheduling can lead to deep resource contention and parameter fluctuations. Existing anomaly detection mechanisms are relatively simplistic and fail to combine the node's topology with effective sensor flags and reliability weighting factors for comprehensive judgment. In actual server operation, routine hardware errors or fluctuations in external environmental factors can easily interfere with monitoring data, making it difficult for existing tools to accurately identify truly valid anomalies, resulting in a high false alarm rate in system monitoring.

[0004] When servers exhibit abnormal operating parameters, existing diagnostic tools typically employ locking mechanisms to capture system context information. This intrusive operation directly blocks underlying normal business logic, impacting business continuity. Lacking a lock-free recording mechanism based on state machine transitions, current methods struggle to fully preserve and stitch together dynamic context snapshots before and after the anomaly. Furthermore, existing tools lack the capability to perform symbolic reverse parsing on the underlying data, failing to map the collected data back into an intuitive cross-node page-resident association call chain diagram. This makes it difficult for operations personnel to accurately trace the specific software call logic that triggered the abnormal server operating parameters, resulting in low troubleshooting efficiency. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a server operation parameter analysis and processing platform, which solves the problems of inaccurate data timing correlation due to physical thermal response lag, high false alarm rate caused by complex architecture and environmental interference, and data capture operations blocking normal business and difficulty in tracing back to the underlying software call logic in existing monitoring technologies.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides a platform for analyzing and processing server operating parameters, comprising:

[0008] The resource topology construction module is used to read hardware description data to establish a topology matrix and generate sensor validity flags and reliability weight factors for non-uniform memory access nodes.

[0009] The status and load acquisition module is used to extract the page fault execution node identifier and the page resident node identifier to calculate the cross-node page fault rate, and to calculate the physical memory throughput by combining the hardware performance counter and the mapping relationship in the topology matrix, so as to collect the underlying load data sequence containing the cross-node page fault rate and the physical memory throughput.

[0010] The residual calculation module is used to receive the underlying load data sequence and read out-of-band temperature sensor data, perform timing alignment processing and compensate for the thermal response delay of the components, extract the original thermal response residual by combining the power consumption temperature baseline model, and generate processor-standardized residual sequence and memory-standardized residual sequence.

[0011] The matrix evaluation and judgment module is used to generate a processor two-dimensional feature matrix and a memory two-dimensional feature matrix based on the sensor validity flag, the reliability weight factor, the processor standardized residual sequence, and the memory standardized residual sequence; calculate the corrected maximum hysteresis similarity; read the underlying hardware state and perform joint verification of the underlying hardware state; and output a valid abnormal state in combination with the joint verification result when the mean squared residual of the unit elements of the processor two-dimensional feature matrix and the memory two-dimensional feature matrix is ​​greater than a preset abnormal mean squared residual threshold, and the corrected maximum hysteresis similarity meets the similarity judgment threshold requirement determined according to the joint verification result.

[0012] The sampling and analysis output module is used to, after receiving the valid abnormal status, splice a dynamic context snapshot containing the instruction address sequence, the page fault execution node identifier, and the page-resident node identifier, perform symbolic reverse parsing on the instruction address sequence, and output a cross-node page-resident association call chain graph.

[0013] Preferably, the resource topology construction module obtains the three-dimensional physical distance from the chassis air inlet to the non-unified memory access node on the specified airflow path, and calculates the thermal interference constant caused by the influence of adjacent non-unified memory access nodes on the non-unified memory access node in combination with the horizontal partition and upstream and downstream relationship. The adjacent non-unified memory access node is located on the same airflow path as the non-unified memory access node, or is determined according to the horizontal partition, upstream and downstream relationship and three-dimensional physical distance.

[0014] The resource topology construction module extracts the real-time rotation speed of the system cooling fan and converts it into the air duct reference wind speed ratio. Based on the relationship between the three-dimensional physical distance and the air duct reference wind speed ratio, it establishes an attenuation model. Combining the sensor validity flag and the thermal interference constant, it calculates the reliability weight factor and performs threshold constraint and normalization processing on the reliability weight factor, mapping it to the topology relationship matrix.

[0015] Preferably, the status and load acquisition module deploys a customized kernel trace point or a dedicated kernel probe module within the physical page allocation success return path in the operating system kernel page fault exception handling path. It obtains the page fault execution node identifier by extracting the processor's scheduling context and extracts the page resident node identifier by parsing the page descriptor, and simultaneously obtains the page fault type and the corresponding process and thread information.

[0016] When the values ​​of the page fault execution node identifier and the page resident node identifier are not equal, the status and load acquisition module records the cross-node access behavior as a cross-node page mapping event, accumulates the number of cross-node page faults and the number of local node page faults within the set sampling time window, and calculates the total number of page fault exceptions and the cross-node page fault rate.

[0017] Preferably, the status and load acquisition module extracts the number of read transaction bus cycles and the number of write transaction bus cycles from the hardware performance counter, calculates the underlying throughput of the memory controller by combining the system cache line specifications, and accumulates and aggregates the data using the mapping relationship in the topology matrix to obtain the physical memory throughput.

[0018] The status and load acquisition module extracts the total change in the number of context switches according to the scheduling statistics of the non-uniform memory access nodes, divides it by the set sampling time window to calculate the context switch frequency, and combines the cross-node page fault rate, the physical memory throughput and the context switch frequency into the underlying load data sequence.

[0019] Preferably, the residual calculation module reads the out-of-band temperature sensor data of the physical sensor through the out-of-band network channel, adds a system receiving timestamp to the out-of-band temperature sensor data, identifies the time tolerance between two consecutive updates of the out-of-band temperature sensor data, performs time alignment processing, and uses the delayed backtracking alignment mode to map the sampled values ​​of discrete periods to a continuous time axis to generate a synchronous temperature sequence.

[0020] The residual calculation module uses the thermal response delay compensation formula to perform advanced phase compensation on the synchronous temperature sequence, eliminating the time lag caused by the chip packaging material and the heat capacity of the external heat sink, and calculates the processor physical temperature and memory physical temperature in the physical temperature after time delay compensation.

[0021] Preferably, the residual calculation module extracts the context switching frequency from the underlying load data sequence, combines the processor's packaged power consumption data and inlet air temperature data, and substitutes them into the processor's multiple linear regression model to calculate the processor's baseline expected temperature. It also extracts the cross-node page fault rate and physical memory throughput from the underlying load data sequence, combines them with the inlet air temperature data, and substitutes them into the memory's multiple linear regression model to calculate the memory's baseline expected temperature.

[0022] The residual calculation module extracts the processor physical temperature and memory physical temperature from the physical temperature after delay compensation, subtracts the processor baseline expected temperature from the processor physical temperature, and subtracts the memory baseline expected temperature from the memory physical temperature, thereby calculating the original thermal response residual.

[0023] The residual calculation module collects the set of original thermal response residuals by maintaining a sliding time window, calculates the median and absolute median difference of the original thermal response residuals, and outputs the processor-standardized residual sequence and the memory-standardized residual sequence after dimensionless standardization of the absolute median difference.

[0024] Preferably, the matrix evaluation and judgment module uses the sensor validity flag to remove nodes that indicate an invalid state, and combines the reliability weighting factor to weight and map the processor standardized residual sequence and the memory standardized residual sequence into the processor two-dimensional feature matrix and the memory two-dimensional feature matrix, respectively.

[0025] The matrix evaluation and judgment module traverses the discrete lag step intervals in the evaluation mode that allows for delayed backtracking, extracts the coupling features with physical time sequence lag offsets, and calculates the spatial two-dimensional cosine similarity and the corrected maximum lag similarity.

[0026] Preferably, the matrix evaluation and judgment module reads the error status and power limit flag of the underlying hardware as hardware status and heat dissipation parameters, extracts the actual speed and target speed of the cooling fan configured in the heat dissipation system to calculate the fan speed deviation, and extracts the inlet air temperature change rate to perform the joint verification of the underlying hardware status.

[0027] Under the premise that the underlying hardware does not find a hardware error state of the preset type, and the rate of change of the intake air temperature is less than or equal to the intake air temperature mutation threshold and the fan speed deviation is less than or equal to the speed deviation threshold, when the mean squared residual of the unit elements of the processor two-dimensional feature matrix and the memory two-dimensional feature matrix are both greater than the preset abnormal mean squared residual threshold, and when there is no power limit flag, the corrected maximum hysteresis similarity is greater than the preset similarity judgment threshold, or when there is a power limit flag, the corrected maximum hysteresis similarity is greater than the temporarily increased similarity judgment threshold, the matrix evaluation and judgment module confirms and outputs the valid abnormal state.

[0028] Preferably, during normal operation, the sampling and analysis output module cyclically writes historical stack records into the user-mode main loop buffer that maintains the pre-allocated capacity limit. Upon receiving the valid abnormal state, the internal state machine of the sampling and analysis output module is triggered to switch to the snapshot retention state and activate the backup loop buffer. The user-mode main loop buffer is locked to stop overwriting, and the write pointer of the receiving thread is atomically redirected to the backup loop buffer with the same capacity as the user-mode main loop buffer. The post-abnormal delay timer is started synchronously.

[0029] When the post-abnormal delay timer expires, the sampling and analysis output module extracts the historical stack records in the user-mode main loop buffer and the newly added stack records in the spare loop buffer, aligns and splices them on the timeline to generate the dynamic context snapshot.

[0030] Preferably, the sampling and analysis output module loads the operating system kernel symbol table and the debugging information file of the user-mode application, performs range matching search on the binary instruction address in the persistent dynamic context snapshot, extracts the number of the non-uniform memory access node where the execution thread is located and the number of the non-uniform memory access node where the corresponding accessed physical memory page is located, and establishes a cross-node affinity mapping relationship.

[0031] The sampling and analysis output module calculates the topological edge weights between adjacent caller functions and callee functions, compares and filters them using a preset topological edge trimming threshold, and performs aggregation based on the extracted cross-node affinity mapping relationship to generate a call topological data set. The non-empty call topological data set after trimming with the topological edge trimming threshold is rendered as the cross-node page dwell association call link graph.

[0032] This invention provides a platform for analyzing and processing server operating parameters, which has the following beneficial effects:

[0033] 1. This invention performs timing alignment processing and compensates for thermal response delay through the residual calculation module, generates the physical temperature after time delay compensation, and extracts the original thermal response residual by combining the underlying load data sequence collected by the state and load acquisition module. This eliminates the time lag deviation caused by the thermal capacity of physical components, establishes an accurate timing correspondence between the software execution load and the underlying physical thermal response, and improves the accuracy of standardized residual sequence extraction.

[0034] 2. This invention utilizes the sensor validity flag and reliability weight factor generated by the resource topology construction module to weight and flatten the standardized residual sequence into a processor two-dimensional feature matrix and a memory two-dimensional feature matrix. Combined with the matrix evaluation and judgment module, the maximum lag similarity is calculated and the underlying hardware status is jointly verified. This eliminates interference caused by conventional hardware errors and environmental fluctuations, and can accurately identify valid abnormal states caused by deep resource competition under non-unified memory access architecture, effectively reducing the false alarm rate of system monitoring.

[0035] 3. Upon receiving a valid abnormal state, the sampling and analysis output module of this invention triggers a state machine switch in the buffer. In a lock-free state, it completes the stitching of dynamic context snapshots before and after the abnormality occurs, avoiding the blocking of the underlying normal business logic during the data collection process. Combined with symbol reverse resolution operation, it restores the underlying binary address mapping and finally outputs a cross-node page-resident association call chain diagram, enabling operation and maintenance personnel to intuitively and accurately trace back the specific software call logic that caused the abnormal server operating parameters. Attached Figure Description

[0036] Figure 1 This is a structural block diagram of the server operation parameter analysis and processing platform of the present invention;

[0037] Figure 2 This is a flowchart illustrating the overall process for analyzing and processing server operating parameters according to the present invention.

[0038] Figure 3 A flowchart illustrating the sub-steps of initializing the heterogeneous hardware resource topology model in this invention;

[0039] Figure 4 This is a flowchart of the sub-steps for collecting execution status and load in this invention;

[0040] Figure 5 A flowchart illustrating the sub-steps for generating standardized residual sequences in this invention;

[0041] Figure 6 This is a flowchart of the sub-steps for performing matrix evaluation and joint verification in this invention;

[0042] Figure 7 The flowchart of the sub-steps for preserving on-site data and generating the call chain diagram in this invention;

[0043] Figure 8 This is a comparison chart of the processor temperature delay compensation and baseline of the present invention;

[0044] Figure 9 This is a similarity evaluation diagram for the discrete lag step size interval of the present invention. Detailed Implementation

[0045] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0046] See attached document Figure 1 The present invention provides a platform for analyzing and processing server operating parameters, including a resource topology construction module, a status and load acquisition module, a residual calculation module, a matrix evaluation and judgment module, and a sampling and analysis output module.

[0047] The resource topology building module is used to read advanced configuration and power interface data, System Management BIOS (SMBIOS) data, and baseboard management controller configuration information. The module establishes a topology matrix including physical memory slots, voltage regulation modules, and non-uniform memory access nodes, and generates sensor validity flags for each non-uniform memory access node.

[0048] The status and load acquisition module is used to set dynamic mount points in the operating system kernel page fault handling path and extract page fault execution node identifiers and page resident node identifiers. The status and load acquisition module utilizes the processor non-core performance monitoring unit to collect physical memory throughput within a set sampling time window and simultaneously acquires context switching frequency data.

[0049] The residual calculation module receives the underlying load data sequence output by the status and load acquisition module, as well as out-of-band temperature sensor data. It then appends the system receiving timestamp and performs timing alignment processing, as well as compensates for the thermal response delay of the components. The residual calculation module calculates the original thermal response residual using a preset power consumption temperature baseline model and performs dimensionless standardization of the original thermal response residual using a sliding time window.

[0050] The matrix evaluation and judgment module flattens the standardized residual sequence into a processor two-dimensional feature matrix and a memory two-dimensional feature matrix based on the sensor validity flag. Within a sliding time window and hysteresis step interval, the module calculates the corrected maximum hysteresis similarity and, combined with the underlying hardware status joint verification results, outputs the resource contention bottleneck confirmation result.

[0051] During normal platform operation, the sampling and analysis output module is in a normal recording state, storing the underlying stack data into the user-mode main loop buffer. Upon receiving an anomaly trigger signal from the matrix evaluation and judgment module, the sampling and analysis output module switches to snapshot retention state, performs state locking on the user-mode main loop buffer, activates the backup loop buffer to start an anomaly delay timer, and then performs asynchronous disk write and symbol reverse resolution operations.

[0052] See attached document Figure 2 This invention provides a method for analyzing and processing server operating parameters, comprising the following steps:

[0053] S10, the resource topology construction module acquires multi-source hardware information, initializes the heterogeneous hardware resource topology model, and establishes the reliability weight factors and spatial correlation relationships of each physical sensor inside the server.

[0054] S20, the status and load acquisition module collects hardware performance counter data and captures page mapping events across nodes through custom kernel tracepoints or dedicated kernel modules;

[0055] S30, the residual calculation module receives the sampled value from the out-of-band temperature sensor, adds the system receiving timestamp and performs timing alignment processing, compensates for the thermal response delay of the components, and generates a continuous processor-normalized residual sequence and a memory-normalized residual sequence.

[0056] S40, the matrix evaluation and judgment module flattens the standardized residual sequence into a two-dimensional feature matrix, calculates the maximum hysteresis similarity between the processor's two-dimensional feature matrix and the memory's two-dimensional feature matrix in the discrete hysteresis step interval, and verifies the error status, fan speed deviation and power limit flag of the server's underlying hardware in parallel.

[0057] S50, after meeting the similarity judgment threshold requirements and passing all pre-filter verifications, the platform triggers the internal state machine of the sampling and analysis output module to switch to the snapshot retention state, retaining the stack data before and after the anomaly occurred, performing aggregation based on cross-node affinity mapping relationship, and outputting a cross-node page dwell association call chain diagram containing source code-level diagnostic evidence.

[0058] To enable those skilled in the art to better understand the present invention, the following will elaborate on the technical details and specific implementation logic of the above-mentioned system operation and method execution process.

[0059] See attached document Figure 3 In the analysis and processing method provided by the present invention, step S10 is mainly executed by the resource topology construction module, which can be achieved by the following sub-steps to initialize the heterogeneous hardware resource topology model.

[0060] S11, the resource topology construction module performs multi-source hardware information reading and preliminary parsing operations. This step aims to obtain multi-source low-level hardware description data to provide basic input for constructing the global topology map. The hardware description data includes at least one of the following: advanced configuration and power interface data, system management SMBIOS data, baseboard management controller configuration information, and operating system virtual file system node information.

[0061] The resource topology construction module reads the server's underlying high-level configuration and power interface data, system management SMBIOS data, and baseboard management controller configuration information. Hardware description information from a single data source typically cannot fully cover the server's underlying physical mapping. The resource topology construction module extracts the logical mapping relationship between processor logical cores and non-uniform memory access nodes by parsing the operating system's virtual file system node information.

[0062] For parsing the memory device type table in the system management SMBIOS data and the system resource affinity table in the advanced configuration and power interface data, those skilled in the art can use standard firmware protocol reading methods. The underlying structure parsing and feature bit extraction mechanisms are well-known technologies in the field and will not be elaborated here.

[0063] S12, the resource topology construction module establishes a quantified topology relationship matrix based on the acquired multi-source hardware information. This step integrates discrete hardware physical attributes and logical attribution relationships into a unified mathematical model.

[0064] The resource topology construction module establishes a topology matrix including physical memory slots, voltage regulation modules, and non-uniform memory access nodes. The system physical and logical topology diagram is defined as follows: In the formula, It represents a set of nodes, specifically including logical processors, non-uniform memory access nodes, memory controllers, physical memory slots, voltage regulation modules, and temperature sensors.

[0065] It represents the set of connection relationships, specifically including the logical affiliation between the processor logic core and non-uniform memory access nodes, the power supply relationship between the voltage regulation module and the core components, the heat dissipation airflow influence relationship between the fan and the temperature sensor, and the address interleaving mapping relationship between physical memory slots. This represents the edge relationship weight matrix corresponding to the above connection relationship, used to quantify the strength of the physical association between nodes. This represents the set of confidence levels assigned when different underlying data sources are merged.

[0066] To handle conflicts between different data sources, when there are inconsistencies in node mapping between system management SMBIOS data and advanced configuration and power interface data, the resource topology building module prioritizes merging based on the hardware direct-connect topology in the system management SMBIOS data. During data source merging, the confidence set... The initial values ​​are calculated and allocated based on the reliability level of the data source. For example, high confidence weights are assigned to hardware underlying firmware data sources, while medium confidence weights are assigned to operating system virtual file node data.

[0067] S13, the resource topology construction module generates sensor validity flags for each non-uniform memory access node. This step is mainly used to establish the reliability weight factors and spatial correlation of each physical sensor inside the server.

[0068] A server's physical architecture typically consists of multiple nodes. Assume the server contains a total of... Each non-uniform memory access node. ,in The resource topology construction module retrieves data from the sensor data record table in the baseboard management controller, and identifies nodes with non-uniform memory access. The bound temperature sensor identifier is used to assess the integrity of temperature sensor coverage and the independence of spatial mapping within the node area, and to generate a sensor validity flag representing the binary state of the node. This establishes the presence and independence of the sensor. Furthermore, to quantify accuracy interference, corresponding sensor confidence coefficients are generated simultaneously. .

[0069] In step S14, the resource topology construction module assigns specific values ​​to the sensor validity flags based on hardware spatial distribution rules. This step addresses the accuracy interference and monitoring blind spots of physical sensors in complex heat dissipation ducts through a quantized allocation method.

[0070] When determining non-uniform memory access nodes based on sensor data logging tables When a temperature sensor is provided that is independent and not thermally coupled to other nodes, the resource topology building module sets the sensor validity flag. And the sensor confidence coefficient When the temperature sensor of a node is shared by multiple adjacent nodes, or when the node's physical location is downstream of the fan exhaust duct and affected by crossflow from the duct, the sensor validity flag is set. And the sensor confidence coefficient The value ranges from 0.3 to 0.7. The specific confidence coefficient value here is set based on the thermodynamic crosstalk influence coefficient set in the original equipment manufacturer (OEM) device configuration file or the board management controller's factory configuration. During factory testing, a standard thermal load is applied to adjacent nodes, and the temperature offset amplitude of the target node's sensor is measured. The larger the offset amplitude, the lower the confidence coefficient. This is obtained by establishing a mapping example table between temperature offset amplitude and confidence coefficient. If the non-uniform memory access node has no temperature sensor coverage, the sensor validity flag is set. And the sensor confidence coefficient This assignment mechanism provides spatial weight input for subsequent thermal response residual calculations.

[0071] In the analysis and processing method provided by the present invention, the specific implementation of step S10 also includes dealing with the accuracy interference problem of physical sensors under complex heat dissipation ducts. The resource topology construction module generates reliability weight factors through the following sub-steps.

[0072] In step S15, the resource topology construction module extracts the heat dissipation airflow parameters within the non-uniform memory access node region to assess the impact of heat crossover and airflow crossover. This step quantifies the heat interference between different nodes due to their physical spatial location.

[0073] The resource topology construction module reads fan configuration data, chassis physical dimension description files, or OEM 3D airflow calibration matrices from the baseboard management controller to obtain the data from the chassis air inlet to each non-uniform memory access node. Three-dimensional physical distance along a specified air duct path The thermal interference constant between nodes is calculated by combining horizontal partitioning and upstream / downstream relationships. The resource topology construction module extracts the real-time speed of the system's cooling fans and converts the fan speed into the actual duct wind speed according to the system's preset fluid dynamics conversion ratio. Then, the actual duct wind speed is divided by the system's preset standard reference wind speed (e.g., 1 m / s) for normalization, thereby eliminating physical dimensions and obtaining a dimensionless duct reference wind speed ratio. .

[0074] For adjacent non-uniform memory access nodes, the resource topology construction module calculates the thermal interference constant between nodes. The parsing and acquisition of heat dissipation airflow parameters and physical space coordinates can be achieved by those skilled in the art using out-of-band interface queries and standard firmware parsing mechanisms; such reading operations are well-known techniques in the field and will not be elaborated upon here.

[0075] S16, the resource topology construction module combines the sensor validity flag and the degree of influence of airflow to calculate the reliability weight factor for each non-uniform memory access node. This step converts the sensor validity flags evaluated in the previous step into reliability weight factors, which are used for confidence adjustment in subsequent residual calculations.

[0076] The resource topology building module establishes an attenuation model based on the relationship between node spatial distance and wind speed, and calculates non-uniform memory access nodes. Reliability weighting factor The specific calculation formula is as follows:

[0077] ;

[0078] in, Indicates a non-uniform memory access node Reliability weighting factor; Indicates a non-uniform memory access node The sensor validity flag bit; Indicates a non-uniform memory access node The sensor confidence coefficient; The environmental convection resistance coefficient is set based on the internal wiring density and baffle configuration of the chassis, with a value ranging from 0.8 to 1.2. The specific value is obtained by referring to a table based on the pre-measured internal space obstruction rate of the chassis. This indicates the relationship between non-uniform memory access nodes. A set of nodes that are on the same airflow path or are physically adjacent. all adjacent nodes Perform a summation operation; Indicates adjacent nodes Non-uniform memory access nodes The generated thermal interference constant, the resource topology building module is based on physical distance and The constant is calculated based on the difference between the distances. The smaller the distance difference, the larger the thermal interference constant. Its value ranges from 0.1 to 0.5. It is determined by being calculated by reducing the value proportionally to the reciprocal of the physical distance difference. This represents the dimensionless reference wind speed ratio for the duct. This represents a very small constant used to prevent division by zero anomalies, and its value can be set from 0.001 to 0.01.

[0079] In step S17, the resource topology construction module performs threshold constraints and normalization on the calculated reliability weight factors. This step ensures that the output weight factors are within a valid and reasonable numerical range, avoiding abnormal extreme values ​​from interfering with subsequent calculations.

[0080] The resource topology construction module sets the lower limit threshold for weighting factors. In typical server monitoring scenarios, the lower limit threshold of this weighting factor is... The value is set to 0.1. When the sensor validity flag bit... At that time, the resource topology construction module directly sets the reliability weight factor. This node does not participate in subsequent calculations. Only when And the reliability weighting factor is calculated using the formula. Less than the lower limit threshold of the weighting factor At that time, the resource topology building module forces the reliability weighting factor. The value is assigned to the lower limit threshold of the weighting factor. This is to preserve the minimum reference value of the node.

[0081] When the reliability weighting factor is calculated by the formula Greater than or equal to the lower limit threshold of the weighting factor At that time, the resource topology building module retains the calculated reliability weighting factor. The original value is then normalized by the resource topology construction module, which normalizes the reliability weight factors that have undergone threshold constraints.

[0082] Specifically, the reliability weight factor is scaled to the range of 0 to 1 by dividing the reliability weight factor of each valid node by the sum of the reliability weight factors of all currently valid nodes. The resource topology construction module then uses the reliability weight factors of each node after threshold constraints and normalization. The updated elements are mapped to the edge relation weight matrix of the topological relation matrix. and confidence set In this context, it is used as a standardized weight multiplier during subsequent residual matrix mapping.

[0083] See attached document Figure 4 In the analysis and processing method provided by the present invention, step S20 is mainly executed by the status and load acquisition module, and specifically, the memory allocation behavior across nodes can be captured through the following sub-steps.

[0084] S21, the status and load acquisition module deploys customized kernel tracepoints or dedicated kernel probe modules for specific kernel versions in the operating system kernel page fault handling path. In order to capture the triggering events of specific kernel functions in real time and accurately, and to avoid the shortcomings of traditional application-layer periodic polling in capturing transient scheduling, the status and load acquisition module attaches probes to kernel execution locations that can determine physical page allocation information and node status, such as the kernel allocating physical pages or physical memory page frames (such as contiguous physical page structures) and preparing to map them to the successful return path in user space. The deployed probe event structure mainly covers page fault paths that actually allocate physical memory, such as anonymous page faults (do_anonymous_page) and copy-on-write page faults (do_wp_page), thereby avoiding the inability to accurately obtain the page resident status due to information loss at the total entry return point.

[0085] The registration and runtime state saving mechanism of the aforementioned kernel probes is a well-known technology in this field and will not be elaborated upon here.

[0086] S22, the status and load acquisition module extracts the page fault execution node identifier in real time. When a process running on the server triggers a page fault, the probe module directly obtains the processor's scheduling context information and the unique event identifier that caused the page fault, and obtains the logical processor number currently executing the instruction. Combining this with the heterogeneous hardware resource topology model built in the preceding steps, the status and load acquisition module maps the obtained logical processor number to its physically belonging non-uniform memory access node. The status and load acquisition module records this node information and uses it as the page fault execution node identifier. .

[0087] S23, the status and load acquisition module extracts the page resident node identifier. Upon completion of physical memory page allocation, the probe module directly parses the page descriptor node attributes of the allocated physical page from the context of the aforementioned customized trace points, thereby directly outputting the non-uniform memory access node where the page was actually allocated, and recording it as the page resident node identifier. If the page descriptor node attributes cannot be obtained due to reasons such as the page being swapped out to the swap area, then the page-resident node identifier will be... The page fault event is marked as unknown and actively ignored in subsequent statistics. Simultaneously, the probe module also extracts and outputs the page fault type (e.g., major page fault) and corresponding process and thread information to ensure comprehensive data correlation and availability.

[0088] S24, the status and load acquisition module statistically analyzes cross-node memory allocation behavior based on the extracted node identifiers. The status and load acquisition module compares the page fault execution node identifiers. Page resident node identifier .

[0089] when and When the values ​​are unequal, it indicates that the processor has accessed the physical memory of other nodes across local nodes (including cross-node fallback allocation degradation triggered due to local node memory exhaustion). The status and load acquisition module records this behavior as a cross-node page mapping event, while excluding page fault events that are not actually newly allocated, such as file cache hits. Specifically, the status and load acquisition module checks the context returned by the page fault handling function to determine whether the underlying physical memory page frame new allocation mechanism has actually been triggered. If the page already exists in the page cache (e.g., file cache hit), is swapped in through the swap area without being allocated a new page, or belongs to a special mapping that does not require physical memory backing, it is judged as a non-actual new allocation event and excluded. Only events in which physical pages are actually newly allocated on non-uniform memory access nodes (including the allocation of transparent big pages) are recorded and included in the set sampling time window. Internally accumulate cross-node page fault counts .

[0090] when and When the values ​​are equal, it indicates that the processor has completed physical memory allocation within its local node. The status and load acquisition module records this behavior as a local node page fault and records it within the sampling time window. Accumulate local node page fault counts .

[0091] The status and load acquisition module calculates the total number of page faults triggered. ,in Subsequently, the status and load acquisition module calculates the cross-node page fault rate. The specific calculation formula is as follows:

[0092] ;

[0093] in, Indicates the sampling time window Page fault rate across nodes within the node; Indicates the sampling time window The number of cross-node page faults counted internally; Indicates the sampling time window The total number of page faults triggered internally; This represents a compensation constant used to prevent division by zero anomalies. In regular kernel data statistics, this compensation constant... The value is set to 1.

[0094] The status and load acquisition module will calculate the cross-node page fault rate. As part of the underlying system load data, it is stored in the memory buffer to provide a quantitative indicator of resource contention status for subsequent thermal response residual calculation.

[0095] In the analysis and processing method provided by the present invention, step S20 is mainly executed by the status and load acquisition module, and can be completed by the following sub-steps to monitor physical memory throughput and context switching frequency.

[0096] S25, the status and load acquisition module reads the configuration register of the non-core performance monitoring unit inside the processor. Typically, the non-core performance monitoring unit is independent of the processor core and can directly monitor hardware transactions of the integrated memory controller, thus bypassing software interference. This is done within a set sampling time window. The status and load acquisition module initializes the hardware performance counters and locks the read and write transaction count values ​​of the physical memory controller.

[0097] The underlying hardware operation logic and register address mapping configuration are standardized and verified at this stage. For the underlying interface calls for register reading under a specific architecture, those skilled in the art can use standard instruction set specifications to implement them. The register read / write mechanism is a well-known technology in this field and will not be described in detail here.

[0098] S26, the status and load acquisition module calculates the final physical memory throughput based on the read hardware performance counter data. The status and load acquisition module extracts the read transaction bus cycle count and write transaction bus cycle count, and directly calculates the underlying throughput of each memory controller by combining this with the system cache line specification. Subsequently, the status and load acquisition module aggregates the mapping relationship matrix from memory controllers to non-uniform memory access nodes in the hardware physical topology. This mapping matrix is ​​established by reading the memory device topology from the system management SMBIOS data, and the mapping weight between controllers and directly connected nodes is set to 1, resulting in the mapping weights of the non-uniform memory access nodes. Physical memory throughput .

[0099] If a counter overflow is detected during the reading process, correction is performed by adding the current value to the counter's maximum capacity threshold and subtracting the previous reading; if the hardware performance counter is unavailable, then... Mark it as invalid and stop evaluating the node in the current window. The specific calculation formula is as follows:

[0100] ;

[0101] in, Indicates a non-uniform memory access node Physical memory throughput, in MB / s; Indicates the sampling time window The number of read transaction bus cycles counted by the internal hardware performance counter; Indicates the sampling time window The number of write transaction bus cycles counted by the internal hardware performance counter; This indicates the standard cache line size of the system. This value is determined according to the processor architecture specification, and the usual value is set to 64 bytes. This represents the unit conversion constant for converting bytes to megabytes.

[0102] S27, The status and load acquisition module synchronously acquires the sampling time window. The context switching frequency data within the memory. The status and load acquisition module reads the operating system scheduler kernel parameters and extracts the data based on the current non-uniform memory access node. The change in the total number of context switches that occurred during scheduling statistics is used to calculate the node-level context switch frequency by dividing this change by the sampling time window. Among them, context switching frequency The unit is times per second.

[0103] The status and load acquisition module will measure the physical memory throughput. Frequency of context switching The data is merged and encapsulated, and the encapsulated underlying load data sequence is directly output to the shared memory area as the basic data source for subsequent residual calculation module to perform timing synchronization and baseline comparison.

[0104] See attached document Figure 5 In the analysis and processing method provided by the present invention, step S30 is mainly executed by the residual calculation module. Specifically, the time difference caused by the out-of-band management network sampling delay and the physical heat dissipation process can be eliminated through the following sub-steps.

[0105] S31, the residual calculation module acquires out-of-band temperature sensor data and records the measurement timestamp. To unify the clock, the residual calculation module ensures that the hardware clock of the baseboard management controller is synchronized with the host kernel clock of the operating system through a precise time protocol or a network time protocol. The residual calculation module reads the sampled values ​​of the processor temperature sensor and the sampled values ​​of the memory region temperature sensor in each non-uniform memory access node area within the server. If the underlying firmware does not support outputting the specific measurement time, the residual calculation module appends a system reception timestamp to the sampled value. By subtracting the estimated fixed network out-of-band transmission delay from the system reception timestamp, the effective measurement timestamp is estimated, and the firmware polling period is used as a time uncertainty in subsequent alignment processing.

[0106] The estimated fixed network out-of-band transmission delay is obtained by sending multiple out-of-band echo requests to the baseboard management controller during the system initialization phase and calculating half of the average round-trip time.

[0107] The server's baseboard management controller polls the underlying hardware sensors via an internal bus. This mechanism results in a dual latency in data delivery to the operating system level due to both network and firmware processing delays. The residual calculation module reads the current sampled values ​​from temperature sensors within various non-uniform memory access node regions via out-of-band network channels.

[0108] After completing the read operation, the residual calculation module calls the high-precision clock interface of the operating system kernel to append the current system's received timestamp to the temperature sample value. For the specific implementation of acquiring out-of-band sensor data through the intelligent platform management interface or the Redfish protocol, those skilled in the art can use standard firmware network communication specifications. The underlying message parsing and reading mechanisms are well-known technologies in the field and will not be elaborated upon here.

[0109] S32, the residual calculation module calculates the out-of-band update cycle tolerance and performs timing alignment processing. The firmware-level temperature data polling cycle is typically in the second range, while the sampling time window of the underlying load data sequence is typically in the millisecond range, resulting in a time-frequency mismatch. The residual calculation module extracts the nominal refresh cycle from the sensor data record table of the baseboard management controller. Combined with the system received timestamp, the residual calculation module identifies the time tolerance between two consecutive valid temperature updates.

[0110] To align low-frequency temperature sampling points with the high-frequency underlying load data sequence, the residual calculation module employs a delayed backtracking alignment mode. Since out-of-band temperature data often lags behind high-speed acquired kernel events, the residual calculation module performs interpolation evaluation on the current window only after acquiring the next valid temperature sampling point after the current sampling time window. Through this backtracking interpolation, the residual calculation module maps discrete-period out-of-band temperature sampling values ​​onto a continuous time axis, generating processor-synchronized temperature sequences and memory-synchronized temperature sequences aligned with the underlying load data sequence, respectively.

[0111] S33, the residual calculation module compensates for the thermal response delay of the components based on a physical heat dissipation model. There is a time lag between a sudden power consumption change in a semiconductor device and the actual temperature change detected by its external surface and ambient temperature sensors, caused by the heat capacity of the chip packaging material and the external heat sink. This heat conduction process approximates a first-order inertial system. To eliminate this time lag, the residual calculation module uses a thermal response delay compensation formula to perform advance phase compensation on the synchronous temperature sequence, calculating the processor's physical temperature after time delay compensation. and memory physical temperature The specific calculation formula is as follows:

[0112] ;

[0113] ;

[0114] in, Indicates a non-uniform memory access node Processor physical temperature after latency compensation; Indicates a non-uniform memory access node Physical temperature of memory after latency compensation; and These represent non-uniform memory access nodes. The processor observed temperature and memory observed temperature in the synchronous temperature sequence corresponding to the current sampling time window; and These represent non-uniform memory access nodes. The processor observed temperature and memory observed temperature in the synchronous temperature sequence corresponding to the previous sampling time window; Indicates a non-uniform memory access node The thermal response time constant is determined based on the physical material specifications of the heatsink mounted on the node and the current actual airflow velocity. Specifically, The value can be obtained by consulting the thermal impedance step response characteristic table provided by the heat sink manufacturer. Select the time value required to reach a steady-state temperature rise of 63.2% under a specific wind speed. In a typical server environment, the value range is set to 2s to 5s. This represents the sampling time window, in seconds. The function is used to limit the amplitude of the discrete derivative term, restricting the derivative value to a certain range. Within the range, prevent impulse noise amplification caused by low-frequency sampling data jumps; This represents the maximum temperature change rate threshold, which is determined based on the maximum transient thermal conductivity of the physical radiator. The typical value range is set from 2℃ / s to 10℃ / s.

[0115] The residual calculation module calculates the processor's physical temperature after time delay compensation as obtained above. and memory physical temperature Stored in the cache. The temperature data after time delay compensation can maintain causal consistency in the time domain with the system load characteristics captured within the same sampling time window.

[0116] In the analysis and processing method provided by the present invention, the specific implementation of step S30 further includes stripping the heat generated by the normal load to extract the deviation amount that characterizes the anomaly, and the residual calculation module generates a standardized residual sequence through the following sub-steps.

[0117] S34, the residual calculation module uses a preset power consumption and temperature baseline model to calculate the baseline expected temperatures of the processor and memory respectively. Under normal operating conditions without malicious attacks or hardware malfunctions, the server's physical temperature and underlying hardware load have a relatively fixed mathematical mapping relationship. The residual calculation module extracts the cross-node page fault rate, physical memory throughput, and context switching frequency obtained in the preceding steps, and simultaneously obtains the non-uniform memory access node by reading the processor's underlying interface (such as the average power limit register). The processor's packaged power consumption data, and the intake air temperature data obtained by reading the chassis intake air temperature sensor through an out-of-band channel.

[0118] Since the intake air temperature constitutes the initial environmental boundary condition for server heat exchange, the package power consumption directly determines the macroscopic basic heat generation of the chip due to the Joule heating effect, and the context switching frequency reflects the transient heat fluctuations caused by micro-software scheduling and resource contention. Compared to simply relying on conventional surface indicators (such as overall CPU utilization) that easily mask the true underlying losses, these three parameters precisely constitute the minimum orthogonal feature set covering environmental noise, hardware work, and software overhead. This avoids introducing other redundant parameters that could lead to model overfitting, while also fully covering the physical and logical factors that determine the normal baseline temperature. Therefore, the residual calculation module substitutes the load data, including the context switching frequency, which can characterize the normal heat generation pattern in multiple dimensions, along with the power consumption and temperature data, into the multiple linear regression model to calculate the non-uniform memory access node. Expected baseline processor temperature within the current sampling time window and memory baseline expected temperature The specific calculation formula is as follows:

[0119] ;

[0120] ;

[0121] in, Indicates a non-uniform memory access node The processor's baseline expected temperature; Indicates a non-uniform memory access node Expected baseline temperature for memory; Indicates the context switching frequency within the current sampling time window; Indicates a non-uniform memory access node The processor's packaged power consumption data; This represents the cross-node page fault rate within the current sampling time window; Indicates a non-uniform memory access node Physical memory throughput within the current sampling time window; This indicates the server's intake air temperature; , , , Represents the regression coefficients of the processor model; , , , These represent the regression coefficients of the memory model. These model coefficients were obtained by least-squares fitting training of the system within a historical normal window where there were no errors and the inlet air temperature was stable.

[0122] The system selects a healthy window of time where no hardware errors occurred within the past 24 hours and the inlet air temperature fluctuation was less than 2°C. Data from this window, containing at least 1000 discrete sampling points, is extracted for training. The model is trained using least squares methods with outlier removal mechanisms, such as random sampling consistency, to eliminate transient noise. If the system detects a hardware configuration change or a sudden change in the absolute value of the inlet air temperature exceeding 5°C, an update freeze condition is triggered, the old model is discarded, and sufficient new valid data is collected for refitting.

[0123] For training and coefficient fitting of multiple linear regression models, those skilled in the art can use standard data mining algorithm libraries. The basic fitting logic is a well-known technology in this field and will not be elaborated here.

[0124] S35, the residual calculation module separately calculates the original thermal response residuals of the processor and memory. Directly calculating the temperature difference is easily affected by the sensor's own accuracy and crosstalk in the physical airflow. To accurately measure the deviation between the actual and expected temperatures, the residual calculation module extracts the time-delay compensated physical temperature generated in the previous step and calculates the processor's original thermal response residuals separately. Compared with the original thermal response residual of memory The specific calculation formula is as follows:

[0125] ;

[0126] ;

[0127] in, Indicates a non-uniform memory access node The processor's original thermal response residual within the current sampling time window; Indicates a non-uniform memory access node The original thermal response residual in memory within the current sampling time window; Indicates a non-uniform memory access node Processor physical temperature after latency compensation; Indicates a non-uniform memory access node Physical temperature of memory after latency compensation; Indicates a non-uniform memory access node The expected baseline temperature of the processor within the current sampling time window; Indicates a non-uniform memory access node The expected baseline temperature of memory within the current sampling time window. This calculation step isolates heat fluctuations caused by normal system load, extracts the actual physical temperature deviation that characterizes potential anomalies, and reduces the impact of routine business loads on subsequent anomaly detection.

[0128] S36, the residual calculation module uses the absolute median difference to perform dimensionless standardization on the original thermal response residual. Different non-uniform memory access nodes have different power consumption benchmarks and absolute temperature ranges, making it impossible to perform a unified comparison from a global perspective by directly using the original residual. The residual calculation module maintains a length of... A sliding time window is used to collect non-uniform memory access nodes. The set of original thermal response residuals within this window In typical server monitoring scenarios, a sliding time window... The length is set to 50 to 100 sampling periods.

[0129] The residual calculation module calculates the median and absolute median difference between the original processor residual and the original memory residual, and outputs the final processor standardized residual. and memory standardization residual Taking the processor as an example (the same applies to memory), the specific calculation formula is as follows:

[0130] ;

[0131] ;

[0132] in, Represents the absolute median difference of the processor's original thermal response residuals within the sliding time window; This indicates the median operation; Indicates the first time within the sliding time window The original thermal response residuals of each processor; This represents the median of the set of original thermal response residuals of the processor within the sliding time window; Indicates a non-uniform memory access node Processor-normalized residuals within the current sampling time window; Indicates a non-uniform memory access node The processor's original thermal response residual within the current sampling time window; This represents the scaling factor. Multiplying by this factor aligns the standard normal distribution, ensuring that the absolute median becomes a statistically consistent estimator of the standard deviation. Used to establish a minimum scale lower bound that depends on the resolution of the sensor itself, where This indicates the physical resolution of the temperature sensor, typically set to 0.5℃ or 1.0℃ depending on the hardware specifications. This represents a very small constant used to prevent division by zero anomalies, and its value is set to 10. -6 .

[0133] The residual calculation module will finalize the processor-normalized residuals. and memory standardization residual By combining them in chronological order, continuous processor-normalized residual sequences and continuous memory-normalized residual sequences are generated. These sequences eliminate thermal fluctuations and differences in physical dimensions caused by normal loads, providing standardized data input for subsequent extraction of anomalous spatial features.

[0134] See attached document Figure 6 In the analysis and processing method provided by the present invention, step S40 is mainly executed by the matrix evaluation and judgment module. Specifically, the abnormal coupling degree between the processor and memory in the spatiotemporal dimension can be quantitatively evaluated through the following sub-steps.

[0135] S41, the matrix evaluation and judgment module flattens the standardized residual sequence into a two-dimensional feature matrix by combining the sensor validity flag bits. In actual server operating environments, some hardware sensors go offline due to bus failures or firmware anomalies. This mask is used to remove nodes that do not meet the criteria. For the filtered valid nodes, the matrix evaluation and judgment module combines the aforementioned reliability weighting factors. The independently generated processor-normalized residual sequences are weighted and mapped into a two-dimensional feature matrix of the processor. (Right now The memory-normalized residual sequences are weighted and mapped into a two-dimensional feature matrix in memory. (Right now ).

[0136] The matrix evaluation and judgment module counts the total number of valid nodes after filtering. If determined This indicates that there is no valid data source within the current sliding time window. The matrix evaluation and judgment module directly terminates the evaluation logic of the current sliding time window and records the sensor global failure event. If the judgment is... The matrix evaluation and determination module maps the processor-standardized residuals of effective nodes into a two-dimensional feature matrix of the processor along the spatiotemporal dimension. The memory-normalized residuals are mapped into a two-dimensional feature matrix of memory. The row indices of the matrix correspond to the numbers of valid non-uniform memory access nodes, and the column indices correspond to the sampling times within the sliding time window. The total number of columns in the matrix is ​​equal to the length of the sliding time window. .

[0137] S42, the matrix evaluation and determination module searches for the maximum lag similarity between the processor's two-dimensional feature matrix and the memory's two-dimensional feature matrix within a discrete lag step interval. Because the increase in processor computational load due to cross-node memory access and the accumulation of heat during memory read / write operations have different physical timing sequences, the matrix evaluation and determination module introduces a time lag step. This allows for the extraction of time-shifted coupling features between the two.

[0138] The matrix evaluation and judgment module is set with a lag step interval of 100%. For each time lag step within this interval And calculate the offset spatial two-dimensional cosine similarity. The specific calculation formula is as follows:

[0139] ;

[0140] in, Indicates the time lag step size Below, the processor's two-dimensional feature matrix With memory two-dimensional feature matrix Spatial two-dimensional cosine similarity; This indicates the total number of valid nodes after filtering by the sensor validity flag. Indicates the index number of the non-uniform memory access node; This represents the sampling time index, and its valid value range is defined as satisfying... and The set of all integers; The processor's two-dimensional feature matrix represents the first... line, number The element values ​​of the column; Represents the two-dimensional feature matrix in memory at the th line, number The element values ​​of the column; This represents a very small constant to prevent division by zero anomalies, set to 10. -6 ; This means iterating through and summing all valid nodes after filtering by the sensor validity flag. This indicates that the sampling times within the sliding time window that satisfy the valid value range are iterated and summed.

[0141] Subsequently, the matrix evaluation and judgment module traverses the lag step interval. Calculate the maximum lag similarity The calculation formula is: .in, This represents the function that takes the maximum value; the matrix evaluation and judgment module traverses the lag step interval in the evaluation mode that allows delayed backtracking. The lag search radius is determined based on the temperature sampling measurement delay and the residual uncertainty of thermal response compensation. It is set to cover the fluctuation range of the temperature update cycle outside the coverage band. In practical applications, its value range is set to 3 to 10 sampling cycles.

[0142] To prevent accidental high-similarity false alarms introduced by multi-lag search, the matrix evaluation and judgment module introduces a degree-of-freedom penalty correction for the maximum lag similarity, using the formula... Perform correction (where) The corrected maximum hysteresis similarity. (where the sliding time window length is), and This serves as the final output. The similarity threshold used subsequently is determined based on the distribution statistics of historical resource contention failure samples from actual data centers, selecting an empirical lower bound that guarantees a recall rate of over 95%. The matrix evaluation and judgment module outputs the corrected maximum lag similarity. This provides a quantitative indicator of the degree of coupling for subsequent pre-filtering mechanisms.

[0143] In the analysis and processing method provided by the present invention, step S40 further includes eliminating false alarms of temperature anomalies caused by non-computational loads. The matrix evaluation and judgment module performs the underlying hardware status joint verification and pre-filtering mechanism through the following sub-steps.

[0144] S43, the matrix evaluation and judgment module verifies the error status and power limit flags of the underlying hardware. Abnormal server temperatures are usually caused by hardware malfunctions or power control mechanisms, rather than resource contention due to computing services. The matrix evaluation and judgment module reads the system event log within the baseboard management controller via the out-of-band network channel to search for hardware error states such as uncorrectable memory errors or fatal bus errors within the current sliding time window.

[0145] Simultaneously, the matrix evaluation and judgment module reads the processor's operating status register to verify whether there is an active power limiting flag triggered by reaching the thermal design power limit. If a hardware error such as an uncorrectable memory error is detected, the matrix evaluation and judgment module marks the system status as a hardware anomaly candidate, saves a snapshot of the current situation, and terminates the resource contention bottleneck judgment for this window. If an active power limiting flag exists, it marks the power constraint status and reduces the confidence level of the cross-node resource contention judgment within the current window. Specifically, when reducing the confidence level to enter the final judgment logic, the matrix evaluation and judgment module temporarily increases the similarity judgment threshold for subsequent comparisons by 10% to 20%, requiring more stringent coupling conditions to confirm the bottleneck.

[0146] For reading the baseboard management controller log and parsing the processor register, those skilled in the art can use the standard communication specifications of the relevant hardware. The underlying message interaction mechanism is a well-known technology in the field and will not be described in detail here.

[0147] S44, the matrix evaluation and judgment module calculates the fan speed deviation and verifies the sudden change in intake air temperature. External data center air conditioning malfunctions or aging server fans can also lead to heat buildup. The matrix evaluation and judgment module extracts data from the chassis intake air temperature sensor and calculates the rate of change of intake air temperature within the current sliding time window. Inlet air temperature change rate Take the difference between the highest and lowest temperatures at the air inlet within the current window and divide it by the time span of the sliding time window.

[0148] The matrix evaluation and judgment module simultaneously extracts the actual speed of each fan in the cooling system from the target speed set in the system firmware, and calculates the fan speed deviation. The specific calculation formula is as follows:

[0149] ;

[0150] in, This indicates the deviation in fan speed of the cooling system; This indicates the total number of effective cooling fans configured inside the server. This indicates that the summation is performed by iterating through and accumulating all valid cooling fans. Indicates the index number of the effective cooling fan; Indicates the first The actual rotational speed of an effective cooling fan; Indicates the first The target speed of an effective cooling fan.

[0151] The matrix evaluation and judgment modules respectively evaluate the inlet air temperature change rate. With temperature change threshold Compare and determine the fan speed deviation. With respect to speed deviation threshold A comparison was performed. Under standard data center operating conditions, the temperature sudden change threshold... The value range is set to 0.033℃ / s to 0.05℃ / s, and the speed deviation threshold is... The value range is set to 0.10 to 0.15. If... or If it indicates that there is an anomaly in the current physical heat dissipation environment or the mechanical structure of the fan, the matrix evaluation and judgment module will intercept and filter it.

[0152] S45, the matrix evaluation and judgment module performs joint judgment and outputs the resource contention bottleneck confirmation result. In order to finally confirm the abnormal state, the matrix evaluation and judgment module must ensure that the preceding hardware status and physical environment verifications pass smoothly.

[0153] When the system event log shows no related hardware error, and the inlet air temperature change rate is met... And fan speed deviation At that time, the matrix evaluation and judgment module will use the corrected maximum lag similarity. Similarity threshold A comparison is performed. Specifically, when there is no power limit indicator, a preset similarity threshold is used. A comparison is performed; if a power limit flag is present, a temporarily increased similarity threshold is used for comparison. Similarity threshold. Used to distinguish between occasional load fluctuations and continuous resource contention, its value range is set from 0.75 to 0.85.

[0154] The matrix evaluation and judgment module synchronously calculates the processor's two-dimensional feature matrix. With memory two-dimensional feature matrix The unit element mean squared residual. The unit element mean squared residual is calculated by summing the squares of all elements in the corresponding two-dimensional feature matrix and then dividing by the total number of elements in the matrix (i.e., the total number of valid nodes). With sliding time window length The product of the processor unit element mean squared residual and the memory unit element mean squared residual is greater than the preset outlier mean squared residual threshold, and the corrected maximum hysteresis similarity is... At that time, it was confirmed that there was a high degree of coupling, and the server status was determined to be a bottleneck caused by cross-node resource contention.

[0155] The threshold values ​​for the aforementioned outlier mean squared residuals are set between 1.5 and 3.0 based on the statistical significance requirements after standardization. For example, in a dual-path architecture (where the node size is...), ), sliding time window length When the total number of matrix elements is 200, and the sum of squares is 400, then the mean squared residual of each element is 2.0; in a four-way architecture ( ), window length When the total number of matrix elements is 200, if the sum of squares is 500, then the average squared residual of the unit element is 2.5. Both can be directly and reliably compared with a fixed threshold in a unified dimension.

[0156] The matrix evaluation and judgment module marks the system status that passes all pre-filter verifications and meets the similarity judgment threshold as a valid abnormal status, providing a reliable event trigger basis for subsequent generation of diagnostic reports and execution of scheduling interventions.

[0157] If the mean squared residual of the unit element meets the standard, but the corrected maximum hysteresis similarity is... This indicates the absence of significant spatial correlation. The module will further combine the hardware status logs to output classification results for single-domain processor anomalies or single-domain memory anomalies. Only when all monitoring metrics and the unit element mean squared residuals are within limits are the servers determined to be in normal operating condition, no anomaly event flags are triggered, and the next sliding time window sampling and evaluation cycle begins. This pre-filtering mechanism eliminates interference introduced by environmental anomalies or hardware aging, improving the accuracy of cross-node resource contention determination.

[0158] See attached document Figure 7 In the analysis and processing method provided by the present invention, step S50 is mainly executed by the sampling and analysis output module. Specifically, it can completely retain the field data before and after the anomaly occurs and clarify the buffer hierarchy between the kernel and user space under the condition of controlling system overhead through the following sub-steps.

[0159] S51, the sampling and analysis output module maintains the main loop buffer in user space during the normal system operation phase. During this phase, the module utilizes the underlying stack trace probe deployed in the system kernel to extract instruction address sequences with unique event identifiers and their corresponding timestamps. The probe module then uses these unique event identifiers to hard-bind the metadata of the page mapping events that triggered cross-node access to the corresponding underlying stack trace records.

[0160] To directly support the subsequent generation of the node association call graph, the dynamic context snapshot record stored in the buffer specifically includes fields such as event trigger timestamp, unique event identifier, page fault execution node identifier, page-resident node identifier, process identifier, thread identifier, and an array of instruction pointer addresses for each level of function call. The kernel probe pushes the captured data to user space through lock-free event transmission channels such as BPF Ring Buffer or Perf Channel. Within user space, the service process of the sampling and analysis output module maintains a pre-allocated buffer with a maximum capacity of [missing information]. The user-mode main loop buffer. Under normal recording conditions where no abnormal signals are received, the receiving thread continuously writes to this user-mode main loop buffer, synchronously saving event metadata and call stack data.

[0161] The user-mode main loop buffer uses a fixed-capacity first-in-first-out (FIFO) overwrite mechanism. When the amount of data written reaches the maximum capacity set for the user-mode main loop buffer... At that time, newly acquired stack data will automatically overwrite the oldest stack data. Through this circular overwrite mechanism, the user-mode main loop buffer maintains the system call stack record most recent to the current moment. Capacity Limit The value is set based on the available memory of the server and the expected backtracking time span. In practical applications, its value range is set from 64MB to 256MB.

[0162] S52, the sampling and analysis output module responds to abnormal events and performs a state switch in the double buffer. When the matrix evaluation and judgment module outputs a valid abnormal state, it indicates that a cross-node resource contention bottleneck has been confirmed in the current system. Upon receiving this abnormal trigger signal, the sampling and analysis output module switches its internal state machine from the normal recording state to the snapshot retention state.

[0163] While in snapshot-preserved state, the sampling and analysis output module performs state locking on the user-space main loop buffer, marking it as a read-only snapshot and stopping overwrite operations. This operation locks the historical stack record prior to the time of the exception, preventing critical pre-exception diagnostic data from being overwritten by subsequent large amounts of state streams. Simultaneously, the write pointer of the receiving thread is atomically redirected to an equivalent capacity (set to) within user space. ,and A backup circular buffer (to maintain consistency) is used to record the evolution of system operation after an anomaly occurs. This mechanism avoids interference from direct write protection instructions on the kernel data transmission channel.

[0164] S53, the sampling and analysis output module performs snapshot stitching and asynchronous disk writing, as well as disaster recovery and degradation. Simultaneously with activating the backup circular buffer, the sampling and analysis output module starts an exception delay timer. The timeout duration of the exception delay timer is set to... This parameter determines the time window for continuous tracking after an anomaly occurs, and its value is set between 10 and 30 seconds to record subsequent system fluctuations caused by the anomaly. During this period, if the used space of the backup circular buffer reaches its capacity limit... It will proactively discard any newly collected data to ensure memory safety.

[0165] When the clock reaches After the timer times out, the receiving thread stops writing data to the backup circular buffer, and the state machine enters the data dump state. The sampling and analysis output module extracts the locked historical stack records in the user-mode main circular buffer and the newly added stack records in the backup circular buffer, respectively, parses the timestamps in the records, aligns and splices the two parts of data on the timeline, generates a dynamic context snapshot covering the period before and after the exception, and persists it to the underlying disk file system through the asynchronous input / output channel.

[0166] Upon receiving confirmation of disk write completion from the file system, the normal cleanup process begins. If an asynchronous write operation times out due to disk failure or other reasons, the sampling and analysis output module records the disk write failure status and uses fallback methods such as network dumping or memory compression to enter an alternative persistence path. If the set maximum memory retention time limit (ranging from 300s to 1800s) is exceeded and fallback persistence continues to fail, the memory address spaces of the user-mode main loop buffer and the backup loop buffer are zeroed and reset, the state lock of the user-mode main loop buffer is released, the state machine is reset to the normal recording state, and the initial loop write logic is restored.

[0167] In the analysis and processing method provided by the present invention, step S50 further includes converting the underlying binary stack data into source code-level diagnostic evidence that is readable by developers. The sampling and analysis output module performs call stack symbol resolution and cross-node page dwell association call link graph generation through the following sub-steps.

[0168] S54, the sampling and analysis output module performs symbolic reverse resolution of binary instruction addresses. This module reads the persistent dynamic context snapshot file and extracts the process identifier, thread identifier, and binary instruction addresses of each function call that triggered cross-node memory access records. Since the runtime addresses captured by the low-level probe cannot be directly used for source-level diagnostics, the sampling and analysis output module loads the operating system kernel symbol table and the corresponding user-mode application's debug information file. It then performs range matching searches in the symbol table and debug information file to convert the extracted binary instruction addresses into specific function names, source file paths, and line numbers.

[0169] If debugging information is missing or a match fails, the sampling and analysis output module marks the address as an unresolved raw hexadecimal address string. This mechanism ensures the logical integrity of the call stack chain and prevents the context call stack from breaking due to a single level of resolution failure.

[0170] S55, the sampling and analysis output module aggregates and generates a cross-node page-resident association call chain graph based on cross-node affinity mapping relationships. After completing symbol resolution, the sampling and analysis output module extracts the non-uniform memory access node number of the executing thread in the stack context, as well as the node number of the corresponding accessed physical memory page, and filters out the function execution chain where cross-node calls actually occur. During execution association, the sampling and analysis output module traverses each extracted stack record. If the page fault execution node identifier in the record is inconsistent with the page-resident node identifier (i.e., ...), it checks the execution chain. If a caller function and a callee function on the corresponding complete call stack are both marked as having actually triggered a cross-node access, the trigger frequencies of all adjacent level pairs in that chain will be accumulated in subsequent statistics. Conversely, if both are consistent, the chain involved in that stack record will not be included in the cross-node association calculation.

[0171] Because identical function chains are triggered frequently within abnormal time windows, the sampling and analysis output module aggregates homogeneous cross-node call chains and calculates the topological edge weights between adjacent caller and callee functions. The specific calculation formula is as follows:

[0172] ;

[0173] in, Indicates the caller function With the callee function Topological edge weights for cross-node access; This indicates the time window of the caller function within the current dynamic context snapshot. Execute and call the callee function And the actual cumulative frequency of cross-node memory access; This indicates the total frequency of all cross-node memory accesses triggered by the current abnormal process within this time window; This represents the caller function that initiated the call in the function call stack; This represents the callee function that receives the call in the function call stack; This represents a very small constant to prevent division by zero anomalies, set to 10. -6 .

[0174] The sampling and analysis output module sets the topology edge trimming threshold. This parameter is used to filter out occasional cross-node calls to extract the main resource contention bottleneck paths. Its value is determined based on the display complexity requirements of the topology graph and ranges from 0.01 to 0.05.

[0175] The sampling and analysis output module will calculate the topology edge weights. With topology edge trimming threshold Perform a comparison. If... The sampling and analysis output module will call the function. With the callee function The weight relationship is added to the topology data set to be rendered. If The sampling and analysis output module treats this call chain as a low-frequency, occasional event and does not include it in the final topology data set.

[0176] Subsequently, the sampling and analysis output module determines whether the pruned call topology data set is empty. If the data set is empty, it indicates that the currently captured cross-node accesses are all scattered, low-frequency calls, and no obvious performance bottleneck path has been formed. The sampling and analysis output module then directly records the regular diagnostic logs and ends the current topology generation process.

[0177] If the dataset is not empty, the sampling and analysis output module renders the threshold-pruned call topology dataset into a directed graph structure of cross-node page-resident association call chain diagrams. In this topology graph, nodes represent the parsed specific function symbols and their respective processor nodes, and directed edges represent the call relationships between functions and the cross-node access traffic weights. The sampling and analysis output module outputs this cross-node page-resident association call chain diagram, providing it as an important reference for system administrators or developers in diagnostic reports, and providing data support for locating the specific source code location of cross-node memory accesses.

[0178] To better aid in understanding the technical solution provided by this invention, a specific application example is provided below.

[0179] Suppose a database server with a dual-socket architecture (i.e., containing two non-uniform memory access nodes, node 0 and node 1) is deployed in a data center. During peak business periods, a high-frequency query process on node 1, due to improper configuration, frequently reads memory from node 0 across nodes, causing a bottleneck caused by cross-node resource contention.

[0180] Before executing specific processing procedures, the system pre-sets relevant judgment thresholds and operating parameters, mainly including the lower limit threshold of the weighting factor. The discrete lag step size interval for the search is [-10, 10], and the similarity threshold is [not specified]. Speed ​​deviation threshold and topology edge trimming threshold The specific process of the system executing the method of this invention is as follows:

[0181] The resource topology building module confirms that the temperature sensor on non-uniform memory access node 1 is independently valid and sets the sensor validity flag. Sensor confidence coefficient Combined with the server fan's airflow reference speed ratio The thermal interference constant with adjacent nodes is determined by the formula. The reliability weighting factor of non-uniform memory access node 1 is calculated. This value is greater than the preset lower threshold of the weighting factor. Normal retention.

[0182] The kernel probe of the status and load acquisition module captured a large number of page faults. This occurred within the set sampling time window. The number of cross-node page faults was counted. Local node page fault count Total number of page faults triggered According to the formula The cross-node page fault rate was calculated. Simultaneously, the hardware performance counters are read to calculate the physical memory throughput of non-uniform memory access node 1. and context switching frequency The aforementioned load data sequence is output continuously.

[0183] During the residual calculation and standardization phase, the processor observation temperature reported by the out-of-band network... Because the heat sink's thermal capacity exhibits a significant lag, the residual calculation module uses the formula... Compensation components reduce thermal response delay, generating a time-delay-compensated physical temperature of the processor that accurately reflects transient thermal changes. .

[0184] Meanwhile, the residual calculation module utilizes a preset multiple linear regression model (substituting...) , With intake air temperature ), calculate the processor baseline expected temperature By calculating the difference between the two, the normal load heat is stripped away, generating the processor's original thermal response residual. The dimensionless standardization is performed using the absolute median difference formula, and the processor-standardized residuals are output. .

[0185] The matrix evaluation and determination module flattens the standardized residuals of valid nodes into a two-dimensional feature matrix for the processor. With memory two-dimensional feature matrix To capture the timing misalignment caused by cross-node access, where the processor heats up first and the remote memory heats up later, the matrix evaluation and judgment module searches for the maximum lag similarity within a preset discrete lag step size interval [-10, 10]. After calculation, at the lag step size At that time, the two achieved the maximum lag similarity. Combined with the set sliding time window length and lag search radius The module introduces a degree-of-freedom penalty correction and calculates the corrected maximum hysteresis similarity. .

[0186] Then, pre-filtering was performed, and the system event log was read. No uncorrectable memory errors or power limit flags were found. The fan speed deviation was then calculated. (Less than the preset speed deviation threshold of 0.10), inlet air temperature change rate Normal. The pre-validation passed, and the corrected maximum hysteresis similarity is [data missing]. Greater than the similarity threshold Furthermore, the mean squared residual of the unit element meets the standard, the system confirms that there is high coupling, determines that the server status belongs to the bottleneck of cross-node resource competition, and outputs a valid abnormal status.

[0187] Upon receiving an anomaly signal, the sampling and analysis output module immediately locks the user-mode main loop buffer, stops overwrite operations, and starts a post-anomaly delay timer. After performing snapshot stitching, the module performs symbol reverse parsing and calculates the topology edge weights based on the actual trigger frequency. Remove elements with topology edge trimming values ​​below a preset threshold. Following the low-frequency event, since the pruned call topology data set is not empty, the sampling and analysis output module renders it as a cross-node page-resident association call chain graph, pointing to the business code line number that triggered the competition.

[0188] To verify the technical effectiveness of this invention, comparative tests were conducted in a database cluster environment. (See attached document.) Figure 8 The horizontal axis represents the sampling time (0 to 100), and the vertical axis represents the temperature (40℃ to 80℃). The figure contains three main curves, which are marked in the legend as representing the processor's observed temperature (gray solid line), the processor's baseline expected temperature (gray dashed line), and the processor's physical temperature after time delay compensation (black dotted line).

[0189] Observing the curves, it can be seen that the system is in normal operation between sampling times 0 and 40. During this period, the processor observed temperature and the processor baseline expected temperature curves basically overlap, while the processor physical temperature curve after latency compensation fluctuates within the range of 40℃ to 60℃. At sampling time 40, a cross-node resource contention anomaly occurs, but the processor baseline expected temperature, representing the expected heat under normal load, still maintains a stable trend. The processor observed temperature, influenced by the first-order inertia of the external heat sink's thermal capacity, shows a slow upward trend.

[0190] After time delay compensation, the processor's physical temperature curve shows a significant increase after time 40, deviating from the baseline expected temperature. The residual calculation module of this invention introduces a time delay compensation formula, using the discrete rate of change of the observed temperature to offset the time difference in heat conduction caused by the physical packaging and airflow cooling process. This compensation mechanism can reflect transient thermal changes in semiconductor devices caused by abnormal competition for underlying resources, extracting the temperature deviation characteristic of the anomaly within the thermal response residual generation region, thereby reducing anomaly detection delay.

[0191] See attached document Figure 9 The horizontal axis represents the time lag step (-10 to 10), and the vertical axis represents the spatial two-dimensional cosine similarity (0.3 to 1.0). The figure includes a lag similarity curve with an inverted U-shape (gray solid line), a similarity judgment threshold reference line at 0.80 (gray dashed line), and the maximum lag similarity point.

[0192] Observing the curve trend, it can be seen that within the range of lag steps of -10 to -4 or 8 to 10, the similarity value is low and the curve tends to flatten. As the time lag step gradually approaches 3, the similarity curve shows a clear upward trend. At a time lag step of 3, the similarity curve reaches its peak, at which point the original maximum lag similarity is achieved. After calculating the degrees of freedom penalty, the corrected maximum hysteresis similarity is obtained. The value is approximately 0.85, which is greater than the similarity threshold. ,Right now .

[0193] The inverted U-shaped curve is due to the fact that cross-node memory access causes the local processor's computational load to rise first, generating heat, followed by the heat generated by the remote memory controller responding to read / write requests. There is a physical time lag between these two processes. The matrix evaluation and judgment module extracts spatiotemporal coupling features with time offsets by traversing discrete lag step intervals. When the corrected maximum lag similarity exceeds the similarity judgment threshold, and no anomalies are found in the underlying system verification, the system can rule out external environmental or non-computational load-related temperature anomalies, confirming a cross-node resource contention bottleneck on the server.

[0194] While specific embodiments of the present invention have been described above, those skilled in the art should understand that these specific embodiments are merely illustrative. Those skilled in the art can omit, substitute, and modify the details of the above methods and systems in various ways without departing from the principles and essence of the present invention. For example, combining the above method steps to perform substantially the same function and achieve substantially the same result using substantially the same method falls within the scope of the present invention.

Claims

1. A platform for analyzing and processing server operating parameters, characterized in that, include: The resource topology construction module is used to read hardware description data, parse discrete hardware physical attributes and logical attribution relationships from the hardware description data, integrate the discrete hardware physical attributes and logical attribution relationships, establish a topology relationship matrix including physical memory slots, voltage regulation modules and non-uniform memory access nodes, and generate sensor validity flag bits and reliability weight factors for non-uniform memory access nodes. The status and load acquisition module is used to extract the page fault execution node identifier and the page resident node identifier to calculate the cross-node page fault rate, and to calculate the physical memory throughput by combining the hardware performance counter and the mapping relationship in the topology matrix, so as to collect the underlying load data sequence containing the cross-node page fault rate and the physical memory throughput. The residual calculation module is used to receive the underlying load data sequence and read out-of-band temperature sensor data, perform timing alignment processing and compensate for the thermal response delay of the components, extract the original thermal response residuals in combination with the power consumption temperature baseline model, and generate processor-standardized residual sequences and memory-standardized residual sequences. The matrix evaluation and judgment module is used to generate a processor two-dimensional feature matrix and a memory two-dimensional feature matrix based on the sensor validity flag, the reliability weight factor, the processor standardized residual sequence, and the memory standardized residual sequence; calculate the corrected maximum hysteresis similarity; read the underlying hardware state and perform joint verification of the underlying hardware state; and output a valid abnormal state in combination with the joint verification result when the mean squared residual of the unit elements of the processor two-dimensional feature matrix and the memory two-dimensional feature matrix is ​​greater than a preset abnormal mean squared residual threshold, and the corrected maximum hysteresis similarity meets the similarity judgment threshold requirement determined according to the joint verification result. The sampling and analysis output module is used to, after receiving the valid abnormal status, splice a dynamic context snapshot containing the instruction address sequence, the page fault execution node identifier, and the page-resident node identifier, perform symbolic reverse parsing on the instruction address sequence, and output a cross-node page-resident association call chain graph.

2. The server operating parameter analysis and processing platform according to claim 1, characterized in that, The resource topology construction module obtains the three-dimensional physical distance from the chassis air inlet to the non-unified memory access node on the specified airflow path, and calculates the thermal interference constant caused by the influence of adjacent non-unified memory access nodes on the non-unified memory access node in combination with the horizontal partition and upstream and downstream relationship. The adjacent non-unified memory access node is located on the same airflow path as the non-unified memory access node, or is determined according to the horizontal partition, upstream and downstream relationship and three-dimensional physical distance. The resource topology construction module extracts the real-time rotation speed of the system cooling fan and converts it into the air duct reference wind speed ratio. Based on the relationship between the three-dimensional physical distance and the air duct reference wind speed ratio, it establishes an attenuation model. Combining the sensor validity flag and the thermal interference constant, it calculates the reliability weight factor and performs threshold constraint and normalization processing on the reliability weight factor, mapping it to the topology relationship matrix.

3. The server operating parameter analysis and processing platform according to claim 1, characterized in that, The status and load acquisition module deploys a customized kernel trace point or a dedicated kernel probe module within the physical page allocation success return path in the operating system kernel page fault exception handling path. It obtains the page fault execution node identifier by extracting the processor's scheduling context and extracts the page resident node identifier by parsing the page descriptor, and simultaneously obtains the page fault type and the corresponding process and thread information. When the values ​​of the page fault execution node identifier and the page resident node identifier are not equal, the status and load acquisition module records the cross-node access behavior as a cross-node page mapping event, accumulates the number of cross-node page faults and the number of local node page faults within the set sampling time window, and calculates the total number of page fault exceptions and the cross-node page fault rate.

4. The server operating parameter analysis and processing platform according to claim 1, characterized in that, The status and load acquisition module extracts the number of read transaction bus cycles and the number of write transaction bus cycles from the hardware performance counter, calculates the underlying throughput of the memory controller by combining the system cache line specifications, and accumulates and aggregates the data using the mapping relationship in the topology matrix to obtain the physical memory throughput. The status and load acquisition module extracts the total change in the number of context switches according to the scheduling statistics of the non-uniform memory access nodes, divides it by the set sampling time window to calculate the context switch frequency, and combines the cross-node page fault rate, the physical memory throughput and the context switch frequency into the underlying load data sequence.

5. The server operating parameter analysis and processing platform according to claim 1, characterized in that, The residual calculation module reads the out-of-band temperature sensor data of the physical sensor through the out-of-band network channel, adds a system receiving timestamp to the out-of-band temperature sensor data, identifies the time tolerance between two consecutive updates of the out-of-band temperature sensor data, performs time alignment processing, and uses the delayed backtracking alignment mode to map the sampled values ​​of discrete periods to a continuous time axis to generate a synchronous temperature sequence. The residual calculation module uses the thermal response delay compensation formula to perform advanced phase compensation on the synchronous temperature sequence, eliminating the time lag caused by the chip packaging material and the heat capacity of the external heat sink, and calculates the processor physical temperature and memory physical temperature in the physical temperature after time delay compensation.

6. The server operating parameter analysis and processing platform according to claim 5, characterized in that, The residual calculation module extracts the context switching frequency from the underlying load data sequence, combines it with the processor's packaged power consumption data and intake air temperature data, and substitutes it into the processor's multiple linear regression model to calculate the processor's baseline expected temperature. It also extracts the cross-node page fault rate and physical memory throughput from the underlying load data sequence, combines it with the intake air temperature data, and substitutes it into the memory's multiple linear regression model to calculate the memory's baseline expected temperature. The residual calculation module extracts the processor physical temperature and memory physical temperature from the physical temperature after delay compensation, subtracts the processor baseline expected temperature from the processor physical temperature, and subtracts the memory baseline expected temperature from the memory physical temperature, thereby calculating the original thermal response residual. The residual calculation module collects the set of original thermal response residuals by maintaining a sliding time window, calculates the median and absolute median difference of the original thermal response residuals, and outputs the processor-standardized residual sequence and the memory-standardized residual sequence after dimensionless standardization of the absolute median difference.

7. The server operating parameter analysis and processing platform according to claim 1, characterized in that, The matrix evaluation and judgment module uses the sensor validity flag to remove nodes that indicate an invalid state, and combines the reliability weighting factor to weight and map the processor standardized residual sequence and the memory standardized residual sequence into the processor two-dimensional feature matrix and the memory two-dimensional feature matrix, respectively. The matrix evaluation and judgment module traverses the discrete lag step intervals in the evaluation mode that allows for delayed backtracking, extracts the coupling features with physical time sequence lag offsets, and calculates the spatial two-dimensional cosine similarity and the corrected maximum lag similarity.

8. The server operating parameter analysis and processing platform according to claim 7, characterized in that, The matrix evaluation and judgment module reads the error status and power limit flag of the underlying hardware as hardware status and heat dissipation parameters, extracts the actual speed and target speed of the cooling fan configured in the heat dissipation system to calculate the fan speed deviation, and extracts the inlet air temperature change rate to perform the joint verification of the underlying hardware status. Under the premise that the underlying hardware does not find a hardware error state of the preset type, and the rate of change of the intake air temperature is less than or equal to the intake air temperature mutation threshold and the fan speed deviation is less than or equal to the speed deviation threshold, when the mean squared residual of the unit elements of the processor two-dimensional feature matrix and the memory two-dimensional feature matrix are both greater than the preset abnormal mean squared residual threshold, and when there is no power limit flag, the corrected maximum hysteresis similarity is greater than the preset similarity judgment threshold, or when there is a power limit flag, the corrected maximum hysteresis similarity is greater than the temporarily increased similarity judgment threshold, the matrix evaluation and judgment module confirms and outputs the valid abnormal state.

9. The server operating parameter analysis and processing platform according to claim 1, characterized in that, During normal operation, the sampling and analysis output module cyclically writes historical stack records into the user-mode main loop buffer that maintains the pre-allocated capacity limit. Upon receiving the valid abnormal state, the internal state machine of the sampling and analysis output module is triggered to switch to the snapshot retention state and activate the backup loop buffer. The user-mode main loop buffer is locked to stop overwriting, and the write pointer of the receiving thread is atomically redirected to the backup loop buffer with the same capacity as the user-mode main loop buffer. The post-abnormal delay timer is started synchronously. When the post-abnormal delay timer expires, the sampling and analysis output module extracts the historical stack records in the user-mode main loop buffer and the newly added stack records in the spare loop buffer, aligns and splices them on the timeline to generate the dynamic context snapshot.

10. The server operating parameter analysis and processing platform according to claim 1, characterized in that, The sampling and analysis output module loads the operating system kernel symbol table and the debugging information file of the user-mode application, performs range matching search on the binary instruction address in the persistent dynamic context snapshot, extracts the number of the non-uniform memory access node where the execution thread is located and the number of the non-uniform memory access node where the corresponding accessed physical memory page is located, and establishes a cross-node affinity mapping relationship. The sampling and analysis output module calculates the topological edge weights between adjacent caller functions and callee functions, compares and filters them using a preset topological edge trimming threshold, and performs aggregation based on the extracted cross-node affinity mapping relationship to generate a call topological data set. The non-empty call topological data set after trimming with the topological edge trimming threshold is rendered as the cross-node page dwell association call link graph.

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