Cable detection method and computing device

Abstract

Embodiments of the present application relate to a cable detection method and a computing device. The method comprises: receiving a cable detection code stream value sent by a board card side; identifying a board card type to which the board card belongs according to a cable detection code stream value range to which the cable detection code stream value belongs; wherein different board card types correspond to different cable detection code stream value ranges, and each board card type corresponds to a preset register set on the mainboard side, and each register set contains a register corresponding to a mainboard high-speed port; determining a register set corresponding to the identified board card type, and determining a register corresponding to a mainboard high-speed port to which the cable detection code stream value is connected, and storing the cable detection code stream value in the determined register; and performing cable detection based on a preset rule corresponding to each board card type according to the cable detection code stream values stored in different register sets. In this way, the accuracy of cable detection and the reliability of BIOS bandwidth resource allocation can be improved.

Description

Technical Field

[0001] This application relates to the field of server technology, and in particular to cable detection methods and computing devices. Background Technology

[0002] In server products, to meet the flexible configuration needs of different application scenarios, it is usually necessary to support the access of multiple types of cards, such as front hard drive backplanes and rear hard drive backplanes. In production and live network upgrade scenarios, precise detection and accurate alarms for cable connections can quickly indicate the location of incorrect connections by maintenance personnel, thereby improving operational efficiency. At the same time, the server's BIOS (basic input output system) will also flexibly allocate bandwidth resources based on the cable detection results of the interfaces. Therefore, the accuracy of cable detection is directly related to the rational allocation of system resources.

[0003] In related technologies, BMC can only obtain indiscriminate bitstream values ​​and cannot distinguish the type of backplane (such as front backplane or rear backplane) from which the bitstream value originates. Furthermore, whitelist alarm policies are set separately according to backplane classification. When server configurations are complex and multiple backplanes are used interchangeably, this lack of information can easily lead to false alarms. For example, a correct bitstream value from a rear backplane might be misjudged as an incorrect connection from a front backplane, resulting in inaccurate cable detection alarms in related technologies. Summary of the Invention

[0004] This application provides a cable testing method and computing device that can improve the accuracy of cable testing.

[0005] According to a first aspect of the embodiments of this application, a cable detection method is provided, the method comprising: Receive the cable detection bitstream value sent by the receiving board side; Based on the range of cable detection bitstream values ​​to which the cable detection bitstream value belongs, the type of board to which the board belongs is identified; different board types correspond to different ranges of cable detection bitstream values, and each board type on the motherboard side has a preset set of registers, and each set of registers contains the registers of the corresponding high-speed port of the motherboard; Determine the set of registers corresponding to the identified board type, determine the register corresponding to the high-speed port of the motherboard to which the cable detection bitstream value is connected, and store the cable detection bitstream value into the determined register; Based on the cable detection bitstream values ​​stored in different register sets, cable detection is performed according to the preset rules corresponding to each board type.

[0006] This embodiment decouples the detection of different types of backplane cables by pre-dividing the board types and their corresponding bitstream value ranges and setting up an independent register set for each type of board in the motherboard. Based on the classified register set, bitstream value storage and cable detection are performed separately, which can locate the board type and port position of the incorrectly connected cable. This fundamentally solves the problem of false alarms caused by the inability to distinguish the source of bitstream values ​​in related technologies, and improves the accuracy of cable detection and the reliability of BIOS bandwidth resource allocation.

[0007] In one possible implementation, the range of cable detection bitstream values ​​corresponding to different board types is pre-allocated in the following way: Board types are classified according to their physical location or functional attributes; Assign non-overlapping stream value ranges for each board type.

[0008] This embodiment ensures the correspondence between bitstream values ​​and board types by dividing the intervals into non-overlapping intervals, avoiding type misjudgment caused by bitstream value conflicts; and developers can adjust the interval divisions at any time according to product iterations and configuration changes, which has good scalability.

[0009] In one possible implementation, the cable detection bitstream value is transmitted using a single-bus protocol. The cable detection bitstream value is hexadecimal data with a value range of 00-FF.

[0010] This embodiment uses a single-bus protocol to transmit the code stream value, requiring only one signal line to complete data communication, effectively saving board interface resources and reducing hardware costs and wiring complexity. The use of a 00-FF hexadecimal data format ensures sufficient information capacity to distinguish different ports and board types, while also matching the register bit width of a CPLD (complex programmable logic device), facilitating data storage and processing. Furthermore, the single-bus protocol is simple to implement, highly reliable, and easy to implement in a CPLD, demonstrating good engineering practicality.

[0011] In one possible implementation, each type of board on the motherboard side has a pre-defined set of registers, including: In the complex programmable logic device (CPLD) on the motherboard, a corresponding number of cable detection register sets are created according to the number of board types. The number of registers in each set is the same as the number of high-speed ports on the motherboard and they correspond one-to-one.

[0012] In this embodiment, an independent register set is pre-created in the motherboard CPLD for each type of board, realizing physical isolation of the code stream value storage space for different board types; each register set contains registers that correspond one-to-one with the high-speed ports of the motherboard, ensuring the mapping between the code stream value storage location and the physical port; when reading, the BMC can directly distinguish the source of the code stream value based on the register set, without the need for additional parsing logic, thus simplifying the processing flow.

[0013] In one possible implementation, the board type is identified based on the range of cable detection bitstream values ​​to which the cable detection bitstream value belongs, including: The bitstream value is detected by analyzing the cable using the motherboard's CPLD. Determine the predefined target cable detection bitstream value range to which the cable detection bitstream value belongs; The board type is determined based on the preset correspondence between the target cable detection bitstream value range and the board type.

[0014] In this embodiment, the identification is performed at the hardware level by the motherboard CPLD, avoiding the delay and complexity caused by uploading the original bitstream value to the BMC and then performing software parsing; the uniqueness and accuracy of the identification are ensured by the preset correspondence between the bitstream value range and the board type, providing a foundation for subsequent storage and alarms.

[0015] In one possible implementation, determining the set of registers corresponding to the identified board type, determining the register corresponding to the high-speed port of the motherboard to which the cable detection bitstream value is connected, and storing the cable detection bitstream value into the determined registers includes: Based on the physical port location of the received cable's detected bitstream value, determine the target register index in the corresponding register set; The cable detection bitstream value is written to the target register based on the target register index.

[0016] This embodiment determines the register index based on the physical port location, which ensures that each bitstream value is stored in the register that uniquely corresponds to its source port; selecting the corresponding register set based on the board type can achieve physical isolation of the bitstream value storage space for different board types; this embodiment can be directly implemented by CPLD hardware without software intervention, and has the characteristics of low latency and high reliability.

[0017] In one possible implementation, cable detection is performed based on preset rules corresponding to each board type, according to the cable detection bitstream values ​​stored in different register sets, including: Read the cable detection bitstream values ​​stored in each register set respectively; The cable detection bitstream value stored in each register set is matched with the preset expected value of the corresponding board type on the motherboard high-speed port; If a mismatch exists, generate alarm information for the corresponding board type and the corresponding high-speed port of the motherboard.

[0018] In this embodiment, the BMC reads and matches registers separately according to the register set, which fundamentally eliminates detection interference between different types of backplanes and avoids false alarms. When the matching fails, the alarm information generated clearly includes the board type and port location, providing maintenance personnel with accurate fault location guidance and greatly improving operation and maintenance efficiency.

[0019] In one possible implementation, the preset expected value is the expected cable detection bitstream value pre-configured for each board type and each motherboard high-speed port.

[0020] This embodiment configures a desired bitstream value for each port of each type of board, providing an accurate matching benchmark for BMC cable detection. The correspondence between the desired value and the board type and port location enables BMC to perform independent matching based on the classified register set, fundamentally avoiding detection interference between different types of backplanes.

[0021] In one possible implementation, before receiving the cable detection bitstream value from the receiving board side, the method further includes: The boards are divided into multiple types, and each type of board is assigned a non-overlapping range of cable detection bitstream values; Create a set of registers in the motherboard CPLD that is the same number as the number of board types; each set contains registers that correspond one-to-one with the high-speed ports of the motherboard. In BMC, the desired cable detection bitrate value is pre-configured for each motherboard high-speed port of each board type.

[0022] This embodiment achieves the encoding of board type information in the bitstream value through board type division and bitstream value range allocation, providing a basis for subsequent identification; the creation of register sets in the motherboard CPLD provides independent storage space for bitstream values ​​of different board types, realizing hardware-level classification and isolation; the pre-configuration of expected values ​​in the BMC provides an accurate matching benchmark for cable detection.

[0023] According to a second aspect of the embodiments of this application, a cable detection device is provided, the device comprising: The bitstream value receiving module is used to receive the cable detection bitstream value sent by the board side; The type identification module is used to identify the type of the board based on the range of cable detection bitstream values ​​to which the cable detection bitstream value belongs. Different board types correspond to different ranges of cable detection bitstream values, and each board type on the motherboard side has a preset set of registers, and each set of registers contains the registers of the corresponding high-speed port of the motherboard. The storage module is used to determine the set of registers corresponding to the identified board type, determine the register corresponding to the high-speed port of the motherboard to which the cable detection bit stream value is connected, and store the cable detection bit stream value into the determined register. The detection module is used to perform cable detection based on the cable detection bitstream values ​​stored in different register sets and on preset rules corresponding to each board type.

[0024] According to a third aspect of the embodiments of this application, a computing device is provided. The computing device includes a memory and a processor, the memory storing a computer program, and the processor executing the program to implement the method as described above.

[0025] According to a fourth aspect of the embodiments of this application, a computer-readable storage medium is provided, on which a computer program is stored, which, when executed by a processor, implements the methods described in the embodiments of this application.

[0026] According to a fifth aspect of the embodiments of this application, a computer program product is provided, including a computer program that, when executed by a processor, implements the methods described above in the embodiments of this application. Attached Figure Description

[0027] More details, features, and advantages of embodiments of the present application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which: Figure 1 A schematic diagram of the system architecture provided for an exemplary embodiment of this application Figure 2 A schematic diagram of the structure of a server provided in an exemplary embodiment of this application; Figure 3 A schematic diagram of the communication protocol between the board and the motherboard provided in an exemplary embodiment of this application; Figure 4 A flowchart illustrating a cable detection method provided in an exemplary embodiment of this application; Figure 5 A schematic diagram of a cable testing process provided for an exemplary embodiment of this application; Figure 6 A schematic diagram of the register set and code stream value storage provided for an exemplary embodiment of this application; Figure 7 A schematic diagram of the BMC alarm processing flow provided for an exemplary embodiment of this application Figure 8 A schematic block diagram of the functional modules of a cable detection device provided in an exemplary embodiment of this application; Figure 9 A structural block diagram of a computing device provided for an exemplary embodiment of this application. Detailed Implementation

[0028] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that embodiments of this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the embodiments of this application. It should be understood that the accompanying drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0029] It should be understood that the various steps described in the method implementation of this application may be performed in different orders and / or in parallel. Furthermore, the method implementation may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.

[0030] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in the embodiments of this application are only used to distinguish different devices, modules, or units, and are not used to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0031] It should be noted that the terms "one" and "more" mentioned in the embodiments of this application are illustrative rather than restrictive. Those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more". The names of the messages or information exchanged between multiple devices in the embodiments of this application are for illustrative purposes only and are not intended to limit the scope of these messages or information.

[0032] As an optional but non-limiting implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device. It is understood that the above notification and user authorization process is merely illustrative and does not constitute a limitation on the implementation of this application's embodiments. Other methods that comply with relevant laws and regulations can also be applied to the implementation of this application's embodiments.

[0033] like Figure 1The diagram shown is a schematic representation of the system architecture provided in an embodiment of this application. Specifically, the system can be a server, including a motherboard 11 and a backplane 12, which can be connected via cables.

[0034] The motherboard 11 is equipped with a CPU 13 and multiple high-speed ports (P0, P1, and P2 as shown in the figure). The motherboard 11 may also contain a CPLD (complex programmable logic device) and a BMC (baseboard management controller). The motherboard CPLD receives cable detection bitstream values ​​sent by the backplane 12, parses and stores them according to preset rules; the BMC reads the bitstream values ​​(i.e., cable detection bitstream values) stored in the motherboard CPLD and generates cable detection alarms.

[0035] The backplane 12 is equipped with various types of boards, such as UBC1, UBC2, UBC3, UBCA, UBCB, and UBCC shown in the figure. Different types of backplanes correspond to different physical locations or functional attributes, such as front hard drive backplanes, rear hard drive backplanes, etc. Each type of backplane can be equipped with a CPLD (not shown in the figure) for generating and sending cable detection bitstream values.

[0036] During system operation, when backplane 12 is connected to a high-speed port (such as P0, P1, P2) of motherboard 11 via a cable, the backplane CPLD sends a preset cable detection bitstream value to the motherboard CPLD via a single-bus protocol. The motherboard CPLD identifies the board type of the backplane that sent the bitstream value based on the bitstream value range of the received bitstream value, and stores the bitstream value in the register set corresponding to the board type and the register corresponding to the high-speed port of the motherboard to which the bitstream value is connected. The BMC reads the bitstream values ​​stored in each register set via a communication protocol (such as I2C) and matches them with the pre-configured expected bitstream value. If a mismatch exists, an alarm message is generated for the corresponding board type and port.

[0037] pass Figure 1 The system architecture shown in this application embodiment can decouple the cable detection of different types of backplanes, avoid false alarms caused by mixed backplane types, and improve the accuracy of cable detection and the reliability of BIOS bandwidth resource allocation.

[0038] like Figure 2 The diagram shown is a functional module schematic diagram provided in an embodiment of this application. This diagram illustrates the various functional modules involved in implementing the cable detection method and their interrelationships. It should be noted that... Figure 2The module shown is a logical functional unit, and its physical deployment location is similar to... Figure 1 The hardware architecture shown corresponds to this.

[0039] Server 10 includes a motherboard 11 and a backplane 12.

[0040] The back panel has the following on 12 sides: The stream generation module 26 is deployed in the backplane CPLD. This module is used to generate cable detection stream values ​​according to a preset protocol (such as a single-bus protocol), and send the generated stream values ​​to the motherboard 11 when the backplane is connected to the motherboard's high-speed port. Different backplane types have different preset stream value ranges, and the stream generation module 26 generates corresponding stream values ​​based on these preset ranges.

[0041] The motherboard has the following features on side 11: The interface decoding module 21 is deployed in the motherboard CPLD. This module is communicatively connected to the stream generation module 26 of the backplane 12, and is used to receive the cable detection stream value sent by the backplane 12, and parse the received stream value according to the corresponding protocol.

[0042] The register assignment module 22, deployed in the motherboard CPLD and connected to the interface decoding module 21, is used to identify the board type of the backplane sending the bitstream value based on the bitstream value range to which the parsed bitstream value belongs, and to store the bitstream value in the register set corresponding to the board type and the register corresponding to the high-speed port of the motherboard to which the bitstream value is connected. Each board type has a pre-set corresponding register set in the motherboard CPLD, and each register set contains registers that correspond one-to-one with all high-speed ports of the motherboard.

[0043] The BMC communication module 23 is deployed in the motherboard CPLD and BMC, serving as the interface between the two. This module is used to realize data interaction between the BMC and CPLD, typically through the I2C bus protocol, enabling the BMC to read the bitstream values ​​stored in various register sets.

[0044] The whitelist matching module 24, deployed in the BMC, is connected to the BMC communication module 23. This module is used to match the bitstream values ​​read from each set of registers with the expected bitstream values ​​pre-configured for each board type and each high-speed port of the motherboard.

[0045] The alarm processing module 25, deployed in the BMC, is connected to the whitelist matching module 24. This module generates alarm information for the corresponding board type and port if there is a mismatch based on the matching results of the whitelist matching module 24, so as to instruct maintenance personnel to handle it in a timely manner.

[0046] During system operation, the interaction flow of each module is as follows: After the backplane 12 is connected to the motherboard 11, the bitstream generation module 26 generates and sends the cable detection bitstream value; the interface decoding module 21 receives and parses the bitstream value; the register assignment module 22 identifies the board type according to the bitstream value range and stores the bitstream value into the corresponding register; the BMC communication module 23 reads the bitstream value in the register; the whitelist matching module 24 compares the read bitstream value with the preset expected value; if the matching fails, the alarm processing module 25 generates and reports alarm information.

[0047] pass Figure 2 The functional modules and their interactions shown can effectively avoid detection interference between different types of backplanes, improve the accuracy of cable detection and the level of alarm precision.

[0048] like Figure 3 The diagram shown is a schematic of the communication protocol between the board and the motherboard provided in an embodiment of this application. The diagram illustrates the physical connection and protocol implementation method for transmitting cable detection bitstream values ​​between the backplane CPLD and the motherboard CPLD.

[0049] exist Figure 3 In this embodiment, the backplane 12 and the motherboard 11 communicate using a single-bus protocol. Specifically, the backplane CPLD and the motherboard CPLD are connected via a single signal line to achieve unidirectional transmission of the bitstream value. Since the data transmission direction in the cable detection scenario is only from the backplane to the motherboard, using a single-wire UART protocol is sufficient to meet the transmission requirements, while also simplifying wiring and reducing costs.

[0050] During signal transmission, the backplane CPLD acts as the transmitter, serially sending the cable detection bitstream value to the motherboard CPLD according to the preset baud rate and data format. The motherboard CPLD acts as the receiver, sampling and parsing the received signal to recover the original hexadecimal bitstream value data.

[0051] The advantages of using the single-bus UART protocol are: only one signal line is needed to complete the transmission of the code stream value, saving board interface resources and reducing hardware costs. At the same time, the protocol is simple, reliable, and easy to implement in CPLD.

[0052] It should be noted that, Figure 3 tx1, tx2, and tx3 in the diagram represent three transmit pins / transmit channels on the CPLD on the backplane. Each tx pin corresponds to a single bus output, used to send cable detection bitstream values ​​to the CPLD on the motherboard. Multiple tx pins can be connected to different high-speed ports on the motherboard, or to different receivers on the same motherboard.

[0053] Additionally, rx1, rx2, rx3, and rx4 represent four receive pins / receive channels on the motherboard CPLD. Each rx pin corresponds to a single bus input, used to receive the bit stream value sent from the backplane CPLD. The four rx pins typically correspond to four high-speed ports on the motherboard (such as P0, P1, P2, and P3).

[0054] The tx pins of the backplane CPLD and the rx pins of the motherboard CPLD are connected one-to-one via a single signal line. For example: backplane tx1 → motherboard rx1 (corresponding to port P0), tx2 → rx2 (corresponding to port P1), and so on. Each connection channel transmits the bit stream value independently without interfering with each other.

[0055] By defining the tx / rx pins, unidirectional serial data transmission from the backplane CPLD to the motherboard CPLD is realized. Each rx pin corresponds to a high-speed port on the motherboard, enabling the motherboard CPLD to directly identify which physical port the current bit stream value is connected from when receiving the bit stream value. This one-to-one correspondence at the pin level provides a hardware foundation for determining the target register index based on the physical port location.

[0056] In this embodiment, 3 tx and 4 rx represent only an exemplary configuration of the number of backplanes and motherboard ports. In practical applications, the number of tx and rx can be flexibly adjusted according to the specific server configuration, and each high-speed port of the motherboard should have a corresponding independent rx receiving channel on the motherboard CPLD.

[0057] Based on the above embodiments, this application also provides a cable detection method, such as... Figure 4 As shown, the method may include the following steps: In step S410, the cable detection bitstream value sent by the receiving board side is received.

[0058] Specifically, when the backplane is connected to the motherboard's high-speed port via a cable, the backplane CPLD acts as the transmitter, sending pre-configured cable detection bitstream values ​​to the motherboard CPLD via a single-bus protocol. The motherboard CPLD's interface decoding module receives these bitstream values ​​and parses them according to the corresponding protocol. The cable detection bitstream values ​​can be hexadecimal data, ranging from 00 to FF, with different board types having pre-defined, non-overlapping bitstream value ranges.

[0059] In this embodiment, the cable detection bitstream value refers to a string of data generated by the backplane CPLD and sent to the motherboard CPLD to identify the cable connection status. Each bitstream value uniquely corresponds to a specific port or a specific connection relationship on the backplane. The backplane CPLD transmits the bitstream value to the motherboard CPLD via a single-bus protocol. The motherboard CPLD determines whether the currently connected cable is correct based on the received bitstream value (i.e., the cable detection bitstream value). The bitstream value itself carries board type information; that is, different board types have preset non-overlapping bitstream value ranges, enabling the motherboard CPLD to identify the type of backplane from which the bitstream value originates when parsing it.

[0060] It should be noted that, in this embodiment, the backplane refers to a physical component in a server used to support multiple boards, such as a front hard drive backplane or a rear hard drive backplane; a board refers to a functional module inserted into or integrated on the backplane, such as a UBC (universal backplane controller). The boards connect to the motherboard through the backplane; that is, the backplane acts as an intermediate carrier, and each board on it is connected to its corresponding high-speed port on the motherboard via a cable, thereby enabling signal transmission and data interaction between the boards and the motherboard.

[0061] In step S420, the board type is identified based on the range of cable detection bitstream values. Different board types correspond to different cable detection bitstream value ranges, and each board type on the motherboard side has a preset set of registers, with each set containing registers for the corresponding high-speed port on the motherboard.

[0062] Different board types correspond to different cable detection bitstream value ranges, and each board type has a corresponding set of registers preset on the motherboard side. Each register set contains registers for all high-speed ports of the corresponding motherboard. In specific implementation, the register assignment module of the motherboard CPLD parses the received bitstream value, determines which predefined bitstream value range the value falls into, and determines the board type to which the board sending the bitstream value belongs based on the preset correspondence between the bitstream value range and the board type. For example, if the bitstream value falls into the 10-2F range corresponding to the front backplane, it is identified as the front backplane; if it falls into the 30-4F range corresponding to the rear backplane, it is identified as the rear backplane.

[0063] In step S430, the set of registers corresponding to the identified board type is determined, the register corresponding to the high-speed port of the motherboard to which the cable detection bitstream value is connected is determined, and the cable detection bitstream value is stored in the determined register.

[0064] In this embodiment, the motherboard CPLD determines the target register index in the corresponding register set based on the physical port location where the bitstream value is received, and writes the bitstream value into the target register. For example, assuming the motherboard has four high-speed ports P0-P3, and the front backplane and rear backplane each correspond to a set of registers, each set containing four registers, if a bitstream value of 0x15 is received from the front backplane at port P1, then the bitstream value is stored in the register corresponding to P1 in the front backplane register set.

[0065] Specifically, the system can first determine the set of registers corresponding to the identified board type in the motherboard CPLD. Since the motherboard CPLD pre-creates an independent set of registers for each board type (e.g., register set A for the front backplane and register set B for the rear backplane), when step S420 identifies that the current board belongs to the front backplane, the system selects the set of registers corresponding to the front backplane as the target set.

[0066] Secondly, based on the location of the physical port receiving the bitstream value, the specific register corresponding to that port in the selected register set can be determined. Each register set contains registers that correspond one-to-one with all high-speed ports on the motherboard. For example, port P0 corresponds to register index 0, port P1 corresponds to register index 1, and so on. The system can determine which register in the target register set should be used to store the bitstream value based on which physical port it is connected from.

[0067] Finally, the obtained cable detection bitstream value can be written into the designated register. The register assignment module of the motherboard CPLD generates a write enable signal, stores the bitstream value data into the storage unit of the register, and completes the storage operation.

[0068] Through the above steps, each bitstream value is accurately stored in a register that uniquely corresponds to its board type and physical port location, thus achieving classified and isolated storage of bitstream values ​​of different board types and different ports.

[0069] In step S440, cable detection is performed based on the cable detection bitstream values ​​stored in different register sets and the preset rules corresponding to each board type.

[0070] In this embodiment, the BMC reads the bitstream values ​​stored in each register set via the I2C bus protocol. For the front backplane register set, the bitstream values ​​are matched with the pre-configured expected bitstream values ​​for each port of the front backplane; for the rear backplane register set, the bitstream values ​​are matched with the pre-configured expected bitstream values ​​for each port of the rear backplane. If a mismatch is found, an alarm message is generated for the corresponding board type and port to instruct maintenance personnel to handle the issue promptly.

[0071] The method provided in this embodiment allows the BMC to independently detect and alarm for each backplane type, since the bitstream values ​​of different backplane types are stored in different register sets, effectively avoiding false alarms caused by mixed backplane types.

[0072] This embodiment decouples the detection of different types of backplane cables by pre-dividing the board types and their corresponding bitstream value ranges and setting up an independent register set for each type of board in the motherboard. Based on the classified register set, bitstream value storage and cable detection are performed separately, which can locate the board type and port position of the incorrectly connected cable. This fundamentally solves the problem of false alarms caused by the inability to distinguish the source of bitstream values ​​in related technologies, improves the accuracy of cable detection and the reliability of BIOS bandwidth resource allocation, and this solution is based on existing hardware and does not require additional costs.

[0073] In this embodiment, the range of cable detection bitstream values ​​corresponding to the different board types can be pre-allocated in the following way: (1) Classify board types according to their physical location or functional attributes.

[0074] In this embodiment, physical location classification refers to categorizing cards based on their installation position within the server chassis, such as front hard drive backplane, rear hard drive backplane, and center backplane. Functional attribute classification refers to categorizing cards based on their assigned business functions, such as hard drive backplane, PCIe expansion card, and power supply backplane. By classifying cards by physical location or functional attributes, the various cards that may exist in a server can be categorized into several distinct types.

[0075] (2) Assign non-overlapping flow value ranges for each board type.

[0076] In this embodiment, the cable detection bitstream value can be transmitted using a single-bus protocol. The bitstream value can be hexadecimal data, ranging from 00 to FF, supporting a total of 256 different bitstream values. Developers can divide this value range into multiple continuous or discontinuous intervals according to actual needs, assigning them to different board types. For example, the 10-2F interval can be assigned to the front backplane, the 30-4F interval to the rear backplane, and the 50-6F interval to special function boards, etc. The bitstream value within each interval can be further used to distinguish different ports or different cables of the same type.

[0077] It should be noted that the above rules for dividing the bitstream value ranges can be customized by developers based on the actual product configuration, as long as the bitstream value ranges corresponding to different board types do not overlap. After the division is completed, the rules will be embedded in the bitstream generation module of the backplane CPLD to guide each backplane in generating the corresponding cable detection bitstream values.

[0078] By pre-allocating the bitstream value range using the above method, this embodiment achieves an explicit mapping between board type and bitstream value space. The non-overlapping interval division ensures the correspondence between bitstream values ​​and board type, avoiding type misjudgment due to bitstream value conflicts; furthermore, developers can adjust the interval division at any time according to product iterations and configuration changes, demonstrating good scalability.

[0079] In one specific implementation, the allocation rules for cable detection bitstream values ​​can be referred to Table 1.

[0080] Table 1:

[0081] Table 1 is a cable detection bitstream value allocation rule table provided in an exemplary embodiment of this application. Table 1 exemplarily shows the mapping relationship between different board types and their corresponding bitstream value ranges.

[0082] As shown in Table 1, for the front backplane, the assigned cable detection bitstream value range is 10-3F (hexadecimal). The bitstream values ​​within this range are used to identify all cable connections from the front backplane.

[0083] For the rear panel, the assigned cable detection bitstream value range is 40-6F (hexadecimal). The bitstream values ​​within this range are used to identify all cable connections from the rear panel.

[0084] For special function boards or expansion boards, the cable detection bitstream value range assigned to them is 70-9F (hexadecimal). For other types of boards, the cable detection bitstream value range assigned to them is a0-FF (hexadecimal), and the bitstream value within this range is used to identify cable connections from other types of boards.

[0085] It should be noted that the bitstream value range allocation shown in Table 1 is only an illustrative example. In actual product applications, developers can flexibly adjust the bitstream value range corresponding to each board type according to the specific hardware configuration and requirements of the server. For example, the range of a certain type can be expanded or narrowed, or a new board type can be added and a new bitstream value range assigned to it. The core is to ensure that the bitstream value ranges corresponding to different board types do not overlap, so as to ensure that the motherboard CPLD can uniquely identify the board type based on the bitstream value.

[0086] According to the allocation rules shown in Table 1, when generating the bitstream value, the backplane CPLD can select a specific bitstream value from the corresponding bitstream value range based on its own board type, thereby realizing the encoding and transmission of board type information in the bitstream value.

[0087] like Figure 5 The diagram shown is a schematic of a cable detection process provided in an exemplary embodiment of this application. It illustrates the specific processing flow of the motherboard CPLD classifying and storing the bitstream values ​​according to their range after receiving them from the backplane. This process can be executed by the register assignment module of the motherboard CPLD and specifically includes the following steps: In step S501, the process begins. After the motherboard CPLD is powered on and initialized, it enters the bitstream value reception waiting state.

[0088] In step S502, the bitstream from the backplane is received. In this embodiment, the bitstream value is detected by receiving the cable transmitted from the backplane. When the backplane is connected to the motherboard's high-speed port and transmits the bitstream value via a single-bus protocol, the interface decoding module of the motherboard's CPLD receives and parses the bitstream value to obtain the original hexadecimal bitstream data.

[0089] In step S503, it is determined whether the bitstream value is greater than 10 and less than 3f (i.e., 3F, hexadecimal). This step is the first-level range judgment, corresponding to the predefined bitstream value range of the front hard disk backplane. If the judgment result is "yes" (Y), that is, the bitstream value falls within the 10-3F range, the process proceeds to step S504; if the judgment result is "no" (N), the process proceeds to step S505 to continue the subsequent range judgment.

[0090] In step S504, the bitstream value is stored in the front hard disk backplane register table. When the bitstream value is determined to belong to the bitstream value range corresponding to the front hard disk backplane, the motherboard CPLD determines the target register index in the front hard disk backplane register set according to the physical port location of the receiving bitstream value, and writes the bitstream value into the corresponding register. The process then proceeds to step S511.

[0091] In step S505, it is determined whether the bitstream value is greater than 40 and less than 6f (i.e., 6F, hexadecimal). This step is the second-level range judgment, corresponding to the predefined bitstream value range of the rear hard disk backplane. If the judgment result is "yes" (Y), that is, the bitstream value falls within the range corresponding to the rear hard disk backplane, the process proceeds to step S506; if the judgment result is "no" (N), the process proceeds to step S507.

[0092] In step S506, the bitstream value is stored in the rear hard disk backplane register table. The motherboard CPLD writes the bitstream value into the register corresponding to the current physical port in the rear hard disk backplane register set. The process then proceeds to step S511.

[0093] In step S507, it is determined whether the bitstream value is greater than 70 and less than 9f (i.e., 9F, hexadecimal). This step is the third-level range judgment, corresponding to the predefined bitstream value range of the special function board. If the judgment result is "yes" (Y), that is, the bitstream value falls within the range corresponding to the special board, the process proceeds to step S508; if the judgment result is "no" (N), the process proceeds to step S509.

[0094] In step S508, the bitstream value is stored in the special board register table. The motherboard CPLD writes the bitstream value into the register corresponding to the current physical port in the special board register set. The process then proceeds to step S511.

[0095] In step S509, it is determined whether the bitstream value is greater than a0 (i.e., A0, in hexadecimal). This step is the fourth-level range judgment, corresponding to the predefined bitstream value range (A0-FF) of other types of boards. If the judgment result is "yes" (Y), that is, the bitstream value falls into the range corresponding to other boards, the process proceeds to step S510; if the judgment result is "no" (N), the process proceeds to step S511 and the bitstream value is not saved (or is regarded as an invalid bitstream value).

[0096] In step S510, the bitstream value is stored in the other board register table. The motherboard CPLD writes the bitstream value into the register corresponding to the current physical port in the other board register set. Then the process proceeds to step S511.

[0097] In step S511, the bitstream value is not saved or the process ends. When the bitstream value does not fall within any predefined legal range, the motherboard CPLD considers it an invalid bitstream value, does not store it, and the process ends; for cases where it has been successfully stored, the process also ends here, waiting for the next bitstream value to be received.

[0098] It should be noted that, Figure 5 The illustrated process is merely an exemplary order of range judgment and interval division. In practical applications, developers can flexibly adjust the judgment order, interval boundary values, and add or remove judgment branches based on the number of board types and specific configurations. The core lies in using multi-level range judgment to classify and store the received bitstream values ​​into corresponding register sets, achieving hardware-level isolation of bitstream values ​​from different board types.

[0099] pass Figure 5 As shown in the process, the motherboard CPLD can complete type identification and classification storage the moment it receives the bit stream value, providing a foundation for subsequent BMC detection and alarm.

[0100] It should be noted that, Figure 5In the example, the lowercase f used to represent hexadecimal and the uppercase F have the same meaning.

[0101] In one specific implementation, the cable detection bitstream value can be transmitted using a single-bus protocol. Specifically, the backplane CPLD and the motherboard CPLD are connected via a single signal line. The backplane CPLD acts as the transmitter, sending the bitstream value serially to the motherboard CPLD according to a preset baud rate and data format. The motherboard CPLD acts as the receiver, sampling and parsing the received signal to recover the original bitstream value data.

[0102] The bitstream values ​​can be hexadecimal data, ranging from 00 to FF, meaning each bitstream value occupies one byte and can represent 256 different states or identifiers. This value range is sufficient to cover the common number of ports and card types in server products, while also facilitating data processing and storage by the CPLD.

[0103] In this embodiment, a single-bus protocol is used to transmit the code stream value. Only one signal line is needed to complete data communication, which effectively saves board interface resources and reduces hardware costs and wiring complexity. The use of a 00-FF hexadecimal data format ensures sufficient information capacity to distinguish different ports and board types, and matches the register bit width of the CPLD, facilitating data storage and processing. At the same time, the single-bus protocol is simple to implement, highly reliable, and easy to implement in the CPLD, making it highly practical for engineering applications.

[0104] In the embodiment, each type of board on the motherboard side has a preset set of registers. Specifically, it may include: in the motherboard CPLD, a corresponding number of cable detection register sets can be created according to the number of board types. The number of registers in each set is the same as the number of high-speed ports on the motherboard and they correspond one-to-one.

[0105] In this embodiment, the motherboard CPLD can create a corresponding number of cable detection register sets based on the predefined number of board types. For example, if the system defines three types: front backplane, rear backplane, and special function backplane, then three independent register sets are created in the motherboard CPLD.

[0106] The number of registers in each register set is the same as the number of high-speed ports on the motherboard, and there is a one-to-one correspondence between them. Assume the motherboard has N high-speed ports (e.g., Figure 1 As shown in the diagram (P0, P1, P2, etc.), each register set contains N registers, which are used to store the cable detection bitstream values ​​from the corresponding board type and connected to each port. For example, register 0 in the front panel backplane register set corresponds to port P0, register 1 corresponds to port P1, and so on.

[0107] It should be noted that the creation of the aforementioned register set is completed during system initialization or hardware design. Once established, it is permanently embedded in the motherboard CPLD logic and does not require dynamic allocation each time a cable is connected. When the backplane is connected to a high-speed port on the motherboard and sends a bitstream value, the motherboard CPLD can quickly locate the corresponding register in the target register set based on the identified board type and the current physical port location, and write the bitstream value into it.

[0108] Through the above method, this embodiment pre-creates an independent register set for each type of board in the motherboard CPLD, realizing physical isolation of the bitstream value storage space for different board types; each register set contains registers that correspond one-to-one with the high-speed ports of the motherboard, ensuring the mapping between the bitstream value storage location and the physical port; when reading, the BMC can directly distinguish the source of the bitstream value based on the register set, without the need for additional parsing logic, simplifying the processing flow; at the same time, this design has good scalability, when adding a new type of board, only the corresponding register set needs to be added in the CPLD, without changing the existing hardware and software architecture.

[0109] Based on the above embodiments, in another embodiment provided in this application, step S420 may specifically include the following steps: In step S421, the bitstream value is detected by parsing the cable through the motherboard CPLD.

[0110] In this embodiment, the interface decoding module of the motherboard CPLD receives the serial data signal sent from the backplane side, samples and parses the signal according to the timing requirements of the single-bus protocol, and recovers the original hexadecimal code stream value data. This parsing process includes operations such as start bit identification, data bit reading, and stop bit verification to ensure that the obtained code stream value is accurate.

[0111] In step S422, the predefined target cable detection bitstream value range to which the cable detection bitstream value belongs is determined.

[0112] After the register assignment module of the motherboard CPLD obtains the parsed bitstream value, it compares it with a bitstream value range partitioning table pre-stored in the CPLD logic or firmware. By determining which predefined interval (e.g., 10-2F, 30-4F, 50-6F, etc.) the bitstream value falls into, the target bitstream value range is determined. This comparison process can be implemented using a numerical comparator or a lookup table.

[0113] In step S423, the board type is determined according to the preset correspondence between the target cable detection bitstream value range and the board type.

[0114] The motherboard CPLD maintains a mapping relationship between bitstream value ranges and board types. For example, if the target bitstream value range is determined to be 10-3F, it is identified as a front backplane according to the preset correspondence; if it is 40-6F, it is identified as a rear backplane; and if it is a0-FF, it is identified as another type of board. Through the above mapping, the board type to which the board sending the bitstream value belongs can be uniquely determined.

[0115] It should be noted that the above steps S421 to S423 are completed continuously by the motherboard CPLD within one processing cycle without the participation of the BMC, thereby realizing rapid identification of the board type and hardware-level decoupling.

[0116] In this embodiment, the identification is performed at the hardware level by the motherboard CPLD, avoiding the delay and complexity caused by uploading the original bitstream value to the BMC and then performing software parsing. The preset correspondence between the bitstream value range and the board type ensures the uniqueness and accuracy of the identification, providing a foundation for subsequent storage and alarms. At the same time, this implementation method makes full use of the CPLD's parallel processing capabilities, which can support rapid identification when multiple ports are connected at the same time, improving the system's real-time performance and processing efficiency.

[0117] Based on the above embodiments, in another embodiment provided in this application, step S430 may specifically include the following steps: In step S431, the target register index in the corresponding register set is determined based on the physical port location that receives the cable detection code stream value.

[0118] Specifically, after identifying the board type, the register assignment module of the motherboard CPLD can further obtain the physical port information currently receiving the bitstream value. Since each high-speed port on the motherboard has a unique physical identifier (such as port numbers P0, P1, P2, etc.), the location of this physical port directly determines its storage location in the corresponding register set. The register assignment module calculates the index value of the target register in the corresponding register set based on a preset port-register mapping relationship. For example, if a bitstream value is received at port P1, the target register index is 1, pointing to the register associated with port P1 in the corresponding register set.

[0119] In step S432, the cable detection bitstream value is written to the target register based on the target register index.

[0120] Based on the determined register set (corresponding to the board type) and register index (corresponding to the physical port), a write enable signal can be generated to write the parsed bitstream value data into the specified target register. After the write operation is completed, the bitstream value is persistently stored in the dedicated register of the corresponding board type and port for subsequent reading and processing by the BMC.

[0121] It should be noted that the above steps S431 and S432 are completed by the motherboard CPLD at the hardware level. Since the register sets of different board types are independent of each other and the register positions of different physical ports are distinct from each other, the storage of bitstream values ​​will not conflict when multiple ports are connected at the same time.

[0122] This embodiment determines the register index based on the physical port location, which ensures that each bitstream value is stored in the register that uniquely corresponds to its source port; selecting the corresponding register set based on the board type can achieve physical isolation of the bitstream value storage space for different board types; this embodiment can be directly implemented by CPLD hardware without software intervention, and has the characteristics of low latency and high reliability.

[0123] Based on the above embodiments, in another embodiment provided in this application, step S440 may specifically include the following steps: In step S441, the cable detection bitstream values ​​stored in each register set are read respectively.

[0124] The BMC periodically or event-triggeredly accesses the motherboard CPLD via a communication protocol (such as the I2C bus protocol) to sequentially read the bitstream values ​​stored in each register set. Since each register set corresponds to a board type, and each register within a set corresponds to a high-speed port on the motherboard, the BMC obtains a port-level bitstream value data matrix categorized by board type.

[0125] In step S442, the cable detection bitstream value stored in each register set is matched with the preset expected value of the corresponding board type on the high-speed port of the motherboard.

[0126] The BMC internally maintains preset expected values ​​for each board type on each high-speed port of the motherboard. These expected values ​​are pre-configured during the system design phase based on the correct cable connection topology. The BMC compares each register value read in step S441 with the expected value for the corresponding board type and port. For example, for the register corresponding to port P0 in the front backplane register set, the read bitstream value should match the expected value for port P0 of the front backplane; if they do not match, it is determined that there is an abnormality in the cable connection of that port.

[0127] In step S443, if a mismatch exists, alarm information is generated for the corresponding board type and the corresponding motherboard high-speed port.

[0128] When a mismatch is found during the comparison in step S442, the BMC's alarm processing module immediately generates an alarm containing specific information. This alarm information includes at least: the type of board exhibiting the anomaly (e.g., "front panel backplane"), the high-speed port of the motherboard where the anomaly occurred (e.g., "P0 port"), and a comparison of the expected and actual values ​​(optional). This alarm can be reported to maintenance personnel via the BMC's web interface, SNMP traps, system logs, etc., instructing them to quickly locate and repair the incorrectly connected cable.

[0129] It should be noted that, since the register sets of different board types are independent of each other, the above matching and alarm processes can be performed in parallel without interference. Even if multiple board types experience anomalies simultaneously, the BMC can generate corresponding alarm information separately without confusion.

[0130] In this embodiment, the BMC reads and matches registers separately according to the register set, which fundamentally eliminates detection interference between different types of backplanes and avoids false alarms. When the matching fails, the alarm information generated clearly includes the board type and port location, providing maintenance personnel with accurate fault location guidance and greatly improving operation and maintenance efficiency.

[0131] In the embodiment, the aforementioned preset expected value can be the expected cable detection bitstream value pre-configured for each type of board and each high-speed port of the motherboard.

[0132] Specifically, during the system design or initialization phase, developers can configure a desired cable detection bitstream value for each high-speed port (e.g., P0, P1, P2) of the motherboard for each possible type of board (e.g., front backplane, rear backplane, special function board, etc.) based on the server's expected correct cable connection topology. This desired value reflects the bitstream value that a specific type of board should send when connected to a specific port under correct connection conditions.

[0133] For example, the expected value can be configured as 0x15 for a correct connection of the front backplane to the P0 port; and as 0x35 for a correct connection of the rear backplane to the P0 port. These expected values ​​are stored in the BMC's non-volatile storage medium or embedded in the BMC's firmware code, forming a complete "expected value mapping table".

[0134] When the BMC performs cable testing, the whitelist matching module queries the corresponding expected value from the mapping table based on the board type and port location corresponding to the currently read register set, and compares the actual read bitstream value with the expected value. If they match, the cable connection at that port is determined to be correct; if they do not match, the connection is determined to be abnormal.

[0135] It should be noted that the above-mentioned expected value configuration is independent of the hardware implementation and can be flexibly adjusted according to product specifications and configuration requirements. When the server supports new card types or the port layout changes, only the expected value mapping table in the BMC needs to be updated, without modifying the hardware logic of the motherboard CPLD.

[0136] This embodiment configures a desired bitstream value for each port of each type of board, providing an accurate matching benchmark for BMC cable detection. The correspondence between the desired value and the board type and port location enables BMC to perform independent matching based on the classified register set, fundamentally avoiding detection interference between different types of backplanes.

[0137] In the embodiments, such as Figure 6 The diagram illustrates a register set and bitstream value storage provided in an exemplary embodiment of this application. It shows register sets configured for different types of backplanes in the motherboard CPLD, and examples of bitstream values ​​stored in each register set.

[0138] Figure 6 The horizontal header shows the register sets corresponding to the three board types: front backplane register set, rear backplane register set, and special board register set. Each register set contains multiple registers that correspond one-to-one with the motherboard's high-speed ports. In this example, it is assumed that the motherboard has four high-speed ports (UBC1-1, UBC1-2, UBC1-3, and UBC1-4 as shown in the figure), therefore each register set contains four registers.

[0139] The second row of the table header shows the physical address or identifier of each register. For example, the addresses of the four registers in the front backplane register set are 0x30, 0x31, 0x32, and 0x33; the addresses of the four registers in the rear backplane register set are 0x34, 0x35, 0x36, and 0x37; and the addresses of the four registers in the special board register set are 0x38, 0x39, 0x3a, and 0x3b. These register addresses are independent of each other in the address space of the motherboard CPLD and are used to distinguish the storage locations of different board types and different ports.

[0140] The main body of the table shows examples of the actual bitstream values ​​stored in each register set for three different backplane access scenarios: Backplane 1 is identified as a front backplane type, and the bitstream value generated after its connection is stored in the front backplane register set. Specifically, bitstream value 0x15 is stored in port UBC1-2 (corresponding address 0x31), bitstream value 0x16 is stored in port UBC1-3 (corresponding address 0x32), while ports UBC1-1 and UBC1-4 are not connected or have not received a valid bitstream value, so their stored value is 0x00. At this time, the register sets of the rear backplane and special board are empty (blank or 0x00).

[0141] Backplane 2 is identified as a rear backplane type, and the bitstream value generated after its connection is stored in the rear backplane register set. Specifically, bitstream value 0x55 is stored in port UBC1-1 (corresponding address 0x34), bitstream value 0x56 is stored in port UBC1-2 (corresponding address 0x35), while ports UBC1-3 and UBC1-4 are not connected and their stored value is 0x00. At this time, there is no data in the register sets of the front backplane and special boards.

[0142] Backplane 3 is identified as a special board type, and the bitstream value generated after its connection is stored in the special board register set. Specifically, the bitstream value 0x90 is stored in port UBC1-2 (corresponding address 0x39), the bitstream value 0x91 is stored in port UBC1-4 (corresponding address 0x3b), while ports UBC1-1 and UBC1-3 are not connected and their stored value is 0x00. At this time, there is no data in the register sets of both the front and rear backplanes.

[0143] pass Figure 6 The example clearly demonstrates that this embodiment achieves physically isolated storage of bitstream values ​​for different backplane types by setting up independent register sets for each board type. Even if multiple backplanes are connected sequentially or simultaneously, their bitstream values ​​will only be stored in the register sets corresponding to their respective types, without mixing. This storage mechanism provides a foundation for subsequent fine-grained detection and alarms by the BMC. When the BMC reads the front backplane register set, the bitstream value obtained will inevitably originate from the front backplane and will not be interfered with by the bitstream values ​​of the rear backplane or special boards, thereby fundamentally avoiding false alarms.

[0144] Based on the above embodiments, in another embodiment provided in this application, before step S410, the method may further include the following steps: In step S401, the boards are divided into multiple types, and each type of board is assigned a non-overlapping range of cable detection bitstream values.

[0145] During the system design phase, the cards that may be connected to the server are first categorized into several distinct types based on their physical location (e.g., front, rear, center) or functional attributes (e.g., hard drive backplane, PCIe expansion cards, power supply backplane). Then, based on the 00-FF hexadecimal bitstream value space, non-overlapping bitstream value ranges are assigned to each card type, as shown in Table 1 above. This allocation rule is embedded in the bitstream generation module of the backplane CPLD to guide the generation of corresponding bitstream values ​​for each type of card.

[0146] In step S402, a set of registers is created in the motherboard CPLD that is the same number as the number of board types; wherein each set contains registers that correspond one-to-one with the high-speed ports of the motherboard.

[0147] Specifically, based on the number of board types identified in step S401, a corresponding number of cable detection register sets can be created in the hardware logic of the motherboard CPLD. Assuming the motherboard has N high-speed ports (e.g., P0, P1, ..., PN-1), each register set contains N registers, each corresponding to one of the N high-speed ports. These register sets occupy independent address spaces in the CPLD and are used to store the bitstream values ​​sent by different types of boards.

[0148] In step S403, the desired cable detection bitstream value is pre-configured in the BMC for each motherboard high-speed port of each board type.

[0149] Based on the server's expected correct cable connection topology, a desired bitrate value is configured for each high-speed port of each board type in the BMC's non-volatile storage medium or firmware code. For example, for a correct connection of the front backplane to the P0 port, the desired value is configured as 0x15; for a correct connection of the rear backplane to the P0 port, the desired value is configured as 0x35. These desired values ​​constitute a complete "desired value mapping table," serving as a matching benchmark for subsequent cable detection.

[0150] It should be noted that steps S401 to S403 above are pre-configuration operations during the system initialization or design phase, and are completed before the server is running normally. Once the configuration is complete, the online cable testing process in subsequent steps S410 to S440 can be supported.

[0151] This embodiment achieves the encoding of board type information in the bitstream value through board type division and bitstream value range allocation, providing a basis for subsequent identification; the creation of register sets in the motherboard CPLD provides independent storage space for bitstream values ​​of different board types, realizing hardware-level classification and isolation; the pre-configuration of expected values ​​in the BMC provides an accurate matching benchmark for cable detection.

[0152] like Figure 7The diagram illustrates a BMC alarm processing flow provided in an exemplary embodiment of this application. It shows the specific processing flow of the BMC after obtaining the bitstream values ​​of each register set in the CPLD, matching them according to a whitelist, and reporting an alarm. This flow can be executed collaboratively by the whitelist matching module and the alarm processing module in the BMC, and specifically includes the following steps: In step S701, the process begins. After the BMC is powered on and initialized, it enters the backplane detection polling state.

[0153] In step S702, it is determined whether a backplane is detected in place. The BMC detects whether a backplane is connected to the motherboard by reading the backplane presence signal in the CPLD or by other communication methods (such as I2C polling). If a backplane is detected in place (Y), the process proceeds to step S703 to start the detection process for the backplane; if a backplane is not detected in place (N), it continues to wait or periodically detect.

[0154] In step S703, a backplane detection is initiated. When a backplane is detected, the BMC initiates a detection task for that backplane. Since different backplane types correspond to independent register sets, "a backplane detection" here is actually an independent detection performed for a specific type of backplane (such as a front backplane, a rear backplane, etc.).

[0155] In step S704, all cable detection registers corresponding to the backplane are read. The BMC reads all register values ​​in the register set corresponding to the currently detected backplane type via communication protocols such as I2C. For example, if the current detection is of the front backplane, all registers in the front backplane register set (corresponding to all high-speed ports on the motherboard) are read to obtain the actual bitstream values ​​of each port stored therein.

[0156] In step S705, the code is compared with the whitelist configured in the code to determine if they match. Specifically, the read bitstream value is checked against the whitelist configured in the code. The BMC compares the actual bitstream value of each port read in step S704 with the pre-configured expected bitstream value (i.e., whitelist) for that backplane type and port. If the actual bitstream value of all ports matches the whitelist (Y), it indicates that the cable connections for the backplane are all correct, and the process proceeds to step S708; if the bitstream value of any port does not match the whitelist (N), the process proceeds to step S706.

[0157] In step S706, the motherboard ports are compared one by one to identify mismatched ports. When a mismatch is found, the BMC further iterates through all ports corresponding to that backplane type, determines which ports have actual bitstream values ​​that do not match the expected values, and records the identifiers and specific mismatch information of these abnormal ports.

[0158] In step S707, an alarm is reported. The BMC's alarm processing module generates detailed alarm information based on the abnormal port information determined in step S706. This alarm information includes at least: the type of backplane where the abnormality occurred (e.g., "front backplane"), the high-speed port of the motherboard where the abnormality occurred (e.g., "P0 port"), and a comparison between the expected and actual values ​​(optional). The alarm information is reported via the BMC's web interface, SNMP traps, system logs, etc., instructing maintenance personnel to quickly locate and repair the incorrectly connected cable.

[0159] In step S708, no alarm is generated. When the bitstream values ​​of all ports match the whitelist, it indicates that the backplane cable connection being tested is correct. The BMC does not generate any alarms, and the process ends or returns to wait for the next test.

[0160] It should be noted that, Figure 7 The illustrated process describes the detection and processing for a single backplane. In practical applications, when multiple backplanes are connected simultaneously, the BMC can execute the above process multiple times in parallel or serially, performing independent detection and alarms for each backplane type. Because the register sets for different backplane types are independent of each other, the detections do not interfere with each other, and false alarms will not occur.

[0161] pass Figure 7 The process shown demonstrates that BMC implements refined cable detection and alarms based on board classification: it reads registers, matches whitelists, and generates alarms separately according to backplane type, fundamentally solving the problem of false alarms caused by the inability of related technologies to distinguish the source of bitstream values. At the same time, it can accurately locate specific abnormal ports, greatly improving operation and maintenance efficiency.

[0162] In the case of dividing each function into different modules, this application provides a cable detection device, which can be a server or a chip applied to a server. Figure 8 This is a schematic block diagram illustrating the functional modules of a cable detection device provided in an exemplary embodiment of this application. Figure 8 As shown, the cable testing device includes: The bitstream value receiving module 81 is used to receive the cable detection bitstream value sent by the board side; The type identification module 82 is used to identify the type of the board according to the range of cable detection bitstream values ​​to which the cable detection bitstream value belongs; wherein, different board types correspond to different ranges of cable detection bitstream values, and each board type on the motherboard side has a preset set of registers, and each set of registers contains the registers of the corresponding high-speed port of the motherboard; Storage module 83 is used to determine the set of registers corresponding to the identified board type, determine the register corresponding to the high-speed port of the motherboard to which the cable detection code stream value is connected, and store the cable detection code stream value into the determined register. The detection module 84 is used to perform cable detection based on the cable detection bitstream values ​​stored in different register sets and the preset rules corresponding to each board type.

[0163] This embodiment decouples the detection of different types of backplane cables by pre-dividing the board types and their corresponding bitstream value ranges and setting up an independent register set for each type of board in the motherboard. The BMC performs whitelist matching and alarm based on the classified register set, and performs bitstream value storage and cable detection based on the classified register set. This fundamentally solves the problem of false alarms caused by the inability to distinguish the source of bitstream values ​​in related technologies, and improves the accuracy of cable detection and the reliability of BIOS bandwidth resource allocation.

[0164] In another embodiment provided in this application, the range of cable detection bitstream values ​​corresponding to the different board types is pre-allocated in the following manner: Board types are classified according to their physical location or functional attributes; Assign non-overlapping stream value ranges for each board type.

[0165] This embodiment ensures the correspondence between bitstream values ​​and board types by dividing the intervals into non-overlapping intervals, avoiding type misjudgment caused by bitstream value conflicts; and developers can adjust the interval divisions at any time according to product iterations and configuration changes, which has good scalability.

[0166] In another embodiment provided in this application, the cable detection code stream value is transmitted using a single bus protocol, and the cable detection code stream value is hexadecimal data with a value range of 00-FF.

[0167] This embodiment uses a single-bus protocol to transmit the code stream value, requiring only one signal line to complete data communication, effectively saving board interface resources and reducing hardware costs and wiring complexity; it adopts a 00-FF hexadecimal data format, which not only ensures sufficient information capacity to distinguish different ports and board types, but also matches the register bit width of the CPLD, facilitating data storage and processing; at the same time, the single-bus protocol is simple to implement, highly reliable, and easy to implement in the CPLD, making it highly practical for engineering applications.

[0168] In another embodiment provided in this application, each type of board on the motherboard side has a preset set of registers, including: In the complex programmable logic device (CPLD) on the motherboard, a corresponding number of cable detection register sets are created according to the number of board types. The number of registers in each set is the same as the number of high-speed ports on the motherboard and they correspond one-to-one.

[0169] In this embodiment, an independent register set is pre-created in the motherboard CPLD for each type of board, realizing physical isolation of the code stream value storage space for different board types; each register set contains registers that correspond one-to-one with the high-speed ports of the motherboard, ensuring the mapping between the code stream value storage location and the physical port; when reading, the BMC can directly distinguish the source of the code stream value based on the register set, without the need for additional parsing logic, thus simplifying the processing flow.

[0170] In another embodiment provided in this application, the type identification module 82 is specifically used for: The bitstream value is detected by analyzing the cable using the motherboard's CPLD. Determine the predefined target cable detection bitstream value range to which the cable detection bitstream value belongs; The board type is determined based on the preset correspondence between the target cable detection bitstream value range and the board type.

[0171] In this embodiment, the identification is performed at the hardware level by the motherboard CPLD, avoiding the delay and complexity caused by uploading the original bitstream value to the BMC and then performing software parsing; the uniqueness and accuracy of the identification are ensured by the preset correspondence between the bitstream value range and the board type, providing a foundation for subsequent storage and alarms.

[0172] In another embodiment provided in this application, the storage module 83 is specifically used for: Based on the physical port location of the received cable's detected bitstream value, determine the target register index in the corresponding register set; The cable detection bitstream value is written to the target register based on the target register index.

[0173] This embodiment determines the register index based on the physical port location, which ensures that each bitstream value is stored in the register that uniquely corresponds to its source port; selecting the corresponding register set based on the board type can achieve physical isolation of the bitstream value storage space for different board types; this embodiment can be directly implemented by CPLD hardware without software intervention, and has the characteristics of low latency and high reliability.

[0174] In another embodiment provided in this application, the detection module 84 is specifically used for: Read the cable detection bitstream values ​​stored in each register set respectively; The cable detection bitstream value stored in each register set is matched with the preset expected value of the corresponding board type on the motherboard high-speed port; If a mismatch exists, generate alarm information for the corresponding board type and the corresponding high-speed port of the motherboard.

[0175] In this embodiment, the BMC reads and matches registers separately according to the register set, which fundamentally eliminates detection interference between different types of backplanes and avoids false alarms. When the matching fails, the alarm information generated clearly includes the board type and port location, providing maintenance personnel with accurate fault location guidance and greatly improving operation and maintenance efficiency.

[0176] In another embodiment provided in this application, the preset expected value is the expected cable detection bitstream value pre-configured for each type of board and each high-speed port of the motherboard.

[0177] This embodiment configures a desired bitstream value for each port of each type of board, providing an accurate matching benchmark for BMC cable detection. The correspondence between the desired value and the board type and port location enables BMC to perform independent matching based on the classified register set, fundamentally avoiding detection interference between different types of backplanes.

[0178] In another embodiment provided in this application, the device further includes a configuration module, specifically used for: The boards are divided into multiple types, and each type of board is assigned a non-overlapping range of cable detection bitstream values; Create a set of registers in the motherboard CPLD that is the same number as the number of board types; each set contains registers that correspond one-to-one with the high-speed ports of the motherboard. In BMC, the desired cable detection bitrate value is pre-configured for each motherboard high-speed port of each board type.

[0179] This embodiment achieves the encoding of board type information in the bitstream value through board type division and bitstream value range allocation, providing a basis for subsequent identification; the creation of register sets in the motherboard CPLD provides independent storage space for bitstream values ​​of different board types, realizing hardware-level classification and isolation; the pre-configuration of expected values ​​in the BMC provides an accurate matching benchmark for cable detection.

[0180] This application also provides a computing device, such as... Figure 9 As shown, Figure 9 This is a schematic diagram of a computing device provided in an embodiment of this application. Specifically, the computing device can be the aforementioned server, including a processor 1901, a communication interface 1902, a memory 1903, a communication bus 1904, a motherboard 1905, and a backplane 1906. The processor 1901, communication interface 1902, memory 1903, motherboard 1905, and backplane 1906 communicate with each other via the communication bus 1904. Multiple circuit boards can be integrated on the backplane 1906.

[0181] Memory 1903 is used to store computer programs; The processor 1901, when executing the program stored in the memory 1903, implements the method described above in the embodiments of this application.

[0182] The communication bus mentioned in the computing device above can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0183] The communication interface is used for communication between the aforementioned computing device and other devices.

[0184] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0185] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0186] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the methods described above in the embodiments of this application.

[0187] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to execute the methods described above in the embodiments of this application.

[0188] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)).

[0189] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0190] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, computing devices, and computer-readable storage media are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0191] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A cable testing method, characterized in that, The method includes: Receive the cable detection bitstream value sent by the receiving board side; Based on the range of cable detection bitstream values ​​to which the cable detection bitstream value belongs, the type of the board to which the board belongs is identified; wherein, different board types correspond to different ranges of cable detection bitstream values, and each board type on the motherboard side has a preset set of registers, and each set of registers contains the registers of the corresponding high-speed port of the motherboard; Determine the set of registers corresponding to the identified board type, determine the register corresponding to the high-speed port of the motherboard to which the cable detection bitstream value is connected, and store the cable detection bitstream value in the determined register; Based on the cable detection bitstream values ​​stored in different register sets, cable detection is performed according to the preset rules corresponding to each board type.

2. The method according to claim 1, characterized in that, The cable detection bitstream value ranges corresponding to different board types are pre-allocated in the following manner: Board types are classified according to their physical location or functional attributes; Assign non-overlapping stream value ranges for each board type.

3. The method according to claim 1, characterized in that, The cable detection code stream value is transmitted using a single-bus protocol. The cable detection code stream value is hexadecimal data with a value range of 00-FF.

4. The method according to claim 1, characterized in that, Each type of board on the motherboard side has a preset set of registers, including: In the complex programmable logic device (CPLD) on the motherboard, a corresponding number of cable detection register sets are created according to the number of board types. The number of registers in each set is the same as the number of high-speed ports on the motherboard and they correspond one-to-one.

5. The method according to claim 1, characterized in that, The step of identifying the board type based on the range of cable detection bitstream values ​​to which the cable detection bitstream value belongs includes: The motherboard CPLD analyzes the cable detection bitstream value; Determine the predefined target cable detection bitstream value range to which the cable detection bitstream value belongs; The board type is determined based on the preset correspondence between the target cable detection bitstream value range and the board type.

6. The method according to claim 1, characterized in that, The process of determining the register set corresponding to the identified board type, determining the register corresponding to the high-speed port of the motherboard to which the cable detection bitstream value is connected, and storing the cable detection bitstream value into the determined register includes: Based on the physical port location that receives the cable detection bitstream value, determine the target register index in the corresponding register set; The cable detection bitstream value is written to the target register based on the target register index.

7. The method according to claim 1, characterized in that, The step of performing cable detection based on the cable detection bitstream values ​​stored in different register sets and according to preset rules corresponding to each board type includes: Read the cable detection bitstream values ​​stored in each register set respectively; The cable detection bitstream value stored in each register set is matched with the preset expected value on the high-speed port of the motherboard for the corresponding board type; If a mismatch exists, an alarm message is generated for the corresponding board type and the corresponding high-speed port of the motherboard.

8. The method according to claim 7, characterized in that, The preset expected value is the expected cable detection bitstream value pre-configured for each type of board and each high-speed port of the motherboard.

9. The method according to any one of claims 1-8, characterized in that, Before receiving the cable detection bitstream value from the receiving board side, the method further includes: The boards are divided into multiple types, and each type of board is assigned a non-overlapping range of cable detection bitstream values; Create a set of registers in the motherboard CPLD that is the same number as the number of board types; each set contains registers that correspond one-to-one with the high-speed ports of the motherboard. In BMC, the desired cable detection bitrate value is pre-configured for each motherboard high-speed port of each board type.

10. A computing device, characterized in that, include: At least one processor; Memory for storing the at least one processor-executable instruction; The at least one processor is configured to execute the instructions to implement the method as described in any one of claims 1-9.

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