An integrated circuit chip clock frequency measuring device and method

Abstract

The application discloses a kind of integrated circuit chip clock frequency measuring device and method.The device includes time reference generation module, synchronization module and counting module, the device is exported fixed length wide pulse signal by time reference generation module, synchronization module is carried out two-stage cross-clock domain synchronization processing to measurement enable signal and wide pulse signal, counting module completes the clock pulse counting of to-be-measured during the effective period of gate control signal after synchronization and exports measurement result.The method is realized based on pure hardware logic circuit in chip, completes the single or batch measurement of clock frequency in chip.The application does not need to rely on external measuring equipment, does not occupy chip processor operation resource, avoids the measurement error of high-frequency clock frequency conversion at the same time, improves measurement precision and multi-clock measurement efficiency, and can be widely applied to all kinds of system-level chip and application-specific integrated circuit research and development, debugging and production test whole process link.

Description

Technical Field

[0001] This invention relates primarily to the field of clock frequency measurement; more specifically, it relates to an integrated circuit chip clock frequency measurement device and method. Background Technology

[0002] As the scale of system-on-chips (SoCs) and application-specific integrated circuits (ASICs) continues to increase, the number of internal functional modules and operating modes also increases significantly. The coordinated operation between these modules becomes crucial for the normal operation of the chip, especially for modules sensitive to data flow and bus bandwidth. Real-time measurement of the operating clock frequency of each internal functional module is a key method for determining the operating status of each module and whether they are working in coordination. Therefore, clock frequency measurement has become an important part of the R&D, debugging, and testing process for SoCs and ASICs.

[0003] Currently, the measurement of internal clock frequencies of system-on-chips (SoCs) and application-specific integrated circuits (ASICs) primarily employs external hardware measurement. This involves using an input / output multiplexer to select a specific internal clock and measuring its frequency at a designated port. For clocks exceeding the throughput of the input / output ports, a large divider with a high division factor is required internally to reduce the output frequency before measurement. The measured clock frequency then needs to be converted back to its original value before division. This measurement method is highly dependent on the external environment. During debugging, any suspected clock-related issues require the cooperation of test engineers and external measurement equipment, sometimes necessitating assistance from SoC design engineers. The numerous modules and complex functionalities within SoCs make the debugging process extremely cumbersome and repetitive, consuming significant manpower and time. Meanwhile, the operation of dividing the high-frequency clock and then converting it to the actual frequency is prone to introducing errors in the conversion process, reducing the accuracy of clock frequency measurement. On the other hand, if the clock frequency measurement is implemented by software counting, it will occupy the computing resources of the chip processor, increase the system load, and make it difficult to adapt to the multi-clock measurement needs of large-scale system-on-a-chip and application-specific integrated circuits.

[0004] Therefore, there is an urgent need for a clock frequency measurement solution for system-on-a-chip and application-specific integrated circuits to solve the problems of high dependence on external hardware environment, cumbersome debugging process and high manpower and time cost of existing measurement methods, and the error that is easily introduced by frequency division and conversion required for high frequency clock measurement. The solution should realize the autonomous clock frequency measurement on the chip, while meeting the practical application requirements of low resource consumption and batch measurement of multiple clocks. Summary of the Invention

[0005] Based on existing technologies, the objective of this invention is to propose an integrated circuit chip clock frequency measurement device and method. This device and method can solve the core pain points of existing clock frequency measurement schemes, such as high external dependence, high resource consumption, insufficient measurement accuracy, and cumbersome operation process, through a purely hardware on-chip integrated architecture design. While ensuring measurement accuracy and stability, it can significantly improve the efficiency and convenience of clock frequency measurement.

[0006] A first aspect of the present invention provides an integrated circuit chip clock frequency measuring device, the device comprising: A time reference generation module, wherein the input terminal of the time reference generation module is used to receive a reference clock signal, and the output terminal of the time reference generation module is used to output a wide pulse signal of fixed length, wherein the wide pulse signal is configured as a reference signal for clock frequency measurement; A synchronization module includes at least two synchronization units. The input terminal of the synchronization module is used to receive and measure the wide pulse signal. The output terminal of the synchronization module is used to output a gate control signal synchronized to the clock domain under test. The effective duration of the gate control signal synchronized to the clock domain under test is consistent with that of the wide pulse signal. The counting module has a first input terminal for receiving the gate control signal synchronized to the clock domain under test, and a second input terminal for receiving the clock signal under test. Within the effective range of the gate control signal synchronized to the clock domain under test, the counting module performs incrementing on the rising edge of the clock signal under test, and stops counting after the gate control signal synchronized to the clock domain under test fails. It latches the current measurement count value and outputs a measurement end signal, wherein the measurement count value is numerically equal to the clock frequency value of the clock under test, and the unit of the clock frequency value is kHz.

[0007] Furthermore, the synchronization module includes: A first synchronization unit, wherein a first input terminal of the first synchronization unit is used to receive a measurement enable signal, a second input terminal is used to receive the wide pulse signal, and an output terminal of the first synchronization unit is used to output a synchronized gate control signal; and The second synchronization unit has a first input terminal that receives the synchronized gate control signal, a second input terminal that receives the clock signal to be tested, and an output terminal that outputs a gate control signal synchronized to the clock domain to be tested.

[0008] Furthermore, the device also includes a clock selection module connected to the second input terminal of the second synchronization unit and the second input terminal of the counting module. The clock selection module is configured to switch different clocks within the chip as the clock to be measured.

[0009] Furthermore, the counting module includes a 32-bit output register for storing and outputting the clock frequency measurement result data and status information, wherein the output register includes the following fields: The clock number field is used to store the unique index number of the clock under test corresponding to the current measurement result; The measurement status field is used to characterize the execution status of the current clock frequency measurement process; The high-order field of the clock frequency is used to store the highest 6 bits of the count value of the clock frequency under test. The clock frequency middle byte field is used to store the middle 8 bits of the clock frequency count value under test; and The low byte field of the clock frequency is used to store the lowest 8 bits of the count value of the clock frequency under test.

[0010] A second aspect of the present invention provides a method for measuring the clock frequency of an integrated circuit chip, characterized in that it is executed based on the apparatus described in the first aspect of the present invention, the method comprising: The time reference generation module generates a wide pulse signal of fixed length based on a reference clock signal with a fixed frequency inside the chip, which serves as the reference signal for frequency measurement. The first synchronization unit synchronizes the received measurement enable signal to the gate clock domain corresponding to the wide pulse signal, and generates a gate control signal with the same effective duration as the wide pulse signal. The second synchronization unit synchronizes the gate control signal to the clock domain under test corresponding to the clock signal under test, and outputs the gate control signal synchronized to the clock domain under test. The counting module increments the count on the rising edge of the clock signal under test within the effective range of the gate control signal synchronized to the clock domain under test, and stops counting after the gate control signal synchronized to the clock domain under test fails, latches the current measurement count value, and outputs a measurement end signal; and After the chip's control module detects the measurement end signal, it reads the measurement count value, which directly corresponds to the frequency value of the clock signal under test in kHz.

[0011] Furthermore, the method also includes reading the measurement count value and clearing the measurement enable signal.

[0012] Furthermore, when performing frequency measurements on a single clock under test, the following steps are also included: A valid level measurement enable signal is input to the logic circuit to trigger clock frequency measurement; The measurement end signal is detected until it becomes valid; Read the measured count value; and An invalid level measurement enable signal is input to the logic circuit to reset the logic circuit to the measurement not started state.

[0013] Furthermore, when performing batch frequency measurements on multiple clocks under test, the following steps are also included: Select the first clock signal to be tested and connect it to the clock signal input terminal of the logic circuit; Complete the frequency measurement of the current clock under test and store the corresponding measurement count value; Select the next clock to be tested and connect it to the clock input terminal of the logic circuit, and disconnect the path of the previous clock to be tested; and Repeat the measurement and storage steps until the frequency measurement of all clocks under test is completed. Generate a summary result of the system clock frequency based on all stored frequency count values ​​and output the result.

[0014] Furthermore, the output results include: Output the clock frequency value of the clock under test, which is numerically equal to the measured count value of the clock under test, in kHz. Output a status bit, which characterizes the measurement status of the clock under test, including at least one of measurement completed, measurement in progress, and measurement not started; and Output the clock number of the clock to be tested.

[0015] The present invention has at least the following beneficial effects: (1) The present invention uses pure hardware logic circuits integrated on the chip to realize clock frequency measurement, which completely eliminates the dependence on external measurement equipment such as oscilloscopes. There is no need to bring the internal clock out of the chip for measurement through input-output multiplexers, nor is there a need to set up a frequency divider for frequency reduction processing for high-frequency clocks. The measured count value does not need to be converted to the clock frequency value in kHz units, which greatly simplifies the operation process of clock frequency measurement and avoids the manpower and time cost consumption caused by cross-position collaboration.

[0016] (2) The clock frequency measurement process of the present invention is completed independently by the pure hardware logic circuit on the chip. No chip processor is required to participate in the counting operation. The measurement process does not occupy the system computing resources and will not increase the system operating load of the chip. The clock frequency measurement can be completed synchronously during the normal operation of the chip without affecting the normal operation of the original functional modules of the chip.

[0017] (3) The present invention achieves equal precision frequency measurement based on a gate clock signal of fixed length. The clock signal under test can be directly connected to the measurement circuit without frequency division and down-conversion processing, thus avoiding the measurement error introduced in the frequency division and conversion process. At the same time, through two-level cross-clock domain synchronization processing, the metastability problem caused by the transmission of signals in different clock domains is eliminated, ensuring the synchronization between the counting window and the clock signal under test, and improving the accuracy and stability of clock frequency measurement.

[0018] (4) This invention supports both manual measurement of a single clock and automatic batch polling measurement of multiple clocks. It can quickly complete the acquisition of the working clock frequency of all functional modules inside the chip by switching clocks. There is no need to configure the measurement environment separately for each clock, which greatly improves the working efficiency of multi-clock measurement of large-scale chips. It can quickly generate a summary of the chip system clock frequency, which makes it easier for technicians to understand the working status of each module inside the chip. It greatly reduces the difficulty of chip research and development, debugging and testing, and reduces repetitive debugging work.

[0019] In summary, this invention, through a purely hardware-integrated on-chip architecture, solves the core pain points of existing clock frequency measurement solutions, such as high external dependence, high resource consumption, insufficient measurement accuracy, and cumbersome operation procedures. While ensuring measurement accuracy and stability, it significantly improves the efficiency and convenience of clock frequency measurement. It can be widely applied to the entire process of R&D, hardware debugging, and mass production testing of various system-on-a-chip and application-specific integrated circuits, and can also be adapted to various integrated circuit application scenarios that require on-chip real-time clock frequency monitoring. Attached Figure Description

[0020] To further illustrate the advantages and other features of the various embodiments of the present invention, a more specific description of the embodiments of the present invention will be presented with reference to the accompanying drawings. It is understood that these drawings depict only typical embodiments of the invention and are therefore not intended to limit its scope. In the drawings, identical or corresponding parts will be indicated by the same or similar reference numerals for clarity.

[0021] Figure 1 A modular architecture diagram of a measuring device in one embodiment of the present invention is shown.

[0022] Figure 2 A data structure diagram of the measurement results is shown in one embodiment of the present invention.

[0023] Figure 3 A signal timing diagram of a measuring device in one embodiment of the present invention is shown.

[0024] Figure 4 A flowchart of a measurement method in one embodiment of the present invention is shown.

[0025] List of reference numerals 100 Measuring device 101 Time Base Generation Module 102 Synchronization Module 102-1 First Synchronization Unit 102-2 Second Synchronization Unit 103 Counting Module 104 Clock Selection Module Detailed Implementation It should be noted that the components in the various figures may be shown exaggeratedly for illustrative purposes and are not necessarily to scale. In each figure, the same reference numerals are used for components that are identical or have the same function.

[0026] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0027] In this invention, unless otherwise specified, the quantifiers “a” and “one” do not exclude scenarios involving multiple elements.

[0028] It should also be noted that, for clarity and simplicity, only a portion of the components may be shown in the embodiments of the present invention. However, those skilled in the art will understand that, under the teachings of the present invention, the required components can be added according to specific needs. Furthermore, unless otherwise stated, features in different embodiments of the present invention can be combined with each other. For example, a feature in the second embodiment can replace a corresponding or functionally identical or similar feature in the first embodiment, and the resulting embodiment will also fall within the scope of disclosure or description of this application.

[0029] It should also be noted that within the scope of this invention, the terms "same", "equal", and "equal to" do not mean that the two values ​​are absolutely equal, but allow for a certain reasonable error. In other words, the terms also cover "substantially the same", "substantially equal", and "substantially equal to".

[0030] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0031] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0032] like Figure 1As shown, in one embodiment of the present invention, an integrated circuit chip clock frequency measuring device 100 (hereinafter referred to as measuring device 100) is provided, including a time base generation module 101, a synchronization module 102, and a counting module 103. In another embodiment of the present invention, the measuring device 100 further includes a clock selection module 104. Each module cooperates through hardware logic circuits to complete the on-chip frequency measurement of the clock under test within the integrated circuit chip. The measuring device 100 is a pure hardware logic circuit integrated on-chip, operating independently of the chip's processor module. The entire measurement process does not occupy system computing resources and can complete the autonomous detection of the clock frequency without relying on external measuring equipment.

[0033] In one embodiment of the present invention, the time reference generation module 101 is configured as the core of the time reference generation of the measurement device 100, used to provide a fixed-length gate time reference for the entire measurement process. The input terminal of the time reference generation module 101 is used to receive a reference clock signal, and the output terminal is used to output a wide pulse signal of fixed length. The reference clock signal is a fixed-frequency, stable, and reliable clock signal within the chip, which cannot be configured or frequency-variable. It includes the clock signal output from the crystal oscillator clock or the phase-locked loop reference clock within the chip, possessing high accuracy and low noise, and serving as the clock basis for the entire chip system operation. Based on the input reference clock signal, the time reference generation module 101 generates a wide pulse signal of fixed length through hardware logic. This wide pulse signal provides a precise gate time window for the subsequent frequency counting process. In a specific embodiment of the present invention, the time reference generation module 101 includes a frequency divider, which divides the reference clock signal to generate a wide pulse signal with a length of 1ms.

[0034] In one embodiment of the present invention, the synchronization module 102 is configured as the core of the cross-clock domain signal processing of the measurement device 100, used to solve the metastability problem of signal transmission between different clock domains and ensure the synchronization of the control signal and the clock signal under test. The synchronization module 102 includes at least two synchronization units, specifically a first synchronization unit 102-1 and a second synchronization unit 102-2. The input terminal of the synchronization module 102 is used to receive the measurement enable signal, the wide pulse signal and the clock signal under test, and the output terminal is used to output a gate control signal synchronized to the clock domain under test.

[0035] In one embodiment of the present invention, the first input terminal of the first synchronization unit 102-1 is used to receive a measurement enable signal, the second input terminal is used to receive a wide pulse signal output by the time base generation module 101, and the output terminal of the first synchronization unit 102-1 is used to output a synchronized gate control signal. The first synchronization unit 102-1 synchronizes the asynchronously input measurement enable signal to the clock domain corresponding to the wide pulse signal, generates a gate control signal whose timing matches the wide pulse signal, and ensures that the effective duration of the gate control signal is completely consistent with the fixed length of the wide pulse signal, providing accurate gate enable control for the subsequent counting process.

[0036] In one embodiment of the present invention, the first input terminal of the second synchronization unit 102-2 is used to receive the synchronized gate control signal output by the first synchronization unit 102-1, the second input terminal is used to receive the clock signal to be tested, and the output terminal of the second synchronization unit 102-2 is used to output the gate control signal synchronized to the clock domain to be tested. The second synchronization unit 102-2 further synchronizes the gate control signal to the clock domain corresponding to the clock signal to be tested, so that the rising edge of the gate control signal is completely matched with the rising edge of the clock signal to be tested, avoiding counting deviations caused by clock domain asynchrony and ensuring the accuracy of the subsequent counting process.

[0037] In one embodiment of the present invention, the counting module 103 is configured as the frequency counting core of the measuring device 100, used to complete the pulse statistics and result output of the clock signal under test. The first input terminal of the counting module 103 is used to receive the gate control signal synchronized to the clock domain under test output by the second synchronization unit 102-2, the second input terminal is used to receive the clock signal under test, and the output terminal of the counting module 103 is used to output the measurement count value and the measurement end signal. The counting module 103 is configured to increment the pulse count of the clock signal under test within the effective range of the gate control signal synchronized to the clock domain under test, and immediately stop the counting operation, latch the current measurement count value, and output the measurement end signal after the gate control signal synchronized to the clock domain under test fails. The measurement count value can directly correspond to the frequency value of the clock signal under test (unit: kHz), and the measurement end signal is used to feedback the measurement completion status to the control module of the chip, indicating that the control module can read the latched measurement count value.

[0038] Figure 2 A data structure diagram of the measurement results is shown in one embodiment of the present invention.

[0039] like Figure 2As shown, in a specific embodiment of the present invention, the counting module 103 includes a 32-bit output register for storing and outputting the clock frequency measurement result data and status information, adapting to the reading and parsing requirements of the chip control module, and supporting data association and management during batch measurement of multiple clock signals under test. In this embodiment, the 32-bit data structure is divided into five fields according to the bit segment from the high bit to the low bit. The bit width, function, and application logic of each field are as follows: The first field is the clock number field, corresponding to the bit range [31:24], with a bit width of 8 bits, and the field identifier is ClockID. The clock number field is used to store the unique index number of the clock under test corresponding to the current measurement result, which is used to identify the target clock object of this measurement. In the scenario of batch polling measurement of multiple clocks under test, the chip control module can accurately associate the read measurement result with the corresponding clock under test through the value of the clock number field, avoiding confusion of measurement data from multiple clocks, eliminating the need for additional configuration of clock-data mapping relationship, and greatly improving the data processing efficiency of batch measurement of multiple clocks.

[0040] The second field is the measurement status field, corresponding to a bit range of [23:22], with a bit width of 2 bits. The field identifier is Done / Counting / Not Start. The measurement status field is used to characterize the execution status of the current clock frequency measurement process, covering all working modes of the entire measurement process. The value of the measurement status field corresponds one-to-one with the measurement status, where a value of 00 corresponds to the measurement not started, a value of 01 corresponds to the measurement in progress, a value of 10 corresponds to the measurement completed, and the remaining values ​​are reserved for extended states. The chip control module can obtain the working status of the measuring device 100 in real time by reading the value of this field. Only when the value of this field indicates the measurement completed will the content of the frequency value-related fields be read, avoiding the reading of invalid intermediate data that has not been counted, thus ensuring the accuracy and validity of the measurement results.

[0041] The third field is the high-order bit field of the clock frequency, corresponding to a bit range of [21:16], with a bit width of 6 bits, and is identified as clock frequency H Bits. The high-order bit field of the clock frequency is used to store the highest 6 bits of the clock frequency count value under test, and is the high-order component of the complete frequency count value.

[0042] The fourth field is the clock frequency middle byte field, corresponding to the bit range [15:8], with a bit width of 8 bits, and the field identifier is clock frequency M Byte. The clock frequency middle byte field is used to store the middle 8 bits of the clock frequency count value under test, and is a middle segment of the complete frequency count value.

[0043] The fifth field is the low byte of the clock frequency field, corresponding to the bit range [7:0], with a bit width of 8 bits, and the field identifier is clock frequency L Byte. The low byte of the clock frequency field is used to store the lowest 8 bits of the clock frequency count value under test, and is the low-order component of the complete frequency count value.

[0044] In this embodiment, the complete clock frequency count value is composed of the high-order byte of the clock frequency, the middle-order byte of the clock frequency, and the low-order byte of the clock frequency, concatenated in descending order of high-order byte. The total bit width is 22 bits, supporting a maximum clock frequency of 4.19 GHz, which can cover the operating clock measurement range of most functional modules within the integrated circuit chip. The concatenated frequency count value directly corresponds to the clock frequency value in kHz. After reading it, the chip control module can directly obtain the actual frequency result of the clock under test without additional conversion processing, greatly simplifying the software processing flow and reducing the computational load of the chip system.

[0045] In one embodiment of the present invention, the output terminal of the clock selection module 104 is connected to the second input terminal of the second synchronization unit 102-2 and the second input terminal of the counting module 103, respectively. The clock selection module 104 is configured to switch different clocks as the clock signals to be tested, and input them to the second synchronization unit 102-2 and the counting module 103 to realize batch polling measurement of multiple clocks to be tested inside the chip. Through the switching operation of the clock selection module 104, the measuring device 100 can sequentially complete the frequency measurement of the working clocks of all functional modules inside the chip, without the need to configure the measurement environment separately for each clock, which greatly improves the efficiency of multi-clock measurement.

[0046] In one embodiment of the present invention, when the measuring device 100 performs frequency measurement on a single-channel clock under test, the time reference generation module 101 first generates a wide pulse signal of fixed length based on the reference clock signal. The chip control module inputs a valid level measurement enable signal to the first synchronization unit 102-1. The first synchronization unit 102-1 synchronizes the measurement enable signal to the clock domain corresponding to the wide pulse signal, generates a gate control signal and outputs it to the second synchronization unit 102-2. The second synchronization unit 102-2 synchronizes the gate control signal to the clock domain under test and outputs it to the counting module 103. The counting module 103 completes the pulse counting of the clock signal under test during the valid period of the gate control signal. After the gate control signal fails, the measurement count value is latched and the measurement end signal is output. After the control module detects the measurement end signal, it reads the measurement count value, completes the measurement, and inputs an invalid level measurement enable signal to the measuring device 100 to reset the measuring device 100 to the initial state.

[0047] In one embodiment of the present invention, when the measuring device 100 performs automatic batch measurement on multiple clocks under test, it first selects the first clock under test through the clock selection module 104 to connect to the measuring device 100, completes the frequency measurement of the clock and stores the corresponding measurement count value. Then, it switches the next clock under test to the measuring device 100 through the clock selection module 104, repeats the single clock measurement process, until the frequency measurement of all clocks under test is completed. Finally, it can generate a system clock frequency table of the chip based on all the stored measurement count values, providing data support for the optimization of the chip's clock configuration and the adjustment of the module's working mode.

[0048] Figure 3 A signal timing diagram of a measuring device in one embodiment of the present invention is shown.

[0049] like Figure 3 As shown, in one embodiment of the present invention, the timing characteristics and functional definitions of each signal are as follows: The reference clock signal corresponds to the input signal of the time base generation module 101. It is a continuous, equally spaced fixed-frequency square wave signal, which comes from the crystal oscillator clock or phase-locked loop reference clock in the chip. It has a stable frequency and high accuracy and is the absolute time base of the entire measurement device 100. The timing actions of all modules are based on the effective transition edge of this signal as the smallest time unit.

[0050] The measurement enable signal, corresponding to the first input signal of the first synchronization unit 102-1 in the synchronization module 102, is output by the chip's control module and is used to trigger the start and stop of the measurement process. This signal is initially in a low-level invalid state, flips to a high-level valid state after the effective transition edge of the reference clock signal, remains high throughout the entire measurement cycle, and can be pulled low after the measurement is completed, resetting the measurement device 100 to an idle state.

[0051] The reference clock counter, corresponding to the output value of the hardware counter inside the time base generation module 101, is the core execution unit for generating a wide pulse signal with a fixed length. The initial state of this signal is indeterminate X. When the measurement enable signal flips to the active state, the counter is immediately cleared to 0. Subsequently, it performs an accumulation count once on each effective transition edge of the reference clock signal, with the value increasing sequentially from 0 until it reaches the preset frequency division coefficient N and then stops. The counting period is perfectly matched with the effective duration of the wide pulse signal.

[0052] The wide pulse signal, corresponding to the output signal of the time reference generation module 101, is also the second input signal of the first synchronization unit 102-1 in the synchronization module 102, providing a fixed-length counting gate window for the entire measurement process. Its initial state is a low-level invalid state. The wide pulse signal remains high throughout the entire cycle of the reference clock count from 0 to N, with a fixed high-level effective duration of 1ms. When the reference clock count reaches the preset value N, the signal synchronously flips to a low-level invalid state, closing the counting gate window.

[0053] The clock signal under test corresponds to the second input signal of the second synchronization unit 102-2 in the synchronization module 102 and the second input signal of the counting module 103. It is the target of frequency measurement and comes from the working clock of the internal functional module of the chip. This signal is a continuous, equally spaced square wave signal, and its frequency is the target value of this measurement. It does not need to be divided or down-divided and can be directly connected to the measuring device 100. The number of pulses within the high-level effective range of the wide pulse signal is the statistical object of the counting module 103.

[0054] The measured count value, corresponding to the core output value of the counting module 103, is used to characterize the frequency result of the clock signal under test. The initial state of this signal is indeterminate X. When the gate control signal synchronized to the clock domain under test becomes valid, the counter is immediately cleared to zero. Subsequently, an accumulation count is performed once on each valid transition edge of the clock signal under test, and the value increases sequentially. When the wide pulse signal flips to a low level and the gate control signal becomes invalid, the counting immediately stops and the final measured count value is latched. The value of the measured count value can be directly mapped to the frequency value (unit: kHz) of the clock signal under test.

[0055] Figure 4 A flowchart of a measurement method in one embodiment of the present invention is shown.

[0056] like Figure 4 As shown, in one embodiment of the present invention, a method for measuring the clock frequency of an integrated circuit chip is provided. This method is executed based on on-chip integrated pure hardware logic circuitry, does not rely on external measurement equipment, and the measurement process runs independently of the chip's processor module, without consuming system computing resources. The method includes the following steps: Step S100: Generate a time base (wide pulse signal) based on the reference clock signal: Based on the reference clock signal within the chip, a wide pulse signal of fixed length is generated through hardware logic. The reference clock signal is a high-precision clock with a fixed frequency and stable performance within the chip, including a clock signal output from a crystal oscillator clock or a phase-locked loop reference clock. It possesses high accuracy and low noise, providing a precise time base for the entire measurement process. The effective duration of the generated wide pulse signal is a fixed value, serving as the gate time window for subsequent pulse counting. In a specific embodiment of the present invention, the effective duration of the wide pulse signal is 1ms.

[0057] Step S200: Perform multi-level synchronization processing across clock domains on the wide pulse signal: Perform multi-level synchronization processing across clock domains on the wide pulse signal generated in step S100 to synchronize the measurement enable signal and the wide pulse signal with the clock domain under test. In a specific embodiment of the present invention, a two-level synchronization is adopted. The first level of synchronization synchronizes the externally input measurement enable signal and the wide pulse to the gate clock domain, generating a synchronized gate control signal, eliminating the metastability risk caused by asynchronous signal transmission, and ensuring that the effective duration of the gate control signal is completely consistent with the preset fixed length. The second level of synchronization further synchronizes the synchronized gate control signal to the clock domain under test, so that the transition edge of the gate control signal is completely matched with the transition edge of the clock signal under test, avoiding counting deviations caused by clock domain asynchrony, and providing accurate enable control for the subsequent counting process.

[0058] Step S300: Perform hardware counting on the clock signal under test during the period when the gate control signal is valid: During the period when the gate control signal synchronized to the clock domain under test is valid, the number of pulses of the clock signal under test is accumulated and counted by hardware counting logic. Counting stops immediately after the gate control signal fails, and the current counting result is latched to obtain the measured count value. The counting logic performs the accumulation operation on the transition edge of the clock signal under test, and the counting is triggered only when the gate control signal is valid, ensuring that the counting result corresponds only to the number of clock pulses under test within a fixed gate time window.

[0059] Step S400: Output Measurement Results and Status Signals: After counting is complete, output the latched measurement count value, which is numerically equal to the frequency value of the clock signal under test (unit: kHz). Simultaneously, output a measurement end signal. The output measurement results also include the status bit and clock number of the clock under test. The clock frequency value is obtained from the measurement count value of the clock under test. The status bit is used to characterize the measurement status of the clock under test, which includes at least one of measurement end, measurement in progress, and measurement not started. The clock number is used to identify the clock under test corresponding to the current measurement result, achieving precise correlation between the measurement result and the corresponding clock.

[0060] In one specific embodiment of the present invention, when performing frequency measurement on a single clock under test, the following steps are specifically included: A valid level measurement enable signal is input to the on-chip pure hardware logic circuit to trigger the current clock frequency measurement process.

[0061] Execute steps S100 to S200 to complete the generation of the gate time reference and the two-level cross-clock domain synchronization processing, and output the gate control signal synchronized to the clock domain under test.

[0062] Execute step S300 to complete the pulse counting of the clock signal under test and latch the measurement count value.

[0063] Execute step S400 to output the measurement end signal and measurement result.

[0064] The system continuously monitors the measurement end signal until it becomes valid, then reads the latched measurement count value. After reading, it inputs an invalid level measurement enable signal to the on-chip pure hardware logic circuit, resetting the circuit to the measurement-not-started state, waiting for the next measurement trigger.

[0065] In one specific embodiment of the present invention, when performing automatic batch frequency measurement on multiple clocks under test, the following steps are specifically included: The on-chip clock selection module selects the first clock under test and connects it to the clock input terminal of the on-chip pure hardware logic circuit to complete the path configuration.

[0066] Perform the frequency measurement steps for a single clock under test in the foregoing embodiments of the present invention to complete the frequency measurement of the current clock under test and store the clock number and corresponding measurement count value of the current clock under test.

[0067] The clock selection module 104 selects the next clock under test to be connected to the clock input terminal of the on-chip pure hardware logic circuit, while disconnecting the access path of the previous clock under test to avoid signal crosstalk.

[0068] Repeat the measurement and clock selection steps until the frequency measurement of all clocks under test is completed. Based on the clock number and corresponding measurement count value of all clocks under test stored, the chip system clock frequency table is generated and output, providing data support for chip clock configuration optimization and functional module working status verification.

[0069] Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A device for measuring the clock frequency of an integrated circuit chip, characterized in that, The device includes: A time reference generation module, wherein the input terminal of the time reference generation module is used to receive a reference clock signal, and the output terminal of the time reference generation module is used to output a wide pulse signal of fixed length, wherein the wide pulse signal is configured as a reference signal for clock frequency measurement; A synchronization module includes at least two synchronization units. The input terminal of the synchronization module is used to receive and measure the wide pulse signal. The output terminal of the synchronization module is used to output a gate control signal synchronized to the clock domain under test. The effective duration of the gate control signal synchronized to the clock domain under test is consistent with that of the wide pulse signal. The counting module has a first input terminal for receiving the gate control signal synchronized to the clock domain under test, and a second input terminal for receiving the clock signal under test. Within the effective range of the gate control signal synchronized to the clock domain under test, the counting module performs incrementing on the rising edge of the clock signal under test, and stops counting after the gate control signal synchronized to the clock domain under test fails. It latches the current measurement count value and outputs a measurement end signal, wherein the measurement count value is numerically equal to the clock frequency value of the clock under test, and the unit of the clock frequency value is kHz.

2. The apparatus according to claim 1, characterized in that, The reference clock signal includes the clock signal output from the crystal oscillator clock within the chip and / or the phase-locked loop reference clock.

3. The apparatus according to claim 1, characterized in that, The synchronization module includes: A first synchronization unit, wherein a first input terminal of the first synchronization unit is used to receive a measurement enable signal, a second input terminal is used to receive the wide pulse signal, and an output terminal of the first synchronization unit is used to output a synchronized gate control signal; and The second synchronization unit has a first input terminal that receives the synchronized gate control signal, a second input terminal that receives the clock signal to be tested, and an output terminal that outputs a gate control signal synchronized to the clock domain to be tested.

4. The apparatus according to claim 3, characterized in that, The device further includes a clock selection module connected to the second input terminal of the second synchronization unit and the second input terminal of the counting module. The clock selection module is configured to switch different clocks within the chip as the clock to be measured.

5. The apparatus according to claim 1, characterized in that, The counting module includes a 32-bit output register for storing and outputting clock frequency measurement results and status information. The output register includes the following fields: The clock number field is used to store the unique index number of the clock under test corresponding to the current measurement result; The measurement status field is used to characterize the execution status of the current clock frequency measurement process; The high-order field of the clock frequency is used to store the highest 6 bits of the count value of the clock frequency under test. The clock frequency middle byte field is used to store the middle 8 bits of the clock frequency count value under test; as well as The low byte field of the clock frequency is used to store the lowest 8 bits of the count value of the clock frequency under test.

6. A method for measuring the clock frequency of an integrated circuit chip, characterized in that, The method is performed using the apparatus according to any one of claims 1-5, and includes: The time reference generation module generates a wide pulse signal of fixed length based on a reference clock signal with a fixed frequency inside the chip, which serves as the reference signal for frequency measurement. The first synchronization unit synchronizes the received measurement enable signal to the gate clock domain corresponding to the wide pulse signal, and generates a gate control signal with the same effective duration as the wide pulse signal. The second synchronization unit synchronizes the gate control signal to the clock domain under test corresponding to the clock signal under test, and outputs the gate control signal synchronized to the clock domain under test. The counting module increments the count on the rising edge of the clock signal under test within the effective range of the gate control signal synchronized to the clock domain under test, and stops counting after the gate control signal synchronized to the clock domain under test fails, latches the current measurement count value, and outputs a measurement end signal; and After the chip's control module detects the measurement end signal, it reads the measurement count value, which directly corresponds to the frequency value of the clock signal under test in kHz.

7. The method according to claim 6, characterized in that, The method further includes reading the measurement count value and clearing the measurement enable signal.

8. The method according to claim 6, characterized in that, When performing frequency measurements on a single clock under test, the following steps are also included: A valid level measurement enable signal is input to the logic circuit to trigger clock frequency measurement; The measurement end signal is detected until it becomes valid; Read the measured count value; and An invalid level measurement enable signal is input to the logic circuit to reset the logic circuit to the measurement not started state.

9. The method according to claim 8, characterized in that, When performing batch frequency measurements on multiple clocks under test, the following steps are also included: Select the first clock signal to be tested and connect it to the clock signal input terminal of the logic circuit; Complete the frequency measurement of the current clock under test and store the corresponding measurement count value; Select the next clock to be tested and connect it to the clock input terminal of the logic circuit, and disconnect the path of the previous clock to be tested; and Repeat the measurement and storage steps until the frequency measurement of all clocks under test is completed. Generate a summary result of the system clock frequency based on all stored frequency count values ​​and output the result.

10. The method according to claim 9, characterized in that, The output results include: Output the clock frequency value of the clock under test; Output a status bit, which characterizes the measurement status of the clock under test, including at least one of measurement completed, measurement in progress, and measurement not started; and Output the clock number of the clock to be tested.

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