Method, system, and storage medium for testing multi-board cards

Abstract

The application relates to the technical field of board card testing, and discloses a multi-board card testing method, a system and a storage medium. The multi-board card testing method is characterized in that a plurality of board cards are one-to-one corresponding to device addresses, testing instructions are issued to the plurality of board cards to drive each testing channel in the board card to independently run a corresponding state machine, the state machine corresponding to each testing channel is controlled to execute a testing process in parallel, and full-dimension fault detection is executed in real time during the running of the state machine to determine a fault detection result, so that a testing result corresponding to each testing channel is obtained. The application can improve the testing efficiency of the multi-board card.

Description

Technical Field

[0001] This application relates to the field of board testing technology, and in particular to a testing method, system and storage medium for multiple boards. Background Technology

[0002] In the field of industrial circuit board module production testing, the industry currently generally adopts a single-channel independent testing method, such as sending Modbus RTU commands one by one through serial port debugging tools (such as SSCOM, SecureCRT, etc.) to perform read and write operations on the module under test.

[0003] However, the single-channel testing method described above requires testing each channel of each board one by one. For multi-channel boards (such as 5-channel simulation boards), it is necessary to switch channels repeatedly to complete a full round of testing. Furthermore, each board needs to be tested individually, which results in long testing time and low testing efficiency for multi-board boards. Summary of the Invention

[0004] This application provides a testing method, system, and storage medium for multiple circuit boards, which can improve the testing efficiency of multiple circuit boards.

[0005] The embodiments of this application provide the following technical solutions: On one hand, embodiments of this application provide a multi-board testing method applied to a magnetic control system, the magnetic control system including a power management module, the power management module including multiple boards, the method including: Obtain multiple device addresses, each of which corresponds to a specific board, and each board corresponds to several test channels. Assign an independent state machine to each test channel of each board; Based on the device address, test commands are sent to multiple boards to drive each test channel within each board to run its corresponding state machine independently; The state machine corresponding to each test channel is controlled to execute the test process in parallel. In addition, full-dimensional fault detection is performed in real time during the operation of the state machine to determine the fault detection result corresponding to each test channel. The test process includes current regulation test and polarity switching cycle test. During the operation of the state machine, full-dimensional fault detection is performed in real time to determine the fault detection result for each test channel, including: During each round of execution, the data of the status register corresponding to each test channel is read in real time; Based on the data in the status register corresponding to each test channel, determine the fault type corresponding to each test channel; Based on the fault type corresponding to each test channel, determine the fault detection result corresponding to each test channel. The fault detection result includes the fault type corresponding to each test channel.

[0006] In some embodiments, the state machine includes an idle state, a current setting state, a current holding state, a reverse polarity state, and a positive polarity state; Control the state machine corresponding to each test channel to execute the test process in parallel, including: The state machine corresponding to each test channel is controlled to enter the idle state, waiting for the start command; Upon receiving the start command, a current regulation test is performed on each test channel, including: The control state machine switches to the current setting state, generates the target current value, and sends the target current value to each test channel; The control state machine switches to the current holding state based on the target current value, and maintains the current target current value for a first preset time. After the first preset duration, a polarity switching loop test is performed on each test channel, including: The control state machine switches to the reverse polarity state and continues for a second preset duration; after the reverse polarity state operation ends, the control state machine switches to the positive polarity state and continues for a third preset duration. The control state machine returns to the current setting state and updates the current step value, completing one cycle of current adjustment and polarity switching; Repeat the current regulation and polarity switching cycle until the preset cycle termination condition is met.

[0007] In some embodiments, the control state machine switches to the current setting state to generate a target current value, including: The control state machine switches to the current setting state. In the current setting state, for each test channel, a target current value is generated through a triangular wave scanning algorithm. The triangular wave scanning algorithm gradually increases the target current value from the initial value to the maximum value and then decreases it back to the initial value according to the triangular wave curve, repeating the cycle.

[0008] In some embodiments, the status register includes at least one error register; Based on the data in the status register corresponding to each test channel, determine the fault type for each test channel, including: Based on the value of the fault status bit in the error register, and based on the preset correspondence between the value of the fault status bit and the fault type, the fault type corresponding to the value of the fault status bit is determined. The fault type corresponding to the value of the fault status bit is determined as the fault type corresponding to the test channel; Obtain the value of the fault status bit corresponding to each test channel to determine the fault type corresponding to each test channel.

[0009] Based on the fault type corresponding to each test channel, determine the fault detection result for each test channel, including: According to the board and channel number to which each test channel belongs, the fault types of each test channel are grouped and statistically analyzed to generate the fault detection results corresponding to each test channel. Each test channel corresponds to a channel number. The fault detection results include: the time of fault occurrence and real-time operating status of each test channel.

[0010] In some embodiments, after determining the fault detection result for each test channel, the method further includes: Based on the fault detection results, an alarm is triggered using a tiered alarm strategy, which includes: If the value corresponding to a certain fault status bit in the fault detection result is "fault", then update the color of the switch status control corresponding to that fault status bit, and / or, label the switch status control; and, If a test channel in the fault detection results detects a first fault, a full-screen warning window will be triggered, and the test of the test channel will be stopped. The first fault includes at least one of the following: short circuit, power supply failure, write current failure, and over-limit alarm.

[0011] In some embodiments, after determining the fault detection result corresponding to each test channel, the method further includes: Based on file generation rules, fault detection files are created, including: Based on a preset amount of data, a fault detection file is generated, where the amount of data is represented by the number of data rows. Name the fault detection file based on its generation time. Store the fault detection files in a predetermined directory.

[0012] In some embodiments, a fault detection file is generated based on a preset data volume, including: Obtain the first format file; The fault detection results are written to the first format file in real time in the form of data rows through an independent working thread; Real-time detection of the number of data lines in the first-format file; If the number of data rows in the current first format file is greater than or equal to a preset threshold, then the current first format file will be used as the fault detection file.

[0013] On the other hand, embodiments of this application provide a multi-board testing system, including: At least one processor; At least one memory for storing at least one program; When at least one program is executed by at least one processor, the at least one processor performs the method described above.

[0014] On the other hand, embodiments of this application provide a non-volatile computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to perform the above-described method.

[0015] This application provides a multi-board testing method applied to a magnetic control system. The magnetic control system includes a power management module, which includes multiple boards. The method includes: acquiring multiple device addresses, wherein each device address corresponds one-to-one with a board, and each board corresponds to several test channels; assigning an independent state machine to each test channel of each board; issuing test commands to the multiple boards based on the device addresses to drive each test channel within each board to independently run its corresponding state machine; controlling the state machine corresponding to each test channel to execute the test process in parallel, and performing full-dimensional fault detection in real time during the operation of the state machine to determine the fault detection result corresponding to each test channel. The test process includes current regulation testing and polarity switching cycle testing.

[0016] By utilizing the device addresses corresponding to multiple boards, test commands are sent to multiple boards to drive each test channel within the board to independently run its corresponding state machine; the state machine corresponding to each test channel is controlled to execute the test process in parallel; and full-dimensional fault detection is performed in real time during the operation of the state machine to determine the fault detection results in order to obtain the test results corresponding to each test channel. This application can improve the testing efficiency of multiple boards. Attached Figure Description

[0017] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0018] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0019] Figure 1This is a schematic diagram of the structure of a magnetic control system provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of a power management module provided in an embodiment of this application; Figure 3 This is a flowchart illustrating a multi-board testing method provided in an embodiment of this application; Figure 4 This is provided by the embodiments of this application. Figure 3 A detailed flowchart of step S304 in the process; Figure 5 This is provided by the embodiments of this application. Figure 3 Another detailed flowchart of step S304 in the process; Figure 6 This is provided by the embodiments of this application. Figure 5 A detailed flowchart of step S347 in the process; Figure 7 This is a schematic diagram of a hierarchical alarm strategy provided after step S348 in an embodiment of this application; Figure 8 This is a schematic diagram of a process for creating a fault detection file provided in an embodiment of this application; Figure 9 This is provided by the embodiments of this application. Figure 8 A detailed flowchart of step S801 in the process; Figure 10 This is a schematic diagram of the structure of a multi-board testing system provided in an embodiment of this application.

[0020] Explanation of icon numbers: Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that, unless there is a conflict, the various features in the embodiments of this application can be combined with each other, all of which are within the protection scope of this application. In addition, the terms "first" and "second" used in this application do not limit the data, but only distinguish the same or similar items with basically the same function and effect.

[0023] The technical solution of this application will be described in detail below with reference to the accompanying drawings: Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of a magnetic control system provided in an embodiment of this application.

[0024] This magnetron control system is applied to semiconductor equipment, such as plasma etching machines, which are used to perform plasma etching processes on substrates such as wafers and display substrates. The working principle of a plasma etching machine is to selectively remove material with nanometer-level precision by using highly reactive gases excited into plasma in a vacuum environment, through the synergistic effect of physical bombardment and chemical reaction.

[0025] like Figure 1 As shown, the plasma etching machine 200 includes a gas output module 21, an etching chamber 22, an electrostatic chuck 23, and a coil 24.

[0026] The gas output module 21 is configured to input a specific type of reactive gas, including fluorine- or chlorine-containing gases, into the gas inlet of the etching chamber 22. The reactive gas is ionized to generate a plasma composed of ions, electrons, and highly reactive free radicals. The gas output module 21 is located outside the plasma etching machine 200 and is connected to the gas inlet of the etching chamber 22 via a pipeline. The gas inlet of the etching chamber 22 is typically designed at the top of the etching chamber 22 to ensure that the gas diffuses evenly throughout the entire etching chamber 22, covers the substrate surface, and then exits from the gas output port at the bottom. The gas output module 21 can output specific types of gas as needed, including CF4, SF6, and CHF3 gases.

[0027] An electrostatic chuck 23 is disposed at the bottom of the etching cavity 22 and is configured to support and hold the substrate 23a. The substrate 23a can be a wafer, a display panel substrate, etc. After the substrate 23a is placed on the surface of the electrostatic chuck 23, the electrostatic chuck 23 firmly fixes the substrate 23a in place through electrostatic adsorption, preventing the substrate 23a from shifting or vibrating during the etching process and ensuring etching uniformity.

[0028] The magnetic control system 100 includes a constant current source device 11, a power management module 12, and a host computer 13.

[0029] The constant current source device 11, located in the plasma etching machine 200, is used to drive the coil 24. It is configured to output a constant driving current according to preset etching process parameters, thereby driving the coil 24 to generate a constant magnetic field within the etching cavity 22, guiding the plasma to etch the substrate. The constant current source device is an adjustable linear constant current power supply with an output current range of 0-20A. It is used to drive the coil 24 to generate a magnetic field, controlling the uniformity of the plasma during the etching process. The etching process parameters include substrate material and etching pattern precision. Based on these parameters, the constant current source device 11 determines the corresponding driving current and transmits it to the coil 24 to generate a magnetic field. This magnetic field can constrain and regulate the plasma ion density, guiding the plasma's directional movement and improving etching accuracy.

[0030] Coil 24 is electrically connected to constant current source device 11 and is sleeved on etching cavity 22. Coil 24 is configured to generate a magnetic field within etching cavity 22 in response to the input of a driving current, guiding the plasma inside etching cavity 22 towards the substrate for etching. It is understood that when coil 24 receives a driving current, it can form a magnetic field of specific intensity and distribution within etching cavity 22. This magnetic field constrains and guides the ionized plasma within etching cavity 22, ensuring that active ions move precisely towards the target area on the substrate surface, thus guaranteeing the directionality and precision of etching.

[0031] The host computer 13 is communicatively connected to the constant current source device 11 and the power management module 12, and is configured to receive user instruction information, generate drive signals, and send drive signals to the constant current source device 11, so that the constant current source device 11 responds to the drive signals and outputs a constant drive current to the coil 24, so as to drive the coil 24 to form a magnetic field of specific intensity and distribution in the etching cavity 22.

[0032] Please refer to the following: Figure 2 , Figure 2 This is a schematic diagram of the structure of a power management module provided in an embodiment of this application.

[0033] The power management module includes multiple boards.

[0034] like Figure 2 As shown, the power management module 12 includes three types of independent boards: the central control board 121, the core board 122, and the power module 123.

[0035] Among them, the central control board 121, the core board 122, and the power module 123 are each configured with a unique Modbus slave address, and each board has multiple independent test channels. The central control board 121 realizes voltage, current, and resistance acquisition and output polarity control. The core board 122 realizes multi-channel current closed-loop regulation. The power module 123 realizes power output and output parameter monitoring.

[0036] In this embodiment, the multi-board testing method is used to perform production testing and aging verification of the power management module. It is applicable to scenarios such as production line aging testing, stress testing (abnormal frame fault tolerance verification), and functional regression testing. For example, it can be used to perform batch functional verification of three types of circuit boards: core board, power module, and central control board. Alternatively, it can be used to perform remote parameter reading and writing and automated testing of the lower-level machine through the Modbus RTU industrial communication protocol.

[0037] Currently, a single-channel independent testing method is usually adopted. For example, Modbus RTU commands are sent one by one through serial port debugging tools (such as SSCOM, SecureCRT, etc.) to perform read and write operations on the module under test.

[0038] However, the single-channel testing method described above requires testing each channel of each board individually. When dealing with multi-channel boards such as 5-channel simulation boards, this solution requires switching channels one by one for testing, and the testing time for a single board increases with the number of channels. Furthermore, the testing system typically only allows sequential testing of single boards; the next board can only be tested after the previous one has been completed, and it does not support concurrent synchronous testing of multiple boards and multiple channels. Testing hardware and host computer computing resources cannot be fully utilized, resulting in a long overall testing cycle and low testing efficiency in mass production scenarios.

[0039] Based on this, this application provides a testing method for multiple boards. By using the device addresses corresponding to each board, test instructions are sent to the multiple boards to drive each test channel within the board to independently run its corresponding state machine. The state machine corresponding to each test channel is controlled to execute the test process in parallel. Furthermore, during the operation of the state machine, full-dimensional fault detection is performed in real time to determine the fault detection results, thereby obtaining the test results corresponding to each test channel and improving the testing efficiency of multiple boards.

[0040] For details, please refer to Figure 3 , Figure 3 This is a flowchart illustrating a multi-board testing method provided in an embodiment of this application.

[0041] The multi-board testing method is applied to a magnetic control system. Specifically, the main body executing the multi-board testing method is one or at least two processors of the host computer.

[0042] like Figure 3 As shown, the testing method for this multi-board unit includes the following steps S301-S304: Step S301: Obtain multiple device addresses, where each device address corresponds to a different board, and each board corresponds to several test channels.

[0043] Specifically, the power management module supports various heterogeneous boards, enabling integrated parallel control of multiple boards, including a central control board, core board, and power module, on a single bus. Using the Modbus RTU protocol and different device addresses to distinguish board types, it achieves coordinated control of three different functional boards simultaneously from a single host computer. Specifically, each board corresponds to a different device address and the parameter being measured. This device address includes the Modbus slave address, for example: The device address of the central control board is 0xA0, and its measured parameters include 5 channels of current, voltage, resistance, enable status, polarity, working status, and accuracy. The core board's device address is 0xA1, and its measured parameters include set current, real-time current, temperature, and operating status. The power module's device address is 0xA2, and its measured parameters include current, temperature, and accuracy.

[0044] It should be noted that each board corresponds to several test channels, for example: The central control board includes multiple test channels such as multi-channel voltage acquisition, multi-channel current acquisition, resistance sampling, and output polarity control, which can perform tests such as voltage / current / resistance sampling, polarity switching, channel enable control, measurement accuracy verification, and status feedback.

[0045] The core board includes multiple programmable current adjustment channels, a real-time current sampling loop, an onboard temperature acquisition circuit, a control logic unit, a Modbus communication interface, and other test channels, enabling it to perform tests such as set current closed-loop adjustment, steady-state current testing, temperature monitoring, and long-term stress testing.

[0046] The power module includes multiple power output channels, an output current sampling circuit, a temperature monitoring circuit, a Modbus communication interface, and other test channels, enabling it to perform tests such as output current stability testing, temperature rise testing, output accuracy verification, and aging cycle testing.

[0047] In this embodiment of the application, curves of different boards are presented through a multi-layer real-time curve visualization scheme based on the functional characteristics of different types of boards.

[0048] Specifically, for a 5-channel central control board, the real-time trend of the central control board is displayed through 7 layers of curves: current, voltage, enable, polarity, status, accuracy, and resistance; for a single-channel core board, the real-time trend of the core board is displayed through 3 layers of curves: current, status, and temperature; and for a single-channel power module, the real-time trend of the power module is displayed through 3 layers of curves: current, temperature, and accuracy.

[0049] Furthermore, for the aging test of the 5-channel central control board, the display is achieved by setting the current, reading back the current, setting the polarity, and reading back the polarity in four layers. At this time, the aging test of the central control board corresponds to 5 channels * 4 = 20 curves.

[0050] In this embodiment, each curve layer has an independent legend and Y-axis range. For example, each waveform curve corresponds to a separate legend label, line color, and line type; multiple curve legends are not bound to each other. Furthermore, each curve is configured with an independent Y-axis range and upper and lower limits, and the scaling of each waveform does not interfere with each other, making it suitable for simultaneous observation of multiple types of heterogeneous signals (analog voltage, current, temperature, and other data with different dimensions). The interface also includes checkbox controls, for example: check → render curve; decheck → stop drawing the curve. Each curve layer is independent of the others, and users can shield unwanted data waveforms as needed.

[0051] Furthermore, the system employs a 50ms timer to construct a 20FPS plotting scheduling mechanism. The sampled raw data is first cached in the data queue, and plotting operations are not performed directly on the data acquisition thread. The scheduled task reads data from the queue at a fixed frame rate and completes waveform redrawing in a unified manner, thereby decoupling the data acquisition process from UI rendering, avoiding large-scale waveform update operations from occupying or blocking the UI main thread, and ensuring the smooth operation of the monitoring interface.

[0052] In this embodiment, a multi-dimensional layered visualization method enables testers to flexibly select and combine the data dimensions they need to observe based on their focus. For a 5-channel control board, testers can simultaneously observe the real-time changing trends of 35 data points (5 channels × 7 layers), quickly locate abnormal channels and abnormal dimensions, and significantly improve the efficiency of data analysis and fault location.

[0053] In this embodiment, through a multi-board heterogeneous parallel control architecture, testers can simultaneously monitor and control three different types of circuit boards on the same interface without switching between multiple independent tools, significantly reducing operational complexity and improving the efficiency of multi-board collaborative debugging. Simultaneously, the unified bus architecture reduces the number of hardware connections, lowering the cost and complexity of test fixtures.

[0054] Step S302: Assign an independent state machine to each test channel of each board.

[0055] Specifically, the host computer instantiates resources for all test channels based on the test channel information of each board. Specifically, for each physical test channel within the central control board, core board, and power module, it creates isolated finite state machine instances. Each state machine has an independent context storage space and independently maintains the channel number, the device address (Modbus slave address) of its parent board, the current operating state, test parameter thresholds, timing timers, fault flags, and sampling buffers. The execution logic of state machines corresponding to different test channels is non-blocking and their states are decoupled.

[0056] For example: assign independent state machines to the multiple voltage acquisition channels, current acquisition channels, and output polarity control channels of the central control board; assign independent state machines to the multiple programmable current adjustment channels of the core board; and assign independent state machines to the multiple power output channels of the power module.

[0057] It should be noted that each state machine has a pre-defined set of unified states, including idle standby, instruction issuance, waiting for response, parameter judgment, fault alarm, loop iteration, and test completion; and can automatically load the matching test process script according to the channel hardware type.

[0058] Step S303: Based on the device address, send test commands to multiple boards to drive each test channel in each board to run its corresponding state machine independently.

[0059] Specifically, the host computer parses the state machine attribution information, locates the Modbus slave address corresponding to the board to which the channel belongs (central control board 0xA0, core board 0xA1, power module 0xA2), fills the corresponding slave address in the message header, encapsulates and generates a read / write instruction frame conforming to the Modbus RTU specification, and obtains the test instruction corresponding to each board; and sends the corresponding test instruction to multiple boards, so that after receiving the test instruction, the board can distinguish the internal target test channel according to the register address, drive the corresponding hardware channel to perform actions, and synchronously collect electrical parameters.

[0060] For example, the polarity channel state machine of the central control board initiates a polarity switching command, and the current channel state machine of the core board initiates a current setting command. The two commands enter the communication queue and are sent out sequentially. When the board returns the sampled response data, the host computer matches the corresponding channel state machine according to the message slave address + register number, refreshes the internal sampled data of the state machine, triggers a state jump, and continuously advances the current regulation test and polarity switching cycle test process.

[0061] In this embodiment, each independent state machine continuously outputs test action requests, and the host computer counts all pending tasks for all channels, supporting asynchronous queuing of multi-channel test tasks. Each channel's state machine independently advances the process and maintains its own timing, thereby enabling a macroscopic realization of multi-channel parallel testing effects.

[0062] Step S304: Control the state machine corresponding to each test channel to execute the test process in parallel, and perform full-dimensional fault detection in real time during the operation of the state machine to determine the fault detection result corresponding to each test channel. The test process includes current regulation test and polarity switching cycle test. Specifically, the state machine corresponding to each test channel includes an idle state, a current setting state, a current holding state, a reverse polarity state, and a positive polarity state. It can be understood that since the current of each channel needs to cycle, the state machine's state is (Idle → SetCurrent → Keep → ReversePolarity → NormalPolarity → Idle). From the idle state to the current setting state, then to the current holding state, then to the reverse polarity state, then to the positive polarity state, and then back to the idle state, a cycle is formed. Each test channel maintains its own independent state structure (AgingChannelState), and the aging process is executed in parallel without interference.

[0063] Please refer to the following: Figure 4 , Figure 4 This is provided by the embodiments of this application. Figure 3 A detailed flowchart of step S304 in the process.

[0064] like Figure 4 As shown, step S304 involves controlling the state machine corresponding to each test channel to execute the test process in parallel, including the following steps S341-S345: Step S341: Control the state machine corresponding to each test channel to enter the idle state and wait for the start command.

[0065] Specifically, after the host computer completes the loading of the board address and the creation and initialization of the state machine instances for each channel, it switches all the independent state machines bound to the test channels to the idle state. In the idle state, the state machine does not issue any control commands to the board under test, stops current adjustment and polarity switching actions, and continuously listens for the host computer's local test start command.

[0066] In this embodiment, during the idle state of the state machine, basic fault inspection is continuously performed: monitoring the connection status of the channel communication link and continuously verifying the basic communication connectivity of the Modbus bus; if channel hardware is detected to be offline or bus communication is abnormal, a channel communication fault record is directly generated; if there is no abnormality, it remains in standby state, waiting for the test start command to be issued.

[0067] It should be noted that each channel's state machine is in an independent idle state, supporting single-channel independent start-up testing as well as multi-channel synchronous trigger start-up, adapting to various working conditions such as single-point debugging and batch parallel testing.

[0068] Step S342: After receiving the start command, perform a current regulation test on each test channel.

[0069] Specifically, upon receiving the start command, a current regulation test is performed on each test channel, including: The control state machine switches to the current setting state (SetCurrent), generates the target current value, and sends the target current value to each test channel; based on the target current value, the control state machine switches to the current holding state, maintaining the current target current value for a first preset duration.

[0070] Specifically, after receiving the start command, the host computer drives the state machine corresponding to all channels under test in parallel to start the current adjustment test process.

[0071] First, the control state machine switches from idle state to current setting state. The state machine reads the preset current parameter configuration table and generates the target current value for the current range based on the current current step index. The host computer encapsulates the current configuration write instruction frame according to the Modbus RTU protocol and sends it to the corresponding board according to the Modbus slave address of the board to which the channel belongs, notifying the tested channel to output the target current. After receiving the instruction for the target current value, the tested board starts the current closed-loop regulation, gradually approaching the target current.

[0072] After the command for the target current value is issued and the board's current adjustment response is confirmed, the control state machine switches to the current holding state. During the current holding state, the measured channel continuously maintains a stable output of the current target current for a first preset duration. Throughout this holding period, the host computer periodically reads the channel's real-time current and temperature sampling data, continuously performs comprehensive fault detection, determines whether the deviation between the actual output current and the target current exceeds the accuracy threshold, and monitors channel temperature rise, current drift, output jitter, and other abnormal phenomena.

[0073] Specifically, the control state machine switches to the current setting state to generate the target current value, including: The control state machine switches to the current setting state. In the current setting state, for each test channel, a target current value is generated through a triangular wave scanning algorithm. The triangular wave scanning algorithm gradually increases the target current value from the initial value to the maximum value and then decreases it back to the initial value according to the triangular wave curve, repeating the cycle.

[0074] In this embodiment, the current of each channel gradually increases from the initial value to the capped value according to the triangular wave curve, and then decreases back to the initial value, repeating the cycle. After each current level is stabilized, a polarity reversal test is performed after a configurable time (default 600 seconds).

[0075] Specifically, the initial current value (starting value), maximum current value (capped value), and fixed current step value are pre-configured for each test channel. The triangular wave scanning algorithm consists of two closed-loop phases: the rising scan phase and the falling scan phase, which are executed repeatedly.

[0076] The first stage is current rise scanning: The algorithm starts from the preset current starting value and generates the target current value by increasing it step by step according to a fixed step value. Each time the target current value is updated, the host computer sends it to the corresponding test channel through the Modbus RTU protocol, driving the channel to output the corresponding current in closed loop. After the current of each level is stably output, it is maintained for a fixed first preset time (default configuration 600 seconds). During this holding period, parameters such as real-time current, temperature, and output accuracy are continuously collected to complete steady-state fault detection and performance verification.

[0077] When the current increases to the preset current cap value, the rising scan phase ends and switches to the second phase of current falling scan: the algorithm starts with the maximum current value, generates the target current value by decreasing it step by step according to the corresponding current increment, sends it down to the test channel in stages and maintains steady-state operation for 600 seconds, and continuously completes the data acquisition and fault detection of each stage of the downward working condition.

[0078] When the current decreases back to the initial value, a complete triangular wave scan cycle is completed, forming a triangular wave curve of "initial value → maximum value → initial value", which is the standard triangular wave current traversal curve. After a single triangular wave scan is completed, the algorithm automatically resets the scan baseline and can repeat multiple rounds of triangular wave cyclic scans according to the test configuration to achieve long-term continuous aging stress testing.

[0079] Furthermore, the triangular wave scanning algorithm forms a strong linkage with the subsequent polarity switching test: after the steady-state holding time (default 600 seconds) of each current level ends, the current level is not updated immediately; instead, the polarity switching loop test process is triggered first. That is, once the current level stabilizes and meets the standard and the steady-state test is completed, the state machine automatically jumps to the reverse polarity state and then to the positive polarity state to complete the bidirectional polarity verification. After all the positive and reverse polarity switching sequences have ended, it returns to the current setting state, updates the next order triangular wave current step value, and enters the scanning test for the next current level.

[0080] In this embodiment, the triangular wave current traversal with reciprocating rise and fall fully covers low, medium, and full-range current output conditions. At the same time, combined with the combined test logic of steady-state holding and positive / negative polarity switching for each range, it can fully expose hidden faults such as accuracy drift, response lag, temperature drift, polarity failure, and abnormal operating condition coupling in the circuit board channel during current rise, fall, steady state, and positive / negative polarity switching processes, thereby improving the comprehensiveness and reliability of batch testing of multiple circuit boards.

[0081] It should be noted that the starting current, capping current, current step value, range holding time (default 600s), and polarity switching time of the triangular wave scanning algorithm can all be flexibly configured through the host computer, which can adapt to the rated parameters of different models of central control boards, core boards, and power modules, as well as the differentiated testing needs of different test scenarios (production line functional testing, long-term aging testing, and pressure fault tolerance testing).

[0082] Step S343: After the first preset duration ends, perform a polarity switching loop test on each test channel.

[0083] Specifically, after the first preset duration, a polarity switching loop test is performed on each test channel, including: The control state machine switches to the reverse polarity state and continues for a second preset duration. After the reverse polarity state operation ends, the control state machine switches to the positive polarity state and continues for a third preset duration. The control state machine returns to the current setting state and updates the current step value, completing one cycle of current adjustment and polarity switching.

[0084] Specifically, the state machine continuously times while in the current-holding state. When the time reaches the first preset duration, the polarity switching cycle test is immediately started.

[0085] First, the control state machine switches to the reverse polarity state, and the host computer issues a polarity reversal command to control the tested channel to switch to reverse polarity output and continue to run for a second preset time. In the reverse polarity state, electrical parameters are continuously sampled to detect the current stability and whether the polarity switching response is normal under reverse polarity, and to identify polarity switching failure and reverse output abnormality faults.

[0086] When the second preset duration is completed, the control state machine switches to the positive polarity state and issues a command to restore the channel to positive polarity output, and continues to run for the third preset duration; during the positive polarity state operation, various parameters under positive operating conditions are continuously collected, and the output consistency under positive and negative polarity operating conditions is compared.

[0087] After the third preset duration ends, the control state machine jumps back to the current setting state, synchronously updates the current step index, and updates the target current value for the next round based on the step rules, thus completing a full test cycle of "current adjustment + positive and negative polarity switching".

[0088] It is understandable that the polarity reversal test is not a separate test procedure independent of the state machine, but rather a fixed transition step embedded within the state machine. Specifically, after the keep phase (Keep state) of each current level ends, the state machine is forced into the reverse polarity state, writes a reverse polarity value to the polarity control register and holds it for a preset time (e.g., 5 seconds), then automatically switches back to the normal polarity state and holds it for a preset time (e.g., 5 seconds), finally returning to the set current state (SetCurrent) to enter the next current level. Therefore, the polarity reversal test is automatically executed once at each current stress level, achieving a deep integration of current stress aging and polarity reversal aging, without the need for additional test steps or manual intervention.

[0089] Step S344: Determine whether the preset loop termination condition is met.

[0090] Specifically, if the preset cycle termination condition is not met, the current regulation and polarity switching cycle will be repeated until the preset cycle termination condition is met.

[0091] Specifically, after each complete cycle and the state machine returns to the current setting state, the host computer verifies the cycle termination condition for the current channel.

[0092] The preset cycle termination condition can be configured as at least one of the following: traversing all preset current levels, accumulating the maximum number of cycles, reaching the set aging time for the total test duration, or detecting an unrecoverable fault in the channel.

[0093] If the loop termination condition is not met, then steps S342-S343 are repeated to continuously iterate and carry out multiple rounds of current adjustment and polarity switching loop tests. If the loop termination condition is met, exit the loop process and jump to step S345.

[0094] Understandably, if the state machine detects a serious fault at any point during the loop, it can be configured to immediately trigger the termination condition, ending the current channel test in advance and achieving rapid fault interception.

[0095] Step S345: Terminate the test process.

[0096] Specifically, when the loop termination condition is met, the host computer controls the corresponding channel state machine to exit the test loop. First, it issues a command to turn off the channel power output, clear the current setting value, and release the polarity lock; then it controls the state machine to switch back to the idle state.

[0097] The host computer collects all sampled data, timing records, and fault detection results for the channel throughout the entire testing cycle, completes data caching, and marks the test completion status; it also supports local storage of test data and export of reports.

[0098] Understandably, the completion of a single-channel test will not affect the other channels that are currently undergoing testing. The state machines of the other channels continue to run the test process independently, achieving channel-level decoupling. After all channels have been tested, this batch test task will be completed as a whole.

[0099] Please refer to the following: Figure 5 , Figure 5 This is provided by the embodiments of this application. Figure 3 Another detailed flowchart of step S304 in the process.

[0100] like Figure 5 As shown, step S304 involves performing full-dimensional fault detection in real time during the operation of the state machine to determine the fault detection result for each test channel, including the following steps S346-S348: Step S346: During each round of execution, read the data of the status register corresponding to each test channel in real time.

[0101] Specifically, the host computer continuously and in parallel polls and collects the status register data of the corresponding board for each test channel during any working stage of the state machine's current setting, current holding, reverse polarity output, and positive polarity output. Fault detection and the testing process run synchronously and without blocking each other, achieving uninterrupted real-time monitoring throughout the entire testing process. Each board under test (central control board, core board, power module) has a built-in dedicated status register group, which includes at least one error register. Each independent test channel has a dedicated register address bit field, enabling independent storage of single-channel status data without interference.

[0102] In this embodiment, the host computer, based on the Modbus RTU communication protocol, precisely addresses each board using its unique slave address and periodically issues register read commands to read the raw data of the status registers of all test channels in real time. The data read frequency covers the entire time-series process of triangular wave current rise and fall scanning, gear steady-state holding, and positive / negative polarity switching, ensuring that there is status data traceability for any running node in each round of current adjustment and polarity switching cycle, with no detection blind spots. Simultaneously, the host computer performs real-time caching and timing marking on the read raw register data, binding it to the corresponding test channel number, test condition, and running timestamp, providing accurate data support for subsequent fault diagnosis.

[0103] Step S347: Determine the fault type corresponding to each test channel based on the data in the status register corresponding to each test channel; The status register includes at least one error register. Specifically, the host computer pre-stores a fault determination mapping database, which stores a one-to-one correspondence between preset fault status bit values ​​and various fault types. The host computer parses the error register data in the status registers of each channel, extracts the corresponding channel's fault status bit value, and combines it with the fault determination mapping database to accurately determine the channel's fault type.

[0104] Step S348: Determine the fault detection result for each test channel based on the fault type corresponding to each test channel, wherein the fault detection result includes the fault type corresponding to each test channel.

[0105] Specifically, based on the fault type corresponding to each test channel, the fault detection result for each test channel is determined, including: According to the board and channel number to which each test channel belongs, the fault types of each test channel are grouped and statistically analyzed to generate the fault detection results corresponding to each test channel. Each test channel corresponds to a channel number. The fault detection results include: the time of fault occurrence and real-time operating status of each test channel.

[0106] Specifically, after the host computer completes the fault type determination for all test channels, it classifies and groups the test channels according to the board to which they belong (e.g., "central control board", "core board", "power module") and the channel number. Each test channel has a unique channel number (e.g., CH1, CH2, ..., CHn) within its board, and each test channel corresponds to a channel number. For example, if the affiliation information of a certain channel is "central control board-CH3", it means that the test channel is located on the central control board and the channel number is CH3.

[0107] The host computer groups the data by "board number + channel number" and categorizes and aggregates the fault type data for each test channel. The specific grouping logic is as follows: First-level grouping: According to the type of board, it is divided into central control board group, core board group, and power module group; Second-level grouping: Within each board group, subgroups are formed according to channel number (CH1, CH2, etc.); each subgroup corresponds to a unique test channel, and all fault-related information of that channel is included in that subgroup.

[0108] Through the above two-level grouping, the system establishes a hierarchical data structure of "board → channel → fault information".

[0109] For each grouped test channel, the host computer further obtains the following information: (1) Fault occurrence time: Record the system timestamp of the most recent fault occurrence of this test channel. If the same test channel experiences multiple similar faults within the same test cycle, the first occurrence time or the most recent occurrence time can be recorded (the specific strategy can be determined by the system configuration). If the test channel does not experience a fault in the current test cycle, the fault occurrence time field is recorded as empty or marked as none.

[0110] (2) Real-time operating status: Read the actual working status of the test channel at the current moment. The operating status includes, but is not limited to: Normal, Fault, Offline, Testing, Idle, Protected, etc. The value of the real-time operating status is directly derived from the latest channel status register value or heartbeat signal reported by the corresponding board to the host computer.

[0111] In this embodiment, the fault detection result includes core information such as the real-time operating status of each test channel, whether a fault exists, the specific fault type, the fault occurrence sequence, and the corresponding test conditions, fully covering all test channels of the central control board, core board, and power module. After summarizing the fault detection results of all test channels, a complete multi-dimensional fault detection result dataset is formed. This fault detection result dataset can be displayed to the user in the form of a table, tree list, or topology diagram through a host computer interface, or it can be exported as a log file for subsequent analysis.

[0112] Furthermore, the host computer iteratively statistically analyzes and persistently stores the fault data from each round of triangular wave scanning cycle and each polarity switching test, distinguishing between instantaneous and intermittent faults and continuous steady-state faults. Ultimately, it generates a traceable and exportable batch test fault detection report, providing data support for the batch selection of good products, fault location, and performance optimization of the magnetic control system boards.

[0113] Please refer to the following: Figure 6 , Figure 6 This is provided by the embodiments of this application. Figure 5 A detailed flowchart of step S347 is shown.

[0114] like Figure 6 As shown, step S347: Based on the data in the status register corresponding to each test channel, determine the fault type corresponding to each test channel, including the following steps S371-S373: Step S371: Based on the value of the fault status bit in the error register and the preset correspondence between the value of the fault status bit and the fault type, determine the fault type corresponding to the value of the fault status bit.

[0115] Specifically, the board's error register uses a bit-field encoding mechanism, where each binary status bit corresponds to an independent fault condition. Different status bit values ​​(0 for normal, 1 for abnormal) correspond to preset, specific fault types. The host computer pre-enters standardized fault mapping rules, covering all fault scenarios across multiple boards in the magnetic control system. Specific fault types include: switching failure, power supply abnormality, switch quantity fault, write current failure, over-limit alarm, communication abnormality, fan status abnormality, and short circuit abnormality. The host computer parses the error register data bit by bit, traversing and matching the preset mapping relationships to accurately locate the specific fault type corresponding to the current status bit value.

[0116] Step S372: Determine the fault type corresponding to the value of the fault status bit as the fault type corresponding to the test channel.

[0117] Specifically, after the host computer completes the matching and verification of the fault status bits and fault types, it directly binds the successfully matched fault type to the fault type corresponding to the current test channel. If multiple fault status bits are set simultaneously in the error register of the same test channel, multiple concurrent fault types can be identified and judged simultaneously, supporting simultaneous detection of multiple faults on a single channel and avoiding missed or false judgments of single faults. At the same time, the fault type is bound and marked with the current channel's triangular wave scan setting, polarity operating status, and test duration to achieve accurate traceability of fault conditions.

[0118] Step S373: Obtain the value of the fault status bit corresponding to each test channel to determine the fault type of the test channel.

[0119] Specifically, the host computer iterates through all test channels in operation, repeatedly executing the fault status bit parsing and fault type matching process for each channel to batch obtain the fault status bit values ​​for all test channels. For test channels without anomalies, all fault status bit values ​​are at the normal threshold, indicating that the channel is currently fault-free and operating normally. For test channels with anomalies, the corresponding fault type is accurately identified, ultimately completing the full coverage fault type determination for all test channels and achieving parallel synchronous fault identification across multiple channels.

[0120] In some embodiments, after determining the fault detection result corresponding to each test channel, the method further includes: issuing an alarm based on the fault detection result using a hierarchical alarm strategy.

[0121] Please refer to the following: Figure 7 , Figure 7 This is a schematic diagram of a hierarchical alarm strategy provided after step S348 in an embodiment of this application.

[0122] like Figure 7 As shown, the alarm process using a tiered alarm strategy includes the following steps S701-S702: Step S701: If the value corresponding to a certain fault status bit in the fault detection result is fault, then update the color of the switch status control corresponding to the fault status bit, and / or, label the switch status control.

[0123] Specifically, if the parsed value of any fault status bit in the fault detection result is an abnormal value, the host computer will not trigger a shutdown operation, but will only update the visual abnormality mark of the switch status control of the corresponding test channel. The host computer test interface configures a dedicated switch status control for each test channel, and each control is bound to a channel fault status bit.

[0124] For example, a customized SwitchButton control uses colors such as red, yellow, and green to visually display fault status. Under normal operating conditions, all channel switch status controls are defaulted to green. When common faults such as slight current deviations, short-term communication jitter, or minor temperature drifts are detected, the corresponding channel control is updated to yellow, with an overlay of the text "Minor Abnormality" and a flashing indicator. If multiple recurring common faults of the same type are detected, the control remains highlighted and locked, and the abnormality record is maintained. This type of visual marker accurately locates the abnormal channel without interfering with parallel testing of other normal channels, enabling traceability of minor faults and uninterrupted batch testing.

[0125] Step S702: If a test channel in the fault detection results detects a first fault, a full-screen warning window is triggered, and the test of the test channel is stopped. The first fault includes at least one of short circuit abnormality, power supply abnormality, write current failure, and over-limit alarm.

[0126] Specifically, high-risk faults are predefined as the first fault, which includes at least one of the following: short circuit, power supply failure, write current failure, and over-limit alarm. This type of fault can lead to serious problems such as damage to board hardware, complete loss of test data, and bus communication failure, and requires the execution of the highest priority alarm handling logic.

[0127] For example, during the triangular wave current rise / fall scanning and polarity switching operation, if any test channel's fault status bit reveals a short circuit, power failure of the board, no response to the current configuration command issued by the host computer, or output current exceeding the hardware's rated range, the host computer immediately triggers a full-screen top-level warning pop-up. The pop-up accurately displays the fault channel number, fault type, fault occurrence time, and current test status, and also triggers a full-screen top-level red warning window (Full Screen Warning). Simultaneously, all test processes for the faulty test channel are immediately stopped, the current fault state machine's operating data is locked, and the channel is prohibited from continuing to perform current adjustment and polarity switching cycle tests. Other normal test channels without faults are unaffected and continue to maintain parallel testing operation, achieving isolated faulty channels while uninterrupted testing of normal channels.

[0128] In this embodiment, an alarm is triggered by a hierarchical alarm strategy, achieving a millisecond-level response from the occurrence of a fault to its detection, thus preventing equipment damage or safety accidents caused by continuous operation of the fault.

[0129] Furthermore, after determining the fault detection results for each test channel, the method also includes: creating a fault detection file based on file generation rules.

[0130] Please refer to the following: Figure 8 , Figure 8 This is a schematic diagram of a process for creating a fault detection file provided in an embodiment of this application.

[0131] like Figure 8 As shown, based on the file generation rules, a fault detection file is created, including the following steps S801-S803: Step S801: Generate a fault detection file based on a preset data volume, wherein the data volume is represented by the number of data rows.

[0132] Specifically, the number of data rows is used as the criterion for determining the amount of data generated in a file. A rolling block storage mechanism is adopted to avoid reading lag and parsing errors caused by excessively large data volume in a single file, thus ensuring the stability of writing faulty data.

[0133] Step S802: Name the fault detection file based on its generation time.

[0134] Specifically, the host computer uses the generation end time of the current fault detection file as the sole naming criterion, employing a standardized naming rule of "year-month-day-hour-minute-second + batch number" to avoid file name conflicts and data confusion. For example, the complete file name is "20260802-183022-fault data-01.csv". The timestamp accurately distinguishes fault files from different test periods and batches, facilitating precise retrieval and traceability later.

[0135] Step S803: Store the fault detection file in a predetermined directory.

[0136] Specifically, the host computer is pre-configured with a fixed storage directory, supporting dedicated folder storage on local disks and also adaptable to shared directory storage on a local area network. All generated fault detection files are automatically archived to the predetermined directory, preventing arbitrary tampering and automatically retaining backups, enabling full traceability, exportability, and replayability of test fault data, providing complete data support for batch quality inspection of boards, fault reproduction, and equipment iteration optimization.

[0137] For further information, please refer to [link / reference]. Figure 9 , Figure 9 This is provided by the embodiments of this application. Figure 8 A detailed flowchart of step S801 is shown.

[0138] like Figure 9 As shown, step S801: Based on a preset data volume, a fault detection file is generated, including the following steps S811-S814: Step S811: Obtain the first format file.

[0139] Specifically, the host computer pre-acquires and initializes the first format file, for example: the first format file is in CSV format (UTF-8 BOM encoding), which is compatible with Excel export, background data analysis, and is suitable for batch test data statistics scenarios.

[0140] Step S812: Write the fault detection results into the first format file in real time in the form of data rows through an independent working thread.

[0141] Specifically, the host computer starts an independent background working thread, which runs asynchronously and in parallel with the front-end testing and fault detection main thread. It continuously writes the real-time fault detection results of each loop and each channel into the first format file in the form of single-line structured data. The single-line data includes: channel number, board address, triangular wave current level, polarity status, fault type, fault timestamp, sampling parameters and other full-dimensional information.

[0142] Step S813: Real-time detection of the number of data lines in the first format file.

[0143] Specifically, the background worker thread counts and detects the number of valid data lines in the current first format file in real time, and continuously compares it with the preset number threshold. For example, the preset number threshold is 5000, that is, the preset maximum number of fault data lines stored in a single file is 5000.

[0144] Step S814: If the number of data rows in the current first format file is greater than or equal to the preset number threshold, then the current first format file is used as the fault detection file.

[0145] Specifically, when the number of data lines in the current file is detected to be greater than or equal to a preset threshold, it is determined that the current batch of data has been written, and the full-capacity first-format file is officially identified as a valid fault detection file; at the same time, a blank first-format file is automatically created, and the rolling writing of the next batch of fault data is started, so as to achieve uninterrupted continuous storage.

[0146] In this embodiment of the application, the problem of difficulty in opening large single files is avoided by using an automatic fragmentation mechanism, which can better generate fault detection files.

[0147] In this embodiment, a multi-board testing method is provided for a magnetic control system. The magnetic control system includes a power management module, which includes multiple boards. The method includes: acquiring multiple device addresses, wherein each device address corresponds one-to-one with a board, and each board corresponds to several test channels; allocating an independent state machine to each test channel of each board; issuing test commands to the multiple boards based on the device addresses to drive each test channel within each board to independently run its corresponding state machine; controlling the state machine corresponding to each test channel to execute the test process in parallel, and performing full-dimensional fault detection in real time during the operation of the state machine to determine the fault detection result corresponding to each test channel. The test process includes current regulation testing and polarity switching cycle testing.

[0148] By utilizing the device addresses corresponding to multiple boards, test commands are sent to multiple boards to drive each test channel within the board to independently run its corresponding state machine; the state machine corresponding to each test channel is controlled to execute the test process in parallel; and full-dimensional fault detection is performed in real time during the operation of the state machine to determine the fault detection results in order to obtain the test results corresponding to each test channel. This application can improve the testing efficiency of multiple boards.

[0149] Please see Figure 10 , Figure 10This is a schematic diagram of the structure of a multi-board testing system provided in an embodiment of this application.

[0150] In this embodiment, the multi-board testing system includes a host computer, which comprises general-purpose computer hardware, a serial communication unit, and testing software running on the hardware. The host computer hardware consists of a general-purpose industrial PC, serving as the core hardware carrier and equipped with a processor to execute all logical operation tasks, including state machine instantiation, parallel scheduling, fault analysis, and data processing. The serial communication hardware unit includes a native RS-232 / RS-485 serial port, or a USB-to-serial adapter, used to establish a Modbus RTU communication physical link with the lower-level multi-board system, enabling command issuance and data transmission.

[0151] like Figure 10 As shown, the multi-board test system 300 includes one or more processors 301 and a memory 302. Among them, Figure 10 Take processor 301 as an example.

[0152] Processor 301 and memory 302 can be connected via a bus or other means. Figure 10 Taking the example of a connection between China and Israel via a bus.

[0153] Processor 301 is used to execute the multi-board testing method of the embodiments of this application, applied to a magnetic control system. The magnetic control system includes a power management module, which includes multiple boards. The method includes: obtaining multiple device addresses, wherein the multiple device addresses correspond one-to-one with the multiple boards, and each board corresponds to several test channels; allocating an independent state machine to each test channel of each board; issuing test instructions to the multiple boards based on the device addresses to drive each test channel in each board to independently run the corresponding state machine; controlling the state machine corresponding to each test channel to execute the test process in parallel, and performing full-dimensional fault detection in real time during the operation of the state machine to determine the fault detection result corresponding to each test channel, wherein the test process includes current regulation test and polarity switching cycle test.

[0154] By utilizing the device addresses corresponding to multiple boards, test commands are sent to multiple boards to drive each test channel within the board to independently run its corresponding state machine; the state machine corresponding to each test channel is controlled to execute the test process in parallel; and full-dimensional fault detection is performed in real time during the operation of the state machine to determine the fault detection results in order to obtain the test results corresponding to each test channel. This application can improve the testing efficiency of multiple boards.

[0155] The memory 302, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the multi-board testing method in the embodiments of this application. The processor 301 executes various functional applications and data processing of the host computer by running the non-volatile software programs, instructions, and modules stored in the memory 302, thereby implementing the multi-board testing method of the above-described method embodiments.

[0156] Memory 302 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 302 may optionally include memory remotely located relative to processor 301. Examples of the above-described networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0157] One or more modules are stored in memory 302. When executed by one or more processors 301, they perform the multi-board testing method described in the above method embodiments, for example, the method described above. Figure 3 The steps shown.

[0158] This application also provides a non-volatile computer-readable storage medium storing computer-executable instructions that are executed by one or more processors. For example, the one or more processors can execute the multi-board testing method in any of the above method embodiments, such as performing the steps described above.

[0159] This application also provides a computer program product, which includes one or more lines of program code stored in a non-volatile computer-readable storage medium. The processor of the host computer reads the program code from the non-volatile computer-readable storage medium and executes the program code to complete the steps of the multi-board testing method provided in the above embodiments.

[0160] Based on the above description of the embodiments, those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program or program code related to hardware. The program can be stored in a non-volatile computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0161] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The non-volatile computer-readable storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0162] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations as described above in different aspects of this application, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A testing method for multiple circuit boards, characterized in that, Applied to a magnetic control system, the magnetic control system including a power management module, the power management module including multiple boards, the method includes: Obtain multiple device addresses, wherein each of the multiple device addresses corresponds one-to-one with a multiple of the boards, and each of the boards corresponds to several test channels; Each test channel of each board is assigned an independent state machine; Based on the device address, test commands are sent to multiple boards to drive each test channel within each board to independently run its corresponding state machine; The state machine corresponding to each test channel is controlled to execute the test process in parallel, and full-dimensional fault detection is performed in real time during the operation of the state machine to determine the fault detection result corresponding to each test channel. The test process includes current adjustment test and polarity switching cycle test. The process of performing full-dimensional fault detection in real time during the operation of the state machine, and determining the fault detection result corresponding to each test channel, includes: During each round of execution, the data of the status register corresponding to each test channel is read in real time; Based on the data in the status register corresponding to each test channel, determine the fault type corresponding to each test channel; Based on the fault type corresponding to each test channel, a fault detection result corresponding to each test channel is determined, wherein the fault detection result includes the fault type corresponding to each test channel.

2. The method according to claim 1, characterized in that, The state machine includes an idle state, a current setting state, a current holding state, a reverse polarity state, and a positive polarity state; The process of controlling the state machine corresponding to each test channel to execute the test process in parallel includes: The state machine corresponding to each test channel is controlled to enter the idle state, waiting for the start command; Upon receiving the start command, a current regulation test is performed on each of the test channels, including: The state machine is controlled to switch to the current setting state, a target current value is generated, and the target current value is sent to each of the test channels; The state machine is controlled to switch to the current holding state based on the target current value, and maintain the current target current value for a first preset duration; After the first preset duration ends, a polarity switching cyclic test is performed on each of the test channels, including: The state machine is controlled to switch to the reverse polarity state and remain in the state for a second preset duration; after the reverse polarity state operation ends, the state machine is controlled to switch to the positive polarity state and remain in the state for a third preset duration. The state machine is controlled to return to the current setting state, and the current step value is updated to complete one cycle of current adjustment and polarity switching. Repeat the current regulation and polarity switching cycle until the preset cycle termination condition is met.

3. The method according to claim 2, characterized in that, The step of controlling the state machine to switch to the current setting state and generating the target current value includes: The state machine is controlled to switch to the current setting state. In the current setting state, for each test channel, a target current value is generated by a triangular wave scanning algorithm. The triangular wave scanning algorithm gradually increases the target current value from the initial value to the maximum value and then decreases it back to the initial value according to the triangular wave curve, and repeats the cycle.

4. The method according to claim 1, characterized in that, The status register includes at least one error register; The step of determining the fault type corresponding to each test channel based on the data in the status register corresponding to each test channel includes: Based on the value of the fault status bit in the error register, and based on the preset correspondence between the value of the fault status bit and the fault type, the fault type corresponding to the value of the fault status bit is determined. The fault type corresponding to the value of the fault status bit is determined as the fault type corresponding to the test channel; Obtain the value of the fault status bit corresponding to each of the test channels, and determine the fault type corresponding to each of the test channels.

5. The method according to claim 1, characterized in that, The step of determining the fault detection result for each test channel based on the fault type for each test channel includes: According to the board and channel number to which each test channel belongs, the fault types of each test channel are grouped and statistically analyzed to generate the fault detection results corresponding to each test channel. Each test channel corresponds to a channel number. The fault detection results include: the fault occurrence time and real-time operating status of each test channel.

6. The method according to claim 1, characterized in that, After determining the fault detection result for each of the test channels, the method further includes: Based on the fault detection results, an alarm is triggered using a tiered alarm strategy, wherein the tiered alarm strategy includes: If the value corresponding to a certain fault status bit in the fault detection result is a fault, then update the color of the switch status control corresponding to that fault status bit, and / or, label the switch status control; and, If a test channel in the fault detection results detects a first fault, a full-screen warning window is triggered, and the test of the test channel is stopped. The first fault includes at least one of short circuit abnormality, power supply abnormality, write current failure, and over-limit alarm.

7. The method according to claim 1, characterized in that, After determining the fault detection result for each of the test channels, the method further includes: Based on file generation rules, a fault detection file is created, wherein creating the fault detection file based on file generation rules includes: The fault detection file is generated based on a preset data volume, wherein the data volume is represented by the number of data rows; Name the fault detection file based on its generation time. The fault detection file is stored in a predetermined directory.

8. The method according to claim 7, characterized in that, The process of generating the fault detection file based on a preset data volume includes: Obtain the first format file; The fault detection results are written to the first format file in real time in the form of data rows through an independent working thread; Real-time detection of the number of data lines in the first format file; If the number of data rows in the first format file is greater than or equal to a preset threshold, then the current first format file is used as the fault detection file.

9. A multi-board testing system, characterized in that, include: At least one processor; At least one memory for storing at least one program; When at least one of the programs is executed by at least one of the processors, such that at least one of the processors implements claim 1 8. Any one of the methods described.

10. A non-volatile computer-readable storage medium storing a processor-executable program, characterized in that, The processor-executable program, when executed by the processor, is used to perform as claimed in claim 1.

8. Any one of the methods described.

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