Method and apparatus for managing multi-core logs

Abstract

The application discloses a method and device for managing multi-core logs. The method comprises the following steps: writing log information generated by a plurality of DSP cores into corresponding memory cache areas respectively, each DSP core being allocated with a dedicated memory cache area; collecting log information from each memory cache area corresponding to the plurality of DSP cores by an MCU master core; and uploading the collected log information to a storage unit for persistent storage by the MCU master core. In the application, each DSP core is allocated with a dedicated memory cache area, so that each DSP core can correspondingly operate the dedicated memory cache area thereof, and through physical isolation of memory space, the application can avoid write conflicts without a multi-core synchronization mechanism, and meanwhile, the MCU master core is specially responsible for log collection and uploading, so that log tasks cannot interfere with audio processing tasks, and the real-time performance of the audio processing tasks is ensured.

Description

Technical Field

[0001] This invention relates to the field of embedded technology, and more particularly to a method and apparatus for managing multi-core logs. Background Technology

[0002] In multi-core in-vehicle audio systems, continuous logging of each core is necessary to ensure reliable system operation and fault diagnosis. Currently, the mainstream approach uses Flash memory as the final log storage medium, forming a process of real-time acquisition, temporary storage, and Flash persistence. However, Flash storage has inherent drawbacks: firstly, frequent log writes accelerate Flash wear, leading to premature Flash failure and impacting long-term reliability; secondly, Flash write latency is high, which can easily interfere with real-time tasks during critical audio processing periods, causing audio stuttering. Summary of the Invention

[0003] This invention provides a method and apparatus for managing multi-core logs. By allocating a dedicated memory cache for each DSP core and having the MCU main core collect and upload log information, it achieves efficient log management without synchronization mechanisms and ensures the real-time performance of audio processing.

[0004] In a first aspect, the present invention provides a method for managing multi-core logs. The method includes: writing log information generated by multiple DSP cores into corresponding memory caches, each DSP core being allocated a dedicated memory cache; collecting log information from the respective memory caches corresponding to the multiple DSP cores via the MCU main core; and uploading the collected log information to a storage unit for persistent storage via the MCU main core.

[0005] In one implementation of the first aspect, uploading the collected log information to the storage unit for persistent storage via the MCU main core includes: determining the log level of the collected log information, determining the upload strategy of the log information based on the log level, and uploading the log information to the storage unit for persistent storage according to the upload strategy.

[0006] In one implementation of the first aspect, determining the upload strategy for the log information based on the log level includes: if the log level is a critical log, then determining that the upload strategy is immediate upload; if the log level is a non-critical log, then determining that the upload strategy is periodic batch upload or delayed upload.

[0007] In one implementation of the first aspect, collecting log information from memory buffers corresponding to the plurality of DSP cores via the MCU master core includes: sending an inter-core interrupt to the MCU master core after log information of the critical log level is generated by any DSP core; and suspending the current task by the MCU master core so as to prioritize collecting log information from the memory buffer corresponding to the DSP core that sent the inter-core interrupt.

[0008] In one implementation of the first aspect, uploading the log information to the storage unit for persistent storage according to the upload strategy includes: polling the memory cache of each DSP core at a preset period through the MCU main core to collect log information with the log level of non-critical logs; and packaging the collected log information with the log level of non-critical logs into a single data packet and uploading the single data packet to the storage unit.

[0009] In one implementation of the first aspect, uploading the collected log information to the storage unit for persistent storage via the MCU main core includes: determining the current audio processing load state and adjusting the preset period according to the audio processing load state.

[0010] In one implementation of the first aspect, writing log information generated by multiple DSP cores into the corresponding memory cache includes: when the DSP core generates the log information, writing the log information into the corresponding memory cache in a cyclic overwrite manner.

[0011] In one implementation of the first aspect, writing the log information to the corresponding memory cache in a circular overwrite manner includes: when writing the log information in a circular overwrite manner, prioritizing the retention of log information with higher log levels.

[0012] In one implementation of the first aspect, the MCU main core runs an independent real-time operating system, the memory cache is a mutually isolated partition opened separately in the memory space, and the storage unit is set in the system-on-a-chip.

[0013] Secondly, the present invention provides an apparatus for managing multi-core logs. The apparatus includes: multiple memory caches, each allocated to a corresponding DSP core among multiple DSP cores, and configured to store log information generated by the corresponding DSP core among the multiple DSP cores; and an MCU main core, configured to collect log information from each memory cache corresponding to the multiple DSP cores, and to upload the collected log information to a storage unit for persistent storage.

[0014] According to embodiments of this disclosure, on the one hand, a dedicated memory cache is allocated to each DSP core, allowing each DSP core to operate within its own dedicated memory cache. Through physical isolation of memory space, this invention avoids write conflicts without a multi-core synchronization mechanism, resolving lock contention and bus congestion issues in traditional shared storage modes. This eliminates CPU time waste and latency caused by lock contention, ensuring the high efficiency of the log recording process. Simultaneously, since memory write speeds can reach nanosecond levels, compared to the microsecond to millisecond write latency of Flash, this invention effectively improves log write efficiency, ensuring that log writing does not affect the real-time performance of audio processing, such as preventing log operations from blocking audio frame processing. On the other hand, the MCU main core is dedicated to log collection and uploading, achieving task separation and ensuring that log tasks do not interfere with audio processing tasks. This prevents log operations from preempting DSP core computing resources, further guaranteeing the real-time performance of audio processing tasks. Attached Figure Description

[0015] Figure 1 This is a flowchart illustrating a method for managing multi-core logs according to an embodiment of the present disclosure.

[0016] Figure 2 This is a system architecture diagram illustrating a multi-core log management system according to an embodiment of the present disclosure.

[0017] Figure 3 This is a block diagram illustrating an apparatus for managing multi-core logs according to an embodiment of the present disclosure. Detailed Implementation

[0018] To explain in detail the technical content, objectives, and effects of the present invention, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0019] With the continuous development of in-vehicle audio technology, current mainstream technical solutions generally adopt Flash as the core carrier for log storage, forming a typical process of real-time acquisition—temporary storage—Flash persistence. The choice of Flash is mainly based on two reasons: first, to utilize its non-volatile characteristics to ensure that critical logs (such as audio decoding anomalies, multi-core synchronization errors, etc.) are not lost after the system is powered off; second, to leverage the storage density and cost advantages of Flash to meet the needs of small-capacity, high-reliability storage in in-vehicle scenarios.

[0020] However, the above-mentioned technical solutions have the following obvious drawbacks: First, Flash memory has a fixed erase / write lifespan (e.g., approximately 10,000 to 100,000 cycles for MLC Flash), while the multi-core system of the in-vehicle audio DSP needs to continuously record logs, and frequent writing will accelerate the wear and tear of the storage medium. Existing solutions lack differentiated writing strategies based on log priority, writing ordinary operation logs and fault-critical logs to Flash indiscriminately, which wastes the erase / write lifespan and may also cause Flash to fail prematurely, affecting the long-term reliability of the system. Second, Flash writing requires an erase-programming process, and the latency of a single write is usually in the microsecond to millisecond range, which conflicts with the high real-time requirements of the in-vehicle audio DSP. If the main core writes logs to Flash in batches during peak audio processing periods, it may consume DSP computing power or bus bandwidth, causing delays in core tasks such as audio decoding and sound effect rendering, resulting in audio stuttering or distortion. Although some solutions use memory temporary storage + timed synchronization to alleviate this, if the synchronization period is not set reasonably, log accumulation and loss or insufficient real-time performance may still occur.

[0021] To address at least the aforementioned technical problems, this disclosure provides a method for managing multi-core logs. According to this disclosure, on the one hand, a dedicated memory cache is allocated to each DSP core, allowing each DSP core to operate within its own dedicated memory cache. Through physical isolation of memory space, this invention avoids write conflicts without a multi-core synchronization mechanism, resolving lock contention and bus congestion issues in traditional shared memory models. This eliminates CPU time waste and latency caused by lock contention, ensuring the high efficiency of the log recording process. Simultaneously, since memory write speeds can reach nanosecond levels, compared to the microsecond to millisecond write latency of Flash, this invention effectively improves log write efficiency, ensuring that log writing does not affect the real-time performance of audio processing, such as preventing log operations from blocking audio frame processing. On the other hand, the MCU main core is dedicated to log collection and uploading, achieving task separation and ensuring that log tasks do not interfere with audio processing tasks (such as audio frame processing and sound effect rendering), preventing log operations from preempting DSP core computing resources, and further ensuring the real-time performance of audio processing tasks.

[0022] In the following, the technical solutions according to this disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0023] Figure 1 This is a flowchart illustrating a method 100 for managing multi-core logs according to an embodiment of the present disclosure. (Refer to...) Figure 1 The method 100 includes the following steps 102 to 104.

[0024] Step 102: The log information generated by multiple DSP cores is written into the corresponding memory cache area, and each DSP core is allocated its own memory cache area.

[0025] The DSP (Digital Signal Processor) core refers to the core of a digital signal processor, which is a computing unit in the chip dedicated to executing audio digital signal processing algorithms (such as decoding, sound effect rendering, mixing, etc.).

[0026] The memory cache refers to a contiguous storage area pre-allocated from the system memory address space and exclusively used by a specific DSP core. It should be noted that the memory cache of any DSP core is physically isolated from the memory caches of other cores. The memory cache is read and written only by its own DSP core and is used to temporarily cache log information generated by that DSP core. In practical applications, the partition size of the memory cache is 1K-10K. Due to the limited hardware resources and the need for long-term stable operation in automotive environments, a lightweight and efficient local cache can be achieved by using small-capacity dynamic adaptation (i.e., configurable from 1K-10K) to avoid wasting memory resources.

[0027] The log information is a record of the operating status generated by the DSP core during audio processing. Logs can be classified into different levels from high to low, such as error level, warning level, information level, and debug level. No specific level is specified here.

[0028] Step 104: Collect log information from the memory caches corresponding to the multiple DSP cores through the MCU main core.

[0029] The MCU (Microcontroller Unit) core is a dedicated MCU processor used for log management. It does not participate in audio data processing tasks but is solely responsible for coordinating the collection, aggregation, and uploading of logs from various DSP cores. This prevents log tasks and audio algorithms from competing for core computing power, and centralized scheduling ensures an orderly and efficient log uploading process. In practical applications, this MCU core typically runs an RTOS (Real-Time Operating System) to leverage its lightweight characteristics and improve log management response efficiency.

[0030] Step 106: The collected log information is uploaded to the storage unit for persistent storage through the MCU main core.

[0031] The storage unit refers to a non-volatile storage module located in a SOC (System on Chip) or an external MCU, used to receive and save log data uploaded from the MCU main core, realizing non-local retention and long-term traceability of log information.

[0032] In some embodiments, uploading collected log information to a storage unit for persistent storage via the MCU main core includes: determining the log level of the collected log information; determining an upload strategy for the log information based on the log level; and uploading the log information to the storage unit for persistent storage according to the upload strategy. It should be noted that precise control is required when performing hierarchical uploading according to the upload strategy, such as prioritizing the uploading of critical logs like errors and warnings, reducing unnecessary data transmission, and ensuring that abnormal information (such as audio decoding errors or multi-core synchronization failures) is captured and uploaded to the storage unit immediately, thus facilitating rapid fault location.

[0033] The log level refers to a classification identifier of the importance of log information. In practical applications, the log level can be divided into two main categories: critical logs (i.e., high-level logs) and non-critical logs (i.e., low-level logs). Critical logs are used to record important fault events that affect the normal operation of the system, such as audio decoding anomalies, multi-core synchronization failures, and clock loss. These logs may include multiple levels of log information, such as error level and warning level. Non-critical logs are used to record ordinary events that do not affect system stability, such as normal operating status and algorithm initialization. These logs may include multiple levels of log information, such as information level and debug level.

[0034] The upload strategy is the timing and method of log upload determined by the MCU main core based on the log level. It may include different upload schemes such as immediate upload, periodic batch upload, or delayed upload.

[0035] As described above, by classifying log information into different levels and formulating differentiated upload strategies accordingly, we can achieve differentiated treatment and refined traffic management of massive log data.

[0036] In some embodiments, determining the upload strategy for the log information based on the log level includes: if the log level is a critical log, then determining that the upload strategy is immediate upload; if the log level is a non-critical log, then determining that the upload strategy is periodic batch upload or delayed upload.

[0037] The instant upload refers to the transmission mechanism that, when the DSP core generates a critical log, immediately triggers the MCU main core through an inter-core interrupt, causing it to pause its current task and prioritize uploading the log information to the storage unit.

[0038] The periodic batch upload refers to the strategy of the MCU main core actively polling the memory cache of each DSP core at fixed time intervals (such as 500ms) to package the collected log information into a single data packet and upload it uniformly.

[0039] The delayed upload refers to a strategy that postpones the collection and upload of log information to a period when system resources are sufficient during peak audio processing periods or when the system load is heavy, in order to avoid interfering with real-time audio tasks.

[0040] As described above, differentiated upload strategies are assigned to log information of different levels to ensure timely responses to high-level logs, while batch aggregating low-level logs effectively reduces the communication frequency with storage units. This minimizes system bus occupancy and data transmission overhead while ensuring timely fault detection, reducing interference from frequent interruptions to real-time tasks such as audio rendering. Specifically, the immediate upload strategy for critical logs enables system anomalies to be captured and reported quickly in real time, significantly shortening the fault location cycle; the periodic batch or delayed upload of non-critical logs uses a time diversity mechanism to aggregate scattered logs into data packets, reducing the number of communication interactions.

[0041] In some embodiments, collecting log information from memory buffers corresponding to the plurality of DSP cores via the MCU master core includes: sending an inter-core interrupt to the MCU master core after log information of the critical log level is generated by any DSP core; and suspending the current task by the MCU master core so as to prioritize collecting log information from the memory buffer corresponding to the DSP core that sent the inter-core interrupt.

[0042] The inter-core interrupt refers to the hardware interrupt signal sent by the DSP core to the MCU main core after generating critical logs, which is used to trigger the immediate response of the MCU main core and realize the rapid collection of high-priority logs.

[0043] As described above, when the DSP core generates error-level log information, it sends an inter-core interrupt to the MCU main core. The MCU main core then pauses its current task to prioritize the collection of critical log information, effectively reducing the delay in the discovery and collection of critical logs.

[0044] In some embodiments, uploading the log information to the storage unit for persistent storage according to the upload strategy includes: polling the memory cache of each DSP core at a preset period through the MCU main core to collect log information with a log level of non-critical logs; and packaging the collected log information with a log level of non-critical logs into a single data packet and uploading the single data packet to the storage unit.

[0045] As described above, using periodic polling and packet uploading to process non-critical logs merges multiple log entries into a single data packet, reducing bus occupancy time and communication interface call overhead, thereby maintaining the continuity of the non-critical log stream at a lower communication cost.

[0046] In some embodiments, uploading the collected log information to the storage unit for persistent storage via the MCU main core includes: determining the current audio processing load state and adjusting the preset period according to the audio processing load state.

[0047] The audio processing load status refers to the measure of the busyness of the DSP core group when executing core audio processing tasks. It can be determined by a combination of indicators such as CPU utilization and memory bandwidth utilization, and is used to reflect the level of real-time load pressure of the system.

[0048] In practical applications, when the audio processing load reaches a preset high load threshold, the MCU main core can extend the interval for periodically collecting the non-critical log information (i.e., extend the preset period). When the audio processing load is less than a preset low load threshold, the MCU main core can shorten the interval for periodically collecting the non-critical log information (i.e., shorten the preset period).

[0049] As described above, the preset period for log collection is dynamically adjusted based on the audio processing load, thereby reducing the frequency of log management activities during peak business periods, avoiding competition with core audio tasks for system bus and CPU resources, and further ensuring the real-time performance of audio processing.

[0050] In some embodiments, writing log information generated by multiple DSP cores into the corresponding memory caches includes: when a DSP core generates the log information, writing the log information into the corresponding memory caches in a cyclic overwrite manner.

[0051] The circular overwrite strategy is a data writing management strategy for a fixed-size buffer. When the memory buffer is full, new data will overwrite the oldest data. This strategy ensures that the buffer can always be written with the latest data without the need for additional space allocation operations.

[0052] As described above, the circular overwrite mechanism resolves the contradiction between limited memory space and continuous log generation, enabling the memory buffer to continuously record logs without worrying about overflow, and ensuring that there is always space available for new logs to be written.

[0053] In some embodiments, writing the log information to the corresponding memory cache in a circular overwrite manner includes: when writing the log information in a circular overwrite manner, prioritizing the retention of log information with higher log levels.

[0054] As described above, when the memory cache is full, lower-level logs are overwritten first, thereby increasing the lifespan of high-value critical logs and reducing the risk of important information being accidentally lost during the caching process.

[0055] In some embodiments, the MCU main core runs an independent real-time operating system, the memory cache is a mutually isolated partition opened separately in the memory space, and the storage unit is located within the system-on-a-chip.

[0056] As described above, the MCU main core runs an independent real-time operating system, ensuring that log management and audio processing do not interfere with each other; the memory partitions are isolated from each other, enabling lock-free log writing; and the storage unit is integrated into the system-on-a-chip, facilitating direct interface with vehicle diagnostic systems and other devices.

[0057] In summary, this invention proposes an optimized scheme based on memory caching and hierarchical uploading for multi-core log management scenarios of automotive audio DSP chips, aiming to circumvent the inherent defects of traditional Flash storage in terms of erase / write lifespan, media wear, and write latency. The core concept of this invention lies in replacing Flash with high-speed memory as the log cache carrier. Through a distributed storage architecture and dedicated management mechanism, it balances the real-time performance, integrity, and system resource efficiency of multi-core logs, as specifically configured below.

[0058] First, this invention adopts a master core overall management mechanism: designating an MCU master core independent of the audio data processing logic as the master core for multi-core log management. This MCU master core runs an RTOS system and is dedicated to coordinating the caching and uploading process of logs from each DSP core, thereby replacing the traditional storage mode that relies on Flash and avoiding log tasks and audio algorithms competing for core computing power.

[0059] Secondly, regarding the storage architecture, a distributed memory cache design is adopted: each DSP core is allocated a dedicated memory cache area, and the size of the memory cache area can be dynamically configured from 1KB to 10KB according to the log output characteristics. After the log information is generated, it is written to the memory cache area of ​​its own core in real time in a circular overwrite manner. Moreover, since the memory cache areas of multiple cores are physically isolated from each other, the log writing process can avoid conflicts without the need for a synchronization mechanism, and the nanosecond-level high-speed characteristics of memory operations ensure that log recording does not affect the real-time performance of audio processing.

[0060] Furthermore, regarding log flow, a centralized upload strategy combined with a hierarchical priority mechanism is adopted: the MCU main core uniformly schedules and periodically or on demand collects log information from each core cache, aggregates it, and uploads it to the SOC or external MCU for persistent storage, achieving non-local retention of log data. Simultaneously, this invention also employs a hierarchical priority mechanism to classify log information by level, prioritizing immediate uploads for critical logs such as errors and warnings, while non-critical logs can be uploaded with delays or in batches, reducing data transmission volume while ensuring timely capture of important information.

[0061] To make the present invention easier to understand, an exemplary application is provided below. This exemplary application uses a vehicle audio system equipped with a DSP chip as an example. The vehicle audio system includes an MCU main core that serves as the log management main core and three DSP cores (DSP0, DSP1, and DSP2) responsible for audio processing. DSP0 core is mainly responsible for audio driving and sound effect processing, while DSP1 and DSP2 cores are responsible for sound effect processing. During the operation of the vehicle audio system, each DSP core continuously generates log information at various log levels.

[0062] (1) Initialization phase Each DSP core has its own memory cache: DSP0 core has a 10KB memory cache for storing audio driver and sound effect related log information; DSP1 and DSP2 cores each have a 2KB memory cache for storing sound effect processing log information. In addition, the MCU main core can also allocate a 10KB circular buffer to store its operation logs.

[0063] (2) Operation phase First, each DSP core generates corresponding log information during operation. For example, when the DSP0 core detects an external clock loss, it immediately generates an error-level log message (e.g., Sai0 rx fs error); the DSP1 core generates an information-level log message (e.g., Eq init error) when initializing the equalizer; and the DSP2 core generates a warning-level log message (e.g., Memory buffer usage 85%) when it detects that the buffer usage rate has reached 85%.

[0064] Secondly, each DSP core writes the generated log information to its corresponding memory buffer at millisecond speeds, employing a circular overwrite strategy during the writing process.

[0065] Furthermore, the MCU master core schedules the upload of log information from the buffer according to priority. On one hand, for critical logs such as errors (e.g., clock errors on the DSP0 core), after the critical log is generated, the DSP core immediately triggers the MCU master core to respond via an inter-core interrupt; the MCU master core suspends its current task, prioritizes reading the error log, and checks whether other cores have high-priority logs, then packages and uploads them to the SOC for storage, ensuring that critical issues are recorded in a timely manner. On the other hand, for non-critical logs such as those at the debug level, the MCU master core periodically polls the memory buffers of each core every 500ms, collects them in batches, packages them, and uploads them to the SOC for storage via the SPI / UART interface to reduce communication overhead.

[0066] In addition, the present invention can also deploy corresponding resource optimization strategies: when the memory buffer is full, new non-critical logs can overwrite the oldest non-critical logs, but the system will retain recent high-level (such as warning / error) logs; at the same time, during peak audio processing periods, the MCU main core can automatically extend the log information collection interval, such as extending it to 1 second, to reduce bus occupancy.

[0067] In summary, compared to traditional solutions that directly write all log information to Flash (i.e., each write takes 10-50ms, affecting real-time performance, and frequent writes shorten Flash lifespan), this invention combines memory caching with tiered uploading, achieving a write time of <1μs and a critical log upload latency of <20ms. This ensures the timeliness of critical log collection while completely eliminating the impact of log operations on Flash lifespan, achieving an effective balance between system real-time performance, reliability, and resource efficiency.

[0068] Figure 2 This is a system architecture diagram illustrating a multi-core log management system according to an embodiment of the present disclosure. (Refer to...) Figure 2 The multi-core log management system includes multiple DSP cores for audio processing (e.g., DSP0 core, DSP1 core, DSP2 core), memory, MCU main core, and storage units (e.g., SOC). The memory includes the memory cache area (i.e., log cache area) corresponding to each DSP core.

[0069] Each DSP core has its own dedicated memory cache for real-time caching of log information generated during its operation. This memory cache uses a circular overwrite structure and can be categorized and stored according to log level (e.g., errors, warnings, debug). Log write operations for each DSP core are completed within their respective memory caches, eliminating the need for cross-core synchronization and thus avoiding multi-core write conflicts and bus contention.

[0070] The MCU main core runs an independent real-time operating system, which is responsible for coordinating and managing the log upload process of each DSP core. It does not participate in audio data processing, but is dedicated to performing log collection, packaging and scheduling tasks.

[0071] The storage unit (e.g., SOC) serves as the final persistent storage destination for log information, receiving log data packets aggregated and uploaded by the MCU main core, thus enabling long-term log storage and integration with upper-layer diagnostic systems or cloud platforms.

[0072] In practical applications, each DSP core writes the generated log information to its own memory cache in real time. The MCU main core collects log information from each memory cache according to a preset strategy (such as event triggering or periodic polling), and after aggregation and priority filtering, uploads it to the SOC through a communication interface (such as SPI / UART). Based on this distributed caching-centralized management-hierarchical upload architecture, the integrity and real-time performance of logs are ensured, while effectively avoiding the lifespan and latency issues caused by Flash storage in traditional solutions.

[0073] Figure 3 This is a block diagram illustrating an apparatus 200 for managing multi-core logs according to an embodiment of the present invention. (Refer to...) Figure 3 The device 200 includes multiple memory caches 210 and an MCU main core 220.

[0074] Multiple memory caches 210 are respectively allocated to corresponding DSP cores in multiple DSP cores, and the multiple memory caches 210 are configured to store log information generated by corresponding DSP cores in multiple DSP cores respectively.

[0075] The MCU main core 220 is configured to collect log information from each memory cache corresponding to the plurality of DSP cores, and to upload the collected log information to the storage unit for persistent storage.

[0076] It should be understood that the plurality of memory caches 210 and the MCU main core 220 can be further configured to perform the corresponding steps or actions in the method for managing multi-core logs described in the above embodiments, which will not be repeated here.

[0077] In summary, according to the method and apparatus for managing multi-core logs provided by the present invention, (1) in terms of storage medium, the present invention innovatively proposes a multi-core log storage architecture based on memory replacing Flash. Addressing the inherent lifespan loss and write latency issues of traditional Flash storage, the present invention allocates an independent 1KB-10KB memory cache area as a log cache for each DSP core. After log information is generated, it is directly written to the corresponding memory cache area without relying on Flash storage throughout the process. Simultaneously, by leveraging the physical isolation characteristics of memory space, multi-core log write conflicts are naturally avoided, eliminating the need for additional synchronization lock mechanisms, thereby solving the lock contention and bus congestion problems in the traditional shared storage mode. Furthermore, due to the nanosecond-level operation speed of memory, the impact of Flash erase / programming latency on audio real-time performance is completely eliminated, ensuring zero interference during the log recording process.

[0078] (2) Regarding the multi-core collaborative architecture and task division, this invention breaks through the traditional hybrid mode of the main core taking into account both business and log processing, and innovatively designs a dedicated log management mechanism for the MCU main core. The MCU main core running the RTOS system and not participating in audio data processing is designated as the log main core, which is dedicated to uniformly collecting the memory cache logs of each DSP core and scheduling the upload process. By completely separating audio processing and log management tasks, it effectively avoids log operations (such as summarization and upload) from occupying the DSP core computing power, ensuring that core businesses such as audio frame processing and sound effect rendering are not affected by performance. At the same time, the lightweight characteristics of RTOS are used to significantly improve the response efficiency and determinism of log management.

[0079] (3) Regarding data flow strategy, this invention proposes a differentiated processing mechanism of hierarchical priority and on-demand upload. Addressing the bandwidth waste and critical information overload issues caused by traditional full uploads, log information is classified according to importance (e.g., errors > warnings > information > debugging). Only critical logs such as errors and warnings are prioritized for upload, while non-critical logs are uploaded with delay or in batches. The MCU main core dynamically schedules upload timing based on log level, uploading immediately in case of anomalies and periodically in batches during normal times. This reduces the frequency of interaction with the SOC, lowers data transmission bandwidth usage, and ensures that fault information is not lost, meeting the stringent requirements for rapid fault location in automotive scenarios.

[0080] (4) In terms of log lifecycle management, this invention adapts to the characteristics of limited hardware resources in the vehicle environment and the need for long-term stable operation. It innovatively designs a lightweight caching + remote retention management scheme. The memory cache adopts a small capacity dynamic adaptation strategy (i.e., 1KB-10KB configurable) to avoid wasting memory resources. The log information is finally persistently stored in the SOC instead of local Flash, which not only achieves non-volatile retention of logs, but also facilitates the connection with the vehicle diagnostic system and cloud platform, supports remote log analysis and system health monitoring, and fully adapts to the development trend of intelligent vehicle operation and maintenance.

[0081] (5) This invention adopts an architecture of memory caching + dedicated management by the MCU main core, so that log operations have no performance interference with the audio processing logic of the DSP core (such as sound effect rendering and multi-channel mixing), ensuring the smoothness of audio output (no stuttering or distortion) and achieving zero performance interference. At the same time, the log information is finally stored in the storage unit such as SOC or external MCU, which facilitates the connection with the vehicle diagnostic system and cloud monitoring platform, supports remote log analysis and fault diagnosis, and has good system scalability, which is in line with the development trend of vehicle intelligence.

[0082] In summary, this invention, through the rational division of hardware resources (i.e., dedicated management by the MCU main core), the optimized selection of storage media (i.e., memory replacing Flash), and the refined design of data flow (i.e., hierarchical uploading), ensures the integrity of the in-vehicle audio DSP multi-core system logs while maximizing the avoidance of the defects of traditional storage solutions, and takes into account system reliability, real-time performance, and ease of operation and maintenance.

[0083] The above description is merely an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent modifications made based on the content of the present invention specification and drawings, or direct or indirect applications in related technical fields, are similarly included within the patent protection scope of the present invention.

Claims

1. A method for managing multi-core logs, characterized in that, include: Log information generated by multiple DSP cores is written to their respective memory caches, with each DSP core having its own dedicated memory cache. Log information is collected from the memory caches corresponding to the multiple DSP cores by the MCU main core; as well as The collected log information is uploaded to the storage unit for persistent storage via the MCU main core.

2. The method according to claim 1, characterized in that, The collected log information is uploaded to the storage unit for persistent storage via the MCU main core, including: Determine the log level of the collected log information, and determine the upload strategy for the log information based on the log level; and The log information is uploaded to the storage unit for persistent storage according to the upload strategy.

3. The method according to claim 2, characterized in that, Determining the log information upload strategy based on the log level includes: If the log level is critical, then the upload strategy is determined to be immediate upload; If the log level is non-critical, then the upload strategy is determined to be periodic batch upload or delayed upload.

4. The method according to claim 3, characterized in that, Log information is collected from the memory caches corresponding to the multiple DSP cores via the MCU main core, including: After any DSP core generates log information at the critical log level, an inter-core interrupt is sent to the MCU main core; and The MCU main core pauses the current task in order to prioritize collecting log information from the memory buffer corresponding to the DSP core that sent the inter-core interrupt.

5. The method according to claim 3, characterized in that, Uploading the log information to the storage unit for persistent storage according to the upload strategy includes: The MCU main core polls the memory cache of each DSP core at a preset period to collect log information of the non-critical log level; and The collected log information at the non-critical log level is packaged into a single data packet, and the single data packet is uploaded to the storage unit.

6. The method according to claim 5, characterized in that, The collected log information is uploaded to the storage unit for persistent storage via the MCU main core, including: Determine the current audio processing load status and adjust the preset cycle according to the audio processing load status.

7. The method according to claim 1, characterized in that, Writing the log information generated by multiple DSP cores into their respective memory caches includes: When the DSP core generates the log information, it writes the log information to the corresponding memory cache in a cyclic overwrite manner.

8. The method according to claim 7, characterized in that, Writing the log information to the corresponding memory cache in a circular overwrite manner includes: When writing the log information in a circular overwrite manner, log information with higher log levels is retained first.

9. The method according to claim 1, characterized in that, The MCU main core runs an independent real-time operating system, the memory cache is a separate, isolated partition in the memory space, and the storage unit is located within the system-on-a-chip.

10. An apparatus for managing multi-core logs, characterized in that, include: Multiple memory caches are allocated to corresponding DSP cores in multiple DSP cores and configured to store log information generated by the corresponding DSP cores in multiple DSP cores respectively; as well as The MCU main core is configured to collect log information from each memory cache corresponding to the plurality of DSP cores, and to upload the collected log information to the storage unit for persistent storage.

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