Method, device and program product for generating an embedded register header file

Abstract

The present disclosure provides a method, device and program product for generating an embedded register header file, the method comprising: pre-storing each source data file in a specified directory; the source data file comprising an SVD generation script, an SVD file of a processor core, a register table, and a conversion tool SVDConv; running a main control script; executing an SVD generation command in a command line mode, calling the SVD generation script, reading in the SVD file of the processor core, reading in the register table, and generating an embedded SVD file according to the SVD format; and executing a header file generation command in the command line mode, calling the conversion tool SVDConv to convert the embedded SVD file to generate an embedded register header file. The present disclosure has high automation, simple operation, high efficiency, clear structure, and is convenient for user modification through error prompts; has high accuracy, is verified through a register test program; is simple to maintain, is convenient for iteration, and reduces manual errors and workload.

Description

Technical Field

[0001] This disclosure relates to the field of digital integrated circuit technology, and in particular to a method, device and program product for generating embedded register header files. Background Technology

[0002] Currently, in the verification phase of System-on-a-Chip (SoC) and the development phase after tape-out, when writing test cases in C language to verify chip functionality, a corresponding register header file is required. The register header file plays a core role in SoC verification and subsequent development, defining peripheral registers, system controls, macro definitions, and other information within the chip, enabling verification personnel or developers to efficiently configure and operate various peripheral functions. Traditionally, generating register header files requires testers to first write the chip's System View Description (SVD) file based on the register table, and then use ARM's (Advanced RISC Machines) SVDConv conversion tool to convert the SVD file into the corresponding register header file. Typically, the SVD file contains information about the chip's processor cores, peripheral register layout, and functionality, resulting in cumbersome and large-scale code. Nowadays, the types and functions of chip peripherals are becoming increasingly diverse, chip development processes are closely linked, and development cycles are becoming shorter and shorter. As a result, the task of testers to write SVD files based on register table information has become extremely arduous. Furthermore, if there are significant changes in design requirements during chip development, repeated manual maintenance and updates are required, which is prone to errors and inefficient. Testers spend a lot of time on simple but tedious tasks, which seriously affects the progress of chip development. Summary of the Invention

[0003] The technical problem to be solved by this disclosure is the aforementioned deficiency in the prior art, and a method, device and program product for generating embedded register header files are provided.

[0004] This disclosure solves the above-mentioned technical problems through the following technical solution:

[0005] This disclosure provides a method for generating an embedded register header file, the method comprising:

[0006] Each source data file is pre-stored in a specified directory; wherein, the source data files include SVD generation scripts, processor core SVD files, register tables, and the conversion tool SVDConv;

[0007] Run the main control script;

[0008] Execute the SVD generation command in command line mode, call the SVD generation script, read in the SVD file of the processor core, read in the register table, and generate an embedded SVD file according to the SVD format;

[0009] Execute the header file generation command in command line mode to call the conversion tool SVDConv to convert the embedded SVD file into the embedded register header file.

[0010] Optionally, the source data file may further include a test program generation script and example program units corresponding to each peripheral device;

[0011] The generation method further includes:

[0012] In command-line mode, execute the register test program generation command, call the test program generation script, read the register table, read the corresponding example program units in the order of the peripherals in the register table, fill in the corresponding parameters in the example program units according to the data in the register table, and merge the example program units with the parameters filled in into a register test program.

[0013] Perform SoC simulation testing, including the embedded register header file, and run the register test program to perform read and write scan tests on all peripherals to test whether the register information in the register table is completely consistent with the SoC RTL code.

[0014] Optionally, the generation method further includes:

[0015] During the process of generating the embedded SVD file, in response to format or syntax errors in the register table, the SVD generation script outputs the location of the error after execution. The error is corrected according to the location of the error, and the process jumps to the "Execute SVD generation command in command line mode" step to regenerate the embedded SVD file.

[0016] During the conversion process of generating the embedded register header file, in response to a syntax error in the contents of the register table, the conversion tool SVDConv outputs an error message after execution. The error is corrected according to the error message, and the process jumps to the "Execute SVD generation command in command line mode" step to regenerate the embedded SVD file.

[0017] Optionally, the generation method further includes:

[0018] In response to an error message that appears after the SoC simulation test is completed, the error message should be corrected according to the simulation test error message. The process should then proceed to the step of "Execute SVD generation command in command line mode" to regenerate the embedded SVD file.

[0019] Optionally, the step of executing the SVD generation command in command-line mode, calling the SVD generation script, reading the SVD file of the processor core, reading the register table, and generating an embedded SVD file according to the SVD format includes:

[0020] In command-line mode, the SVD generation command is executed. The SVD generation script reads the corresponding controller core SVD file from the core_svd_lib directory according to the configuration parameters passed by the main control script, replaces the corresponding fields in the controller core SVD file in sequence according to the configuration parameters, and writes them into the target SVD file as the start segment of the embedded SVD file to be generated.

[0021] Read the register table from the reglist directory;

[0022] For the peripheral overview table in the register table, store all peripheral information into the corresponding arrays column by column from top to bottom and left to right;

[0023] For each peripheral device, a first SVD file code is generated based on the SVD format to start the current peripheral device, and written into the corresponding segment of the embedded SVD file to be generated; the register information of the current peripheral device is read and element preprocessed, and the preprocessed register information is pushed into the corresponding array of the current peripheral device; the element information of each register of the current peripheral device is extracted, a second SVD file code is generated based on a preset format, and written into the corresponding segment of the embedded SVD file to be generated.

[0024] Optionally, the reading and element preprocessing of the register information of the current peripheral device includes:

[0025] When the SVD generation script performs a scan and read operation on the current peripheral device, it obtains and records the column numbers of each category item other than the Wen column in the header from left to right.

[0026] Scan all register information except for the Wen column from top to bottom and from left to right. For each cell, check if there are any illegal characters in the current cell. If there are illegal characters in the current cell, record the error. If there are no illegal characters in the current cell, replace the column elements that do not conform to the register SVD format requirements to make the column elements conform to the register SVD format requirements.

[0027] Optionally, the step of extracting element information from each register of the current peripheral device, generating second SVD file code based on a preset format, and writing it into the corresponding segment of the embedded SVD file to be generated includes:

[0028] Traverse the reg_name array that stores all register names, find the valid elements of the non-empty cells in the reg_name array, record the index of the valid elements and store them in the reg_index array, until the reg_name array is traversed to the last element, then increment the index by 1 and store it in the reg_index array;

[0029] The reg_index array is traversed to generate SVD files for each register of the current peripheral in turn. When $i=0, the elements with indices 0 and 1 are taken from the reg_index array as the start index and end index, respectively.

[0030] The register element information is extracted from the reg_name array, reg_descrip array, offset array, width array, access array, rst_val array and mask array of the current peripheral device to generate the first sub-SVD file code based on the first preset format, and written into the corresponding segment of the embedded SVD file to be generated;

[0031] Using the start index and "end index - 1" as the boundaries of the array, extract the data of all fields of a register block from the field array, field_width array, rw_type array, default_val array, field_descrip array, enum_name array, enum_descrip array, and enum_val array of the current peripheral, and store them into the new field_tmp array, field_width_tmp array, rw_type_tmp array, default_val_tmp array, field_descrip_tmp array, enum_name_tmp array, enum_descrip_tmp array, and enum_val_tmp array respectively;

[0032] For the field_tmp array, SVD files for each field of the current register are generated sequentially. The field_width_tmp array, the rw_type_tmp array, the default_val_tmp array, the field_descrip_tmp array, the enum_name_tmp array, the enum_descrip_tmp array, and the enum_val_tmp array are extracted from bottom to top and stored in the field_final, field_width_final, rw_type_final, default_val_final, field_descrip_final, enum_name_final, enum_descrip_final, and enum_val_final variables respectively. The code for the second sub-SVD file is generated based on the second preset format and written to the corresponding segment of the embedded SVD file to be generated.

[0033] In response to the presence of a valid character in the `enum_name_final` variable, the `split` function is used to split the contents of the `enum_name_final`, `enum_descrip_final`, and `enum_val_final` variables using " / " as the delimiter, and store them respectively in the `enum_name_tmp1`, `enum_descrip_tmp1`, and `enum_val_tmp1` arrays. Simultaneously, the `enum_name_tmp1`, `enum_descrip_tmp1`, and `enum_val_tmp1` arrays are traversed, and one element is retrieved at a time to generate a third sub-SVD file code based on a third preset format. This code is then written to the corresponding segment of the embedded SVD file to be generated, thus completing the generation of the SVD file for the current field of the current register. In response to the presence of a valid character in the `enum_name_final` variable, the generation of the SVD file for the current field of the current register is also completed.

[0034] Optionally, the step of executing the register test program generation command in command-line mode, calling the test program generation script, reading the register table, sequentially reading the corresponding example program units according to the order of the peripherals in the register table, filling in the corresponding parameters in the example program units according to the data in the register table, and merging the example program units with filled parameters into a register test program includes:

[0035] In command-line mode, the register test program generation command is executed. The test program generation script reads the corresponding register table from the reglist directory according to the register table path information passed by the main control script, reads the Module column of the peripheral overview table in the register table, and stores all peripheral names into the module array.

[0036] Each element of the module array is read sequentially. After matching an example program unit with the same name as each element of the module array, it is read into and written into the register test program; wherein, one element of the module array represents a peripheral device.

[0037] For each element of the module array, read the register information of the current peripheral in the register table, obtain the column numbers of the Register column, Reset_Val column, Mask column, and Wen column from left to right, and store the data of the Register column, Reset_Val column, Mask column, and Wen column into the register array, reset_val array, mask array, and Wen array respectively, from top to bottom and from left to right.

[0038] Iterate through the register array, reset_val array, mask array, and wen array of the current peripheral device, extract the element corresponding to each register in the register array, reset_val array, mask array, and wen array, generate test entries for each register in sequence according to the format of the predefined register read and write test function, and write them into the register test program.

[0039] This disclosure also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and used to run on the processor, wherein the processor executes the computer program to implement the aforementioned method for generating an embedded register header file.

[0040] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the aforementioned method for generating embedded register header files.

[0041] Based on common knowledge in the field, the above-mentioned preferred conditions can be combined arbitrarily to obtain various preferred embodiments of this disclosure.

[0042] The positive improvements of this disclosure are as follows: The method for generating embedded register header files is highly automated, simple to operate, efficient, and has a clear structural hierarchy. Users only need to place a table (Excel) of all peripheral registers in the current chip, filled in according to a given format, in the reglist directory, and configure the required project name, processor core parameters, and other parameters in the main control script. Then, they can use the gen_svd and gen_headfile commands sequentially in command-line mode to generate the SVD file and register header file. Furthermore, the SVD generation script can print details and locations of format and syntax errors in the register table after execution, facilitating user correction. The generated header file is also highly accurate. The gen_testc command in command-line mode generates a register test program to verify whether the register information in the register table is completely consistent with the SoC RTL code. Simultaneously, the generated header file is easy to maintain and iterate upon. Subsequent iterations only require updating a single register table, effectively reducing errors and workload caused by manual coding. Attached Figure Description

[0043] Figure 1 A flowchart illustrating a method for generating an embedded register header file as provided in Embodiment 1 of this disclosure;

[0044] Figure 2 A flowchart illustrating the generation and testing of an embedded register header file, as provided in Embodiment 1 of this disclosure;

[0045] Figure 3 A flowchart illustrating a specific implementation of a method for generating an embedded register header file as provided in Embodiment 1 of this disclosure;

[0046] Figure 4 A flowchart illustrating another specific implementation of a method for generating an embedded register header file provided in Embodiment 1 of this disclosure;

[0047] Figure 5 A flowchart illustrating a specific implementation of step S13 of a method for generating an embedded register header file provided in Embodiment 1 of this disclosure;

[0048] Figure 6 A flowchart illustrating the SVD generation script for an embedded register header file generation method provided in Embodiment 1 of this disclosure;

[0049] Figure 7 A flowchart illustrating a specific implementation of step S134 of an embedded register header file generation method provided in Embodiment 1 of this disclosure;

[0050] Figure 8 A flowchart illustrating register reading and element preprocessing in an embedded register header file generation method provided in Embodiment 1 of this disclosure;

[0051] Figure 9 A flowchart of another specific implementation of step S134 of the method for generating an embedded register header file provided in Embodiment 1 of this disclosure;

[0052] Figure 10 This is a flowchart illustrating the register array extraction and SVD generation method for an embedded register header file generation method provided in Embodiment 1 of this disclosure;

[0053] Figure 11 A flowchart illustrating a specific implementation of step S15 of a method for generating an embedded register header file according to Embodiment 1 of this disclosure;

[0054] Figure 12 A flowchart illustrating the register test program generation script of an embedded register header file generation method provided in Embodiment 1 of this disclosure;

[0055] Figure 13 This is a schematic diagram of the structure of an electronic device provided in Embodiment 2 of this disclosure. Detailed Implementation

[0056] The present disclosure is further illustrated below by way of embodiments, but the present disclosure is not limited to the scope of the embodiments described herein.

[0057] The prefixes such as "first" and "second" used in this disclosure are merely for distinguishing different descriptive objects and do not limit the position, order, priority, quantity, or content of the described objects. The use of ordinal numbers and other prefixes used to distinguish descriptive objects in this disclosure does not constitute a limitation on the described objects. The description of the described objects is given in the claims or the context of the embodiments, and should not be construed as an unnecessary limitation. Furthermore, in the description of this embodiment, unless otherwise stated, "multiple" means two or more.

[0058] Example 1

[0059] Figure 1 A flowchart illustrating an exemplary embodiment of this disclosure provides a method for generating an embedded register header file. The method includes:

[0060] S11. Pre-store each source data file in the specified directory. The source data files include the SVD generation script, the processor core's SVD file, the register table, and the conversion tool SVDConv.

[0061] S12, Run the main control script.

[0062] S13. Execute the SVD generation command in command line mode, call the SVD generation script, read the SVD file of the processor core, read the register table, and generate an embedded SVD file according to the SVD format.

[0063] S14. Execute the header file generation command in command line mode, and call the conversion tool SVDConv to convert the embedded SVD file into an embedded register header file.

[0064] Among them, the SVD file is an XML plain text file defined by the ARM standard. It is specifically used to describe in a machine-readable and complete manner all the hardware registers and peripheral memory mappings of an MCU (microcontroller unit) chip. It is equivalent to a digital and structured chip register manual.

[0065] The following is an example of a specified directory in this embodiment, using 7 specified directories.

[0066] (1) The processor core SVD file reference library (core_svd_lib) contains SVD files of ARMCORTEX-M (such as ARMCM3.svd, ARMCM4.svd) and other processor cores (such as OTHER.svd). When generating SVD files later, the SVD of the selected processor core is read first and the parameters are replaced, and then written to the beginning segment of the chip SVD file;

[0067] (2) Register test C program library (testc_lib) contains pre-written configuration programs for each peripheral (IP) (e.g., IPA_reg.c, ..., IPN_reg.c), which are used to enable the register read and write protection words of each peripheral in advance. When generating register test programs later, these programs will be supplemented and added to them.

[0068] (3) The tool directory contains the ARM SVDConv conversion tool, which can convert the SVD file generated earlier into the final register header file;

[0069] (4) Register table directory (reglist), which contains an Excel table of all peripheral registers in the current chip filled in according to a given format (e.g. example_reglist.xlsx).

[0070] (5) The script directory contains the generation script svd_gen.pl for generating SVD files from register table information and the generation script test_reg_gen.pl for generating C programs for register testing. It is the core module of this invention.

[0071] (6) Output directory contains the chip SVD file (such as example.svd), register header file (example.h) and register test program (test_reg.c) generated by the script.

[0072] (7) The main control script (gen.cmd) is the control panel for the entire generation process. After configuring the project name, processor core type and parameters here, the user can generate each file by issuing different commands (such as svd, headfile, testc).

[0073] Specifically, Figure 2 The process of generating and including tests for the register embedded header file is shown.

[0074] Before starting the generation process via the main control script, ensure that the configured project name (example in the example) and core-related information (core type, core component information) are correct, that the latest version of the chip's register table is stored in the reglist directory, and that the core_svd_lib contains the chip's processor core SVD file.

[0075] After running the main control script, execute the SVD generation command (gen_svd command) in command-line mode. The main control script (gen.cmd) will then call the SVD generation script (svd_gen.pl), sequentially reading the selected core SVD file and register table (example_reglist.xlsx), and then generating an embedded SVD file (example.svd) according to the SVD format. During this process, if there are format or syntax errors in the register table, the SVD generation script will print the specific location of the error after execution. The user needs to modify the corresponding content in the register table as required and then execute the gen_svd command again until there are no format or syntax error messages. Only when there are no format or syntax error messages can the header file generation command be executed to generate the embedded register header file.

[0076] Execute the header file generation command (gen_headfile) in command-line mode. The main control script will then call the conversion tool SVDConv to read the previously generated embedded SVD file (example.svd) and convert it into the corresponding embedded register header file (example.h). After execution, if syntax errors are detected, the user needs to modify the corresponding entries in the register table as required and then execute the gen_svd and gen_headfile commands sequentially until no syntax errors are detected. At this point, the format and syntax errors in the register table have been resolved.

[0077] In addition, to test whether the register information in the register table is completely consistent with that in the SoC RTL code, the register test program generation command (gen_testc command) can be executed in the command-line mode of the main control script. At this time, the main control script will call the register test program generation script (test_reg_gen.pl), read the register table, and sequentially read the corresponding programs under testc_lib (e.g., IPA_reg.c, IPB_reg.c) according to the IP order in the table. Then, it will add the corresponding IP's register read / write test programs to these programs. After all IPs have been traversed, a general register test program, test_reg.c, will be generated.

[0078] At this point, users can include the generated register header file (example.h) in their SoC simulation and run the generated register test program (test_reg.c) to verify that the register information in the register table is completely consistent with the SoC RTL code. If inconsistency errors occur in the SoC simulation results, the corresponding register contents in the register table need to be modified, and then the gen_svd, gen_headfile, and gen_testc commands need to be executed again until no more inconsistency error messages are printed. After all errors converge, the entire process of generating (including testing) the register embedded header file is complete.

[0079] In this embodiment, the method for generating embedded register header files disclosed herein boasts a high degree of automation, simplicity, efficiency, and a clear structural hierarchy. Users simply need to place a table (Excel) of all peripheral registers in the current chip, filled out according to a given format, into the `reglist` directory. After configuring the required project name, processor core parameters, and other parameters in the main control script, the `gen_svd` and `gen_headfile` commands can be used sequentially in command-line mode to generate the SVD file and register header file. Furthermore, the SVD generation script can print details and locations of formatting and syntax errors in the register table after execution, facilitating user correction. The generated header file also exhibits high accuracy. The `gen_testc` command in command-line mode generates a register test program to verify whether the register information in the register table is completely consistent with the SoC RTL code. Simultaneously, the generated header file is easy to maintain and iterate upon; subsequent iterations only require updating a single register table, effectively reducing errors and workload associated with manual coding.

[0080] In an optional embodiment, the source data file also includes a test program generation script and example program units corresponding to each peripheral.

[0081] Reference Figure 3 The generation method also includes:

[0082] S15. Execute the register test program generation command in command line mode, call the test program generation script, read the register table, read the corresponding example program units in the order of peripherals in the register table, fill in the corresponding parameters in the example program units according to the data in the register table, and merge the example program units with filled parameters into a register test program.

[0083] S16. Perform SoC simulation testing. Include the embedded register header file in the SoC simulation test and run the register test program to perform read and write scan tests on all peripherals to test whether the register information in the register table is completely consistent with the SoC RTL code.

[0084] To test whether the register information in the register table is completely consistent with the SoC RTL code, the register test program generation command (gen_testc command) needs to be executed in the command-line mode of the main control script. At this time, the main control script will call the register test program generation script (test_reg_gen.pl), read the register table, and sequentially read the corresponding example program units under testc_lib (e.g., IPA_reg.c, IPB_reg.c) according to the IP order in the table. Then, it adds the corresponding IP's register read / write test program to these example program units. After all IPs have been traversed, a general register test program, test_reg.c, will be generated.

[0085] At this point, users can include the generated register header file (example.h) in the SoC simulation and run the generated register test program (test_reg.c) to verify whether the register information in the register table is completely consistent with that in the SoC RTL code.

[0086] If inconsistencies occur in the SoC simulation results, the corresponding register contents in the register table need to be modified. Then, the `gen_svd`, `gen_headfile`, and `gen_testc` commands should be executed again until no more inconsistencies are printed. Once all errors have converged, the entire process of generating (including testing) the register embedded header file is complete.

[0087] This embodiment provides a specific implementation method for generating a register test program and testing the register header file using the register test program (test_reg.c) to verify whether the information of the registers in the register table is completely consistent with that in the SoC RTL code.

[0088] In an optional embodiment, refer to Figure 4 The generation methods also include:

[0089] S21. During the process of generating the embedded SVD file, in response to the presence of format or syntax errors in the register table, the SVD generation script outputs the location of the error after execution. Correct the error according to the location of the error and jump to step S13 to regenerate the embedded SVD file.

[0090] S22. During the process of generating the embedded register header file, in response to the syntax error in the register table, the conversion tool SVDConv outputs an error message after running. Correct the error according to the error message and jump to step S13 to regenerate the embedded SVD file.

[0091] During the process of generating the embedded SVD file using the SVD generation script (svd_gen.pl), if there are format or syntax errors in the register table, the script will print the specific location of the error after execution. The user needs to modify the corresponding content in the register table as required and then execute the gen_svd command again until there are no format or syntax error messages. Only when there are no format or syntax error messages can the header file generation command be executed to generate the embedded register header file.

[0092] During the process of converting embedded SVD files into embedded register header files, if the conversion tool SVDConv warns of syntax errors after it finishes running, the user needs to modify the corresponding content in the register table as required, and then execute the gen_svd and gen_headfile commands sequentially until no syntax errors are reported. At this point, the format and syntax errors in the register table have been resolved.

[0093] This embodiment provides handling operations for format and syntax errors that occur during the generation of embedded SVD files and during the conversion of embedded register header files.

[0094] In an optional embodiment, the generation method further includes:

[0095] In response to an error message after the SoC simulation test is completed, the error message is corrected according to the simulation test error message, and the process jumps to step S13 to regenerate the embedded SVD file.

[0096] This embodiment provides a handling procedure for errors that occur after the SoC simulation test is completed.

[0097] In an optional embodiment, refer to Figure 5 Step S13 includes:

[0098] S131. Execute the SVD generation command in command line mode. The SVD generation script reads the corresponding controller core SVD file from the core_svd_lib directory according to the configuration parameters passed by the main control script, replaces the corresponding fields in the controller core SVD file in turn according to the configuration parameters, and writes them to the target SVD file as the start segment of the embedded SVD file to be generated.

[0099] S132. Read the register table from the reglist directory.

[0100] S133. For the peripheral overview table in the register table, store all peripheral information into the corresponding arrays by column from top to bottom and from left to right.

[0101] S134. For each peripheral device, generate the first SVD file code of the current peripheral device's start segment based on the SVD format, and write it into the corresponding segment of the embedded SVD file to be generated; read and preprocess the register information of the current peripheral device, and push the preprocessed register information into the corresponding array of the current peripheral device; extract the element information of each register of the current peripheral device, generate the second SVD file code based on the preset format, and write it into the corresponding segment of the embedded SVD file to be generated.

[0102] The following is an example of a register table (Excel).

[0103] Tables 1 and 2 show the IP overview table (1) and IP overview table (2) in the register table in the example, respectively. Tables 3 and 4 show the IP part register information table (1) and IP part register information table (2) in the register table (taking IPA as an example) in the example, respectively. In Tables 1-4, the first row is the Chinese name of the array and the second row is the English name of the array.

[0104] Table 1

[0105]

[0106] Table 2

[0107]

[0108] Table 3

[0109]

[0110]

[0111] Table 4

[0112]

[0113]

[0114]

[0115] Specifically, Figure 6 The workflow of the SVD generation script is shown.

[0116] First, after the user executes the `gen_svd` command in command-line mode, the SVD generation script reads the corresponding processor core SVD file from the `core_svd_lib` directory based on the register table, project name (e.g., `example`), processor core, and other relevant parameters passed by the main control script (e.g., processor core selected as CM3, `mpuPresent` configured as `true`). Then, it replaces the corresponding fields according to the configuration information (as shown in the example below). <mpupresent> false< / mpupresent> Replace with <mpupresent> true< / mpupresent> Then write it to the target SVD file as the beginning segment of the entire SVD file to be generated.

[0117] Example of a processor core SVD file (using ARM Cortex-M3 as an example):

[0118] <cpu>

[0119] <name> CM3< / name>

[0120] <revision> r2p1< / revision>

[0121] <endian> little< / endian>

[0122] <mpupresent> false< / mpupresent>

[0123] <fpupresent> false< / fpupresent>

[0124] <vtorpresent> true< / vtorpresent>

[0125] <nvicpriobits> 3< / nvicpriobits>

[0126] <vendorsystickconfig> false< / vendorsystickconfig>

[0127] < / cpu>

[0128] Then, read the register Excel spreadsheet from the reglist directory and perform the following steps:

[0129] (1) Read the IP overview table as shown in Table 1 and Table 2, and store all IP information into the corresponding arrays from top to bottom and from left to right in columns (store 14 elements from IPA to IPN into the module array (corresponding to Module in Table 1), ..., store 14 elements from IPAinterrupt to IPN interrupt into the int_descrip array (corresponding to Interrupt_Description in Table 1), and store 1 to 14 into the int_val array (corresponding to Interrupt_Val in Table 1).

[0130] (2) Read the first element of all arrays created in (1) (all information of the IPA peripheral), then generate the SVD of the peripheral start segment in the format shown in the example below, and write it to the corresponding segment of the SVD file to be generated.

[0131] Example of the start segment format for an IPA SVD file:

[0132] <peripheral>

[0133] <name> IPA< / name>

[0134] <version> 1.0< / version>

[0135] <description> Example IPA< / description>

[0136] <groupname> IPA< / groupname>

[0137] <baseaddress> 0x48000000< / baseaddress>

[0138] <size> 32< / size>

[0139] <access> read-write< / access>

[0140] <addressblock>

[0141] <offset> 0x0< / offset>

[0142] <size> 0x400< / size>

[0143] <usage> registers< / usage>

[0144] < / addressblock>

[0145] <interrupt>

[0146] <name> IPA< / name>

[0147] <description> IPA interrupt< / description>

[0148] <value> 1< / value>

[0149] < / interrupt>

[0150] …

[0151] < / peripheral>

[0152] (3) Read and preprocess the register information of the current IP. As shown in Tables 3 and 4, the register table of the current IP (the first element IPA of the Module array) is obtained from left to right. Then, all register information is scanned from top to bottom and from left to right by column. When the corresponding column is identified, the presence of illegal characters is checked first, and then different replacement methods are used to process it (e.g., when the Width column is identified, [31:0] is replaced with 32; when the R / W column is identified, the character R / O is replaced with read-only, and R / W is replaced with read-write, etc.). After processing, it is pushed into the corresponding array.

[0153] (4) The array created in (3) above stores the information of all registers of the current IP. This step requires extracting the relevant information of each register (such as determining the row range used by IPAR0, extracting the information of merged cells, and extracting the information of each row of the Field column from bottom to top) and generating SVD in the format shown in the example below, and writing it to the corresponding segment of the SVD file to be generated.

[0154] Example of the start segment format of the SVD in IPA register IPAR1:

[0155] <register>

[0156] <name> IPAR1< / name>

[0157] <description> IPA registerl< / description>

[0158] <address0ffset> 0x4< / address0ffset>

[0159] <size> 32< / size>

[0160] <access> read-write< / access>

[0161] <resetvalue> 0x00000000< / resetvalue>

[0162] <resetmask> 0x0000FFFF< / resetmask>

[0163] …

[0164] Example of the field segment format for SVD in IPA register IPAR1:

[0165] …

[0166] <fields>

[0167] <field>

[0168] <name> R1FIELD0< / name>

[0169] <description> IPA register1 field0< / description>

[0170] <bitrange> [3:0]< / bitrange>

[0171] <access> read-write< / access>

[0172] <enumeratedvalues>

[0173] <enumeratedvalue>

[0174] <name> enumvalue0< / name>

[0175] <description> enum descrip0< / description>

[0176] <value> 0xABCD5678< / value>

[0177] < / enumeratedvalue>

[0178] <enumeratedvalue>

[0179] <name> enumvaluel< / name>

[0180] <description> enum descrip1< / description>

[0181] <value> 0xABCD1234< / value>

[0182] < / enumeratedvalue>

[0183] < / enumeratedvalues>

[0184] < / field>

[0185] <field>

[0186] <name> R1FIELD1< / name>

[0187] <description> IPA register1 field1< / description>

[0188] <bitrange> [19:4]< / bitrange>

[0189] <access> read-write< / access>

[0190] <enumeratedvalues>

[0191] <enumeratedvalue>

[0192] <name> enumvalue0< / name>

[0193] <description> enum descripe< / description>

[0194] <value> 0x11223344< / value>

[0195] < / enumeratedvalue>

[0196] <enumeratedvalue>

[0197] <name> enumvaluel< / name>

[0198] <description> enum descrip1< / description>

[0199] <value> 0x55667788< / value>

[0200] < / enumeratedvalue>

[0201] < / enumeratedvalues>

[0202] < / field>

[0203] < / fields>

[0204] < / register>

[0205] (5) After completing the SVD code generation of all registers of peripheral IPA, repeat the above steps to continue generating the SVD code of the next IP (the next element of the module array, which is IPB in this example) until the SVD code of the last peripheral (execute the $#module loop, that is, traverse to the last element IPN of the module array) is generated.

[0206] If any formatting or syntax errors are detected in the register table information during the SVD generation script's execution, the number of errors (error_cnt) and the content of the errors will be recorded. After the execution is complete, "FAIL" (error_cnt ≠ 0, SVD generation failed) and the specific locations of all error messages will be printed. The user can then modify the errors in the table according to the prompts and re-execute the process until "PASS" (error_cnt = 0, SVD generation successful) is finally printed.

[0207] This embodiment provides a specific implementation method for generating embedded SVD files by calling an SVD generation script through an SVD generation command.

[0208] In an optional embodiment, refer to Figure 7 Step S134, "reading and preprocessing the register information of the current peripheral device," includes:

[0209] When the S1341 and SVD generation scripts perform a scan and read operation on the current peripheral device, they retrieve and record the column numbers of each category item other than the Wen column in the header from left to right.

[0210] S1342. Scan all register information except for column Wen from top to bottom and from left to right. For each cell, check if there are any illegal characters in the current cell. If there are illegal characters in the current cell, record the error. If there are no illegal characters in the current cell, replace the column elements that do not conform to the register SVD format requirements to make the column elements conform to the register SVD format requirements.

[0211] in, Figure 8 The register reading and element preprocessing process is illustrated.

[0212] When the SVD generation script performs the scan and read operation on this page, it first obtains and records the column numbers of each category item (except Wen) in the header from left to right. Then, it scans all register information except for the Wen column from top to bottom and from left to right. When a corresponding column is matched, it first checks whether there are illegal characters in the current cell (e.g., whether there are characters other than numbers, letters, and underscores in the Register and Field columns; whether the Width and Field_Width columns meet the format requirements of the register bit width). If it detects an illegal character, it increments the error counter error_cnt by 1 and records the row and column coordinates of the illegal character in the table and the error details. Otherwise, it proceeds to the next step, replacing column elements that are different from the register SVD format requirements (e.g., when the Width column is detected, [31:0] is replaced with 32; when the R / W column is detected, the character R / O is replaced with read-only, and R / W is replaced with read-write, etc.). After processing, the information is pushed into the corresponding array. The corresponding arrays for each column are: Register: reg_name, Description: reg_descrip, Offset: offset, Width: width, Access: access, Reset_Val: rst_val, Mask: mask, Field: field, Field_Width: field_width, R / W: rw_type, Default: default_val, Field_Description: field_descrip, Enum: enum_name, Enum_Description: enum_descrip, Enum_Val: enum_val). This process continues until all column information for the current IP has been scanned and processed.

[0213] After the above operations are completed, to prevent "undefined empty cells" from appearing during the register table filling process, which could lead to misalignment when generating the register field SVD, the script will automatically compare the number of elements in all the above column arrays. If they are different, the error counter error_cnt will be incremented by 1, and the specific column with the different number of elements from the other columns will be recorded.

[0214] This embodiment provides a specific implementation method for register reading and element preprocessing using SVD generation scripts.

[0215] In an optional embodiment, refer to Figure 9Step S134, "extracting element information from each register of the current peripheral, generating second SVD file code based on a preset format, and writing it to the corresponding segment of the embedded SVD file to be generated," includes:

[0216] S1343. Traverse the reg_name array that stores all register names, find the valid elements in the non-empty cells of the reg_name array, record the index of the valid elements and store them in the reg_index array, until the reg_name array is traversed to the last element, increment the index by 1 and store it in the reg_index array.

[0217] S1344. Traverse the reg_index array to generate the SVD file for each register of the current peripheral in turn. When $i=0, take the elements with index 0 and 1 from the reg_index array as the start index (reg_index_begin) and end index (reg_index_end) respectively.

[0218] S1345. Extract register element information from the current peripheral's reg_name array, reg_descrip array, offset array, width array, access array, rst_val array, and mask array to generate the first sub-SVD file code based on the first preset format, and write it into the corresponding segment of the embedded SVD file to be generated.

[0219] S1346. Using the start index and "end index - 1" as the boundaries of the array, extract the data of all fields of a register block from the field array, field_width array, rw_type array, default_val array, field_descrip array, enum_name array, enum_descrip array, and enum_val array of the current peripheral, and store them into the new field_tmp array, field_width_tmp array, rw_type_tmp array, default_val_tmp array, field_descrip_tmp array, enum_name_tmp array, enum_descrip_tmp array, and enum_val_tmp array, respectively.

[0220] S1347. For the field_tmp array, generate SVD files for each field of the current register in sequence, as well as the field_width_tmp array, rw_type_tmp array, default_val_tmp array, field_descrip_tmp array, enum_name_tmp array, enum_descrip_tmp array, and enum_val_tmp array. Extract the field information of the register from bottom to top and store it into the field_final variable, field_width_final variable, rw_type_final variable, default_val_final variable, field_descrip_final variable, enum_name_final variable, enum_descrip_final variable, and enum_val_final variable respectively. Generate the code for the second sub-SVD file based on the second preset format and write it into the corresponding segment of the embedded SVD file to be generated.

[0221] S1348. In response to the presence of a valid character in the `enum_name_final` variable, the `split` function is used to split the contents of the `enum_name_final`, `enum_descrip_final`, and `enum_val_final` variables using " / " as the delimiter. The split contents are then stored in the `enum_name_tmp1`, `enum_descrip_tmp1`, and `enum_val_tmp1` arrays, respectively. Simultaneously, the `enum_name_tmp1`, `enum_descrip_tmp1`, and `enum_val_tmp1` arrays are traversed, and one element is retrieved at a time. Based on a third preset format, third sub-SVD file code is generated and written to the corresponding segment of the embedded SVD file to be generated, thus completing the generation of the SVD file for the current field of the current register. (This is repeated in the original text.)

[0222] in, Figure 10 The process of extracting the register array and generating SVD is shown.

[0223] (1) Traverse the array reg_name that stores all register names and find the valid elements of the non-empty cells in the array, namely IPAR0, IPAR1, ... in the Register column of Table 3;

[0224] (2) Record the index of these valid elements and store them in the reg_index array until the last element is traversed in the process array (1). Then, increment the index of the element by 1 (index+1) and store it in the reg_index array.

[0225] (3) Traverse the reg_index array. When $i=0, take the elements with indices 0 and 1 from reg_index in sequence as the start index reg_index_begin and the end index reg_index_end, respectively;

[0226] (4) Using reg_index_begin as the index, extract the register contents from the created arrays reg_name, reg_descrip, offset, width, access, rst_val, and mask, and then... Figure 9 Generate an SVD in the format shown and write it to the corresponding section of the SVD file to be generated;

[0227] (5) Using reg_index_begin and reg_index_end-1 as the boundaries of the array, extract the contents of all fields of a register block from the created arrays field, field_width, rw_type, default_val, field_descrip, enum_name, enum_descrip, and enum_val, and store them into the new arrays field_tmp, field_width_tmp, rw_type_tmp, default_val_tmp, field_descrip_tmp, enum_name_tmp, enum_descrip_tmp, and enum_val_tmp respectively;

[0228] (6) Traverse the field_tmp array. Since the current register fields are sorted in the register table as shown in Tables 3 and 4, with the high bits at the top and the low bits at the bottom, the register field information needs to be extracted from bottom to top in the new array ending with _tmp created in process (5). That is, the information of each register field is extracted from the above array using the index $#reg_name_tmp-$j, and then stored in the variables field_final, field_width_final, rw_type_final, default_val_final, field_descrip_final, enum_name_final, enum_descrip_final, and enum_val_final respectively. Ignore the case where the field is Reserved, generate the SVD according to the preset format, and write it to the corresponding segment of the SVD file to be generated;

[0229] (7) Determine whether there are valid characters in the variable enum_name_final. Only if there are valid characters will the split function be used to split the contents of the variables enum_name_final, enum_descrip_final and enum_val_final with " / " as the separator (e.g., split the string enumvalue0 / enumvalue1 in enum_name_final into two elements enumvalue0 and enumvalue1), and store them in the arrays enum_name_tmp1, enum_descrip_tmp1 and enum_val_tmp1 respectively. Then, the above three arrays are traversed, and one element is taken out at a time. SVD is generated according to the preset enumeration segment format and written to the corresponding segment of the SVD file to be generated.

[0230] (8) At this point, the SVD of the first complete field and its enumerated fields is generated. Then the number of field loops $j is incremented by 1, and the process returns to step (6) to process the next field. This process is repeated until the field_tmp array is traversed and the SVD of the last field of the current register is generated ($j=$#field_tmp).

[0231] (9) At this point, the SVD of the first complete register and its fields and enumeration fields is generated. Then the register loop count $i is incremented by 1, and the process returns to step (3) to process the next register. This process is repeated until $i is $#reg_index-1, at which point the generation of the last register SVD of the current IP is completed.

[0232] (10) After the above steps are completed, the end segment of the SVD of the current IP is generated.

[0233] This embodiment provides a specific implementation method for SVD generation script to extract register arrays and perform SVD generation processing.

[0234] In an optional embodiment, refer to Figure 11 Step S15 includes:

[0235] S151. Execute the register test program generation command in command line mode. The test program generation script reads the corresponding register table from the reglist directory according to the register table path information passed by the main control script, reads the Module column of the peripheral overview table in the register table, and stores all peripheral names into the module array.

[0236] S152. Read each element of the module array sequentially. After matching the example program unit with the same name as each element of the module array, read it and write it into the register test program. Here, each element of the module array represents a peripheral device.

[0237] S153. For each element of the module array, read the register information of the current peripheral in the register table, obtain the column numbers of the Register column, Reset_Val column, Mask column, and Wen column from left to right, and store the data of the Register column, Reset_Val column, Mask column, and Wen column into the register array, reset_val array, mask array, and Wen array respectively, from top to bottom and from left to right.

[0238] S154. Traverse the register array, reset_val array, mask array, and wen array of the current peripheral device, extract the element corresponding to each register in the register array, reset_val array, mask array, and wen array, generate the test entry for each register in sequence according to the format of the predefined register read and write test function, and write it into the register test program.

[0239] Specifically, Figure 12 The workflow of the register test program generating script is shown.

[0240] After the user executes the `gen_testc` command in command-line mode, the register test program generates a script that, based on the register table path information passed by the main control script, reads the corresponding register Excel spreadsheet from the `reglist` directory. First, it reads the `Module` column of the IP overview table shown in Table 1 and stores all IP names into the `module` array (14 elements from IPA to IPN are stored in the `module` array). Then, it executes the following steps:

[0241] (1) Read the first element (IPA) of the module array. In the testc_lib directory, find the example program (IPA_reg.c) with the same name as the above element, read it and write it to the target file test_reg.c;

[0242] (2) Read in the register table information of the current IP (the first element IPA of the module array) as shown in Tables 3 and 4. First, obtain the column number of each category (column) of Register / Reset_Val / Mask / Wen from left to right. Then, store IPAR0, IPAR1, ... in the register array, store 0x00000008, 0x00000000, ... in the reset_val array, store 0x00000DF8, 0x000FFFFF, ... in the mask array, and store 0x000001F8, 0x000FFFFF, ... in the wen array.

[0243] (3) Take the first element of the arrays register, reset_val, mask, and wen, and generate the test entry for the first register according to the format of the defined register read / write test function: "reg_test(reg_addr,wen,mask,dft_val)" (reg_addr is the address of the register, wen is the number of bits allowed to be written to the register, mask is the valid definition bits of the register, and dft_val is the default value of the register. In this example, &IPA->IPAR0 is filled in reg_addr; 0x000001F8 is filled in wen; 0x00000DF8 is filled in mask; and 0x00000008 is filled in dft_val). Write the test entry for the first register into the target file test_reg.c. Then take the second element from the arrays register, reset_val, mask, and wen to generate the test entry for the second register, and so on, until the last element is taken out and the test entry for the current IP is generated according to the format.

[0244] (4) Read the next element (IPB) of the module array. In the testc_lib directory, after matching the example program (IPB_reg.c) with the same name as the above element, read it and write it into the target file test_reg.c. Then perform the same operation as steps (2) and (3). Continue in this way until the test program of the last element (IPN) in the module array is generated.

[0245] Once the target file test_reg.c is fully generated, the user can include the previously generated register header file (example.h) in the SoC simulation and run the generated register test program (test_reg.c) to perform read and write scan tests on the registers of all IPs, thereby verifying whether the register information in the register table is completely consistent with the SoC RTL code.

[0246] This embodiment provides a specific implementation method for generating a register test program by calling a test program generation script through a register test program generation command.

[0247] The following is an example of a method for generating embedded register header files.

[0248] Before initiating the `gen_svd` command, the user needs to configure the project name, register Excel spreadsheet name, and processor core parameter information in the main control script. For example, configure the project name as `example`, the register spreadsheet name as `example_reglist`, the processor core type as `CM3`, the processor core parameter `mpuPresent` as `true`, and the processor core parameter `fpuPresent` as `false`. These parameters will be passed down through the main control script when it calls the SVD generation script.

[0249] like Figure 6 As shown, after the user executes the `gen_svd` command in command-line mode, the SVD generation script first reads the corresponding processor core's SVD file from the `core_svd_lib` directory based on the processor core's `core_type` information (CM3 in this example). Then, according to the processor core configuration in the main control script, it generates the SVD file as shown in the example. <mpupresent> false< / mpupresent> Replace with <mpupresent> true< / mpupresent> , <fpupresent> false< / fpupresent> Then leave it unchanged and write it to the target SVD file as the beginning of the entire SVD file to be generated. Next, locate and read the register table named example_reglist from the reglist directory and perform the following operations:

[0250] (1) After reading the table, the IP overview table is processed first. As shown in Table 1 and Table 2, this table page contains description information of each IP peripheral with the header Module, Description, Group, Base_Addr, Size, Access, Block_Offset, Block_Size, Block_Usage, Interrupt, Interrupt_Description and Interrupt_Val. These are the information needed to generate the IP start segment SVD as shown in the example. When the script performs the scan and read operation on this page, it stores all IP information into the corresponding arrays from top to bottom and from left to right for use in subsequent steps (14 elements from IPA to IPN are stored in the module array, ..., 14 elements from IPA interrupt to IPN interrupt are stored in the int_descrip array, and 14 elements from 1 to 14 are stored in the int_val array).

[0251] (2) After the above operations are completed, read the first element of all the arrays created above (all the description information of the IPA peripheral), and then generate the SVD of the peripheral start segment in the format shown in the example, and write it to the corresponding segment of the SVD file to be generated;

[0252] (3) Read the Sheet page matching the name of the current IP (the first element IPA in the module array above), and extract and preprocess all register information. Tables 3 and 4 show the register table of the current IP (the first element IPA in the module array). This table contains detailed information on all registers of the current IP peripheral with headers of Register, Description, Offset, Width, Access, Reset_Val, Mask, Field, Field_Width, R / W, Default, Field_Description, Enum, Enum_Description, and Enum_Val. This information is needed when generating the IP register SVD. Figure 8As shown, when the script performs the scanning and reading operation on this page, it first obtains and records the column numbers of each category item (except Wen) in the header from left to right. Then, it scans all register information except for the Wen column from top to bottom and from left to right. When a corresponding column is matched, it first checks whether there are illegal characters in the current cell (such as checking whether there are characters other than numbers, letters, and underscores in the Register and Field columns; checking whether the Width and Field_Width columns meet the format requirements of the register bit width). If it detects an illegal character, it increments the error counter error_cnt by 1 and records the row and column coordinates of the illegal character in the table and the error details. Otherwise, it proceeds to the next step, replacing column elements that are different from the register SVD format requirements (such as replacing [31:0] with 32 when the Width column is detected; replacing the character R / O with read-only and R / W with read-write when the R / W column is detected). After processing, the information is pushed into the corresponding array. The corresponding arrays for each column are: Register: reg_name, Description: reg_descrip, Offset: offset, Width: width, Access: access, Reset_Val: rst_val, Mask: mask, Field: field, Field_Width: field_width, R / W: rw_type, Default: default_val, Field_Description: field_descrip, Enum: enum_name, Enum_Description: enum_descrip, Enum_Val: enum_val). This process continues until all column information for the current IP has been scanned and processed.

[0253] (4) After the above operations are completed, in order to prevent "undefined empty cells" from appearing during the register table filling process, which could lead to misalignment when generating the register field SVD, the script will automatically compare whether the number of elements in all the above column arrays is the same. If they are different, the error counter error_cnt will be incremented by 1, and the specific column with a different number of elements from the other columns will be recorded;

[0254] (5) The array created in process (3) above stores all register information of the current IP. This step requires extracting the relevant information of each register from it, such as Figure 10 As shown, the specific execution steps are as follows:

[0255] (a) Traverse the array reg_name that stores all register names and find the valid elements of the non-empty cells in the array, i.e. IPAR0, IPAR1, ... in the Register column of Table 3;

[0256] (b) Record the index of these valid elements and store them in the reg_index array until the array in process (a) is traversed to the last element, then increment the index of that element by 1 (index+1) and store it in the reg_index array;

[0257] (c) Iterate through the reg_index array. When $i=0, take the elements with indices 0 and 1 from reg_index and use them as the start index reg_index_begin and end index reg_index_end, respectively;

[0258] (d) Using reg_index_begin as the index, extract the register contents from the arrays reg_name, reg_descrip, offset, width, access, rst_val and mask created in process (3), generate the SVD according to the format shown in the example, and write it to the corresponding segment of the SVD file to be generated;

[0259] (e) Using reg_index_begin and reg_index_end-1 as the boundaries of the array, extract the contents of all fields of a register block from the field, field_width, rw_type, default_val, field_descrip, enum_name, enum_descrip and enum_val arrays created in procedure (3), and store them into the new field_tmp, field_width_tmp, rw_type_tmp, default_val_tmp, field_descrip_tmp, enum_name_tmp, enum_descrip_tmp and enum_val_tmp arrays respectively;

[0260] (f) Iterate through the field_tmp array. Since the current register fields are sorted in the register table as shown in Tables 3 and 4, with high bits at the top and low bits at the bottom, the register field information needs to be extracted from bottom to top in the new array ending with _tmp created in procedure (e). That is, the information of each register field is extracted from the above array using the index $#reg_name_tmp-$j, and then stored in the variables field_final, field_width_final, rw_type_final, default_val_final, field_descrip_final, enum_name_final, enum_descrip_final, and enum_val_final respectively. Ignore the case where the field is Reserved, generate the SVD according to the example's preset format, and write it to the corresponding section of the SVD file to be generated;

[0261] (g) Determine if there are valid characters in the variable enum_name_final. If there are valid characters, the split function will be used to split the contents of the variables enum_name_final, enum_descrip_final and enum_val_final with " / " as the delimiter (e.g., split the string enumvalue0 / enumvalue1 in enum_name_final into two elements enumvalue0 and enumvalue1), and store them in the arrays enum_name_tmp1, enum_descrip_tmp1 and enum_val_tmp1 respectively. Then, the three arrays will be traversed, and one element will be taken out at a time. SVD will be generated according to the preset enumeration segment format of the example, and written to the corresponding segment of the SVD file to be generated.

[0262] (h) At this point, the SVD of the first complete field and its enumerated fields is generated. Then the field loop count $j is incremented by 1, and the process returns to step (f) to process the next field. This process is repeated until the field_tmp array is traversed and the SVD of the last field of the current register is generated ($j=$#field_tmp).

[0263] (i) At this point, the SVD of the first complete register and its fields and enumeration fields is generated. Then the register loop count $i is incremented by 1, and the process returns to step (c) to process the next register. This process is repeated until $i is $#reg_index-1, at which point the generation of the last register SVD of the current IP is completed.

[0264] (j) After the above steps are completed, the end segment of the SVD of the current IP is generated.

[0265] (6) After the above operations are completed, return to step (2), read the next element of all arrays created in step (1) (all description information of IPB peripherals), execute steps (3), (4), and (5) above, generate the SVD code of the next peripheral IP, repeat the process until the SVD code of the last peripheral IPN in the module array is generated.

[0266] (7) After generating the SVD file for the entire chip, the script will perform the following printing based on the error counter error_cnt:

[0267] (a) If error_cnt is non-zero, it means that a format or syntax error was detected in the register table during the execution of the SVD generation script. After the execution is completed, "FAIL" (SVD generation failed) and the specific location of all error messages will be printed.

[0268] (b) If error_cnt is zero, it means that no format or syntax errors were detected in the register table during the SVD generation script. After the script finishes running, it will print "PASS" (SVD generation was successful).

[0269] The method for generating the embedded register header file in this embodiment has the following advantages:

[0270] (1) High degree of automation, simple operation, and high efficiency. The structure of this invention is clear. Users only need to put an Excel spreadsheet of all peripheral registers in the current chip filled in according to the given format in the reglist directory, and configure the required project name, processor core parameters, and other parameters in the main control script. Then, they can use the gen_svd and gen_headfile commands in the command line mode to generate SVD files and register header files. In addition, the SVD generation script can print out the details and location of format and syntax errors in the register table after the run is completed, which is convenient for users to modify.

[0271] (2) High accuracy. The gen_testc command is used in command line mode to generate a register test program to verify whether the information of the registers in the register table is completely consistent with that in the SoC RTL code;

[0272] (3) Simple maintenance. The later iteration process only needs to update a single register table, which effectively reduces the errors and workload caused by manual writing.

[0273] Example 2

[0274] Figure 13This is a schematic diagram of the structure of an electronic device according to an example embodiment of the present disclosure. The electronic device includes a memory, a processor, and a computer program stored in the memory and used to run on the processor. When the processor executes the computer program, it implements the embedded register header file generation method described in any of the above embodiments. Figure 13 The electronic device 90 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0275] like Figure 13 As shown, the electronic device 90 can be manifested as a general-purpose computing device, such as a server device. The components of the electronic device 90 may include, but are not limited to: at least one processor 91, at least one memory 92, and a bus 93 connecting different system components (including memory 92 and processor 91).

[0276] Bus 93 includes a data bus, an address bus, and a control bus.

[0277] The memory 92 may include volatile memory, such as random access memory (RAM) 921 and / or cache memory 922, and may further include read-only memory (ROM) 923.

[0278] The memory 92 may also include a program tool 925 (or utility) having a set (at least one) program module 924, such program module 924 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of these examples may include an implementation of a network environment.

[0279] The processor 91 executes various functional applications and data processing by running computer programs stored in the memory 92, such as the embedded register header file generation method provided in any of the above embodiments.

[0280] Electronic device 90 can also communicate with one or more external devices 94 (e.g., keyboard, pointing device, etc.). This communication can be performed via input / output (I / O) interface 95. Furthermore, electronic device 90 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 96. Figure 13 As shown, network adapter 96 communicates with other modules of electronic device 90 via bus 93. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with electronic device 90, including but not limited to: microcode, device drivers, redundant processors, external disk drive arrays, RAID (disk array) systems, tape drives, and data backup storage systems.

[0281] It should be noted that although several units / modules or sub-units / modules of the electronic device have been mentioned in the detailed description above, this division is merely exemplary and not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more units / modules described above can be embodied in one unit / module. Conversely, the features and functions of one unit / module described above can be further divided and embodied by multiple units / modules.

[0282] Example 3

[0283] This disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the embedded register header file generation method described in any of the preceding embodiments.

[0284] The program code for executing the computer program product of this disclosure can be written in any combination of one or more programming languages, and the program code can be executed entirely on a user device, partially on a user device, as a stand-alone software package, partially on a user device and partially on a remote device, or entirely on a remote device.

[0285] While specific embodiments of this disclosure have been described above, those skilled in the art should understand that these are merely illustrative examples, and the scope of protection of this disclosure is defined by the appended claims. Those skilled in the art can make various changes or modifications to these embodiments without departing from the principles and essence of this disclosure, but all such changes and modifications fall within the scope of protection of this disclosure.

Claims

1. A method for generating an embedded register header file, characterized in that, The generation method includes: Each source data file is pre-stored in a specified directory; wherein, the source data files include SVD generation scripts, processor core SVD files, register tables, and the conversion tool SVDConv; Run the main control script; Execute the SVD generation command in command line mode, call the SVD generation script, read in the SVD file of the processor core, read in the register table, and generate an embedded SVD file according to the SVD format; Execute the header file generation command in command line mode to call the conversion tool SVDConv to convert the embedded SVD file into the embedded register header file.

2. The method for generating an embedded register header file as described in claim 1, characterized in that, The source data file also includes a test program generation script and sample program units corresponding to each peripheral device. The generation method further includes: In command-line mode, execute the register test program generation command, call the test program generation script, read the register table, read the corresponding example program units in the order of the peripherals in the register table, fill in the corresponding parameters in the example program units according to the data in the register table, and merge the example program units with the parameters filled in into a register test program. Perform SoC simulation testing, including the embedded register header file, and run the register test program to perform read and write scan tests on all peripherals to test whether the register information in the register table is completely consistent with the SoC RTL code.

3. The method for generating an embedded register header file as described in claim 1, characterized in that, The generation method further includes: During the process of generating the embedded SVD file, in response to the presence of format or syntax errors in the register table, the SVD generation script outputs the location of the error after execution. The error is corrected according to the location of the error, and the process jumps to the "Execute SVD generation command in command line mode" step to regenerate the embedded SVD file. During the conversion process of generating the embedded register header file, in response to a syntax error in the contents of the register table, the conversion tool SVDConv outputs an error message after execution. The error is corrected according to the error message, and the process jumps to the "Execute SVD generation command in command line mode" step to regenerate the embedded SVD file.

4. The method for generating an embedded register header file as described in claim 2, characterized in that, The generation method further includes: In response to an error message that appears after the SoC simulation test is completed, the error message should be corrected according to the simulation test error message. The process should then proceed to the step "Execute SVD generation command in command line mode" to regenerate the embedded SVD file.

5. The method for generating an embedded register header file as described in claim 1, characterized in that, The step of executing the SVD generation command in command-line mode, calling the SVD generation script, reading the SVD file of the processor core, reading the register table, and generating an embedded SVD file according to the SVD format includes: In command-line mode, the SVD generation command is executed. The SVD generation script reads the corresponding controller core SVD file from the core_svd_lib directory according to the configuration parameters passed by the main control script, replaces the corresponding fields in the controller core SVD file in sequence according to the configuration parameters, and writes them into the target SVD file as the start segment of the embedded SVD file to be generated. Read the register table from the reglist directory; For the peripheral overview table in the register table, store all peripheral information into the corresponding arrays column by column from top to bottom and left to right; For each peripheral device, a first SVD file code is generated based on the SVD format to start the current peripheral device, and written into the corresponding segment of the embedded SVD file to be generated; the register information of the current peripheral device is read and element preprocessed, and the preprocessed register information is pushed into the corresponding array of the current peripheral device; the element information of each register of the current peripheral device is extracted, a second SVD file code is generated based on a preset format, and written into the corresponding segment of the embedded SVD file to be generated.

6. The method for generating an embedded register header file as described in claim 5, characterized in that, The reading and element preprocessing of the register information of the current peripheral device includes: When the SVD generation script performs a scan and read operation on the current peripheral device, it obtains and records the column numbers of each category item other than the Wen column in the header from left to right. Scan all register information except for the Wen column from top to bottom and from left to right. For each cell, check if there are any illegal characters in the current cell. If there are illegal characters in the current cell, record the error. If there are no illegal characters in the current cell, replace the column elements that do not conform to the register SVD format requirements to make the column elements conform to the register SVD format requirements.

7. The method for generating an embedded register header file as described in claim 5, characterized in that, The step of extracting element information from each register of the current peripheral device, generating second SVD file code based on a preset format, and writing it into the corresponding segment of the embedded SVD file to be generated includes: Traverse the reg_name array that stores all register names, find the valid elements of the non-empty cells in the reg_name array, record the index of the valid elements and store them in the reg_index array, until the reg_name array is traversed to the last element, then increment the index by 1 and store it in the reg_index array; The reg_index array is traversed to generate SVD files for each register of the current peripheral in turn. When $i=0, the elements with indices 0 and 1 are taken from the reg_index array as the start index and end index, respectively. The register element information is extracted from the reg_name array, reg_descrip array, offset array, width array, access array, rst_val array and mask array of the current peripheral device to generate the first sub-SVD file code based on the first preset format, and written into the corresponding segment of the embedded SVD file to be generated; Using the start index and "end index - 1" as the boundaries of the array, extract the data of all fields of a register block from the field array, field_width array, rw_type array, default_val array, field_descrip array, enum_name array, enum_descrip array, and enum_val array of the current peripheral, and store them into the new field_tmp array, field_width_tmp array, rw_type_tmp array, default_val_tmp array, field_descrip_tmp array, enum_name_tmp array, enum_descrip_tmp array, and enum_val_tmp array respectively; For the field_tmp array, SVD files for each field of the current register are generated sequentially. The field_width_tmp array, the rw_type_tmp array, the default_val_tmp array, the field_descrip_tmp array, the enum_name_tmp array, the enum_descrip_tmp array, and the enum_val_tmp array are extracted from bottom to top and stored in the field_final, field_width_final, rw_type_final, default_val_final, field_descrip_final, enum_name_final, enum_descrip_final, and enum_val_final variables respectively. The code for the second sub-SVD file is generated based on the second preset format and written to the corresponding segment of the embedded SVD file to be generated. In response to the presence of a valid character in the `enum_name_final` variable, the `split` function is used to split the contents of the `enum_name_final`, `enum_descrip_final`, and `enum_val_final` variables using " / " as the delimiter, and store them respectively in the `enum_name_tmp1`, `enum_descrip_tmp1`, and `enum_val_tmp1` arrays. Simultaneously, the `enum_name_tmp1`, `enum_descrip_tmp1`, and `enum_val_tmp1` arrays are traversed, and one element is retrieved at a time to generate a third sub-SVD file code based on a third preset format. This code is then written to the corresponding segment of the embedded SVD file to be generated, thus completing the generation of the SVD file for the current field of the current register. In response to the presence of a valid character in the `enum_name_final` variable, the generation of the SVD file for the current field of the current register is also completed.

8. The method for generating an embedded register header file as described in claim 2, characterized in that, The step of executing the register test program generation command in command-line mode, calling the test program generation script, reading the register table, sequentially reading the corresponding example program units according to the order of the peripherals in the register table, filling in the corresponding parameters in the example program units according to the data in the register table, and merging the example program units with filled parameters into a register test program includes: In command-line mode, the register test program generation command is executed. The test program generation script reads the corresponding register table from the reglist directory according to the register table path information passed by the main control script, reads the Module column of the peripheral overview table in the register table, and stores all peripheral names into the module array. Each element of the module array is read sequentially. After matching an example program unit with the same name as each element of the module array, it is read into and written into the register test program; wherein, one element of the module array represents a peripheral device. For each element of the module array, read the register information of the current peripheral in the register table, obtain the column numbers of the Register column, Reset_Val column, Mask column, and Wen column from left to right, and store the data of the Register column, Reset_Val column, Mask column, and Wen column into the register array, reset_val array, mask array, and Wen array respectively, from top to bottom and from left to right. Iterate through the register array, reset_val array, mask array, and wen array of the current peripheral device, extract the element corresponding to each register in the register array, reset_val array, mask array, and wen array, generate test entries for each register in sequence according to the format of the predefined register read and write test function, and write them into the register test program.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and for running on the processor, characterized in that, When the processor executes the computer program, it implements the method for generating the embedded register header file as described in any one of claims 1 to 8.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the method for generating the embedded register header file as described in any one of claims 1-8.

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