A test address generation method and device, a storage medium and an electronic device

Abstract

The application discloses a test address generation method and device, a storage medium and an electronic device, relates to the chip technical field, and comprises the following steps: acquiring the cache capacity of an address cache area; determining the distribution information of the addresses in the address cache area in an address page; according to the distribution information, analyzing the bit segment distribution situation, and determining the address page access type; based on the target capacity occupation state of the address cache area, the target function test demand corresponding to the target capacity occupation state, and the address page access type, generating a plurality of test addresses; and in response to the function test of the address cache area in a target test scene, selecting a target test address that is adapted to the target test scene. According to the application, the plurality of test addresses capable of covering all address pages are generated according to the distribution information, the comprehensive coverage of the test addresses is improved, the target test address adapted to the scene is selected in response to the function test demand in the target test scene, and the reusability and verification efficiency of the function verification of the address cache area are improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a test address generation method, apparatus, storage medium and electronic device. Background Technology

[0002] The Memory Management Unit (MMU) module in the chip includes a Translation Lookaside Buffer (TLB). The TLB can cache the mapping relationship between virtual addresses and physical addresses in advance to improve the address translation efficiency during data access.

[0003] Currently, in scenarios where address translation functionality is verified for TLBs, test address sequences are either manually written based on the fixed capacity of the TLB or randomly generated.

[0004] However, the test address coverage generated in this way is limited, and the generation of test address sequences cannot adapt to changes in TLB hardware specifications, resulting in incomplete test address sequence coverage and low reusability, which in turn leads to low efficiency in TLB address translation function verification. Summary of the Invention

[0005] In view of this, this application provides a test address generation method, apparatus, storage medium and electronic device, the main purpose of which is to improve the technical problems of limited test address coverage and inability of the test address sequence generation to adapt to changes in TLB hardware specifications in the prior art, which leads to incomplete test address sequence coverage, low reusability and thus low efficiency of TLB address translation function verification.

[0006] Firstly, this application provides a method for generating a test address, including: Get the cache capacity of the address cache area; Based on the cache capacity, determine the distribution information of addresses in the address cache area within the address pages; Based on the distribution information, the bit segment distribution of the addresses in the address cache in the address pages is analyzed to determine the address page access type of the address cache. The address page access type includes at least one of the following: continuous access to the same address page, alternating access to different address pages, and replacement access when the number of address pages exceeds the cache capacity. Based on the target capacity occupancy status of the address cache, the target function test requirements corresponding to the target capacity occupancy status, and the address page access type, multiple test addresses are generated for the address cache, and the multiple test addresses can cover all the address pages. In response to performing functional testing on the address cache under the target test scenario, a target test address that is compatible with the target test scenario is selected from the plurality of test addresses, and the target test address is used to perform functional testing on the address cache.

[0007] Optionally, the method further includes: determining, based on the address page access type, a test address cluster for functional testing of the address cache and the target distribution location of the test address cluster in the address page, wherein the test address cluster is used to determine the distribution location of the plurality of test addresses in the address page.

[0008] Optionally, generating multiple test addresses for the address cache based on the target capacity occupancy status of the address cache, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type includes: Based on the cache capacity, determine the target capacity occupancy status of the address cache area, and analyze the target functional test requirements of the address cache area under the target capacity occupancy status. Based on the target function testing requirements and the test address cluster, the multiple test addresses are generated.

[0009] Optionally, generating the plurality of test addresses based on the target function test requirements and the test address cluster includes: Based on the target function testing requirements, determine the index identifier of the test address cluster; Based on the index identifier, determine the address page coverage range of the test address cluster in the address page, and generate the multiple test addresses.

[0010] Optionally, determining the address page coverage range of the test address cluster in the address page based on the index identifier, and generating the plurality of test addresses, includes: Based on the index identifier, determine the address page coverage range of the test address cluster in the address page; The cache capacity, the address page coverage, and the page capacity of the address page are input into the constraint solver, and the constraint solver generates the multiple test addresses.

[0011] Optionally, the step of responding to perform functional testing on the address cache under the target test scenario, and selecting a target test address suitable for the target test scenario from the plurality of test addresses, includes: Obtain the target test scenario of the address cache area and determine the target test requirements of the target test scenario; Among the multiple test addresses, the test address that meets the target test requirements is determined as the target test address; According to the address access order of the target test scenario, the target test addresses are combined and sorted to obtain the target test address sequence of the address cache area; The address cache is functionally tested according to the target test address sequence.

[0012] Secondly, this application provides a test address generation apparatus, comprising: The acquisition module is configured to retrieve the cache capacity of the address cache area; The determination module is configured to determine the distribution information of addresses in the address cache in the address page based on the cache capacity; The analysis module is configured to analyze the bit segment distribution of addresses in the address cache in the address pages based on the distribution information, and determine the address page access type of the address cache. The address page access type includes at least one of continuous access to the same address page, alternating access to different address pages, and replacement access when the number of address pages exceeds the cache capacity. The generation module is configured to generate multiple test addresses for the address cache based on the target capacity occupancy status of the address cache, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type. The multiple test addresses can cover all the address pages. The selection module is configured to select a target test address from the plurality of test addresses that is compatible with the target test scenario in response to performing functional testing on the address cache under the target test scenario. The target test address is used to perform functional testing on the address cache.

[0013] Thirdly, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the test address generation method described in the first aspect.

[0014] Fourthly, this application provides an electronic device, including a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, wherein the processor executes the computer program to implement the test address generation method described in the first aspect.

[0015] By means of the above technical solution, this application provides a test address generation method, apparatus, storage medium, and electronic device, comprising: obtaining the cache capacity of an address cache area; determining the distribution information of addresses in the address cache area in address pages based on the cache capacity; analyzing the bit segment distribution of addresses in the address cache area in address pages according to the distribution information, and determining the address page access type of the address cache area; generating multiple test addresses for the address cache area based on the target capacity occupancy status of the address cache area, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type, wherein the multiple test addresses can cover all address pages; and in response to performing functional testing on the address cache area under a target test scenario, selecting a target test address adapted to the target test scenario from the multiple test addresses, wherein the target test address is used to perform functional testing on the address cache area. Compared with existing technologies, this application achieves the basic input of hardware specifications as test address generation by obtaining the cache capacity of the address cache area; establishes the distribution relationship between addresses and address pages by determining the distribution information of addresses in the address cache area in address pages based on the cache capacity; improves the comprehensiveness of test address coverage by generating multiple test addresses that can cover all address pages based on the distribution information; and improves the reusability and verification efficiency of address cache area functional verification by selecting target test addresses for testing in response to the functional testing requirements of the address cache area under the target testing scenario. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a test address generation method provided in an embodiment of this application is shown; Figure 2 A flowchart illustrating a test address generation method provided in an embodiment of this application is shown; Figure 3 This paper shows a schematic diagram of the structure of a test address generation device provided in an embodiment of this application; Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of this application is shown. Detailed Implementation

[0019] The embodiments of this application will now be described in more detail with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0020] To address the limitations of current technologies in generating test addresses, which suffer from limited coverage and inability to adapt to changes in TLB hardware specifications, leading to incomplete test address sequence coverage, low reusability, and consequently low efficiency in TLB address translation function verification, this embodiment provides a test address generation method. Figure 1 As shown, the method includes: Step 101: Obtain the cache capacity of the address cache area.

[0021] In this embodiment, the address cache can be an internal storage area of ​​the MMU used to cache address translation entries. The address cache can store cache entries (TLB Entries) and can cache the mapping relationship between virtual addresses and physical addresses to accelerate the translation process from virtual to physical addresses. For example, the address cache in this embodiment may specifically include various page table caching hardware modules such as instruction TLB, data TLB, and unified TLB.

[0022] In this embodiment, the cache capacity can be the maximum number of address mapping entries that the address cache can hold. The cache capacity can be characterized by the parameter N, which can represent the total number of TLB entries or the number of TLB cache lines. For example, the cache capacity in this embodiment can be 8, 16, 32, 64, 128, etc., to adapt to different parameterized MMU hardware designs.

[0023] For the embodiments of this application, the implementation methods for obtaining the cache capacity may include, but are not limited to, reading the predefined TLB entry number parameter in the hardware configuration file and reading the hardware specification register value of the MMU under test through the simulation environment register interface.

[0024] In this embodiment, the cache capacity N can be used as the seed parameter for the entire address generation method. When the number of TLB entries is iteratively modified, only the updated cache capacity value needs to be read again, without modifying the address generation logic. This solves the defects of existing technologies where incentives are hard-coded and bound to TLB specifications, resulting in low reusability.

[0025] Step 102: Based on the cache capacity, determine the distribution information of addresses in the address cache in the address pages.

[0026] In this embodiment, the address page can be a memory range corresponding to the memory paging granularity agreed upon by the operating system and the hardware. The address page can be divided into types such as 4KB small pages and 2MB large pages according to the hardware configuration. The low bit address offset within the same address page will not change the page number or virtual page number (VPN). For example, in this embodiment, the offset bit width G of the 4KB address page can be 11bit→12bit, with address bits [11:0] corresponding to the offset within the page, and bits 12 and above used to distinguish different address pages.

[0027] In this embodiment, the distribution information can be a combination of factors such as the bit distribution of the virtual address within the address page space, the distribution of the number of pages, the degree of page dispersion, and the probability of page conflicts. This distribution information can be generated by a cache capacity constraint N. For example, the distribution information in this embodiment may specifically include the number of bits in a variable page number, the total number of valid pages, the probability of two consecutive accesses to the same page, and the density of page dispersion.

[0028] In the embodiments of this application, the distribution information can be divided into multiple types of subdivided data. The subdivided data may include variable page number bit length, total number of valid pages, probability of two consecutive accesses to the same page, page high bit association rules, and discrete distribution intervals of M test address clusters. The subdivided data can be directly used for subsequent bit segment distribution parsing and test address cluster construction.

[0029] In this embodiment of the application, taking a 4KB address page scenario as an example, the page offset bit width G can be fixed at 11bit→12bit, the page distinguishing bit expands upward from bit12, and the distribution information can be automatically associated with the binary value of bit12 and above high bits and the test address cluster index i, so as to realize the adaptive adjustment of the page distribution pattern when N changes, and overcome the technical problems of existing technologies that cannot adapt to different cache line numbers and one set of stimulus can only adapt to a single TLB specification.

[0030] Step 103: Based on the distribution information, analyze the bit segment distribution of addresses in the address cache within the address pages to determine the address page access type of the address cache.

[0031] The address page access types include at least one of the following: consecutive access to the same address page, alternating access to different address pages, and replacement access when the number of address pages exceeds the cache capacity.

[0032] In this embodiment of the application, the distribution information may be the division rule of the high-order bits and low-order offset bits of the virtual address. The distribution information can distinguish between fixed random bit segments and variable page number bit segments. The distribution information can be used to determine whether two accesses cross different address pages.

[0033] In this embodiment, the address page access type can be a classification of memory access behavior simulated by the test address. For example, the address page access type in this embodiment can specifically include three categories: continuous access to the same address page, alternating access to different address pages, and replacement access when the number of address pages exceeds the cache capacity. Additional extended types such as concurrent access conflicts and cross-ASID multi-VPN access can also be added.

[0034] For the embodiments of this application, the variable page number bit length, total number of valid pages, and probability of two consecutive accesses to the same page can be determined for different bit segment divisions. For example, the bit segment and page parameters corresponding to the standard random method in the 4KB page scenario of this application embodiment may include: in the case of [11:0] random (i.e., only the lowest 0~11 bits of the virtual address are randomized), the variable page number bit can be none, the total number of valid pages can be 1, and the probability of two adjacent accesses to the same page can be 1; in the case of [12:0] random (i.e., only the lowest 0~12 bits of the virtual address are randomized), the variable page number bit is bit 13, the total number of valid pages can be 2, and the probability of two adjacent accesses to the same page can be 1 / 2; in the case of [13:12]--[13:0] random (i.e., first fix the high-order bits 12~13 of the page number, then randomize all bits 0~13), the variable page number bit is bit 14, the total number of valid pages can be 4, and the probability of two adjacent accesses to the same page can be 1 / 4; in the case of [14:12]--[14:0] random... In the random case (i.e., first fix the high-order bits 12~14 for page number, and then randomly assign all bits 0~14), the variable page number bit is bit 15, the total number of valid pages can be 8, and the probability of two adjacent entries being on the same page can be 1 / 8.

[0035] For example, in the [15:12]--[15:0] random case (i.e., first fix the high-order bits 12~15 of the page number, then randomly assign all bits 0~15), the variable page number bit is bit 16, the total number of valid pages can be 16, and the probability of two adjacent entries being on the same page can be 1 / 16; in the [16:12]--[16:0] random case (i.e., first fix the high-order bits 12~16 of the page number, then randomly assign all bits 0~16), the variable page number bits are bits 17-bit 16, the total number of valid pages can be 32, and the probability of two adjacent entries being on the same page can be 1 / 32; In the case of [17:12]--[17:0]random (i.e., first fix the high-order bits 12~17 of the page number, and then randomly assign all bits 0~17), the variable page number bits are bits 18-bit17, the total number of valid pages can be 64, and the probability of two adjacent entries being on the same page can be 1 / 64; in the case of [18:12]--[18:0]random (i.e., first fix the high-order bits 12~18 of the page number, and then randomly assign all bits 0~18), the variable page number bits are bits 19-bit18, the total number of valid pages can be 128, and the probability of two adjacent entries being on the same page can be 1 / 128.

[0036] In this embodiment, the basic address page access type can be divided according to the total number of valid pages corresponding to the bit segment distribution. When the total number of valid pages is 1, only the continuous access type of the same address page can be generated. When the total number of valid pages is greater than 1 and less than the cache capacity N, the alternating access type of different address pages is adapted. When the total number of valid pages is greater than the cache capacity N, the number of pages exceeds the TLB storage limit, and the replacement access type when the number of address pages exceeds the cache capacity is automatically matched.

[0037] Step 104: Based on the target capacity occupancy status of the address cache, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type, generate multiple test addresses for the address cache.

[0038] Among them, multiple test addresses were able to cover all address pages.

[0039] In this embodiment, the test address can be a virtual address generated through multi-layer constraint solving. The test address can have controllable page conflict attributes and is not an unconstrained, completely random address. The test address can carry a one-to-one physical address mapping relationship. For example, the test addresses in this embodiment can be specifically divided into different types of address samples, such as same-page addresses, alternating double-page addresses, and full-capacity replacement addresses.

[0040] In this embodiment of the application, a complete set of test addresses with controllable page conflict attributes can be generated in batches. The combination of all test addresses in the complete set can completely cover all address pages accessible by the hardware, avoiding the problem of missing boundary scenarios when manually constructing addresses.

[0041] In the embodiments of this application, the test address is a constrained random address under multi-layer constraints, which can accurately control the page type to which the address belongs, and construct key verification scenarios that are difficult to fully cover manually, such as full TLB capacity, multiple VPN conflicts with the same Address Space Identifier (ASID), and continuous access across lines. This solves the problems of existing simple random addresses being unable to accurately control page distribution, incomplete scenario coverage, and high tape-out risk.

[0042] Step 105: In response to performing functional testing on the address cache under the target test scenario, select the target test address that is suitable for the target test scenario from multiple test addresses.

[0043] The target test address is used to perform functional testing on the address cache.

[0044] In this embodiment, the target test scenario can be a pre-set test case scenario during MMU simulation verification. The target test scenario can correspond to different hardware specifications and different verification focuses. For example, the target test scenario in this embodiment may specifically include worst-case performance stress testing with TLB full missing (Miss), critical scenario regression of replacement algorithm, universal multiplexing verification of multi-specification MMUs, side-channel collision detection test, etc.

[0045] In this embodiment, the target test address can be a virtual address sample selected from all test addresses and matching the constraints of the current test scenario. The target test address can be used alone or combined and sorted to form a continuous access sequence. For example, the target test address in this embodiment can specifically be a fully discrete, non-repeating page address, a circular address within the same page, or a cross-ASID conflict address.

[0046] In this embodiment, in response to the MMU function test command initiated by the simulation environment, the constraint requirements corresponding to the test scenario can be parsed first, and the matching address can be selected from the test addresses as the target test address. Only the target test address is injected into the simulation environment, without loading the entire set of test addresses. This can solve the technical problems of large fixed stimulus redundancy and serious waste of storage resources and test time in the prior art.

[0047] In the embodiments of this application, the selected target test addresses can be output and used separately, or they can be reorganized into a continuous address stream according to the scenario access rules to adapt to various simulation access modes such as sequential access, cyclic access, and random mixed access, covering all types of verification scenarios such as TLB stress testing, replacement algorithm regression, and concurrent conflict verification.

[0048] In this embodiment, different target test scenarios can reuse the same set of basic test addresses without having to generate address sequences repeatedly, which greatly shortens the verification convergence cycle of multi-specification MMU projects and reduces the manpower cost of manually constructing addresses and modifying test cases for verification.

[0049] Compared with existing technologies, this application achieves the basic input of hardware specifications as test address generation by obtaining the cache capacity of the address cache area; establishes the distribution relationship between addresses and address pages by determining the distribution information of addresses in the address cache area in address pages based on the cache capacity; improves the comprehensiveness of test address coverage by generating multiple test addresses that can cover all address pages based on the distribution information; and improves the reusability and verification efficiency of address cache area functional verification by selecting target test addresses for testing in response to the functional testing requirements of the address cache area under the target testing scenario.

[0050] As an optional approach, the following methods can be used, but are not limited to these: Figure 2 As shown, it includes: Step 201: Based on the address page access type, determine the test address clusters for functional testing in the address cache and the target distribution location of the test address clusters in the address pages.

[0051] The test address cluster is used to determine the distribution of multiple test addresses within the address page.

[0052] In the embodiments of this application, the test address cluster can be a standardized address generation template, or it can be a test page cluster. A single test address cluster can derive a set of test addresses with unified conflict attributes, and the test address cluster can be distinguished by the index identifier Base_VPN_i.

[0053] In the embodiments of this application, the page distribution location of the test address cluster can be constrained by binding the high-order bits of the page with the binary value of index i. When the cache capacity N changes, the value of M is synchronously and adaptively adjusted. The number of test address clusters and the distribution density of the virtual address space automatically adapt to the new TLB specification without the need for manual modification of the test address template.

[0054] For the embodiments of this application, additional access types can be added, such as concurrent access conflict, cross-ASID multi-VPN access, and page mask (PBM) adapted access. These additional types can be used as optional supplements to adapt to special MMU authentication requirements.

[0055] In this embodiment, the target distribution position of the corresponding test address cluster can be adjusted according to the selected address page access type to construct an address template that matches the access behavior. For example, the replacement access type corresponds to evenly and discretely distributing the test address cluster in the high-order range of the virtual address, generating more than N different page addresses in batches, and forcibly triggering the TLB replacement logic; the same-page continuous access type corresponds to locking a single group of test address clusters with m=0, with all addresses belonging to the same page.

[0056] In the embodiments of this application, key test scenarios such as TLB replacement, Miss, and full capacity, which are difficult to fully cover manually, can be constructed in a targeted manner, solving the problems of existing technologies that rely on manual design of test addresses, resulting in incomplete test address coverage and non-reusability.

[0057] As an optional approach, when performing the task of "generating multiple test addresses for the address cache based on the target capacity occupancy status of the address cache, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type", the following method can be used, but is not limited to: determining the target capacity occupancy status of the address cache based on the cache capacity, and analyzing the target functional test requirements of the address cache under the target capacity occupancy status; generating multiple test addresses based on the target functional test requirements and the test address cluster.

[0058] In this embodiment, the target capacity occupancy status can be the degree to which TLB entries are occupied, and the target capacity occupancy status can be used to construct a TLB stress test scenario. For example, the target capacity occupancy status in this embodiment can specifically include empty cache, half-full cache, and full cache status.

[0059] In this embodiment, the target functional test requirement can be a test objective that needs to be covered for MMU hardware verification. The target functional test requirement can correspond to requirements such as replacement algorithm verification, TLB Miss / Hit verification, boundary entry stability testing, and concurrent conflict stress testing. For example, the target functional test requirement in this embodiment may specifically include verification of the correctness of Least Recently Used (LRU) / First In First Out (FIFO) / Pseudo Least Recently Used (PLRU) replacement algorithms, cache full capacity pollution protection verification, and PBM mask adaptation verification.

[0060] In the embodiments of this application, the target capacity occupancy status is divided based on the cache capacity N. The empty cache status corresponds to no TLB entries occupied, the half-full cache status corresponds to the number of entries occupied being between 1 and N-1, and the full cache status corresponds to all entries being occupied with no free space. The three types of status can correspond to different target function test requirements.

[0061] In this embodiment, the test requirement for an empty cache state can be to verify the logic of full miss during the first address translation; the test requirement for a half-full cache state can be to verify the mixed access behavior of partial hits and partial misses; and the test requirement for a full cache state can be to verify the correctness of the LRU / FIFO / PLRU replacement algorithm, the cache pollution protection capability, and the stability of boundary entry access.

[0062] In the embodiments of this application, test address clusters matching the discreteness of pages can be retrieved to complete address generation. For example, for full cache stress testing requirements, a multi-page test address cluster of m=M-1 can be retrieved to generate more than N discrete page addresses in batches, continuously triggering TLB full capacity replacement, thus overcoming the shortcomings of existing technologies in address generation that are unaware of TLB occupancy status and cannot verify the critical behavior of replacement algorithms.

[0063] As an optional approach, when performing the "generate multiple test addresses based on the target function test requirements and test address clusters" step, the following method can be used, but is not limited to: determining the index identifier of the test address cluster based on the target function test requirements; determining the address page coverage range of the test address cluster in the address page based on the index identifier, and generating multiple test addresses.

[0064] In this embodiment of the application, the index identifier can be a sequence number used to distinguish different test address clusters. The index identifier can correspond to the binary value of the high-order bit segment of the page. The index identifier can directly control the distribution position of the address cluster in the virtual address space.

[0065] For the embodiments of this application, the corresponding index identifier Base_VPN_i can be selected according to the target function test requirements. For example, when it is necessary to generate fully discrete page addresses with a high probability and construct a TLB full miss load test scenario, a test address cluster with a high m value and a high index i can be selected; when it is necessary to perform a loop Hit test on the same page, a base address cluster with m=0 and index i=0 can be selected.

[0066] In this embodiment of the application, the probability of page repetition needs to be quantified during the generation of test addresses. The formula for calculating the probability that K consecutive samples all use different address pages can be shown in Formula 1, where, M can represent the probability that all K accesses use different address pages; M can represent the total number of valid independent pages in the current random mode; K can represent the number of consecutive access samplings, and in this embodiment, K can take the value 16; ! can represent factorial operation.

[0067] (Formula 1) For the embodiments of this application, when the value of M is large and K is much smaller than M, an approximate calculation formula can be used. The approximate calculation formula is as shown in Formula 2, where, M can represent the probability that all K visits use different address pages; M can represent the total number of valid independent pages in the current random mode; K can represent the number of consecutive access samplings.

[0068] (Formula 2) In this embodiment, with 4KB pages and K=16 consecutive accesses, the probability of all pages being different after consecutive accesses can be calculated based on the bit segment division: The total number of valid pages M in the random modes [11:0], [12:0], [13:12], and [14:12] are 1, 2, 4, and 8 respectively, all less than the sampling number of 16. Therefore, page duplication will occur in 16 accesses, and the probability of all pages being different can be 0%. In the random mode [15:0], the total number of valid pages M=16, and the probability of all pages being different calculated using Formula 1 is approximately 1.05×10⁻⁶. -7 %; [16:0] Random mode M=32, the probability of all different pages calculated by substituting into Formula 2 is about 2.43%; [17:0] Random mode M=64, the probability of all different pages calculated by substituting into Formula 2 is about 15.97%; [18:0] Random mode M=128, the probability of all different pages calculated by substituting into Formula 2 is about 39.93%.

[0069] For the embodiments of this application, if the probability of 16 accesses to completely different pages is to be close to 50%, i.e., K=16, =0.5, the critical value of M can be solved by an approximate formula. Simplifying by taking the natural logarithm of both sides of Formula 2, we get 120 / M=ln2, and the calculated M is approximately 173. That is, at least 173 valid independent pages need to be provided by configuring variable page number bits. For example, by extending to the [20:0] random bit segment partitioning mode, the probability of 16 accesses being all different pages can be close to 50%.

[0070] In the embodiments of this application, the above probability calculation results can directly guide the selection of random mode for TLB stress testing. If it is necessary to construct a full miss worst-case performance stress test stream, a random mode with a bit width of [16:0] or higher can be selected. If only a stable TLB hit access stream is needed, a low-bit random mode can be selected.

[0071] As an optional approach, when performing the task of "determining the address page coverage of the test address cluster in the address page based on the index identifier and generating multiple test addresses", the following method can be used, but is not limited to: determining the address page coverage of the test address cluster in the address page based on the index identifier; inputting the cache capacity, address page coverage, and page capacity of the address page into the constraint solver, and generating multiple test addresses through the constraint solver.

[0072] In this embodiment, the address generation process can be adapted to the TLB testing requirements of different PBM masks by adjusting the address mask parameters through the constraint solver.

[0073] In the embodiments of this application, the address page coverage range of the test address cluster can be defined based on the high-bit constraints bound to index i. Compliant test addresses can be generated by superimposing forced constraints through a constraint solver. Constraints can include legality constraints, spatial distribution constraints, and scenario-based relationship constraints. Legality constraints can force addresses to meet page alignment rules. For example, for a 4KB page, all bits [11:0] of the constraint address are set to 0. Spatial distribution constraints can bind the high-bits of the address to the binary value of index i to achieve adaptive page distribution density when N changes. Scenario-based relationship constraints can control the access sequence order and the scale of page conflicts, and construct scenario addresses such as stress testing, cyclic access, and mask adaptation.

[0074] In this embodiment of the application, a complete set of test addresses can be generated in batches based on M groups of test address clusters and multiple layers of address constraints. During the generation process, legality constraints, spatial distribution constraints, and scenario-based relationship constraints can be applied simultaneously. The constraints can be solved by a constraint solver to output compliant address samples.

[0075] In the embodiments of this application, the constraint solver can be a random address solving module for generating multi-level address constraints. The constraint solver can accept parameter inputs such as cache capacity N, address page coverage range, and address page size, and output a set of compliant test addresses in batches. The constraint solver includes, but is not limited to, the Universal Verification Methodology (UVM) random constraint solver and the SystemVerilog built-in constraint randomization tool.

[0076] As an optional approach, when performing the action of "selecting a target test address from multiple test addresses that fits the target test scenario in response to performing functional testing on the address cache in the target test scenario", the following method can be used, but is not limited to: obtaining the target test scenario of the address cache and determining the target test requirements of the target test scenario; determining the test address that meets the target test requirements as the target test address from among multiple test addresses; combining and sorting the target test addresses according to the address access order of the target test scenario to obtain the target test address sequence of the address cache; and performing functional testing on the address cache according to the target test address sequence.

[0077] In this embodiment, the target test requirement can be the address flow constraint requirement corresponding to the target test scenario. The target test requirement can limit conditions such as page repetition probability, number of pages, and access order. For example, the target test requirement in this embodiment can specifically be 16 consecutive accesses all using different address pages, cyclically accessing the same page to construct a continuous TLB hit, or batch generating overcapacity pages to trigger frequent replacements.

[0078] In this embodiment, the target test address sequence can be a continuous address stream ordered by scenario access sequence. The target test address sequence can be directly injected into the MMU verification simulation environment to drive simulation execution. For example, the target test address sequence in this embodiment can specifically be in the form of sequentially traversing all test address clusters, randomly mixing multiple clusters of addresses, or cyclically accessing a concentrated single cluster of addresses.

[0079] In this embodiment of the application, the target test scenario configured in the current simulation environment can be read, and the target test requirements corresponding to the scenario can be parsed. For example, the target test scenario can be a TLB full miss load test scenario, and the corresponding test requirement is to use different address pages as much as possible for 16 consecutive accesses; the target test scenario can be a replacement algorithm regression scenario, and the corresponding test requirement is to generate discrete page addresses in batches that exceed the cache capacity N.

[0080] In this embodiment, all test addresses can be traversed to select address samples that meet the page constraints and access constraints required for testing as target test addresses, and redundant and mismatched address samples can be filtered out to reduce simulation storage usage and simulation time.

[0081] In the embodiments of this application, the target test address can be sorted and combined according to the access order rules preset in the scenario. The sorting method may include, but is not limited to, sequentially traversing all test address clusters, randomly mixing multiple cluster addresses, and cyclically accessing a single cluster address. After the combination is completed, a standardized target test address sequence is output.

[0082] In this embodiment, the target test address sequence can be input into the MMU verification simulation environment to drive hardware simulation to complete the functional verification. The entire process does not require manual modification of the stimulus code or maintenance of multiple test cases for different TLB specifications, thus solving the shortcomings of existing technologies such as poor standardization and portability, high difficulty in reuse between projects, and high maintenance costs.

[0083] Optionally, in addition to the basic 4KB small page implementation, this application embodiment can also be adapted to the 2MB large page verification scenario. The offset bit width within the 2MB large page can be 20bit→21bit, with only bit 21 and above used to distinguish different address pages. The random bit segment division mode falls entirely within the offset range of the 2MB page. All test addresses generated using the random mode can belong to the same 2MB address page 100%, which can be used to verify the performance scenario of continuous hits in large page TLB.

[0084] Compared with existing technologies, the embodiments of this application achieve layered construction of test address generation constraints by analyzing the address segment distribution based on distribution information, determining test address clusters, and generating multiple test addresses based on the test address clusters; by determining the address page access type based on the segment distribution and matching the test address clusters and their target distribution locations, test addresses adapted to various access behaviors are generated, achieving comprehensive coverage of test addresses; by determining the target capacity occupancy status based on cache capacity and generating multiple test addresses in combination with the target functional test requirements and test address clusters, test addresses are matched with test requirements corresponding to different cache occupancy statuses; by obtaining the target test requirements of the target test scenario, filtering the target test addresses, and sorting them to form a target test address sequence for execution, the reusability of test addresses is improved, the cost of manually generating test addresses is reduced, and the stable operation of address cache function verification is ensured.

[0085] Furthermore, as Figure 1 and Figure 2 The specific implementation of the method shown in this embodiment provides a test address generation device, such as... Figure 3 As shown, the device includes: an acquisition module 31, a determination module 32, an analysis module 33, a generation module 34, and a selection module 35.

[0086] Module 31 is configured to retrieve the cache capacity of the address cache area; Module 32 is configured to determine the distribution information of addresses in the address cache in the address pages based on the cache capacity. Analysis module 33 is configured to analyze the bit segment distribution of addresses in address cache in address pages based on distribution information, and determine the address page access type of address cache. The address page access type includes at least one of the following: continuous access to the same address page, alternating access to different address pages, and replacement access when the number of address pages exceeds the cache capacity. The generation module 34 is configured to generate multiple test addresses for the address cache based on the target capacity occupancy status of the address cache, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type. These multiple test addresses can cover all address pages. Module 35 is selected and configured to select a target test address from multiple test addresses that are suitable for the target test scenario in response to functional testing of the address cache in the target test scenario. The target test address is used to perform functional testing on the address cache.

[0087] In some examples of this embodiment, the analysis module 33 is specifically configured to determine the test address cluster for functional testing of the address cache and the target distribution location of the test address cluster in the address page based on the address page access type. The test address cluster is used to determine the distribution location of multiple test addresses in the address page.

[0088] In some examples of this embodiment, the generation module 34 is specifically configured to determine the target capacity occupancy status of the address cache based on the cache capacity, and analyze the target functional test requirements of the address cache under the target capacity occupancy status; and generate multiple test addresses according to the target functional test requirements and the test address cluster.

[0089] In some examples of this embodiment, the generation module 34 is further configured to determine the index identifier of the test address cluster according to the target functional test requirements; determine the address page coverage range of the test address cluster in the address page according to the index identifier, and generate multiple test addresses.

[0090] In some examples of this embodiment, the generation module 34 is further configured to determine the address page coverage range of the test address cluster in the address page according to the index identifier; input the cache capacity, address page coverage range, and address page capacity into the constraint solver, and generate multiple test addresses through the constraint solver.

[0091] In some examples of this embodiment, module 35 is selected and specifically configured to obtain the target test scenario of the address cache area, determine the target test requirements of the target test scenario; among multiple test addresses, determine the test address that meets the target test requirements as the target test address; combine and sort the target test addresses according to the address access order of the target test scenario to obtain the target test address sequence of the address cache area; and perform functional testing on the address cache area according to the target test address sequence.

[0092] It should be noted that other corresponding descriptions of the functional units involved in the test address generation device provided in this embodiment can be found in [reference]. Figure 1 and Figure 2 The corresponding description in [the document] will not be repeated here.

[0093] Based on the above, Figure 1 and Figure 2 Accordingly, this embodiment also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the above-described method. Figure 1 and Figure 2 The method shown.

[0094] Based on this understanding, the technical solution of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as CD-ROM, USB flash drive, mobile hard drive, etc.) and includes several instructions to cause a computer device (such as personal computer, server, or network device, etc.) to execute the methods of various implementation scenarios of this application.

[0095] like Figure 4 The diagram shown is a hardware structure schematic of an electronic device according to the present invention, comprising: At least one processor 401; and, Memory 402 is communicatively connected to at least one processor 401; wherein, The memory 402 stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the test address generation method as described above.

[0096] Figure 4 Take a processor 401 as an example.

[0097] The electronic device may also include an input device 403 and an output device 404.

[0098] The processor 401, memory 402, input device 403, and output device 404 can be connected via a bus or other means. Figure 4 Taking the example of a connection between China and Israel via a bus.

[0099] Memory 402, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules, such as the program instructions / modules corresponding to the test address generation method in the embodiments of this application, for example, Figure 1 and Figure 2The method flow is shown. The processor 401 executes various functional applications and terminal device processing by running non-volatile software programs, instructions, and modules stored in the memory 402, thereby implementing the test address generation method in the above embodiments.

[0100] Memory 402 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created according to the use of the test address generation method, etc. Furthermore, memory 402 may include high-speed random access memory and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 402 may optionally include memory remotely located relative to processor 401, and these remote memories may be connected via a network to the apparatus performing the test address generation method. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, processing networks of mobile terminal devices, and combinations thereof.

[0101] Input device 403 can receive user clicks and generate signal inputs related to user settings and function control for the test address generation method. Output device 404 may include display devices such as a display screen.

[0102] One or more modules are stored in memory 402, and when run by one or more processors 401, the test address generation method in any of the above method embodiments is executed.

[0103] Optionally, the aforementioned physical devices may also include a user interface, a network interface, a camera, radio frequency (RF) circuitry, sensors, audio circuitry, a Wi-Fi module, etc. The user interface may include a display screen, input units such as a keyboard, etc., and optional user interfaces may also include USB interfaces, card reader interfaces, etc. The network interface may optionally include standard wired interfaces, wireless interfaces (such as Wi-Fi interfaces), etc.

[0104] Those skilled in the art will understand that the physical device structure provided in this embodiment does not constitute a limitation on the physical device, and may include more or fewer components, or combine certain components, or have different component arrangements.

[0105] The storage medium may also include an operating system and a processing module for network terminal devices. The operating system is a program that manages the hardware and software resources of the aforementioned physical devices, supporting the operation of information processing programs and other software and / or programs. The processing module for network terminal devices is used to enable terminal device processing between the various components within the storage medium, as well as terminal device processing with other hardware and software within the information processing physical device.

[0106] Through the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms, or it can be implemented by hardware. By applying the solution of this embodiment, compared with the prior art, this application embodiment achieves the basic input of hardware specification parameters as test address generation by obtaining the cache capacity of the address cache area; by determining the distribution information of addresses in the address cache area in the address pages based on the cache capacity, the distribution association relationship between addresses and address pages is established; by generating multiple test addresses that can cover all address pages according to the distribution information, the comprehensiveness of test address coverage is improved; by responding to the functional test requirements of the address cache area under the target test scenario, the target test address of the appropriate scenario is selected for testing, realizing the test address adaptation to different test scenarios, and improving the reusability and verification efficiency of address cache area functional verification.

[0107] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the element.

[0108] The above are merely specific embodiments of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to these embodiments, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A method for generating a test address, characterized in that, include: Get the cache capacity of the address cache area; Based on the cache capacity, determine the distribution information of addresses in the address cache area within the address pages; Based on the distribution information, the bit segment distribution of the addresses in the address cache in the address pages is analyzed to determine the address page access type of the address cache. The address page access type includes at least one of the following: continuous access to the same address page, alternating access to different address pages, and replacement access when the number of address pages exceeds the cache capacity. Based on the target capacity occupancy status of the address cache, the target function test requirements corresponding to the target capacity occupancy status, and the address page access type, multiple test addresses are generated for the address cache, and the multiple test addresses can cover all the address pages. In response to performing functional testing on the address cache under the target test scenario, a target test address that is compatible with the target test scenario is selected from the plurality of test addresses, and the target test address is used to perform functional testing on the address cache.

2. The method according to claim 1, characterized in that, The method further includes: Based on the address page access type, the test address clusters for functional testing of the address cache and the target distribution positions of the test address clusters in the address page are determined. The test address clusters are used to determine the distribution positions of the multiple test addresses in the address page.

3. The method according to claim 2, characterized in that, Based on the target capacity occupancy status of the address cache, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type, multiple test addresses for the address cache are generated, including: Based on the cache capacity, determine the target capacity occupancy status of the address cache area, and analyze the target functional test requirements of the address cache area under the target capacity occupancy status. Based on the target function testing requirements and the test address cluster, the multiple test addresses are generated.

4. The method according to claim 3, characterized in that, The step of generating the multiple test addresses based on the target function test requirements and the test address cluster includes: Based on the target function testing requirements, determine the index identifier of the test address cluster; Based on the index identifier, determine the address page coverage range of the test address cluster in the address page, and generate the multiple test addresses.

5. The method according to claim 4, characterized in that, The step of determining the address page coverage range of the test address cluster in the address page according to the index identifier, and generating the plurality of test addresses, includes: Based on the index identifier, determine the address page coverage range of the test address cluster in the address page; The cache capacity, the address page coverage, and the page capacity of the address page are input into the constraint solver, and the constraint solver generates the multiple test addresses.

6. The method according to claim 1, characterized in that, The step of responding to perform functional testing on the address cache under the target test scenario, and selecting a target test address suitable for the target test scenario from the plurality of test addresses, includes: Obtain the target test scenario of the address cache area and determine the target test requirements of the target test scenario; Among the multiple test addresses, the test address that meets the target test requirements is determined as the target test address; According to the address access order of the target test scenario, the target test addresses are combined and sorted to obtain the target test address sequence of the address cache area; The address cache is functionally tested according to the target test address sequence.

7. A test address generation device, characterized in that, include: The acquisition module is configured to retrieve the cache capacity of the address cache area; The determination module is configured to determine the distribution information of addresses in the address cache in the address page based on the cache capacity; The analysis module is configured to analyze the bit segment distribution of addresses in the address cache in the address pages based on the distribution information, and determine the address page access type of the address cache. The address page access type includes at least one of continuous access to the same address page, alternating access to different address pages, and replacement access when the number of address pages exceeds the cache capacity. The generation module is configured to generate multiple test addresses for the address cache based on the target capacity occupancy status of the address cache, the target functional test requirements corresponding to the target capacity occupancy status, and the address page access type. The multiple test addresses can cover all the address pages. The selection module is configured to select a target test address from the plurality of test addresses that is compatible with the target test scenario in response to performing functional testing on the address cache under the target test scenario. The target test address is used to perform functional testing on the address cache.

8. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method of any one of claims 1 to 6.

9. An electronic device, comprising a storage medium, a processor, and a computer program stored on the storage medium and executable on the processor, characterized in that, When the processor executes the computer program, it implements the method of any one of claims 1 to 6.

10. A computer program product, the computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in any one of claims 1 to 6.

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