An inter-chip data exchange system and method

Abstract

The application relates to an inter-chip data exchange system and method, wherein a local shadow memory mapped with an external chip is arranged at a master chip end, and is divided into a DATA storage domain for storing low real-time data and a FLAG storage domain for storing high real-time data; meanwhile, a read / write flag bit and an interrupt logic circuit are configured, so that when a processor performs a read / write operation, the processor does not need to actively poll scheduling and frequently start a serial communication interface, but the serial communication interface is automatically triggered by the read / write flag bit, the processor only needs to read / write data from the local shadow memory, the chip running load is greatly reduced, and the computing power is released. Through the configurable interrupt logic circuit, the processor can be interrupted in time and respond when an abnormal state occurs on the external chip, the abnormal event response and processing speed are improved, the defects of high communication load and lagging response of existing chips are avoided, and the communication timeliness and reliability are improved.

Description

Technical Field

[0001] This invention relates to an inter-chip data exchange system and method, applicable to the field of data transmission technology. Background Technology

[0002] As automotive electronic and electrical architectures have evolved from distributed electronic control unit architectures to domain controller and area controller architectures, the number of external expansion chips connected to the main control chip has increased significantly. To reduce hardware design costs, improve system reliability, and simplify software development, the industry has developed peripheral chips that integrate various functional modules, such as IO expansion, analog-to-digital conversion, and sensor acquisition. The main control chip and peripheral chips primarily exchange register data through serial communication interfaces such as SPI, I2C, and UART. Currently, the mainstream interaction method is for the main control unit to actively initiate read and write operations, accessing the internal registers of the peripheral chip through a serial interface to complete parameter configuration and status acquisition. When the peripheral chip detects faults, parameter exceeding limits, or other anomalies, it can also actively upload raw register data for event reporting.

[0003] However, the existing communication architecture has significant drawbacks: First, to ensure continuous configuration effectiveness and real-time status synchronization, the main control chip needs to periodically and frequently poll the peripheral chip registers, repeatedly initialize the communication interface, send and receive data, and parse it. This frequent activation of the communication interface for data interaction consumes a large amount of core computing power, crowding out the bandwidth of the main business processing, resulting in high overall system load and limited scalability. Second, the abnormal event handling link is cumbersome and lacks real-time performance. The peripheral chip can only push raw register data and trigger only general interrupts, unable to distinguish between abnormal types and fault locations. After the main control chip responds to the interrupt, it still needs to rely on software logic to parse the data and determine the fault. The superposition of multiple processing steps results in significant delays, making it difficult to meet the high real-time fault handling requirements of the vehicle system. At the same time, the existing solution does not differentiate the real-time requirements of different data. The unified transmission and response mechanism cannot take into account both the transmission efficiency of ordinary configuration data and the response speed of emergency status flags, leaving considerable room for optimization in the overall architecture. Summary of the Invention

[0004] To address the shortcomings of the existing technology, this invention proposes an inter-chip data exchange system and method.

[0005] On one hand, this invention provides an inter-chip data exchange system, including a main control chip, peripheral chips, and a serial communication interface connecting the two. The main control chip includes a processor, a DATA storage field for storing low-real-time configuration data, and a FLAG storage field for storing high-real-time status flags, both connected to the processor. The DATA storage field includes several first memories, and the FLAG storage field includes several second memories. The addresses of the first memories and the addresses of the second memories are each mapped one-to-one to the register addresses of the peripheral chips. The main control chip also includes read flags corresponding one-to-one to the register addresses in the peripheral chips. The write flag and read flag are used to indicate whether the serial communication interface has written the data sent by the peripheral chip into the corresponding first memory or / and second memory. The write flag is also used to indicate whether the serial communication interface has transmitted the data written by the processor into the first memory or / and second memory to the peripheral chip. The FLAG memory field also includes an interrupt enable bit that corresponds one-to-one with the second memory and is used to trigger or block the interrupt signal sent by the second memory to the processor. Each status flag bit of the second memory and its corresponding interrupt enable bit are connected to an AND gate. The output of each pair of AND gates is connected to an OR gate. The output of all OR gates is connected to the processor.

[0006] By setting up a local shadow memory system on the main control chip that maps one-to-one with the register addresses of peripheral chips, and dividing the local shadow memory system into DATA and FLAG memory domains according to data real-time requirements, low-real-time configuration and regular data are stored in the DATA memory domain, while high-real-time status and alarm flags are stored in the FLAG memory domain. When the processor performs read and write operations, it only needs to access the local shadow memory. Updated data is uniformly sent and received by the serial communication interface, avoiding the computational power consumption caused by the processor frequently scheduling the serial communication interface, polling the status of peripheral chip registers, and participating in data transmission and reception. This frees up the processor's processing bandwidth for main business processing, reducing the overall machine's operating load. Furthermore, partitioning and storing data of different real-time requirements can balance the transmission efficiency of ordinary data and the response speed of abnormal status flags, greatly improving the efficiency of data interaction between chips.

[0007] By setting read and write flags, the serial communication interface can be automatically triggered by hardware logic, enabling automatic data transmission without processor intervention. Furthermore, the data transmission status can be marked so that the processor can poll and read the data, avoiding wasted computing power due to invalid reads. Specifically, the serial communication interface includes port modules located in the main control chip and peripheral chips. The read and write flags establish a handshake mechanism between the processor inside the main control chip and the serial communication interface port, thereby marking the data transmission status and automatically triggering the serial communication interface. Furthermore, since peripheral chips include multiple functional modules, but in practical applications only one or a few modules may need to be enabled, an interrupt enable bit corresponding to the second memory is set. This allows the processor to flexibly configure the level state of the interrupt enable bit corresponding to each module register according to requirements. Combined with AND gates and OR gates to form a logic circuit, when the abnormal flag data of the functional module is written to the corresponding second memory, the status flag of the second memory is set. Only when the interrupt enable bit corresponding to the second memory is also set will an interrupt signal be generated through an OR gate and sent to the processor. This allows the processor to respond to the interrupt in a timely manner and read and process the abnormal data in the corresponding second memory. By selectively configuring the interrupt enable bit and combining it with AND and OR gate logic circuits, invalid interrupts or interference signals can be accurately filtered, reducing unnecessary interrupt responses from the processor and lowering the operating load. At the same time, it can flexibly adapt to the configuration requirements of different application scenarios and improve system flexibility.

[0008] Furthermore, the first memory is built from static random access memory (SRAM). Using SRAM to carry low real-time configuration data can meet the needs of large-capacity storage while taking into account hardware costs.

[0009] Furthermore, the second memory, read flag, and write flag are all constructed using electronic triggers. The use of triggers enables high-speed storage of flags and status bits, providing extremely fast response speed and ensuring timely transmission of high real-time signals.

[0010] Furthermore, the main control chip also includes trigger circuits connected between the serial communication interface and the read flag bit, and between the serial communication interface and the write flag bit, respectively. When the trigger circuit detects that the write flag bit is set, it triggers the serial communication interface to transmit data corresponding to the first memory and / or the second memory, and resets the write flag bit after the transmission is completed. When the serial communication interface receives data uploaded by the peripheral chip, the trigger circuit sets the corresponding read flag bit and resets the read flag bit after the data is written to the serial communication interface. Specifically, the trigger circuit includes a synchronous finite state machine-based main control circuit, combined with a flag bit detection logic circuit, a serial interface handshake logic circuit, and a flag bit driving logic circuit, thereby realizing the triggering and control of the write and read flag bits and the serial communication interface.

[0011] Furthermore, the main control chip also includes an address decoding module for selecting the corresponding address of the first memory, the second memory, the read flag, or the write flag based on the register address decoding. The address decoding module is connected to the processor, the first memory, the second memory, the read flag, and the write flag, respectively. Specifically, the address decoding module uses an AND gate array to form a combinational logic unit to achieve address decoding and selection, thereby achieving accurate addressing during data transmission and preventing transmission crosstalk.

[0012] Furthermore, the main control chip also includes write detection modules connected between the first memory and the corresponding write flag bit, and between the second memory and the corresponding write flag bit. When a write enable pulse is generated in the first memory and / or the second memory, the write detection module sets the corresponding write flag bit. Specifically, the write detection module uses two cascaded D flip-flops and an AND gate to form a digital sequential logic circuit, so as to detect the pulse signal generated when the processor writes data to the first memory or the second memory, thereby triggering the setting of the write flag bit, so as to provide a basis for the implementation of subsequent automatic transfer logic.

[0013] On the other hand, the present invention also provides a chip-to-chip data exchange method, applied to the above-mentioned data exchange system, the method comprising: Main control chip write: When the processor initiates a write operation to a register address in a peripheral chip, it synchronously writes the data to the first and second memories corresponding to the register address and sets the corresponding write flag. When the write flag is set, the serial communication interface is triggered, and the data to be sent from the first or second memory corresponding to the write flag is transmitted to the peripheral chip through the serial communication interface. After the transmission is completed, the corresponding write flag is reset, and the peripheral chip writes the data to the corresponding register. When the processor sends data to the peripheral chip, it writes the data to be sent to the corresponding first and second memories and sets the corresponding write flag after writing. The setting of the write flag triggers the serial communication interface to transmit automatically, without the need for active scheduling by the processor, effectively reducing the processor load. After the transmission is completed, the write flag is automatically reset, which facilitates the processor to perform write operations again later. Furthermore, when the processor writes the data to be sent to the same register address to both the DATA memory domain and the FLAG memory domain at the same time, the serial communication interface prioritizes the transmission of data in the FLAG memory domain. When only the data in the DATA memory domain is updated, the data in the DATA memory domain is transmitted first.

[0014] Main control chip reads: Peripheral chips send their register return data to the serial communication interface. The serial communication interface parses the register address corresponding to the return data and sets the corresponding read flag. Then, it transmits the return data and writes it to the corresponding first memory. After writing, it resets the read flag. When the processor needs to read the return data, it only accesses the corresponding first memory. When peripheral chips return configuration data with low real-time requirements, the serial communication interface transmits the configuration data and writes it to the corresponding first memory. Before and after writing, it sets and resets the corresponding read flag. When the processor is idle, it polls each first memory in the DATA storage domain, sets and resets the read flag corresponding to the first memory, and reads the data in the first memory. The data is read through the local shadow memory without actively initiating bus access. At the same time, the read flag verifies the validity of the data, which not only reduces the processor load but also improves the reliability of data reading.

[0015] Peripheral chip reports anomalies: The processor pre-configures interrupt enable bits according to user requirements, setting the required interrupt enable bits to "1" and the remaining interrupt enable bits to "0". When the peripheral chip detects a register anomaly, it sends the anomaly data to the serial communication interface. The serial communication interface parses the register address corresponding to the anomaly data and sets the corresponding read flag bit, then transmits the anomaly data and writes it to the corresponding second memory. After writing, it resets the read flag bit and sets the status flag bit of the corresponding second memory to "1". When the status flag bit of the second memory is set to "1" and its corresponding interrupt enable bit is set to "1", the corresponding OR gate generates an interrupt signal and sends it to the processor. After receiving the interrupt signal, the processor reads the anomaly data in the corresponding second memory, processes it, updates the second memory, and sets the corresponding write flag bit. The serial communication interface and the peripheral chip write the processed data to the corresponding register according to the steps written by the main control chip. Specifically, setting "1" indicates that the flag bit is high, and setting "0" indicates that the flag bit is high. This indicates that the flag position is low. When an abnormal event occurs in the internal functional module of the peripheral chip, the abnormal data is packaged into high real-time data and sent back. This abnormal data is transmitted through the serial communication interface and written to the corresponding second memory in the FLAG storage domain. At the same time, the corresponding read flag bit marks the write status. After the write is completed, the status flag bit of the second memory is set to high. The hardware logic automatically detects whether the interrupt enable bit corresponding to the second memory is set to high beforehand. When both are set to high, an interrupt signal is generated and sent to the processor so that the processor can respond to the interrupt and process the abnormal data in the second memory. Through the configurable interrupt enable bit and the corresponding logic circuit, timely response and processing of abnormal events can be achieved, shortening the abnormal response link and improving the efficiency of abnormal processing. Furthermore, through the on-demand configurable interrupt enable bit, invalid interrupts can be filtered, improving adaptability flexibility.

[0016] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art: The chip-to-chip data exchange system and method of this invention establishes a local shadow memory mapped to the peripheral chip on the main control chip, dividing the shadow memory into a DATA storage domain for storing low real-time data and a FLAG storage domain for storing high real-time data. Simultaneously, read / write flags and interrupt logic circuits are configured. This allows the processor to automatically trigger the serial communication interface during read / write operations without actively polling or frequently starting the serial communication interface. The processor only needs to read and write data from the local shadow memory, significantly reducing the chip's workload and freeing up computing power. Furthermore, the configurable interrupt logic circuits can promptly interrupt the processor and respond when the peripheral chip uploads an abnormal status, improving the response and processing speed of abnormal events and avoiding the high load and delayed response defects of existing chip-to-chip communication, thus improving communication timeliness and reliability. Attached Figure Description

[0017] The following sections will describe some specific embodiments of the invention in a detailed manner, by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar components or parts. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic diagram of the system architecture of one embodiment of the present invention; Figure 2 yes Figure 1 The schematic diagram of the DATA storage domain in the illustrated embodiment; Figure 3 yes Figure 1 The illustrated embodiment is a schematic diagram of the FLAG storage domain architecture.

[0018] The annotations in the attached figures are explained as follows: 1. Main control chip; 11. Processor; 12. DATA storage area; 121. First memory; 13. FLAG storage area; 131. Second memory; 132. Interrupt enable bit; 14. Read flag bit; 15. Write flag bit; 2. Peripheral chip; 3. Serial communication interface. Detailed Implementation

[0019] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] In the description of this invention, it should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; furthermore, the technical features involved in the different embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0021] Reference Appendix Figures 1-3 On one hand, the inter-chip data exchange system in this embodiment includes a main control chip 1, a peripheral chip 2, and a serial communication interface 3 connecting the two. The main control chip 1 includes a processor 11, a DATA storage field 12 for storing low real-time configuration data and a FLAG storage field 13 for storing high real-time status flags, both connected to the processor 11. The DATA storage field 12 includes several first memories 121, and the FLAG storage field 13 includes several second memories 131. The addresses of the several first memories 121 and the several second memories 131 are respectively connected to the register addresses of the peripheral chip 2 (as shown in the attached diagram). Figure 2 , 3 (As shown in the reference numeral a) One-to-one mapping; the main control chip 1 also includes a read flag bit 14 and a write flag bit 15 that correspond one-to-one with the addresses of each register in the peripheral chip 2. The read flag bit 14 is used to indicate whether the serial communication interface 3 has written the data sent by the peripheral chip 2 into the corresponding first memory 121 or / and second memory 131. The write flag bit 15 is used to indicate whether the serial communication interface 3 has transmitted the data written by the processor 11 into the first memory 121 or / and second memory 131 to the peripheral chip 2. The FLAG storage field 13 also includes an interrupt enable bit 132 that corresponds one-to-one with the second memory 131 and is used to trigger or block the interrupt signal sent by the second memory 131 to the processor 11. The status flag bit of each second memory 131 and its corresponding interrupt enable bit 132 are respectively connected to an AND gate. The output of each pair of AND gates is connected to an OR gate. The output of all OR gates is connected to the processor 11.

[0022] By setting up a local shadow memory system at the main control chip 1 that maps one-to-one with the register addresses of peripheral chip 2, and dividing the local shadow memory system into DATA storage domain 12 and FLAG storage domain 13 according to data real-time performance, low real-time configuration and regular data are stored in DATA storage domain 12, while high real-time status and alarm flags are stored in FLAG storage domain 13. When the processor 11 performs read and write operations, it only needs to access the local shadow memory. Updated data is uniformly sent and received by the serial communication interface 3, avoiding the computing power consumption caused by the processor 11 frequently scheduling the serial communication interface 3, polling the register status of peripheral chip 2, and participating in data transmission and reception. This frees up the processor 11's processing bandwidth for main business processing, reducing the overall machine's operating load. Furthermore, partitioning and storing data of different real-time performance can balance the transmission efficiency of ordinary data and the response speed of abnormal status flags, greatly improving the efficiency of data interaction between chips.

[0023] By setting read and write flags, the serial communication interface 3 can be automatically triggered by hardware logic, thus enabling automatic data transmission without the intervention of the processor 11. Furthermore, the data transmission status can be marked so that the processor 11 can poll and read the data, avoiding wasted computing power due to invalid reads. Specifically, the serial communication interface 3 includes port modules respectively located in the main control chip 1 and the peripheral chip 2. The read flag 14 and write flag 15 establish a handshake mechanism between the processor 11 inside the main control chip 1 and the port of the serial communication interface 3, thereby enabling the marking of the data transmission status and the automatic triggering of the serial communication interface 3. Furthermore, since peripheral chip 2 includes multiple functional modules, but in actual applications only one or a few modules may need to be enabled, an interrupt enable bit 132 corresponding to the second memory 131 is set. This allows the processor 11 to flexibly configure the level state of the interrupt enable bit 132 corresponding to each module register according to requirements, and to form a logic circuit with AND gates and OR gates. When the abnormal flag data of the functional module is written to the corresponding second memory 131, the status flag of the second memory 131 is set. Only when the interrupt enable bit 132 corresponding to the second memory 131 is also set will an interrupt signal be generated through an OR gate and sent to the processor 11, so that the processor 11 can respond to the interrupt in time and read and process the abnormal data of the corresponding second memory 131. By selectively configuring the interrupt enable bit 132 and cooperating with the AND and OR gate logic circuit, invalid interrupts or interference signals can be accurately filtered, reducing unnecessary interrupt responses of the processor 11 and reducing the operating load. At the same time, it can flexibly adapt to the configuration requirements of different application scenarios and improve system flexibility.

[0024] In a more preferred embodiment, the first memory 121 is constructed from static random access memory (SRAM). Using SRAM to carry low real-time configuration data can meet the needs of large-capacity storage while taking into account hardware costs.

[0025] In a more preferred embodiment, the second memory 131, the read flag bit 14, and the write flag bit 15 are all constructed using electronic triggers. The use of triggers enables high-speed storage of flag bits and status bits, providing extremely fast response speed and ensuring timely transmission of high real-time signals.

[0026] In a more preferred embodiment, the main control chip 1 further includes trigger circuits (not shown in the figures) connected between the serial communication interface 3 and the read flag 14 and between the serial communication interface 3 and the write flag 15, respectively. When the trigger circuit detects that the write flag 15 is set, it triggers the serial communication interface 3 to transmit data corresponding to the first memory 121 and / or the second memory 131, and resets the write flag 15 after the transmission is completed. When the serial communication interface 3 receives data uploaded by the peripheral chip 2, the trigger circuit sets the corresponding read flag 14 and resets the read flag 14 after the data is written to the serial communication interface 3. Specifically, the trigger circuit includes a synchronous finite state machine-based main control circuit, combined with a flag detection logic circuit, a serial interface handshake logic circuit, and a flag drive logic circuit, thereby realizing the triggering and control of the write and read flags and the serial communication interface.

[0027] In a more preferred embodiment, the main control chip 1 further includes an address decoding module (not shown in the figures) for selecting the corresponding address of the first memory 121, the second memory 131, the read flag 14, or the write flag 15 based on the register address decoding. The address decoding module is connected to the processor 11, the first memory 121, the second memory 131, the read flag 14, and the write flag 15, respectively. Specifically, the address decoding module uses an AND gate array to form a combinational logic unit to achieve address decoding and selection, thereby achieving accurate addressing during data transmission and preventing transmission crosstalk.

[0028] In a more preferred embodiment, the main control chip 1 further includes a write detection module (not shown in the figures) connected between the first memory 121 and the corresponding write flag 15, and between the second memory 131 and the corresponding write flag 15. When a write enable pulse is generated in the first memory 121 and / or the second memory 131, the write detection module sets the corresponding write flag 15. Specifically, the write detection module forms a digital sequential logic circuit with two cascaded D flip-flops and an AND gate to detect the pulse signal generated when the processor 11 writes data to the first memory 121 or the second memory 131, thereby triggering the setting of the write flag 15 to provide a basis for the implementation of subsequent automatic transfer logic.

[0029] On the other hand, an inter-chip data exchange method in this embodiment is applied to the above-mentioned data exchange system, and the method includes: When the main control chip 1 writes data to a register address in the peripheral chip 2, the processor 11 synchronously writes the data to be sent to the first memory 121 and the second memory 131 corresponding to the register address and sets the corresponding write flag 15. When the write flag 15 is set, the serial communication interface 3 is triggered, and the data to be sent from the first memory 121 or the second memory 131 corresponding to the write flag 15 is transmitted to the peripheral chip 2 through the serial communication interface 3. After the transmission is completed, the corresponding write flag 15 is reset, and the peripheral chip 2 writes the data to be sent to the corresponding register. When the processor 11 sends data to the peripheral chip 2, it writes the data to be sent to the corresponding first memory. The processor 121 and the second memory 131 are connected, and the write flag 15 corresponding to the write bit is set after the write operation. The serial communication interface 3 is automatically transmitted by setting the write flag 15, which does not require active scheduling by the processor 11, effectively reducing the processor load. After the transmission is completed, the write flag 15 is automatically reset, which makes it convenient for the processor 11 to perform write operations again. Furthermore, when the processor 11 writes the data sent to the same register address into the DATA memory domain 12 and the FLAG memory domain 13 at the same time, the serial communication interface 3 prioritizes the transmission of the data in the FLAG memory domain 13. When only the data in the DATA memory domain 12 is updated, the data in the DATA memory domain 12 is transmitted first.

[0030] The main control chip 1 reads data from the peripheral chip 2, which sends the data returned from its registers to the serial communication interface 3. The serial communication interface 3 parses the register address corresponding to the returned data and sets the corresponding read flag 14. Then, it transmits the returned data and writes it into the corresponding first memory 121. After writing, it resets the read flag 14. When the processor 11 needs to read the returned data, it only accesses the corresponding first memory 121 to read it. When the peripheral chip 2 returns configuration data with low real-time requirements, the serial communication interface 3 returns the configuration data and writes it into the corresponding first memory 121. Before and after writing, it sets and resets the corresponding read flag 14. When the processor 11 is idle, it polls each first memory 121 in the DATA storage domain 12 and reads the data in the first memory 121 after setting and resetting the read flag 14 corresponding to the first memory 121. The data is read through the local shadow memory without actively initiating bus access. At the same time, the validity of the data is verified by the read flag, which not only reduces the processor load but also improves the reliability of data reading.

[0031] Peripheral chip 2 reports an anomaly: Processor 11 pre-configures interrupt enable bits 132 according to user requirements, setting the required interrupt enable bits 132 to "1" and the remaining interrupt enable bits 132 to "0"; when peripheral chip 2 detects a register anomaly, it sends its anomaly data to serial communication interface 3. Serial communication interface 3 parses the register address corresponding to the anomaly data and sets the corresponding read flag bit 14, then transmits the anomaly data and writes it to the corresponding second memory 131. After writing is complete, it resets the read flag bit 14 and sets the status flag of the corresponding second memory 131 to "0". When the status flag of the second memory 131 is set to "1" and its corresponding interrupt enable bit 132 is set to "1", the corresponding OR gate generates an interrupt signal and sends it to the processor 11. After receiving the interrupt signal, the processor 11 reads the abnormal data in the corresponding second memory 131, processes it, and updates the second memory 131. At the same time, it sets the corresponding write flag bit 15. The serial communication interface 3 and the peripheral chip 2 write the processed data to the corresponding register according to the steps written by the main control chip 1. Specifically, setting "1" indicates that the flag is at a high level, and setting "0" indicates that the flag is at a high level. This indicates that the flag position is low. When an abnormal event occurs in the internal functional module of peripheral chip 2, the abnormal data is packaged into high real-time data and sent back. This abnormal data is transmitted by serial communication interface 3 and written into the corresponding second memory 131 in FLAG storage domain 13. At the same time, the corresponding read flag bit 14 marks the write status. After the write is completed, the status flag bit of the second memory 131 is set to high level. The hardware logic automatically detects whether the interrupt enable bit 132 corresponding to the second memory 131 is set to high level in advance. When both are set to high level, an interrupt signal is generated and sent to processor 11 so that processor 11 can respond to the interrupt and process the abnormal data in the second memory 131. Through the configurable interrupt enable bit 132 and the supporting logic circuit, timely response and processing of abnormal events can be realized, shortening the abnormal response link and improving the efficiency of abnormal processing. Furthermore, through the on-demand configured interrupt enable bit, invalid interrupts can be filtered, improving the adaptability flexibility.

[0032] Due to the application of the above technical solution, the present invention has the following advantages compared with the prior art: The chip-to-chip data exchange system and method of this invention establishes a local shadow memory mapped to the peripheral chip on the main control chip, dividing the shadow memory into a DATA storage domain for storing low real-time data and a FLAG storage domain for storing high real-time data. Simultaneously, read / write flags and interrupt logic circuits are configured. This allows the processor to automatically trigger the serial communication interface during read / write operations without actively polling or frequently starting the serial communication interface. The processor only needs to read and write data from the local shadow memory, significantly reducing the chip's workload and freeing up computing power. Furthermore, the configurable interrupt logic circuits can promptly interrupt the processor and respond when the peripheral chip uploads an abnormal status, improving the response and processing speed of abnormal events and avoiding the high load and delayed response defects of existing chip-to-chip communication, thus improving communication timeliness and reliability.

[0033] The above embodiments are only for illustrating the technical concept and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A chip-to-chip data exchange system, characterized in that: The system includes a main control chip (1), a peripheral chip (2), and a serial communication interface (3) connecting the two. The main control chip (1) includes a processor (11), a DATA storage field (12) for storing low real-time configuration data and a FLAG storage field (13) for storing high real-time status flags, which are respectively connected to the processor (11). The DATA storage field (12) includes a plurality of first memories (121), and the FLAG storage field (13) includes a plurality of second memories (131). The addresses of the plurality of first memories (121) and the addresses of the plurality of second memories (131) are respectively mapped one-to-one with the register addresses of the peripheral chip (2). The main control chip (1) also includes a read flag (14) and a write flag (15) that correspond one-to-one with the addresses of each register in the peripheral chip (2). The read flag (14) is used to indicate whether the serial communication interface (3) has written the data sent by the peripheral chip (2) into the corresponding first memory (121) or / and second memory (131). The write flag (15) is used to indicate whether the serial communication interface (3) has transmitted the data written by the processor (11) into the first memory (121) or / and second memory (131) to the peripheral chip (2). The FLAG storage domain (13) also includes an interrupt enable bit (132) that corresponds one-to-one with the second memory (131) and is used to trigger or block the interrupt signal sent by the second memory (131) to the processor (11). The status flag bit of each second memory (131) and its corresponding interrupt enable bit (132) are respectively connected to an AND gate. The output of each pair of AND gates is connected to an OR gate. The output of all OR gates is connected to the processor (11).

2. The inter-chip data exchange system according to claim 1, characterized in that: The first memory (121) is constructed from a static random access memory.

3. The inter-chip data exchange system according to claim 1, characterized in that: The second memory (131), read flag (14) and write flag (15) are all constructed using electronic triggers.

4. The inter-chip data exchange system according to claim 1, characterized in that: The main control chip (1) also includes a trigger circuit connected between the serial communication interface (3) and the read flag (14) and between the serial communication interface (3) and the write flag (15). When the trigger circuit detects that the write flag (15) is set, it triggers the serial communication interface (3) to transmit the data in the corresponding first memory (121) and / or second memory (131), and resets the write flag (15) after the transmission is completed. When the serial communication interface (3) receives the data uploaded by the peripheral chip (2), the trigger circuit sets the corresponding read flag (14) and resets the read flag (14) after the serial communication interface (3) has written the data.

5. The inter-chip data exchange system according to claim 1, characterized in that: The main control chip (1) also includes an address decoding module for selecting the corresponding address of the first memory (121), the second memory (131), the read flag (14) or the write flag (15) according to the register address decoding. The address decoding module is connected to the processor (11), the first memory (121), the second memory (131), the read flag (14) and the write flag (15) respectively.

6. The inter-chip data exchange system according to claim 1, characterized in that: The main control chip (1) further includes a write detection module connected between the first memory (121) and the corresponding write flag (15) and the second memory (131) and the corresponding write flag (15). When a write enable pulse is generated in the first memory (121) or / and the second memory (131), the write detection module sets the corresponding write flag (15).

7. A method for inter-chip data exchange, characterized in that, The method, applied to the data exchange system according to any one of claims 1 to 6, comprises: The main control chip (1) writes: When the processor (11) initiates a write operation for the register address in the peripheral chip (2), it synchronously writes the data to the first memory (121) and the second memory (131) corresponding to the register address and sets the corresponding write flag (15). When the write flag (15) is set, the serial communication interface (3) is triggered, and the data to be sent from the first memory (121) or the second memory (131) corresponding to the write flag (15) is transmitted to the peripheral chip (2) through the serial communication interface (3). After the transmission is completed, the corresponding write flag (15) is reset, and the peripheral chip (2) writes the data to the corresponding register. The main control chip (1) reads: The peripheral chip (2) sends the return data of its register to the serial communication interface (3). The serial communication interface (3) parses the register address corresponding to the return data and sets the corresponding read flag bit (14). Then, it transmits the return data and writes it into the corresponding first memory (121). After writing, it resets the read flag bit (14). When the processor (11) needs to read the return data, it only accesses the corresponding first memory (121) to read it. The peripheral chip (2) reports an anomaly: The processor (11) pre-configures the interrupt enable bit (132) according to user requirements, sets the required interrupt enable bit (132) to "1", and sets the remaining interrupt enable bits (132) to "0"; when the peripheral chip (2) detects a register anomaly, it sends its anomaly data to the serial communication interface (3), the serial communication interface (3) parses the register address corresponding to the anomaly data and sets the corresponding read flag bit (14), then transmits the anomaly data and writes it to the corresponding second memory (131), after writing is completed, resets the read flag bit (14) and sets the corresponding second memory (131). When the status flag of the second memory (131) is set to "1" and the corresponding interrupt enable bit (132) is set to "1", the corresponding OR gate generates an interrupt signal and sends it to the processor (11). After receiving the interrupt signal, the processor (11) reads the abnormal data in the corresponding second memory (131), processes it, updates it to the second memory (131), and sets the corresponding write flag bit (15). The serial communication interface (3) and the peripheral chip (2) write the processed data to the corresponding register according to the steps written by the main control chip (1).

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