A microprocessor automatic layout optimization method considering power budget

Abstract

The present application belongs to the field of integrated circuit physical design and microprocessor power-thermal collaborative optimization, and proposes a microprocessor automatic layout optimization method considering power budget. The method generates microprocessor function module level candidate layout under the constraints of area utilization rate and temperature threshold, and carries out geometric legality screening. Based on the steady-state thermal model, the allowable layout related power budget of the candidate layout under the temperature threshold is solved, and the sustainable running frequency is mapped. Combined with the geometric distance change and running frequency of the key interconnection path, the cycle level additional overhead is calculated, and the online performance evaluation index is constructed. The evaluation index is embedded into the heuristic search algorithm, and the microprocessor layout satisfying the area and thermal constraints is output. The present application can improve the consistency of layout search target and final performance verification result, and reduce the static index evaluation deviation.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit physical design, microprocessor architecture modeling, power consumption and thermal co-optimization, and automatic layout planning. In particular, it relates to an automatic layout optimization method for microprocessors based on power budget solving, sustainable operating frequency mapping, and cycle-level interconnection overhead evaluation under temperature threshold and area utilization constraints. Background Technology

[0002] As the integration and power density of high-performance microprocessors continue to increase, the spatial power consumption distribution, heat dissipation paths, and interconnect delays of internal functional modules have an increasingly significant impact on system performance and reliability. For single-core out-of-order microprocessors, there are complex data and control path relationships between functional modules such as instruction fetch / decode, branch prediction, scheduling queue, reorder buffer, register file, execution unit, load storage unit, and multi-level cache. Layout planning that alters the relative positions of these modules not only affects traditional physical parameters such as trace length and area but also changes thermal diffusion conditions, module-level available power space, and cycle-level delay overhead of critical interconnect paths.

[0003] Existing microprocessor layout planning methods typically use area, line length, peak temperature, temperature gradient, or a weighted sum thereof as the evaluation criteria for candidate layouts. While these static surrogate metrics can reflect physical implementation costs and thermal safety to some extent, they cannot directly characterize the operating frequency that a candidate layout can ultimately maintain under temperature threshold constraints, nor can they effectively depict the impact of layout changes on the cycle-level performance of the processor pipeline.

[0004] Specifically, even if a candidate layout has a low peak temperature, the increased distance between critical modules may introduce additional cycle delays, leading to a decrease in the number of instructions per cycle. Conversely, even if a candidate layout has a short line length, localized heat concentration may reduce its frequency of sustainable operation under the thermal threshold. Therefore, relying solely on static indicators such as line length or peak temperature to evaluate candidate layouts can easily lead to inconsistencies between the search target and the final sustainable performance.

[0005] Therefore, there is a need for an automatic layout optimization method that can simultaneously consider temperature threshold, power budget, sustainable frequency and cycle-level interconnection overhead during the layout search process, so that the evaluation of candidate layouts is more directly oriented towards the sustainable performance target under thermal constraints, and improves the consistency between the layout search results and the final performance verification results. Summary of the Invention

[0006] The purpose of this invention is to provide an automatic microprocessor layout optimization method that considers power budget, addressing the problem that existing layout planning methods mainly rely on static surrogate indicators such as area, line length, and peak temperature, which are difficult to directly reflect the sustainable performance of candidate layouts under temperature threshold constraints. This method introduces power budget solving under temperature thresholds, sustainable operating frequency mapping, and cycle-level interconnection overhead evaluation into the layout search process, thereby obtaining a functional module-level layout with better sustainable performance under area utilization and thermal constraints.

[0007] To achieve the above objectives, the present invention adopts the following technical solution. First, the functional module set, module area, power consumption parameters, critical interconnection path set, reference layout, area utilization threshold, and temperature threshold of the microprocessor to be laid out are obtained, and a unified mapping relationship is established from logic modules to physical functional blocks, power consumption items, and heat source units.

[0008] Secondly, candidate layouts are generated using layout coding methods such as normalized Polish notation, and geometric construction is performed based on the coding results to obtain the coordinates of each module, module size, chip outer contour area, and geometric distance between modules. Candidate layouts are then screened based on geometric validity, area utilization, and shape constraints. Only candidate layouts that pass the hard constraint screening proceed to subsequent power consumption and thermal evaluation and performance assessment.

[0009] Next, a steady-state thermal model is constructed for the candidate layouts selected through constraint screening. The steady-state temperature distribution is calculated based on the module-level power consumption vector and thermal resistance relationship. Using a given temperature threshold as the peak temperature constraint, the maximum power budget allowed for the layout under that temperature threshold is derived. This power budget varies with the layout's thermal diffusion conditions and power consumption spatial distribution, thus characterizing the power carrying capacity of the candidate layout under thermal constraints.

[0010] Then, based on the dynamic voltage-frequency regulation relationship, the layout-related power budget is mapped to a sustainable operating frequency. The sustainable operating frequency is used to characterize the upper bound of the operating frequency that the candidate layout can maintain over a long period of time under temperature threshold constraints.

[0011] Furthermore, based on the geometric distance variation of the critical interconnect path, the interconnect propagation delay variation of the candidate layout relative to the reference layout is calculated, and the continuous time delay is mapped to periodic overhead in conjunction with the sustained operating frequency. Based on the additional periodic delay of the critical path and the calibrated performance sensitivity weights, the performance degradation term corresponding to the candidate layout is calculated.

[0012] Finally, an online performance evaluation index is constructed by combining the sustainable operating frequency and performance degradation term. This index is then used as the cost function for heuristic search algorithms such as simulated annealing. Neighborhood perturbation, constraint screening, cost evaluation, and acceptance determination are performed until the termination condition is met, at which point the optimized layout is output.

[0013] Compared with the prior art, the present invention has the following innovations: First, this invention no longer indirectly evaluates candidate layouts solely based on static indicators such as line length, area, or peak temperature. Instead, it infers the layout-related power budget of the candidate layout from the temperature threshold and further maps it to obtain the sustainable operating frequency, enabling the layout evaluation to directly reflect the performance potential under thermal constraints.

[0014] Second, this invention further maps the continuous time delay of critical interconnect paths into periodic overhead, thereby characterizing the real performance impact of layout changes during processor pipeline execution and avoiding the problem that low-temperature layouts or short-line long layouts may not necessarily be optimal in final performance.

[0015] Third, this invention connects candidate layout generation, performance statistics, power consumption decomposition, thermal evaluation, frequency verification and final performance verification into the same evaluation framework through a unified module mapping relationship, thereby improving the consistency and reproducibility of the multi-toolchain collaborative optimization process.

[0016] Fourth, the present invention first performs geometric validity and area utilization hard constraint screening during the layout search process, and then performs power consumption and thermal evaluation and performance evaluation, which can reduce the computational overhead caused by invalid candidate layouts and improve search efficiency. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the overall process of the automatic layout optimization method for microprocessors that takes power budget into account, provided in an embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the process for solving the layout-related power budget and mapping the sustainable operating frequency based on the temperature threshold in an embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram illustrating the process of constructing online performance evaluation indicators based on sustainable operating frequency and periodic interconnection overhead in an embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the layout search process based on normalized Polish notation and simulated annealing in an embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of a cross-tool consistency joint evaluation framework in an embodiment of the present invention. Detailed Implementation

[0024] like Figure 1 As shown, this embodiment provides an automatic layout optimization method for microprocessors that considers power budget. This method takes the layout of microprocessor functional modules as the optimization object, and under given temperature thresholds and area utilization constraints, uses sustainable performance as the evaluation target for candidate layouts.

[0025] Step S1: Input the set of functional modules of the microprocessor to be laid out. Each functional module With area parameters Candidate aspect ratio range, reference power consumption parameters and the set of key interconnect paths related to performance. Set of critical interconnection paths This can include pipeline performance-sensitive module interaction paths such as branch prediction to instruction fetch, instruction fetch to decoding, decoding to renaming, scheduling queue to execution unit, execution unit to register file, and execution unit to load storage unit.

[0026] Step S2: Generate candidate layouts using layout encoding. The position coordinates of each module are obtained through geometric construction. ,size and chip outer contour area Calculate the area utilization rate. and judge Does it fall within the preset area utilization constraint range? If a candidate layout has overlapping modules, exceeds the boundary, or does not meet the area utilization constraint, then the candidate layout is directly rejected.

[0027] Step S3: Perform steady-state thermal evaluation on the candidate layouts that have passed the constraint screening. Module-level power consumption vectors are then used. Mapped to a heat source vector and processed through a steady-state thermal model Obtain the temperature vector ,in Representation and candidate layout The relevant equivalent thermal resistance relationship, Indicates ambient temperature.

[0028] Step S4, using a temperature threshold To constrain the power budget, solve for the maximum allowable power of the candidate layout. ,make This power budget reflects the maximum power level that the candidate layout can handle under current thermal conditions.

[0029] Step S5, based on power budget Solving for the sustainable operating frequency of candidate layouts using dynamic voltage-frequency regulation In one implementation, the following is adopted: The approximate relationship, where For reference frequency, For reference power consumption, This is the frequency power scaling factor.

[0030] Step S6, combined Calculate additional cycle delay based on delay variations in critical interconnect paths. For critical interconnect paths If its interconnect latency in the candidate layout is The interconnect delay in the reference layout is Then, according to Alternatively, calculate the cycle-level overhead in an equivalent form.

[0031] Step S7, based on the additional cycle delay and performance sensitivity weights of multiple critical paths. Computational performance degradation terms .

[0032] Step S8: Construct online performance evaluation metrics. For example, the sustainability performance of a candidate layout can be expressed as... Alternatively, it can be equivalently transformed into a cost function to be minimized. ,in Used to describe constraint violations or engineering constraint penalties.

[0033] Step S9: Embed the above evaluation index into simulated annealing or other heuristic search algorithms, iteratively generate candidate layouts, perform hard constraint screening, calculate cost value, and update the current solution and historical best solutions according to the acceptance criteria, and finally output the optimal or near-optimal layout scheme.

[0034] Example 2: Power Budget and Sustainable Frequency Solution like Figure 2 As shown, this embodiment further illustrates the implementation of steps S3 to S5. For candidate layouts... First, a steady-state thermal model is constructed based on the module's geometric location and package heat dissipation parameters. The steady-state thermal model can be implemented using a compact thermal resistance network, a mesh thermal model, or other equivalent models.

[0035] In one implementation, let the normalized power consumption distribution corresponding to the candidate layout be... Using proportional coefficient Scaling the power consumption yields Calculated based on the steady-state thermal model and with Solving for boundary conditions Therefore, we can conclude that... .

[0036] get Then, the sustainable operating frequency is solved using the dynamic voltage-frequency regulation relationship. This relationship can be replaced with a monotonic mapping function based on the specific process, voltage-frequency curve, or chip power consumption model.

[0037] Therefore, the candidate layout not only has static indicators such as geometric area, line length and peak temperature, but also has a sustainable operating frequency indicator directly derived from the temperature threshold constraint.

[0038] Example 3: Cycle-level interconnect overhead and online performance evaluation like Figure 3 As shown, this embodiment further illustrates the calculation of the periodic additional overhead of critical interconnect paths. For each critical interconnect path... The path propagation delay is estimated based on the geometric center distance between the source and target modules in the candidate layout, the interconnection delay coefficient, and the necessary buffer delay. .

[0039] Since microprocessor performance is ultimately reflected at the clock cycle granularity, this embodiment maps continuous time delays to integer cycle delays. For operating frequency... ,path The periodic delay can be expressed as The additional cycle delay relative to the reference layout is... .

[0040] To ensure that online evaluation metrics are more consistent with actual workload performance, this embodiment uses delayed injection calibration experiments to obtain the sensitivity weight of each critical path to IPC or IPS. For multiple benchmark programs, results can be obtained separately for each workload. The workload weights are obtained by arithmetic or weighted averaging.

[0041] Ultimately, the performance degradation term of the candidate layout is represented by the weighted sum of the additional cycle delays of each critical path, and the online performance evaluation metric is determined jointly by the sustainable operating frequency and the performance degradation term. This avoids simply pursuing a high sustainable frequency while ignoring the critical path cycle boundary effect, and also avoids simply pursuing short-term longevity while ignoring the frequency limitation under the hot threshold.

[0042] Example 4: Simulated Annealing Search Implementation like Figure 4As shown, this embodiment uses the simulated annealing algorithm to perform layout search. The initial state is represented by normalized Polish notation, and an initial candidate layout is obtained after geometric construction. Each iteration generates neighborhood candidate solutions by swapping adjacent module symbols, changing the cutting direction, swapping sub-expressions, or locally rewriting.

[0043] For each neighborhood candidate solution, the validity of the normalized Polish notation is first checked, followed by geometry construction and area utilization screening. If a candidate solution fails the hard constraint screening, thermal model solving and performance evaluation are not performed. If a candidate solution passes the hard constraint screening, power budget solving, sustainable frequency mapping, cycle-level interconnection overhead calculation, and online performance evaluation are performed.

[0044] If the cost of a new candidate layout is better than the current layout, the new candidate layout is accepted; if the new candidate layout is worse, it is accepted with a certain probability according to the Metropolis criterion, thereby reducing the risk of the search process getting trapped in local optima. As the annealing temperature decreases, the algorithm gradually reduces the probability of accepting inferior solutions, and terminates after reaching the lower limit of the temperature, after several consecutive rounds without improvement, or after the maximum number of evaluations.

[0045] Example 5: Joint Evaluation and Verification Framework like Figure 5 As shown, this embodiment provides a cross-tool consistency joint evaluation framework. This framework includes a performance simulation module, a power consumption analysis module, a thermal evaluation module, a frequency verification module, and a final performance verification module. The performance simulation module is used to obtain performance statistics of the microprocessor on benchmark programs; the power consumption analysis module is used to map performance statistics to module-level power consumption; the thermal evaluation module is used to solve for steady-state temperature based on candidate layouts and module-level power consumption; the frequency verification module is used to determine the sustainable operating frequency based on temperature thresholds and power budgets; and the final performance verification module is used to evaluate the IPS, IPC, total power consumption, and peak temperature of candidate layouts under sustainable frequency and cycle-level delay settings.

[0046] This framework ensures that the optimization and verification phases use the same functional module divisions and physical layout inputs through unified module naming, unified power consumption mapping rules, and unified intermediate data interfaces, thereby improving the fairness and reproducibility of candidate layout comparisons.

Claims

1. A method for automatic layout optimization of microprocessors considering power budget, characterized in that, The method is used to automatically search and evaluate the internal functional module-level layout of a microprocessor under given area utilization and temperature threshold constraints. The method includes the following steps: (1) Obtain the set of functional modules, module area parameters, module power consumption parameters, reference layout, set of critical interconnect paths, area utilization threshold and temperature threshold of the microprocessor to be laid out; (2) A candidate layout is generated using the layout representation method, and the candidate layout is geometrically constructed to obtain the geometric coordinates, dimensions, chip outer contour area, and geometric distance between modules of each functional module. (3) Determine whether the candidate layout meets the area utilization constraint based on the chip outer contour area and the module area parameters, and determine whether the candidate layout meets the geometric legality constraint based on module overlap, outer contour overrun and aspect ratio constraints. (4) For a candidate layout that satisfies the area utilization constraint and geometric legality constraint, the layout-related power budget allowed under the temperature threshold is solved based on the steady-state thermal model and module-level power consumption mapping relationship. (5) Determine the sustainable operating frequency corresponding to the candidate layout based on the layout-related power budget and dynamic voltage-frequency adjustment relationship; (6) Calculate the periodic additional overhead introduced by the critical interconnect path at the sustainable operating frequency based on the geometric distance change of the critical interconnect path in the candidate layout; (7) Based on the sustainable operating frequency and the periodic additional overhead, construct an online performance evaluation index for the candidate layout, and use the online performance evaluation index as at least a part of the layout search cost function; (8) Using a heuristic search algorithm, the candidate layout is iteratively perturbed, constrained, evaluated, and accepted, and the microprocessor functional module-level layout that satisfies the area utilization constraint and temperature threshold constraint is output, and the online performance evaluation index meets the preset optimization target.

2. The automatic microprocessor placement optimization method considering power budget according to claim 1, characterized in that, In step (4), the steady-state thermal model is used to map the module-level power consumption vector corresponding to the candidate layout to the module temperature vector. When solving the layout-related power budget, the temperature threshold is used as the upper bound of the peak temperature. A uniform power scaling factor is applied to the module-level power consumption vector. Under the condition that the relative power consumption ratio between each functional module remains unchanged, the maximum power scaling factor that satisfies the peak temperature constraint is obtained. The layout-related power budget is obtained from the maximum power scaling factor.

3. The automatic microprocessor placement optimization method considering power budget according to claim 1, characterized in that, In step (5), the dynamic voltage frequency adjustment relationship is a mapping relationship between power consumption and operating frequency. Based on the reference frequency and reference power consumption, the highest frequency at which the candidate layout can continue to operate under the temperature threshold constraint is determined according to the layout-related power budget.

4. The microprocessor automatic placement optimization method considering power budget according to claim 1, characterized in that, In step (6), the cycle-level additional overhead is determined by the propagation delay of the critical interconnect path and the sustainable operating frequency, and the impact of layout changes on the cycle-level performance of the processor pipeline execution process is characterized by mapping the continuous time delay to an integer cycle delay.

5. The automatic microprocessor placement optimization method considering power budget according to claim 1, characterized in that, In step (7), the online performance evaluation index includes a sustainable operating frequency term and a performance degradation term; the performance degradation term is obtained by weighting the periodic additional overhead of multiple key interconnect paths, and the weights are obtained by the latency calibration experiment or performance sensitivity analysis of the benchmark test program.

6. The automatic microprocessor placement optimization method considering power budget according to claim 1, characterized in that, In step (8), the heuristic search algorithm is the simulated annealing algorithm, the candidate layout is encoded using normalized Polish notation, and the neighborhood candidate layout is generated by exchanging adjacent operands, changing the cutting direction, or perturbing the local substring.

7. The automatic microprocessor placement optimization method considering power budget according to claim 6, characterized in that, After each neighborhood perturbation, the simulated annealing algorithm first performs geometric legality and area utilization hard constraints to screen candidate layouts; for candidate layouts that do not meet the hard constraints, thermal evaluation and performance evaluation are not performed to reduce the computational overhead caused by invalid candidate layouts.

8. The automatic microprocessor placement optimization method considering power budget according to claim 1, characterized in that, The method also includes a cross-tool consistency modeling step, which is used to establish a unified mapping relationship between logical modules, physical functional blocks, power consumption statistics items and heat source units, so that candidate layout generation, performance statistics extraction, module-level power consumption decomposition, steady-state thermal assessment, frequency verification and final performance verification are performed under the same module naming system.

9. A microprocessor automatic layout optimization system, characterized in that, It includes a candidate layout generation module, a constraint screening module, a layout-related power budget solving module, a sustainable operating frequency mapping module, an interconnect cycle-level overhead calculation module, an online performance evaluation module, and a layout search module; The candidate layout generation module is used to generate candidate layouts at the microprocessor functional module level. The constraint filtering module is used to filter candidate layouts that satisfy geometric legality constraints and area utilization constraints. The layout-related power budget solving module is used to solve the layout-related power budget corresponding to the candidate layout based on the steady-state thermal model and temperature threshold. The sustainable operating frequency mapping module is used to map the layout-related power budget to the sustainable operating frequency corresponding to the candidate layout. The interconnect cycle-level overhead calculation module is used to calculate the cycle-level additional overhead of critical interconnect paths; The online performance evaluation module is used to generate the cost of candidate layouts based on the sustainable operating frequency and the periodic additional overhead. The layout search module is used to output an optimized microprocessor functional module-level layout based on the layout cost.

10. A microprocessor automatic layout optimization system, characterized in that, It includes a candidate layout generation module, a constraint screening module, a layout-related power budget solving module, a sustainable operating frequency mapping module, an interconnect cycle-level overhead calculation module, an online performance evaluation module, and a layout search module; The candidate layout generation module is used to generate candidate layouts at the microprocessor functional module level. The constraint filtering module is used to filter candidate layouts that satisfy geometric legality constraints and area utilization constraints. The layout-related power budget solving module is used to solve the layout-related power budget corresponding to the candidate layout based on the steady-state thermal model and temperature threshold. The sustainable operating frequency mapping module is used to map the layout-related power budget to the sustainable operating frequency corresponding to the candidate layout. The interconnect cycle-level overhead calculation module is used to calculate the cycle-level additional overhead of critical interconnect paths; The online performance evaluation module is used to generate the cost of candidate layouts based on the sustainable operating frequency and the periodic additional overhead. The layout search module is used to output an optimized microprocessor functional module-level layout based on the layout cost.

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