A PCB data processing method based on a local large model and a related device

Abstract

The application provides a PCB data processing method based on a local large model and a related device, and relates to the technical field of intelligent PCB manufacturing. The method analyzes unstructured specification files through a locally deployed multi-modal large language model, extracts structured design data in combination with a Gerber analysis library, and automatically fuses to generate standardized PCB design requirements. On this basis, according to a factory process rule library, an impedance calculation model and a board splicing algorithm are used to automatically generate an optimized lamination and board splicing scheme, and a database and a pricing system are connected to complete cost accounting. The scheme realizes full-process automatic processing of PCB design data from input to production preparation, significantly improves engineering processing speed and result accuracy through intelligent analysis and algorithm optimization, and reduces labor cost and material waste. Local deployment ensures the safety of core design data and avoids leakage of sensitive information, and is particularly suitable for manufacturing environments with high security requirements.

Description

Technical Field

[0001] This invention relates to the field of intelligent PCB manufacturing technology, and in particular to a PCB data processing method and related equipment based on a local large model. Background Technology

[0002] In existing printed circuit board (PCB) manufacturing technologies, the review of PCB design documents relies heavily on manual operation. Engineers need to manually unzip files and read specification documents to organize key requirements, then open the graphic data in specialized software such as Genesis or CAM350 to obtain layer and via information. Next, engineers need to calculate dielectric layer thickness and design the stack-up structure based on impedance requirements, then use independent panelization tools to plan the cutting method, and finally summarize all the results and manually enter them into the quotation system. This process not only consumes a lot of human resources, but also leads to inefficiency, error-proneness, suboptimal results, and difficulty in traceability due to frequent software switching, reliance on subjective judgment, and lack of systematic recording. Summary of the Invention

[0003] The purpose of this invention is to provide a PCB data processing method and related equipment based on a local large model, in order to solve one or more technical problems existing in the prior art, and at least provide a beneficial option or create conditions to realize the fully automated processing of PCB design data from parsing and review to stack-up and panelization optimization, thereby improving processing efficiency and accuracy, and effectively reducing manufacturing costs.

[0004] On the one hand, this application provides a PCB data processing method based on a local large model, including the following steps: Obtain a PCB design data package, which includes unstructured specification documents and structured Gerber design data; The specification document is semantically segmented and parsed using a locally deployed multimodal large language model to extract key design parameters; The Gerber design data is parsed using a pre-defined Gerber parsing library, and key layer and hole layer information is extracted based on the file header description, file name rules and file content. The key design parameters are compared and fused with the key layer and hole layer information to generate structured PCB design requirements information. Based on the PCB design requirements, and combined with the preset PCB manufacturing plant process rule library, optimized stack-up structure schemes and panelization schemes are automatically generated using impedance calculation models and panelization algorithms. The optimized stacked structure scheme and panel scheme data are stored in the database and connected to the quotation system to calculate costs, thereby obtaining production costs and quotations.

[0005] Furthermore, the step of using a locally deployed multimodal large language model to perform semantic region segmentation and parsing of the specification document to extract key design parameters specifically includes: The target detection model is used to identify the pages of the specification document and segment the pages into stack-up diagrams, drilling tables, board block diagrams, impedance tables and specification requirement block images. During the segmentation process, an inclusive annotation rule is adopted to incorporate all dimension lines, arrows, leaders, and numbers that are visually or semantically related to the PCB main drawing into the outline dimension drawing area. The segmented block images are input into the multimodal large language model, and the multimodal large language model is guided by a preset prompt template to output key design parameters in structured JSON format; The key design parameters include impedance value, plate thickness, material type, plate frame size, and number of layers.

[0006] Furthermore, the step of using a preset Gerber parsing library to parse the Gerber design data and extract key layers and hole layer information specifically includes: The preset graphic data parsing tool is invoked to parse Gerber files and drill files that conform to the PCB manufacturing standard format; Layer types are identified based on preset layer naming mapping rules. These rules map solder mask identifiers contained in filenames or file headers to solder mask layers, silkscreen identifiers to text layers, and drill identifiers to drill layers. The file header and content of the borehole layer are parsed to obtain information on the start layer, end layer, borehole diameter and number of boreholes, identify the drilling process and borehole type, and calculate the borehole density and borehole wall gold area. The drilling types include through holes, blind holes, buried holes, back drilled holes, fixed-depth drilled holes, or countersunk holes.

[0007] Furthermore, the method also includes a collision detection step: When the PCB size or number of layers in the key design parameters is inconsistent with the information extracted from the Gerber design data, the program determines it as an error message; The error message and related information are sent to the engineer's terminal for manual secondary evaluation.

[0008] Furthermore, the automatic generation of optimized stacked structure schemes using impedance calculation models specifically includes: The initial stacked structure is determined based on borehole layer information and the total number of layers; If there is an impedance requirement and the dielectric layer thickness is not defined in the document, the dielectric layer thickness can be calculated by working backward from the impedance calculation formula based on the impedance requirement and the line width / line spacing. When calculating the thickness of the dielectric layer, a preset priority iteration strategy is adopted. The priority iteration strategy includes: inner layer first, then outer layer; differential first, then characteristic; core board thickness first, then prepreg thickness; and layers with impedance first, then layers without impedance. Under the conditions of satisfying the total board thickness tolerance, the symmetry of the laminated structure and the constraints of factory material inventory, the final laminated structure scheme is generated with the goal of minimizing the number of prepreg sheets and simplifying the laminated structure.

[0009] Furthermore, the method includes the following impedance calculation steps: Inner layer single-ended impedance calculation: Based on the stripline transmission model, a logarithmic function relationship is constructed using the inner layer dielectric thickness, conductor width and copper thickness to calculate the inner layer single-ended impedance value; Inner layer differential impedance calculation: Based on the inner layer single-ended impedance value, an exponential decay function is constructed using the ratio of the differential pair line spacing to the inner layer dielectric thickness, and the line coupling correction coefficient is calculated to obtain the inner layer differential impedance value. Outer layer single-ended impedance calculation: First, the effective dielectric constant, including the influence of the solder mask layer, is calculated based on the substrate dielectric constant. Then, based on the microstrip line transmission model, a logarithmic function relationship is constructed using the effective dielectric constant, outer layer dielectric thickness, conductor width, and copper thickness to calculate the outer layer single-ended impedance value. Calculation of outer layer differential impedance: Based on the single-ended impedance value of the outer layer, an exponential decay function is constructed using the ratio of the differential pair line spacing to the outer layer dielectric thickness. The line coupling correction coefficient is then calculated to obtain the outer layer differential impedance value.

[0010] Furthermore, optimized puzzle layouts are automatically generated using a puzzle algorithm, specifically including: The planning is based on the hierarchical relationship between the raw material board size, the production panel size, the panel array size, and the unit board size; When it is necessary to design the array size, define the unit board spacing, the spacing between the unit board and the broken edge, and the broken edge width according to the factory rules; Multiple array panel sizes are designed using an enumeration method. For each array panel size, the production panel size with the highest utilization rate is selected based on the rules for margins and gaps in the production panels. Calculate the overall utilization rate corresponding to each array panel size, where the overall utilization rate is equal to the product of the panel utilization rate and the large panel utilization rate; The array panel size with the highest overall utilization rate and the corresponding production panel size are selected as the final panel design.

[0011] On the other hand, this application provides a PCB data processing system based on a local large model, for implementing the aforementioned PCB data processing method based on a local large model; The system includes: The data parsing module is used to obtain PCB design data packages, use a locally deployed multimodal large language model to parse specification documents to extract key design parameters, and use the Gerber parsing library to parse Gerber design data to extract key layer and hole layer information. The information fusion module is used to compare and fuse the key design parameters with the key layer and hole layer information to generate structured PCB design requirement information. The intelligent optimization module is used to automatically generate optimized stack-up structure schemes and panelization schemes based on the PCB design requirements information and in combination with a preset PCB manufacturing plant process rule library, using impedance calculation models and panelization algorithms. The data docking module is used to store the optimized stacked structure scheme and panel scheme data into the database, and dock with the quotation system to calculate costs and obtain production costs and quotations.

[0012] On the other hand, this application provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the PCB data processing method based on the local large model as described above.

[0013] On the other hand, this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the aforementioned PCB data processing method based on a local large model.

[0014] The beneficial effects of this invention are as follows: This application provides a PCB data processing method based on a local large-scale model. This method parses unstructured specification documents using a locally deployed multimodal large-scale language model, extracts structured design data using a Gerber parsing library, and automatically generates standardized PCB design requirements. Based on this, according to the factory process rule library, it automatically generates optimized layer stack-up and panelization schemes using impedance calculation models and panelization algorithms, and connects to the database and quotation system to complete cost accounting. This solution achieves fully automated processing of PCB design data from input to production preparation, overcoming the shortcomings of traditional manual review, such as low efficiency, high error rate, reliance on experience, and difficulty in traceability. Through intelligent parsing and algorithm optimization, it significantly improves engineering processing speed and result accuracy, and reduces labor costs and material waste. Local deployment ensures the security of core design data and avoids leakage of sensitive information, making it particularly suitable for manufacturing environments with high confidentiality requirements. This application also provides related equipment corresponding to the above method; the beneficial effects of the related equipment are similar to those of the above method and will not be elaborated here.

[0015] Other features and advantages of this application will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description, claims and drawings. Attached Figure Description

[0016] The accompanying drawings are provided to further understand the technical solutions of the present invention and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the technical solutions of the present invention, and do not constitute a limitation on the technical solutions of the present invention.

[0017] Figure 1 This is a flowchart of the PCB data processing method based on a local large model provided in this application; Figure 2 This is a structural diagram of the PCB data processing system based on a local large model provided in this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0019] The present application will be further described below with reference to the accompanying drawings and specific embodiments. The described embodiments should not be considered as limitations on the present application, and all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of the present application.

[0020] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] In the manufacturing process of printed circuit boards (PCBs), the initial engineering data processing is a crucial link between design and manufacturing. Its accuracy and efficiency directly determine the quality and cost of subsequent production. As electronic products move towards miniaturization and high density, PCB designs are becoming increasingly complex, placing higher demands on the accuracy and speed of engineering data processing.

[0023] In existing technologies, the engineering processing stage in the early stages of printed circuit board manufacturing is usually referred to as engineering confirmation or engineering Q&A, a process that is highly dependent on manual operation. After the factory receives the customer's design data, senior engineering engineers need to manually unzip the file package, first read the unstructured specification document, usually a PDF or Word document, and manually identify and extract key design parameters such as board thickness, copper thickness, surface treatment process, and impedance requirements.

[0024] Subsequently, engineers need to open the structured Gerber design data in professional software such as Genesis or CAM350, and confirm the graphical information such as circuit layers and drill layers through visual observation and manual measurement. After obtaining the basic parameters, engineers also need to manually calculate the dielectric layer thickness according to the impedance formula to design the stack-up structure, and use independent panelization tools or simple auxiliary software to plan the cutting method. Finally, all the summarized results are manually entered into the company's quotation system for cost accounting.

[0025] However, this traditional existing technology has significant drawbacks. First, the manual processing mode is extremely inefficient. Faced with massive amounts of design documents, engineers need to frequently switch between different software systems, and a lot of time is spent on repetitive data transfer and verification, resulting in long production preparation cycles and making it difficult to meet the market demand for rapid delivery.

[0026] Secondly, manual review is highly prone to errors. Due to the wide variety of specifications and the complexity of design drawings, engineers, especially when fatigued, are prone to overlooking, misreading, or making data entry errors. If these errors reach the production stage, they will cause the entire batch of boards to be scrapped, resulting in huge economic losses. Furthermore, existing laminated designs and panel planning often rely on the personal experience of engineers, lacking a systematic global optimization algorithm. This leads to designs that are often not the most cost-effective solutions, resulting in the waste of raw materials.

[0027] Finally, traditional methods lack a systematic data recording and traceability mechanism, and customers' design documents often contain highly sensitive trade secrets. Transmitting them over the network or using public cloud services poses a significant risk of data leakage and cannot meet the stringent requirements for intellectual property protection in the high-end manufacturing sector.

[0028] To address the aforementioned issues, this application provides a PCB data processing method and related equipment based on a local large model. This technical solution adopts an architecture that deeply integrates a locally deployed multimodal large language model with a dedicated parsing algorithm. It can simultaneously process unstructured specification documents and structured Gerber design data. It accurately extracts key design parameters through semantic region segmentation technology and automatically compares and merges them with layer and hole layer information parsed from graphic data to generate standardized PCB design requirement information.

[0029] Based on this, the system combines a pre-set factory process rule library and uses a built-in impedance calculation model and panel optimization algorithm to automatically generate a laminated structure and panel scheme that meets electrical performance requirements and maximizes material utilization. Finally, the processing results are automatically stored and connected to the quotation system, realizing a fully intelligent closed loop from raw data input to production preparation data output. Under the premise of ensuring the local security of core design data, it completely replaces the traditional manual review and experience-based design mode.

[0030] First, the PCB data processing method based on a local large model provided in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0031] Reference Figure 1 The implementation of the PCB data processing method based on a local large model provided in this application includes, but is not limited to, the following steps.

[0032] Step S100: Obtain the PCB design data package.

[0033] The PCB design data package includes unstructured specification documents and structured Gerber design data.

[0034] In step S100, the PCB design data package is obtained to provide the system with complete and heterogeneous input data from multiple sources. The PCB design data package is usually provided by the customer and includes not only structured Gerber design data that defines the electrical connections and graphical information of the circuit, but also unstructured specification documents that define physical properties, material requirements, impedance control standards, and appearance inspection standards.

[0035] This breaks down the barriers of scattered and inconsistent file formats in traditional processes, centrally loading all the original information required for subsequent processing into the local environment, laying the foundation for subsequent multimodal analysis, and also establishing the data boundary for localized processing, thus ensuring the security and privacy of customer design data from the source.

[0036] Step S200: Use a locally deployed multimodal large language model to perform semantic region segmentation and parsing on the specification document to extract key design parameters.

[0037] Step S200 addresses the challenge of automatically understanding unstructured documents, a problem inherent in traditional technologies. Due to the diverse layouts of specification documents, traditional regular expressions or OCR techniques often struggle to accurately extract information. This step utilizes a local multimodal large language model fine-tuned with PCB expertise to simulate the reading logic of human engineers. First, it segments the document page semantically, accurately identifying key areas such as stack-up diagrams, drilling parameter tables, and impedance bars. Then, it delves into the semantics of the text, extracting key design parameters such as board thickness, copper thickness, minimum trace width and spacing, and surface treatment processes. This achieves intelligent understanding and digital reconstruction of complex engineering documents, significantly improving the accuracy and robustness of information extraction and avoiding the tediousness and errors of manual data entry.

[0038] Step S300: Use the preset Gerber parsing library to parse the Gerber design data and extract key layer and hole layer information based on the file header description, file name rules and file content.

[0039] Step S300 focuses on in-depth mining and structured extraction of graphic data. Gerber files, as a standard format for PCB manufacturing, contain a large amount of coordinate data and attribute information. Using a pre-defined Gerber parsing library, the system can automatically scan the file header description to confirm units and format, analyze filename rules to identify layer functions, and deeply analyze the file content to obtain specific circuit diagrams and drilling data. The purpose of this step is to transform abstract graphic files into computer-quantifiable layer and hole information, such as layer counts, hole diameter distribution, and board frame dimensions, providing accurate graphic data support for subsequent comparison with design specifications and ensuring consistency between design intent and the actual graphic.

[0040] Step S400: Compare and integrate the key design parameters with the key layer and hole layer information to generate structured PCB design requirement information.

[0041] In step S400, in actual engineering projects, inconsistencies often exist between the documents and graphic data provided by the client. This step cross-compares the text parameters extracted in step S200 with the graphic information extracted in step S300. For example, it verifies whether the number of layers described in the document matches the actual number of layers in the Gerber file, and whether the aperture requirements match. By automatically identifying and marking potential design conflicts or omissions, data silos are eliminated, and scattered text parameters and graphic attributes are integrated into a complete, unified, and unambiguous structured PCB design requirements information. This provides high-quality data input for subsequent engineering calculations and effectively avoids production accidents caused by data inconsistencies.

[0042] Step S500: Based on the PCB design requirements information and combined with the preset PCB manufacturing plant process rule library, the optimized stack-up structure scheme and panelization scheme are automatically generated using the impedance calculation model and panelization algorithm.

[0043] In step S500, the system no longer relies on engineers' personal experience for trial and error, but directly calls upon the actual production capacity data of the factory, i.e., the PCB manufacturing plant's process rule library. Using an impedance calculation model, the system can automatically deduce and design a stack-up structure that meets electrical performance requirements and complies with the factory's process capabilities based on the target impedance value. Simultaneously, using a panelization algorithm, the system can automatically calculate the optimal panelization method and cutting path based on the board frame size and utilization requirements, achieving automation and optimization of engineering design. This not only significantly shortens engineering processing time but also maximizes board utilization while ensuring quality, thereby significantly reducing production costs.

[0044] In step S600, the optimized stacked structure scheme and panel scheme data are stored in the database and connected to the quotation system to calculate the cost, thereby obtaining the production cost and quotation.

[0045] In step S600, the data flow loop is closed and the business value is transformed. All optimization schemes and parameter information generated in the preceding steps are persistently stored in the database, which not only establishes a traceable engineering archive to facilitate subsequent production queries and quality backtracking, but also provides a data foundation for accumulating an enterprise knowledge base.

[0046] Meanwhile, by directly connecting to the quotation system, the technical solutions are transformed into economic data. The system can automatically generate accurate production costs and quotations based on material usage and process difficulty, thus realizing data-driven automated quotation.

[0047] In some embodiments of this application, step S200 involves using a locally deployed multimodal large language model to perform semantic region segmentation and parsing of the specification document, extracting key design parameters, specifically including: Step S210: Use the target detection model to identify the pages of the specification document and segment the pages into stack-up structure diagrams, drilling tables, board block diagrams, impedance tables, and specification requirement block images.

[0048] In step S210, high-precision preprocessed input is provided for the multimodal large language model, thereby overcoming the problems of key semantic loss, cognitive deficiencies, and logical gaps that are easily caused when directly inputting unstructured PDFs or scanned documents into the large model. Because PCB specification documents have extremely complex layouts and varied formats, directly parsing the entire document can easily lead to a significant decrease in the accuracy of information extraction.

[0049] By introducing a specialized target detection model, the system can, like a human engineer, first perform a macroscopic visual understanding and structural decomposition of the document page, accurately locating and segmenting overlay diagrams, borehole tables, board block diagrams, impedance tables, and plain text specification blocks. This refined semantic region segmentation not only significantly improves the focus and accuracy of subsequent large-scale model parsing but also effectively reduces the computational power consumption and response time of model processing, laying a solid foundation for the lossless extraction of key information from complex engineering drawings.

[0050] Step S220: During the segmentation process, an inclusive annotation rule is adopted to incorporate all dimension lines, arrows, leaders, and numbers that are visually or semantically related to the PCB main drawing into the outline dimension drawing area.

[0051] Step S220 addresses common issues of contextual structure fragmentation and semantic separation in engineering drawing parsing, ensuring that the large model can acquire complete and coherent visual contextual information. In traditional OCR or ordinary image recognition, dimension lines, arrows, leaders, and numbers close to the edge of the drawing are often treated as independent noise or irrelevant elements, resulting in the fragmentation of the drawing's geometric dimension information and consequently causing logical gaps in AI understanding. This application adopts inclusive annotation rules, forcibly packaging these auxiliary elements that are visually closely connected to the PCB main drawing and semantically mutually interpretable into the overall dimension drawing area.

[0052] This processing method restores the original reading logic of engineering drawings, allowing subsequent large models to simultaneously see the graphic outline and its corresponding dimension annotations and leader lines when analyzing the dimensions of the plate frame. This greatly improves the completeness and accuracy of the extracted dimension parameters and avoids parsing errors caused by information fragmentation.

[0053] Step S230: Input the segmented block image into the multimodal large language model, and guide the multimodal large language model to output key design parameters in structured JSON format through a preset prompt template; among which, key design parameters include impedance value, plate thickness, material type, plate frame size and number of layers.

[0054] Step S230 is a crucial step in converting unstructured engineering documents into standardized, machine-readable data. It leverages the deep semantic understanding capabilities of the large model and the strong constraints of the prompting engineering to achieve high-precision automated parameter extraction and formatted output. After inputting precisely segmented and context-complete block images into the locally deployed multimodal large language model, the system guides the model to simulate the thought process of a senior PCB engineering expert through preset professional prompt templates, performing deep correlation analysis on the tabular data, graphic parameters, and text descriptions in the images.

[0055] Ultimately, the model is required to output structured JSON data that strictly conforms to the preset schema, covering core manufacturing parameters such as impedance values, plate thickness, material type, plate frame dimensions, and number of layers. This mechanism not only completely eliminates the illusions and arbitrariness that may arise in serious engineering analysis using large models, but also directly transforms the extracted results into standard interface data that can be directly called by downstream databases, impedance calculation models, and panelization algorithms. This greatly simplifies the data cleaning and conversion process and achieves seamless integration from drawing reading to digital production preparation.

[0056] In some embodiments of this application, the parsing of the PCB design specification PDF file in step S200 above does not employ a simple OCR character recognition method, but rather completes page-level semantic region segmentation and attribution correction.

[0057] PCB engineering drawings differ significantly from ordinary document pages, typically including the main PCB drawing, dimension lines and arrows, detailed lead descriptions, parameter figures, tables, and technical requirements blocks. The core challenge of such pages is not "whether a single character is visible," but rather determining which semantic area these visual elements should ultimately belong to.

[0058] To address this, this application employs a combined approach of inclusive annotation and nearest-neighbor merging. On one hand, through annotation rules, dimension lines, arrows, leaders, reference symbols, and small numbers closely attached to the PCB main drawing are collectively merged into the outline dimension drawing, avoiding the model learning the erroneous prior notion that "the drawing is the drawing, and the numbers are another block" during training. On the other hand, during the inference phase, a limited merging process is performed on a small number of nearby small targets that are misclassified as "notes / annotations," and they are re-attached to their respective outline dimension drawings or tables while satisfying geometric, environmental, and morphological rules.

[0059] To achieve this goal, this embodiment collected over 2000 PCB design drawings in PDF format and annotated and trained the model. Specifically, the PDF files were first processed by a trained YOLO deep learning object detection algorithm to identify and segment them into different block images, such as stack-up diagrams, drill bit tables, board block diagrams, impedance tables, and specifications. Subsequently, the segmented PDF images and the generated Markdown files were parsed by a multimodal large model and a structured JSON file was output.

[0060] In some embodiments of this application, in order to ensure the accuracy and standardization of the structured JSON data output by the multimodal large language model, a terminology library, a rule library, and a template library are pre-built.

[0061] The terminology library includes approximately 200 common PCB technical terms, such as impedance, stack-up, V-cut, and soldermask, to ensure a consistent understanding of these terms within the model. The rule library defines reasonable ranges for various design parameters, such as board size ranges, interlayer thickness ranges, impedance value ranges, and trace width and spacing ranges, to constrain the model's output. The template library contains standard formats such as stack-up structure templates, impedance table templates, and drill table templates to guide the model in generating structured data.

[0062] In step S230 above, the system calls these libraries to construct preset prompt templates, thereby guiding the large model to parse them. This not only improves the model's ability to understand professional content, but also effectively reduces the arbitrariness of the model's output through the constraints of rules and templates, ensuring that the final generated JSON file conforms to engineering standards.

[0063] In some embodiments of this application, step S300 involves using a preset Gerber parsing library to parse Gerber design data and extract key layers and hole layer information, specifically including: Step S310: Call the preset graphic data parsing tool to parse the Gerber file and drilling file that conform to the PCB manufacturing standard format.

[0064] In step S310, accurate and reliable underlying graphic data support is provided for the automated processing of the entire PCB design data. Since Gerber files are the core data format connecting design and production in the PCB manufacturing process, carrying precise physical information of each layer of circuitry, pads, solder mask, and silkscreen, and drilling files contain the position and size instructions of all mechanical holes and metallized holes, calling professional graphic data parsing tools to parse them ensures that the system can accurately read and understand these files that conform to PCB manufacturing standard formats.

[0065] This step effectively avoids the risk of parsing failure due to non-standard file formats or data corruption, transforming the low-level vector graphics and coordinate instructions that could only be read by CAM software into raw data streams that the system can further process, laying a solid data foundation for subsequent layer recognition and process parameter extraction.

[0066] Step S320: Identify layer types based on preset layer naming mapping rules. The layer naming mapping rules map solder resist identifiers contained in file names or file headers to solder resist layers, silkscreen identifiers to text layers, and drill identifiers to drill layers.

[0067] Step S320 addresses the pain point of inconsistent naming rules and the lack of absolute industry standards when different EDA design software generates Gerber files, achieving automated classification and standardized identification of multi-source heterogeneous graphic data. In actual engineering practice, design engineers may use different tools such as Altium Designer, Cadence Allegro, or KiCad, resulting in significant differences in the extensions and naming conventions of the output solder mask, silkscreen, or drill files.

[0068] By establishing a rigorous set of preset layer naming mapping rules, the system can intelligently scan filenames or deeply parse file header descriptions to accurately map various forms of solder mask identifiers, silkscreen identifiers, and drill identifiers to the system's internally standardized solder mask layer, text layer, and drill layer. This mechanism greatly improves the system's compatibility and robustness with different customer design data, eliminates the tedious operation of manually confirming layer attributes, and ensures the accuracy of subsequent stack-up structure analysis and panel optimization.

[0069] Step S330: Parse the header and content of the drill layer to obtain the starting layer, ending layer, hole diameter, and number of holes; identify the drilling process and drill type; and calculate the hole density and the area of ​​metal on the hole wall. Drill types include through holes, blind holes, buried holes, back-drilled holes, fixed-depth drilled holes, or countersunk holes.

[0070] In step S330, a refined quantitative assessment of the PCB drilling process is achieved, providing key quantitative indicators for subsequent production cost accounting and process feasibility review. Drilling is not only a time-consuming and costly process in PCB manufacturing, but its complexity also directly determines the electrical performance and production yield of the board. By deeply analyzing the file header and specific coordinate content of the drilling layer, the system can not only accurately obtain basic physical parameters such as the starting layer, ending layer, hole diameter, and number of holes, but also accurately identify complex drilling process types such as through holes, blind holes, buried holes, back drilled holes, fixed-depth drilled holes, or countersunk holes.

[0071] Based on this, the system further automatically calculates derived indicators such as pore density and gold plating area on the pore walls. These data are crucial for evaluating the chemical consumption of the electroplating process, the working hours of the drilling machine, and the final price of the sheet material, thus realizing a leap from simple graphical analysis to in-depth engineering process analysis.

[0072] In some embodiments of this application, in step S300, the Gerber design data is parsed using a preset Gerber parsing library, specifically including calling tools such as the Python gerber library, pcb-tools library, and odbppy library to support multiple formats such as RX-274D, RX-274X, odb++, and excellon drill files.

[0073] Layer and hole layer information is extracted as follows: First, the file header description of each layer is parsed to obtain basic attributes; second, descriptive files in the compressed package, such as .extrep, .asc, .txt, .ipc, .dsn, etc., are analyzed to supplement key information; finally, preset filename rules are applied for identification, for example, files containing identifiers such as sm, smt, smb, soldermask are mapped to solder mask layers, files containing identifiers such as silkscreen, legend, sst, ssb are mapped to text layers, and files containing identifiers such as drill, drl, pth, npth, slot, backdrill, blind, buried, etc. are mapped to drill layers.

[0074] By deeply analyzing the header and content of the borehole layers, key information such as the starting layer, ending layer, borehole diameter, number of boreholes, and PTH and NPTH can be obtained. Based on this data, the system can identify the drilling process (such as mechanical boreholes, laser boreholes, etc.) and borehole type (such as through holes, blind holes, buried holes, back drilled holes, fixed-depth drilled holes, countersunk holes, etc.), and further analyze and calculate derived indicators such as borehole density and borehole wall gold area.

[0075] Furthermore, to ensure the accuracy of the analysis, this embodiment also incorporates several error detection mechanisms: 1. Verifying whether the board size, line width, line spacing, hole diameter, and other specifications are within a reasonable range; 2. Detecting whether analysis results show an odd number of copper layers (except for single-sided boards); 3. Verifying whether the starting and ending layers of the holes match the identified number of copper layers; 4. Checking for duplicate definitions of solder mask, solder paste, drill layers, etc. These mechanisms collectively constitute a data quality assurance system, effectively improving the robustness of the system's parsing.

[0076] In some embodiments of this application, the method further includes a conflict detection step: when the PCB size or number of layers in the key design parameters is inconsistent with the information extracted from the Gerber design data, the program determines it as an error message; the error message and related content are sent to the engineer's terminal for manual secondary judgment.

[0077] Specifically, the construction of a human-machine collaborative automated error correction and risk mitigation mechanism effectively solves the potential "garbage in, garbage out" problem in fully automated data processing workflows. In actual PCB engineering practice, unstructured specifications and structured Gerber graphic materials provided by customers are often written by different personnel or updated out of sync, which can easily lead to serious conflicts where the board thickness, dimensions, and number of layers described in the documents do not match the actual content of the Gerber files.

[0078] This step uses an automated logical comparison algorithm to verify the consistency between text parameters and graphic data in real time. Once a critical contradiction is found, such as the document describing an eight-layer board while the Gerber file only has six layers, or the document's labeled dimensions not matching the actual graphic borders, the program immediately identifies it as an error message and blocks subsequent automated processes to prevent erroneous data from flowing into the production process and causing significant economic losses.

[0079] Meanwhile, the system accurately pushes these conflict points and related contextual information to the engineer's terminal for secondary human judgment, which not only retains the efficiency of machine processing, but also introduces the final review authority of human experts at key decision points, achieving a perfect balance between automation efficiency and engineering rigor.

[0080] In some embodiments of this application, step S500, which automatically generates an optimized stacked structure scheme using an impedance calculation model, specifically includes: Step S511: Determine the initial stacked structure based on borehole layer information and total number of layers.

[0081] In step S511, the physical architecture foundation is laid for subsequent impedance calculations and layer stack-up design, ensuring that the generated solution is mechanically feasible. The drilling layer information not only includes the hole diameter but also implies the key inter-layer interconnection logic such as the start and end layers of through-holes, blind vias, and buried vias, while the total number of layers limits the overall electrical layer scale of the PCB.

[0082] By comprehensively analyzing these two types of data, the system can accurately construct the initial physical framework of the PCB and clarify the potential distribution locations of signal layers and reference layers (power or ground layers). This step effectively avoids structural errors in subsequent designs that violate mechanical drilling processes or interlayer connection logic, ensuring that the stack-up scheme not only meets electrical performance requirements but also fully complies with the actual lamination and drilling production capabilities of the PCB manufacturing plant.

[0083] Step S512: If there is an impedance requirement and the dielectric layer thickness is not defined in the document, the dielectric layer thickness is calculated backward using the impedance calculation formula based on the impedance value requirement and the line width / line spacing.

[0084] In step S512, the common problem of missing design parameters in design data is addressed by using electromagnetic field theory and mathematical models to achieve reverse engineering transformation from electrical performance indicators to physical structural parameters. In actual engineering, customers often only specify characteristic impedance values ​​(such as 50 ohms for single-ended and 100 ohms for differential) and line width, but ignore the precise requirements for dielectric layer thickness.

[0085] This step utilizes a built-in impedance calculation model, based on transmission line theory formulas such as microstrip lines or striplines, to establish a functional relationship between impedance, dielectric constant, copper thickness, line width and spacing, and dielectric thickness. When a missing dielectric thickness is detected, the system automatically uses the target impedance value and known line width and spacing as input variables to inversely calculate the theoretical dielectric layer thickness that meets signal integrity requirements. This mechanism significantly enhances the automation of the design process, fills gaps in design documentation, and ensures that the PCB achieves the expected signal transmission quality after production.

[0086] Step S513: When deducing the thickness of the dielectric layer, a preset priority iteration strategy is adopted. The priority iteration strategy includes: inner layer first, outer layer second; differential first, characteristic first; core board thickness first, prepreg thickness second; and layers with impedance first, layers without impedance second.

[0087] In step S513, the logical thinking of a senior PCB CAM engineer is simulated, and the solution space is optimized through a scientific calculation sequence to ensure the efficiency and rationality of the stack-up design. PCB stack-up design is a complex process involving multiple coupled variables; disordered calculations can easily lead to parameter conflicts or getting trapped in local optima.

[0088] The priority iteration strategy introduced in this step first follows the principle of inner layers before outer layers, prioritizing the fixing of the inner core structure which is less affected by the pressure bonding environment; secondly, it follows the principle of differential before characteristic, because differential signals are more sensitive to line spacing and dielectric thickness, so their stringent impedance control requirements are prioritized; thirdly, it follows the principle of determining the core board thickness before determining the prepreg thickness, because the core board, as a standard component, has relatively fixed specifications, while the prepreg can be adjusted through combination, a strategy that aligns with the actual situation of factory material management; finally, it prioritizes the processing of layers with impedance requirements, and then fills in layers without impedance requirements.

[0089] This hierarchical and priority-based iterative strategy effectively avoids repeated oscillations during parameter adjustment, significantly improving the speed of computational convergence and the reliability of the stacked structure.

[0090] Step S514: Under the conditions of satisfying the total board thickness tolerance, the symmetry of the laminated structure and the factory material inventory constraints, the final laminated structure scheme is generated with the goal of minimizing the number of prepreg sheets and simplifying the laminated structure.

[0091] In step S514, electrical performance, manufacturing reliability, and production costs are balanced to output the most manufacturable final solution. PCB manufacturing has strict requirements on the warpage of the board material, therefore the principle of symmetry in the stack-up structure must be strictly followed to prevent bending or twisting of the board after lamination; at the same time, the total board thickness must be controlled within the tolerance range allowed by the customer. Based on this, this step introduces factory material inventory constraints to ensure that the selected core board and prepreg models are materials commonly available on the production line, avoiding procurement delays caused by special materials.

[0092] Furthermore, the system optimizes for minimizing the number of prepreg sheets and simplifying the structure, as excessive prepreg stacking not only increases material costs but also introduces more thickness accumulation errors and delamination risks. Through this multi-objective optimization algorithm, the final stacking scheme generated by the system not only accurately matches impedance and thickness requirements but also boasts extremely high production yield and cost advantages, achieving a seamless transition from theoretical design to mass production.

[0093] In some embodiments of this application, the method includes the following impedance calculation steps: (1) Calculation of single-ended impedance of inner layer: Based on the stripline transmission model, the logarithmic function relationship is constructed using the inner layer dielectric thickness, conductor width and copper thickness to calculate the single-ended impedance value of inner layer.

[0094] Specifically, the purpose of calculating the inner layer single-ended impedance is to provide an accurate reference impedance model for signals inside multilayer printed circuit boards. This step is based on stripline transmission theory and fully considers the electromagnetic field distribution characteristics of the inner layer signal lines sandwiched between two reference planes. By introducing key geometric parameters such as inner layer dielectric thickness, conductor width, and copper thickness to construct a logarithmic function relationship, it can effectively characterize the obstruction effect on signal transmission in a uniform dielectric environment. This allows for the accurate calculation of the inner layer single-ended signal impedance value without the influence of inter-line coupling, laying the physical foundation for the subsequent derivation of differential impedance.

[0095] (2) Calculation of inner layer differential impedance: Based on the inner layer single-ended impedance value, an exponential decay function is constructed using the ratio of the differential pair line spacing to the inner layer dielectric thickness, and the line coupling correction coefficient is calculated to obtain the inner layer differential impedance value.

[0096] Specifically, the purpose of inner-layer differential impedance calculation is to address the electromagnetic coupling quantization problem between high-speed differential signal pairs in the inner layer. This step no longer considers a single signal line in isolation, but rather, based on the obtained inner-layer single-ended impedance value, focuses on analyzing the influence of the ratio of differential pair spacing to inner-layer dielectric thickness on the electromagnetic field. An exponential decay function model is used to simulate the field cancellation effect between two signal lines of opposite polarity due to their proximity. By calculating the inter-line coupling correction coefficient, the impedance value is dynamically adjusted, thereby accurately obtaining the inner-layer differential impedance value that reflects the actual differential transmission characteristics, ensuring the integrity and anti-interference capability of high-speed signals during transmission within the board.

[0097] (3) Calculation of single-ended impedance of outer layer: First, the effective dielectric constant including the influence of solder resist layer is calculated based on the dielectric constant of substrate. Then, based on microstrip line transmission model, logarithmic function relationship is constructed using effective dielectric constant, outer layer dielectric thickness, conductor width and copper thickness to calculate the single-ended impedance value of outer layer.

[0098] Specifically, the purpose of calculating the single-ended impedance of the outer layer is to eliminate the interference of the non-uniform dielectric environment on impedance control. Since the outer layer signal line is in contact with air on one side and the substrate on the other side and is covered with solder resist ink, its electromagnetic field distribution is much more complex than that of the inner layer. Therefore, this step first calculates the equivalent effective dielectric constant including the influence of the solder resist layer based on the dielectric constant of the substrate, thereby correcting the error caused by the non-uniform dielectric. Then, based on the microstrip line transmission model, a logarithmic function relationship is constructed by combining the outer layer dielectric thickness, conductor width, and copper thickness, so as to accurately calculate the reference impedance of the outer layer single-ended signal in the complex surface environment, ensuring the accuracy of the surface layer signal transmission characteristics.

[0099] (4) Calculation of outer layer differential impedance: Based on the single-ended impedance value of the outer layer, an exponential decay function is constructed using the ratio of the differential pair line spacing to the outer layer dielectric thickness. The line coupling correction coefficient is calculated, and then the outer layer differential impedance value is obtained.

[0100] Specifically, the outer layer differential impedance calculation aims to achieve accurate impedance matching of the surface layer differential signal in high-noise environments. This step uses the outer layer single-ended impedance as a reference. Taking into account the asymmetric electric field distribution of microstrip lines, an exponential decay function is constructed using the ratio of the differential pair spacing to the outer layer dielectric thickness. This function is specifically used to quantify the coupling effect between surface layer differential pairs caused by edge field effects. The reference impedance is then corrected by calculating the inter-line coupling correction coefficient, ultimately determining the outer layer differential impedance value. This process is crucial for optimizing the signal quality of the outer layer high-speed interface, reducing electromagnetic radiation, and improving the noise immunity of the clock signal.

[0101] In some embodiments of this application, the impedance calculation model incorporates a variety of standard impedance calculation formulas to accurately cover the simulation requirements of different signal transmission scenarios, such as inner and outer layers, single-ended and differential signals.

[0102] Specifically, regarding the inner layer single-ended impedance The system uses the following formula for calculation: ; in, The dielectric constant (default value is 4.2). The dielectric thickness from the line to the lower reference layer. The dielectric thickness from the line to the upper reference layer, if not provided It then degenerates into a symmetric stripline structure, that is , For line width, Copper thickness; The inner impedance characteristic constant related to the transmission line mode. This is a correction factor for the inner layer geometry. This is the correction factor for the effective width of the line.

[0103] Furthermore, these three coefficients are empirically fitted values ​​derived from electromagnetic field theory and corrected by engineering measurements, aiming to improve the accuracy of impedance calculations. Among them, It can be set to 60, which is calculated based on the ratio of free space wave impedance to transmission line geometry factor, representing the basic impedance reference under unit dielectric constant. It can be set to 1.9 to compensate for the edge field effect of the conductor sidewall and the additional capacitance caused by non-ideal rectangular conductors, and to prevent the impedance calculation from being too high due to ignoring the edge electric field divergence; It can be set to 0.8, which reflects the uneven current distribution caused by the skin effect and proximity effect under high frequency signals (current crowding at the edge of the conductor), and simulates the actual electrical performance more accurately by equivalently reducing the conductive width.

[0104] Based on this, the inner layer differential impedance The calculation is based on the inner single-ended impedance results. The line spacing parameter is corrected by introducing a differential method, as shown in the following formula: ; Among them, the total dielectric thickness of the inner stripline structure , The inner single-ended impedance obtained from the above calculation is... The differential pair spacing is used. This formula reflects the effect of inter-line coupling on impedance through an exponential decay function. (Coefficient) and These are empirically corrected parameters derived from electromagnetic field simulations and fitting of a large amount of measured data, designed to accurately describe the nonlinear effect of differential pair line coupling on impedance.

[0105] in, It can be set to 0.374, representing the normalized amplitude of the maximum coupling strength, reflecting the limiting proportion (approximately 37.4%) of impedance reduction caused by the coupling effect under extremely small spacing. Setting it to -2.9 gives the coupling attenuation rate exponent, which controls the rate of decrease as the line spacing increases. The rate at which the coupling effect decreases exponentially with increasing impedance is determined by these two coefficients. Together, they construct a high-precision calibration function, ensuring that the formula dynamically corrects for single-ended impedance within the range of common PCB manufacturing processes, resulting in calculations that closely match actual physical measurements.

[0106] To address the signal transmission characteristics of the outer layer, due to the influence of the surface solder mask, the model first calculates the effective dielectric constant. ,coefficient It can be set to 0.95, coefficient The value can be set to 1.41. These two values ​​are not derived from theory, but are empirical values ​​fitted based on a large amount of electromagnetic field simulation data and actual measurement results. The purpose is to make the calculation results closer to the real physical situation.

[0107] Specifically, the coefficient 0.95 reflects the main contribution of the substrate dielectric constant to the overall effective dielectric constant, while 1.41 is a compensation term used to correct for the effects of air and solder mask. This linear combination, while simple, provides sufficiently accurate impedance estimation for most standard FR-4 substrates and standard linewidth / dielectric thickness ratios, making it particularly suitable for rapid design and initial stack-up planning. It's important to note that these constants apply only to specific microstrip line models and empirical formulas. Changing the calculation method or using high-frequency / special substrates may require recalibration or the use of more complex models.

[0108] Furthermore, solve for the outer single-ended impedance. The calculation logic is as follows: ; The coefficients in the above outer layer impedance formula are engineering fit values ​​based on the quasi-TEM model characteristics of the microstrip line and the influence of the surface solder mask. Among them, It is the thickness of the medium; It can be set to 87, which is based on the free-space wave impedance combined with the effective dielectric constant. Numerical calibration performed within a specific domain makes it suitable for the non-uniform outer medium environment; It can be set to 5.98 to correct the asymmetry of the microstrip line edge field diverging into the air and solder mask, which effectively increases the vertical height of the electric field effect; A value of 0.8 can be used to reflect the reduction in electrical width caused by current concentration at the edge of the conductor under the high-frequency skin effect. These coefficients collectively simplify the complex Maxwell's equations into a high-precision algebraic model suitable for PCB outer layer traces.

[0109] Finally, outer differential impedance Using the outer single-ended impedance as a reference, and combining the relationship between dielectric thickness and line spacing, we can derive: ; in, The outer single-ended impedance, For differential pair line spacing, The thickness of the medium.

[0110] Coefficients in the outer differential impedance formula and These are empirically corrected parameters derived from fitting electromagnetic field simulation and measured data under non-uniform microstrip dielectric conditions. It can be set to 0.48, representing the maximum coupling strength amplitude of the outer differential pair. Due to the presence of air or solder mask layer above the outer layer, the electric field distribution is more divergent than that of the inner layer, resulting in a relatively weaker inter-line coupling effect (adjusted from 0.374 for the inner layer). This value quantifies the maximum impedance reduction ratio under this specific environment. It can be set to -0.96, which is the coupling attenuation rate constant, controlling the rate of decrease as the line spacing increases. Relative to the thickness of the medium The rate at which the coupling effect weakens upon increase is also considered. These two coefficients together constitute a calibration function for the outer asymmetric dielectric structure, ensuring that the calculated differential impedance, after considering the mixed dielectric properties of air and substrate, accurately reflects the line-to-line coupling behavior in real-world physical scenarios.

[0111] By combining the above four core algorithms, the system can provide real-time and accurate feedback on the impact of physical parameter adjustments on the final impedance value when automatically optimizing the stacked structure, ensuring that the design meets signal integrity requirements.

[0112] In a specific embodiment of this application, the core materials in the printed circuit board (PCB) stack-up structure are first clearly defined. The core board is the core material constituting the basic rigid structure of the multilayer PCB. It is a solid, rigid substrate covered with copper foil on both sides, typically made of glass fiber reinforced epoxy resin such as FR-4. Its internal insulating layer and the copper foil on both sides are fully cured before leaving the factory, possessing stable mechanical strength and electrical properties. It serves as the skeleton that carries the inner layer circuitry and provides structural support. Prepreg (PP) is used in conjunction with it. It is an incompletely cured adhesive material, mainly composed of resin-impregnated glass fiber cloth. During the pressing process, it melts and flows under heat and eventually cures, thereby firmly bonding multiple core boards or core boards to the outer copper foil, while also providing insulation and filling. Therefore, a typical multilayer PCB stack-up structure is usually described as copper foil + prepreg + core board + prepreg + copper foil, where the core board provides the rigid foundation and conductive layer, while the prepreg is responsible for interlayer bonding and insulation.

[0113] In some embodiments of this application, the method includes the following stacked structure design steps: First, analyze the drilling information and total number of layers in the PCB design documentation to determine the basic stack-up framework. For example, for an 8-layer board design, if there are only mechanically drilled holes through L1 to L8, it is determined to be a basic symmetrical stack-up structure, i.e., a five-layer structure from the outside in: copper foil, core board 1, core board 2, core board 3, and copper foil. However, if, in addition to the through holes from L1 to L8, there are also blind and buried vias from L2 to L7, it is determined to be a multi-layer lamination structure, i.e., a six-layer structure from the outside in: copper foil, copper foil, core board 1, core board 2, copper foil, and copper foil. This step, by analyzing the drilling layer information, accurately identifies the electrical connection requirements inside the PCB, providing a basic framework for subsequent dielectric layer design.

[0114] When the design document contains explicit impedance requirements, different processing strategies are adopted depending on whether the dielectric layer thickness is defined in the document. If the thickness of each dielectric layer is explicitly defined in the document, these parameters are directly used for impedance verification calculation. If the dielectric layer thickness is not defined in the document, the required dielectric layer thickness needs to be calculated backward using the impedance calculation formula based on the target impedance value and the actual line width and spacing parameters. During the backward calculation, specific priority principles are followed: inner layer signals are processed first, then outer layer signals; differential impedance requirements are determined first, then single-ended characteristic impedance is processed; the thickness of the core board material is determined first, then the thickness of the prepreg (PP); the dielectric thickness of layers with impedance requirements is determined first, then the thickness of layers without impedance requirements is determined according to the symmetry principle of the stack-up structure; finally, the most suitable material specifications are selected from the PCB manufacturing plant's commonly used material list.

[0115] When there are no explicit impedance requirements in the design document, the approach depends on whether the dielectric layer thickness is defined in the document. If the dielectric layer thickness is defined in the document, these parameters are used directly; if the dielectric layer thickness is not defined in the document, the simplest design approach for a laminated structure is adopted, prioritizing a single type of PP material and using an average core board thickness design to simplify manufacturing processes and material management.

[0116] When designing a laminated structure, several engineering constraints need to be considered: ensuring the total board thickness is within manufacturing tolerances; maintaining the symmetry of the laminated structure to avoid board bending or warping; for applications with explicit 2-ply requirements, ensuring that each dielectric layer uses at least two sheets of PP material; verifying the filler thickness to avoid quality issues caused by insufficient filler, such as avoiding the use of low-filler-content PP material near 2oz copper thickness; selecting the most cost-effective solution, prioritizing combinations with the fewest PP sheets, and using commonly used materials from the bill of materials as much as possible; and ultimately ensuring the laminated structure is as simple as possible for easy on-site operations, including minimizing the types of PP and cores to improve production efficiency and yield.

[0117] In some embodiments of this application, step S500, which involves automatically generating an optimized mosaicking scheme using a mosaicking algorithm, specifically includes: Step S521: Plan according to the hierarchical relationship of raw material board size, production panel size, panel array size and unit board size.

[0118] In step S521, a rigorous top-down and bottom-up combined panel design logic framework was constructed to ensure that subsequent automated calculations strictly adhere to the physical constraints and process flow of the PCB manufacturing site. In actual production, panelization is not a simple graphic replication, but a complex system engineering project involving multi-level nested dimensions. The size of the raw material board determines the upper limit of the physical boundary of production, the size of the production panel is limited by the equipment processing capacity and transportation requirements, the size of the panel array is the intermediate carrier connecting the unit boards and the main board, and the size of the unit board is the core origin of the design.

[0119] By clarifying the hierarchical dependencies among these four elements, the system can establish a structured parameter model, avoiding unmanufacturable puzzle designs or material waste caused by chaotic size definitions. This step defines a legitimate search space for subsequent algorithm iterations, ensuring that each generated puzzle design is physically feasible and executable. It also provides a clear traceability path for size adjustments at different levels, serving as the fundamental architectural support for intelligent puzzle optimization.

[0120] Step S522: When it is necessary to design the array size, define the unit board spacing, the spacing between the unit board and the broken edge, and the width of the broken edge according to the factory rules.

[0121] In step S522, the abstract geometric arrangement is transformed into a physical layout that meets the specific manufacturing process requirements of the factory, ensuring the manufacturability and yield of the panelization scheme. Different PCB manufacturers have different equipment capabilities and process specifications, such as the minimum spacing requirements of V-cut depaneling machines, the limitations on the width of the broken edge of milling cutters, and the regulations on the safe distance of components in surface mount technology (SMT) plants.

[0122] This step automatically fills in necessary isolation areas between unit boards and between unit boards and process edges by calling a preset factory rule library. This is not only to prevent damage to circuits or components during the board separation process, but also to reserve sufficient process edges to support reference points, test points, and conveyor track clamping areas. By standardizing these key spacing parameters, the system can effectively avoid the risk of batch scrap due to design violations, while ensuring the mechanical strength of the panel structure, making it stable in subsequent SMT placement and assembly testing stages, demonstrating the deep adaptation of the design to the manufacturing environment.

[0123] Step S523: Use enumeration to design multiple array panel sizes, and for each array panel size, select the production panel size with the highest utilization rate according to the rules for margins and gaps in the production panels.

[0124] In step S523, an exhaustive search strategy is used to overcome the limitations of human experience, searching for local optima in a multi-dimensional solution space to maximize the potential for material utilization. Since the size of the unit panel and the size of the large panel are often not integer multiples, simple row and column arrangements easily generate edge waste. This step utilizes the high-speed computing power of a computer to systematically traverse all possible row and column combinations (i.e., various array panel sizes) and simulate the arrangement of each combination in a standard production panel.

[0125] During this process, the system strictly applies edge allowance and gap rules to eliminate invalid solutions that, while theoretically numerous, cannot be practically produced due to exceeding process edge limits. This rule-based screening mechanism ensures that the retained candidate solutions are not only mathematically feasible but also engineering compliant. It effectively solves the problem of balancing edge allowance and output quantity in traditional manual panelization, providing a rich and high-quality set of alternatives for final global optimization.

[0126] Step S524: Calculate the overall utilization rate corresponding to each array panel size. The overall utilization rate is equal to the product of the panel utilization rate and the large panel utilization rate.

[0127] In step S524, a scientific, comprehensive evaluation index system that maximizes economic benefits was established, correcting the decision-making bias that might result from a single-dimensional evaluation. Traditional panelization thinking often focuses only on the number of unit panels within a single production panel (i.e., panel utilization rate), neglecting the cutting efficiency of that production panel on the raw material slab (i.e., slab utilization rate). Sometimes, a high-output production panel size may result in a large amount of waste due to the inability to neatly arrange it on the slab, thus reducing overall efficiency.

[0128] This step introduces the composite indicator of comprehensive utilization rate, coupling the micro-level panel assembly efficiency with the macro-level material cutting efficiency for calculation. The product is maximized only when both reach a high level. This dual constraint mechanism forces the algorithm to pursue high output per panel while also considering the neatness of large panel cutting, thus truly achieving cost control throughout the entire chain from raw material procurement to finished product output, embodying the core concept of lean manufacturing.

[0129] Step S525: Select the array panel size with the highest overall utilization rate and the corresponding production panel size as the final panel scheme.

[0130] In step S525, the closed loop from massive data calculation to final engineering decision-making is completed, outputting the optimal execution instruction that combines economy and operability. After layers of screening and quantitative evaluation in the preceding steps, the system has generated a ranked list containing various potential solutions. This step, as the decision endpoint, directly identifies the combination with the highest comprehensive utilization rate as the sole recommended solution. This not only means that this solution can save the customer the most sheet metal costs, but also that it is the optimal resource allocation method under the current factory rules.

[0131] More importantly, this step outputs not just two dimensional figures, but a complete set of production guidance data, including specific row and column numbers, process edge widths, and layout coordinates. It transforms complex operations research calculations into standardized work documents that frontline CAM engineers can directly apply or only need simple confirmation, greatly shortening project lead time and improving quotation response speed. This is a key delivery step for automated panelization systems to generate real commercial value.

[0132] In some embodiments of this application, the four hierarchical concepts involved in the panelization process and their logical relationship from smallest to largest size are first clarified: unit size (PCS), panel size (Array), production panel size (Panel), and raw material size (Sheet). The raw material size (Sheet) is typically a few fixed specifications, such as 36 inches x 48 inches, 40 inches x 48 inches, and 42 inches x 48 inches. These standard sizes are stored and managed using configuration files. The production panel size (Panel) generally varies between 14 inches x 16 inches and 24 inches x 36 inches, depending on the factory's equipment and process capabilities. Some factories may directly use pre-cut panels provided by raw material suppliers without secondary cutting from the raw materials. Commonly used panel sizes are also preset through configuration files.

[0133] In some embodiments of this application, the system first determines whether it needs to automatically generate the array size. In some cases, the array size has already been pre-designed in the customer-provided data, or the unit size (PCS) itself is large enough that no additional array design is required according to factory rules. In both cases, the system will skip the array size design stage and directly proceed to the subsequent large board size selection process.

[0134] In some embodiments of this application, when the system determines that panel dimensions need to be automatically generated, it first defines relevant process parameters according to factory rules, including the spacing between units, the spacing between units and the break-off edge, and the width of the break-off edge. Simultaneously, the system also defines the margin and gap rules in the large panel according to factory rules. For example, different margin width requirements are set for panels with different numbers of layers or different pressing times, providing accurate constraints for subsequent automated enumeration design.

[0135] In some embodiments of this application, the system employs an enumeration method to design various panel size schemes. For example, the system will try various permutations and combinations such as 2 panels (e.g., 2 x 1, 1 x 2), 3 panels (e.g., 3 x 1, 1 x 3), and 4 panels (e.g., 2 x 2, 1 x 4, 4 x 1). Furthermore, in each panel size scheme, it will further distinguish whether the broken edge is added to the top or bottom or left and right positions, thereby exhaustively enumerating all potential panel layout schemes that conform to the process rules.

[0136] In some embodiments of this application, for each panel size scheme generated by enumeration, the system selects the panel size with the highest utilization rate and its corresponding raw material size from the configuration file based on the aforementioned panel margin and gap rules. Subsequently, the system calculates the overall utilization rate of each scheme, which is the product of the panel utilization rate and the raw material utilization rate. By comparing the overall utilization rates of all schemes, the system ultimately selects the panel size with the highest overall utilization rate as the recommended panel design scheme.

[0137] In some embodiments of this application, for cases where panel size design is not required, the system directly employs the margin and gap rule definition, large board size screening, and overall utilization calculation steps described above, i.e., directly selecting the optimal large board size based solely on the unit size. This automated panel design method effectively overcomes the limitations imposed by engineers' time and experience in traditional manual panel design, avoiding suboptimal material utilization and thus significantly reducing raw material costs in the PCB manufacturing process.

[0138] Secondly, refer to Figure 2 This application provides a PCB data processing system based on a local large-scale model, used to implement the aforementioned PCB data processing method based on a local large-scale model. The system includes a data parsing module, an information fusion module, an intelligent optimization module, and a data interface module.

[0139] In some embodiments of this application, the data parsing module is used to obtain PCB design data packages, use a locally deployed multimodal large language model to parse specification documents to extract key design parameters, and use a Gerber parsing library to parse Gerber design data to extract key layer and hole layer information.

[0140] Specifically, this module first acquires a PCB design data package containing specifications and Gerber files. It then utilizes a locally deployed multimodal large language model to deeply understand the natural language descriptions in the specifications, accurately extracting key design parameters such as target impedance and board type. Simultaneously, it uses a professional Gerber parsing library to process the binary graphic data, extracting key layers and via information such as trace layers, dielectric layers, and drill layers. This process achieves cross-modal conversion between machine language and engineering language, laying a solid data foundation for subsequent automated processing.

[0141] In some embodiments of this application, the information fusion module is used to compare and fuse key design parameters with key layer and hole layer information to generate structured PCB design requirement information.

[0142] Specifically, this module performs in-depth comparison and correlation analysis of key design parameters obtained during the data parsing phase with key layer and hole layer information. For example, it verifies whether the drilling data is consistent with the interlayer connection requirements, or whether the impedance requirements have a corresponding reference plane. Through this fusion process, the system can generate a set of logically consistent, complete, and structured PCB design requirements information, ensuring that subsequent design solutions meet both the customer's electrical performance expectations and the requirements for physical structural integrity.

[0143] In some embodiments of this application, the intelligent optimization module is used to automatically generate optimized stack-up structure schemes and panelization schemes based on PCB design requirements information and a preset PCB manufacturing plant process rule library, using impedance calculation models and panelization algorithms.

[0144] Specifically, based on structured PCB design requirements, this module strictly adheres to constraints in a pre-defined PCB manufacturing plant process rule library, and uses a high-precision impedance calculation model and an efficient panelization algorithm for parallel computation. It can not only automatically derive stack-up structure schemes that meet signal integrity requirements but also generate panelization schemes with optimal material utilization. This step replaces the traditional process of repeated manual trial and error, automating and optimizing engineering design schemes, and significantly improving design efficiency and quality.

[0145] In some embodiments of this application, the data docking module is used to store the optimized stacked structure scheme and panel scheme data into the database, and dock with the quotation system to calculate the cost and obtain the production cost and quotation.

[0146] Specifically, this module standardizes and encapsulates the final stacked structure and panel design data generated by the intelligent optimization module and stores them in a database, forming a traceable project archive. Simultaneously, it directly connects to the company's quotation system, transmitting design data including material usage, layer count, and process complexity in real time, triggering an automated cost calculation process. This not only streamlines the data link from engineering design to commercial quotation but also significantly shortens order response time and improves the company's market responsiveness.

[0147] In some embodiments of this application, the system employs a PostgreSQL relational database as its core data storage engine to persistently store all structured data analyzed in the aforementioned steps. Specifically, the system establishes dedicated data table structures such as impedance tables, drilling tables, laminated structure tables, and panel design tables, storing the calculated impedance parameters, drilling process information, finalized laminated schemes, and panel utilization data in a corresponding manner. This relational database-based storage method not only ensures data consistency and integrity but also supports complex relational queries, providing a solid data foundation for subsequent data mining, historical scheme backtracking, and the construction of an enterprise knowledge base.

[0148] In some embodiments of this application, the system possesses a high degree of openness and compatibility, supporting seamless integration with existing factory quotation systems, work order design systems, or manufacturing execution systems (MES) via application programming interfaces (APIs) or structured query languages ​​(SQL). Through standardized data interfaces, the system can push the generated stacked structure schemes and panelization schemes to downstream business systems in real time, breaking down information silos and automating the data flow from engineering data processing to production management, ensuring data consistency and real-time performance at each stage.

[0149] In some embodiments of this application, the system's cost calculation function employs a flexible, configurable design. The cost calculation model is defined by each PCB manufacturing plant based on its own equipment status, material costs, and process capabilities. The system does not pre-set a fixed cost formula but provides a configurable parameter interface, allowing plants to input specific material unit prices, process rates, and loss coefficients. Upon receiving stack-up and panelization data, the system automatically performs calculations based on the plant's custom model, thereby generating quotation data that accurately reflects the plant's actual production costs, meeting the personalized management needs of plants of different sizes and types.

[0150] Furthermore, embodiments of this application provide an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the PCB data processing method based on the local large model as described above.

[0151] Furthermore, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the aforementioned PCB data processing method based on a local large model.

[0152] In summary, the PCB data processing method and related equipment based on a local large model provided in this application have the following technical effects.

[0153] This application employs a locally deployed multimodal large language model, which effectively protects the privacy and security of core PCB design data while achieving automated fusion and structured processing of multi-source heterogeneous data. By leveraging the semantic understanding and image recognition capabilities of the large model to automatically extract specification parameters and cross-compare and detect conflicts with Gerber parsing results, it not only replaces the traditional, inefficient, and error-prone manual data entry and verification process but also significantly improves the accuracy and error tolerance of engineering data processing through a "machine review + human review" fault-tolerance mechanism, greatly reducing the risk of production accidents caused by data errors.

[0154] Building upon this foundation, this application integrates a pre-defined factory process rule library to achieve intelligent and cost-optimized process design. By employing an iterative strategy with pre-defined priorities to automatically generate stack-up structures that meet impedance requirements, and using an enumeration method to calculate the panelization scheme with the highest overall utilization rate (the product of panel utilization rate and large board utilization rate), it can minimize the waste of raw materials such as prepreg and improve board utilization rate while ensuring electrical performance and manufacturing compliance. This directly reduces the company's production costs and effectively enhances the market competitiveness of PCB manufacturers.

[0155] It should be noted that in all specific embodiments of this application, when processing data related to user identity or characteristics, such as user information, user behavior data, user historical data, and user location information, user permission or consent is obtained first. Furthermore, the collection, use, and processing of this data comply with relevant laws, regulations, and standards of the relevant countries and regions. In addition, when embodiments of this application require access to sensitive personal information of users, separate permission or consent from the user is obtained through pop-ups or redirects to confirmation pages. Only after obtaining the user's separate permission or consent is the necessary user-related data for the proper functioning of the embodiments of this application obtained.

[0156] In some alternative embodiments, the functions / operations mentioned in the block diagrams may not occur in the order shown in the operation diagrams. For example, depending on the functions / operations involved, two consecutively shown blocks may actually be executed substantially simultaneously, or the blocks may sometimes be executed in reverse order. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example to provide a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and sub-operations described as part of a larger operation are executed independently.

[0157] Furthermore, although this application is described in the context of functional modules, it should be understood that, unless otherwise stated, one or more of the functions and / or features may be integrated into a single physical device and / or software module, or one or more functions and / or features may be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding this application. Rather, given the properties, functions, and internal relationships of the various functional modules in the apparatus disclosed herein, the actual implementation of the module will be understood within the scope of ordinary skill of an engineer. Therefore, those skilled in the art can implement the application set forth in the claims using ordinary skill. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of this application, which is determined by the full scope of the appended claims and their equivalents.

[0158] If a function is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several programs to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0159] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequential list of executable programs for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, a program execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can retrieve and execute a program from or in conjunction with such a program execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can mean any means that can contain, store, communicate, propagate, or transmit a program for use by or in conjunction with a program execution system, apparatus, or device.

[0160] More specific examples (a non-exhaustive list) of computer-readable media include: electrical connections (electronic devices) having one or more wires, portable computer disk drives (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Furthermore, computer-readable media can even be paper or other suitable media on which programs can be printed, because programs can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpreting, or, if necessary, processing in a suitable manner, and then stored in computer memory.

[0161] It should be understood that various parts of the present invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in memory and executed by a suitable program execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0162] In the foregoing description of this specification, the reference to terms such as "one embodiment / implementation," "another embodiment / implementation," or "certain embodiments / implementations," etc., indicates that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in an embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0163] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

[0164] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A PCB data processing method based on a local large model, characterized in that, Includes the following steps: Obtain a PCB design data package, which includes unstructured specification documents and structured Gerber design data; The specification document is semantically segmented and parsed using a locally deployed multimodal large language model to extract key design parameters; The Gerber design data is parsed using a pre-defined Gerber parsing library, and key layer and hole layer information is extracted based on the file header description, file name rules and file content. The key design parameters are compared and fused with the key layer and hole layer information to generate structured PCB design requirements information. Based on the PCB design requirements, and combined with the preset PCB manufacturing plant process rule library, optimized stack-up structure schemes and panelization schemes are automatically generated using impedance calculation models and panelization algorithms. The optimized stacked structure scheme and panel scheme data are stored in the database and connected to the quotation system to calculate costs, thereby obtaining production costs and quotations.

2. The PCB data processing method based on a local large model according to claim 1, characterized in that, The step of using a locally deployed multimodal large language model to perform semantic region segmentation and parsing of the specification document to extract key design parameters specifically includes: The target detection model is used to identify the pages of the specification document and segment the pages into stack-up diagrams, drilling tables, board block diagrams, impedance tables and specification requirement block images. During the segmentation process, an inclusive annotation rule is adopted to incorporate all dimension lines, arrows, leaders, and numbers that are visually or semantically related to the PCB main drawing into the outline dimension drawing area. The segmented block images are input into the multimodal large language model, and the multimodal large language model is guided by a preset prompt template to output key design parameters in structured JSON format; The key design parameters include impedance value, plate thickness, material type, plate frame size, and number of layers.

3. The PCB data processing method based on a local large model according to claim 1, characterized in that, The step of using a pre-defined Gerber parsing library to parse the Gerber design data and extract key layers and hole layer information specifically includes: The preset graphic data parsing tool is invoked to parse Gerber files and drill files that conform to the PCB manufacturing standard format; Layer types are identified based on preset layer naming mapping rules. These rules map solder mask identifiers contained in filenames or file headers to solder mask layers, silkscreen identifiers to text layers, and drill identifiers to drill layers. The file header and content of the borehole layer are parsed to obtain information on the start layer, end layer, borehole diameter and number of boreholes, identify the drilling process and borehole type, and calculate the borehole density and borehole wall gold area. The drilling types include through holes, blind holes, buried holes, back drilled holes, fixed-depth drilled holes, or countersunk holes.

4. The PCB data processing method based on a local large model according to claim 1, characterized in that, The method also includes a collision detection step: When the PCB size or number of layers in the key design parameters is inconsistent with the information extracted from the Gerber design data, the program determines it as an error message; The error message and related information are sent to the engineer's terminal for manual secondary evaluation.

5. The PCB data processing method based on a local large model according to claim 1, characterized in that, The method of automatically generating optimized stacked structure schemes using impedance calculation models specifically includes: The initial stacked structure is determined based on borehole layer information and the total number of layers; If there is an impedance requirement and the dielectric layer thickness is not defined in the document, the dielectric layer thickness can be calculated by working backward from the impedance calculation formula based on the impedance requirement and the line width / line spacing. When calculating the thickness of the dielectric layer, a preset priority iteration strategy is adopted. The priority iteration strategy includes: inner layer first, then outer layer; differential first, then characteristic; core board thickness first, then prepreg thickness; and layers with impedance first, then layers without impedance. Under the conditions of satisfying the total board thickness tolerance, the symmetry of the laminated structure and the constraints of factory material inventory, the final laminated structure scheme is generated with the goal of minimizing the number of prepreg sheets and simplifying the laminated structure.

6. The PCB data processing method based on a local large model according to claim 5, characterized in that, The method includes the following impedance calculation steps: Inner layer single-ended impedance calculation: Based on the stripline transmission model, a logarithmic function relationship is constructed using the inner layer dielectric thickness, conductor width and copper thickness to calculate the inner layer single-ended impedance value; Inner layer differential impedance calculation: Based on the inner layer single-ended impedance value, an exponential decay function is constructed using the ratio of the differential pair line spacing to the inner layer dielectric thickness, and the line coupling correction coefficient is calculated to obtain the inner layer differential impedance value. Outer layer single-ended impedance calculation: First, the effective dielectric constant, including the influence of the solder mask layer, is calculated based on the substrate dielectric constant. Then, based on the microstrip line transmission model, a logarithmic function relationship is constructed using the effective dielectric constant, outer layer dielectric thickness, conductor width, and copper thickness to calculate the outer layer single-ended impedance value. Calculation of outer layer differential impedance: Based on the single-ended impedance value of the outer layer, an exponential decay function is constructed using the ratio of the differential pair line spacing to the outer layer dielectric thickness. The line coupling correction coefficient is then calculated to obtain the outer layer differential impedance value.

7. The PCB data processing method based on a local large model according to claim 1, characterized in that, The algorithm automatically generates optimized puzzle layouts, including: The planning is based on the hierarchical relationship between the raw material board size, the production panel size, the panel array size, and the unit board size; When it is necessary to design the array size, define the unit board spacing, the spacing between the unit board and the broken edge, and the broken edge width according to the factory rules; Multiple array panel sizes are designed using an enumeration method. For each array panel size, the production panel size with the highest utilization rate is selected based on the rules for margins and gaps in the production panels. Calculate the overall utilization rate corresponding to each array panel size, where the overall utilization rate is equal to the product of the panel utilization rate and the large panel utilization rate; The array panel size with the highest overall utilization rate and the corresponding production panel size are selected as the final panel design.

8. A PCB data processing system based on a local large model, characterized in that, Used to implement the PCB data processing method based on a local large model as described in any one of claims 1 to 7; The system includes: The data parsing module is used to obtain PCB design data packages, use a locally deployed multimodal large language model to parse specification documents to extract key design parameters, and use the Gerber parsing library to parse Gerber design data to extract key layer and hole layer information. The information fusion module is used to compare and fuse the key design parameters with the key layer and hole layer information to generate structured PCB design requirement information. The intelligent optimization module is used to automatically generate optimized stack-up structure schemes and panelization schemes based on the PCB design requirements information and in combination with a preset PCB manufacturing plant process rule library, using impedance calculation models and panelization algorithms. The data docking module is used to store the optimized stacked structure scheme and panel scheme data into the database, and dock with the quotation system to calculate costs and obtain production costs and quotations.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the PCB data processing method based on a local large model as described in any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the PCB data processing method based on a local large model as described in any one of claims 1 to 7.

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