Fpga timing hypergraph construction method and device, terminal equipment and storage medium

Abstract

The application discloses an FPGA timing hypergraph construction method and device, a terminal equipment and a storage medium, wherein the method comprises the following steps: traversing a user netlist, and dividing function modules for realizing the user netlist in an FPGA chip into macro unit modules, programmable logic modules and combination logic modules; creating a corresponding first hypernode and a corresponding hyperedge for each combination logic module; creating a group of second hypernodes and corresponding hyperedges for the macro unit modules; creating a corresponding third hypernode and a corresponding hyperedge for each programmable logic module, and performing topological sorting according to the hierarchical relationship between the modules to obtain a first timing hypergraph. The application can effectively avoid repeated definition of nodes or redundant connection caused by unclear module types, effectively reduce the node management complexity, and further effectively improve the mapping efficiency. Moreover, the hyperedges are created in steps based on the module types and data transmission relationship, so that the calculation amount of the hyperedge generation is reduced, and the mapping efficiency is further effectively improved.

Description

Technical Field

[0001] This invention relates to the field of microcircuit analysis technology, and in particular to a method, apparatus, terminal device and storage medium for constructing FPGA timing hypergraphs. Background Technology

[0002] After the user's design is synthesized using FPGA (Field Programmable Gate Array) dedicated EDA tools, it is transformed into a circuit netlist composed of various circuit modules on the FPGA. The timing diagram is a graphical representation of the circuit netlist from a timing analysis perspective. A timing diagram is a directed acyclic graph (DAG) consisting of timing nodes and timing edges. Timing nodes correspond one-to-one with the pins of circuit modules, and timing edges represent the signal transmission relationships between the pins of different circuit modules, which are reflected in the timing diagram as the topological relationships between timing nodes. After building the timing diagram based on the circuit netlist, the delay information of various components in the circuit, as well as user-defined constraints, can be marked on the timing diagram. Finally, timing analysis can be performed on this marked timing diagram to identify timing paths with timing violations in the current stage of the circuit, guiding the EDA engine to optimize these violation paths until timing convergence is achieved, thus meeting the user's design goals. The timing hypergraph is implemented based on the established timing graph. If the timing graph is a directed acyclic graph with pins as the granularity, the timing hypergraph is a directed acyclic graph with FPGA basic circuit modules as the granularity after abstracting and extracting certain key features from the timing graph. The timing hypergraph can provide optimization guidance for EDA tools from a higher level of perspective.

[0003] As the application scenarios of FPGA chips become increasingly complex and their integration levels continue to rise, more and more heterogeneous functional modules (IPs) that meet specific needs are being integrated into FPGA chips. Examples include block RAM (BRAM) modules for storage and digital signal processing (DSP) modules for mathematical and logical operations. During the back-end placement and routing phase, these heterogeneous modules are uniformly treated as macrocells and participate in placement along with the PLB modules in the FPGA. However, since these macrocells typically require a large number of signals to interact with, competition for routing resources arises between macrocells. Therefore, for a design, the rationality of the initial allocation of macrocell positions during the placement phase directly affects the subsequent routing success and the complexity of timing convergence.

[0004] Existing FPGA timing hypergraph construction methods suffer from problems such as mixed module types and redundant dependencies during the timing hypergraph construction process, resulting in low construction efficiency. Summary of the Invention

[0005] This invention provides a method, apparatus, terminal device, and storage medium for constructing FPGA timing hypergraphs, in order to solve the technical problem that existing FPGA timing hypergraph construction methods have problems such as mixed module types and redundant dependencies during the timing hypergraph construction process, resulting in low construction efficiency of timing hypergraphs.

[0006] This invention provides a method for constructing an FPGA timing hypergraph, comprising:

[0007] Traverse the user netlist and divide the functional modules in the FPGA chip that implement the user netlist into macrocell modules, programmable logic modules, and combinational logic modules; wherein, the user netlist is obtained based on user design mapping;

[0008] For each of the combined logic modules, a corresponding first super node is created, and based on the data signal transmission relationship in the user netlist, a corresponding super edge is created for the first super node;

[0009] A set of second supernodes is created for the macrocell module, and a superedge corresponding to the second supernode is created according to the data signal transmission relationship between the second supernode and the first supernode;

[0010] A third supernode is created for each of the programmable logic modules. Based on the data transmission relationship between the third supernode and the second and first supernodes, a superedge is created for the third supernode. The topology is sorted according to the hierarchical relationship between the macrocell module, the programmable logic module and the combinational logic module to obtain a first temporal hypergraph.

[0011] Furthermore, after obtaining the first temporal hypergraph, it also includes:

[0012] According to the order of the first time sequence hypergraph from low to high, each super node of each of the first time sequence hypergraphs is traversed to determine whether each super node corresponds to a pure combinational logic module.

[0013] When determining that the current supernode in the first temporal hypergraph corresponds to a pure combinational logic module, the current supernode is eliminated from the first temporal hypergraph, and the upstream and downstream superedges in the current supernode are merged to obtain the second temporal hypergraph.

[0014] Furthermore, after obtaining the second temporal hypergraph, it also includes:

[0015] Traverse the second supernodes of the macrocell modules in the second temporal hypergraph, construct the hyperpaths between the macrocell modules based on the second supernodes, and obtain the third temporal hypergraph.

[0016] Furthermore, the creation of the third supernode corresponding to each of the programmable logic modules includes:

[0017] Based on the configuration information of the programmable logic module, a third supernode is created corresponding to each programmable logic module, wherein the configuration information is used to configure the programmable logic module as a pure combinational logic module or a sequential logic module.

[0018] Furthermore, the step of constructing the hyperpaths between the macrounit modules based on the second supernode to obtain the third temporal hypergraph includes:

[0019] Based on the total number of timing units recorded in the second supernode and the ID information of the starting macrocell module, a superpath between macrocell modules is constructed to obtain a third timing supergraph, wherein the starting macrocell module is the first macrocell module in a data transmission path.

[0020] Furthermore, before constructing the hyperpath between macrocell modules based on the total number of temporal units recorded in the second supernode and the ID information of the starting macrocell module to obtain the third temporal hypergraph, the process also includes:

[0021] According to the level of the second time sequence hypergraph from low to high, traverse each super node of each level in the second time sequence hypergraph and determine whether each super node corresponds to a time sequence logic module.

[0022] When determining the timing logic module corresponding to the current supernode in the second timing supergraph, all input source supernodes within the current supernode are traversed, and the timing unit count value is obtained according to the input source supernode. The total number of timing units when traversing to the endpoint macrocell module of the data transmission path is counted, and the total number of timing units and the starting macrocell module ID of each data transmission path are recorded on the second supernode of the endpoint macrocell module.

[0023] Furthermore, the second supernode includes an input supernode and an output supernode.

[0024] The present invention also provides an FPGA timing hypergraph construction apparatus, comprising:

[0025] The functional module partitioning module is used to traverse the user netlist and divide the functional modules in the FPGA chip that implement the user netlist into macrocell modules, programmable logic modules, and combinational logic modules; wherein, the user netlist is obtained based on user design mapping;

[0026] The first superedge creation module is used to create a corresponding first supernode for each of the combinational logic modules, and to create a corresponding superedge for the first supernode based on the data signal transmission relationship in the user netlist.

[0027] The second superedge creation module is used to create a set of second supernodes for the macrocell module and create the superedge corresponding to the second supernode according to the data signal transmission relationship between the second supernode and the first supernode.

[0028] The first temporal hypergraph construction module is used to create a third supernode corresponding to each of the programmable logic modules, create a hyperedge corresponding to the third supernode according to the data transmission relationship between the third supernode and the second supernode and the first supernode respectively, and perform topological sorting according to the hierarchical relationship between the macrocell module, the programmable logic module and the combinational logic module to obtain the first temporal hypergraph.

[0029] The present invention also provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the FPGA timing hypergraph construction method as described above.

[0030] The present invention also provides a computer-readable storage medium comprising a stored computer program; wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the FPGA timing hypergraph construction method as described above.

[0031] This invention divides the functional modules for implementing user netlists into macro-unit modules, programmable logic modules, and combinational logic modules, and creates corresponding supernodes for each different category of modules. This effectively avoids redundant node definitions or connections caused by unclear module types, effectively reduces node management complexity, and thus effectively improves graph construction efficiency. Moreover, the embodiments of this invention create hyperedges step by step based on module type and data transmission relationship, which reduces the computational load of hyperedge generation and thus effectively improves graph construction efficiency.

[0032] Furthermore, this invention constructs hyperpaths between macrocell modules using two core parameters: the total number of timing units and the starting macrocell ID. This allows the dispersed physical paths to be abstracted into global optimization features, significantly improving the automation level of FPGA design and effectively increasing mapping efficiency. Attached Figure Description

[0033] Figure 1 This is a flowchart illustrating the FPGA timing hypergraph construction method provided in this embodiment of the invention;

[0034] Figure 2 This is a schematic diagram of the structure of the first temporal hypergraph provided in an embodiment of the present invention;

[0035] Figure 3 This is a schematic diagram of the structure of the second temporal hypergraph provided in an embodiment of the present invention;

[0036] Figure 4 This is a schematic diagram of the structure of the third temporal hypergraph provided in an embodiment of the present invention;

[0037] Figure 5 This is a schematic diagram of the FPGA timing supergraph construction device provided in an embodiment of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0039] In the description of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "multiple" means two or more.

[0040] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0041] Please see Figure 1 This invention provides a method for constructing an FPGA timing hypergraph, comprising:

[0042] S1. Traverse the user netlist and divide the functional modules in the FPGA chip that implement the user netlist into macrocell modules, programmable logic modules, and combinational logic modules; where the user netlist is obtained based on the user design mapping;

[0043] In this embodiment of the invention, user designs can be optimized using EDA, mapping the user design into a user netlist implemented by various functional modules on the FPGA chip. The user design is a description of the circuit function and behavior defined by the user using a hardware description language (such as Verilog, VHDL) or a high-level synthesis tool (HLS), describing the functional modules, signal transmission relationships, and timing constraints of the circuit, but not yet bound to specific hardware resources. The user netlist is the physical implementation structure generated after the user design is synthesized, optimized, and mapped by EDA tools (such as Vivado, Quartus), describing how the user design is instantiated by specific hardware resources on the FPGA chip (such as LUTs, registers, DSPs, BRAMs, etc.) and containing the connection relationships between modules.

[0044] In this embodiment of the invention, a static timing analysis tool can also be used to perform static timing analysis on the user netlist at this stage in order to construct the timing diagram corresponding to the user netlist.

[0045] In this embodiment of the invention, the macrocell module includes DSP / ERAM / IO, the programmable logic module is the PLB module, and the combinational logic module can be an adder, etc.

[0046] S2. Create a corresponding first supernode for each combinational logic module, and create a corresponding superedge for the first supernode based on the data signal transmission relationship in the user netlist.

[0047] When creating a first hypernode for each combinational logic module, macrocell modules and programmable logic modules encountered during traversal are skipped. At the same time, these skipped modules are collected for later processing, which can effectively reduce the number of traversals and thus improve graph construction efficiency.

[0048] In this embodiment of the invention, there is at most one hyperedge between two hypernodes. Hyperedges can be created between existing hypernodes based on the data signal transmission relationships in the user netlist. If the creation of a hyperedge involves signal transmission between the hypernode and the macrocell module or programmable logic module, the creation of corresponding hyperedges for these hypernodes is skipped first.

[0049] S3. Create a set of second supernodes for the macrocell module, and create the superedges corresponding to the second supernodes according to the data signal transmission relationship between the second supernodes and the first supernodes;

[0050] In this embodiment of the invention, a set of second supernodes includes input supernodes and output supernodes of macrounit modules. Since the timing hypergraph can describe the timing proximity between macrounit modules, the final hyperpath formed by pairwise connections between macrounits in the timing hypergraph is based on the macrounit module as both the starting and ending point. This embodiment of the invention creates a set of second supernodes for each macrounit module, where the input supernode serves as the ending point of the hyperpath from other macrounit modules, and the output supernode serves as the starting point for transmission to other macrounit modules.

[0051] S4. Create a third supernode corresponding to each programmable logic module. Based on the data transmission relationship between the third supernode and the second and first supernodes, create a superedge corresponding to the third supernode. Perform topological sorting based on the hierarchical relationship between macrocell modules, programmable logic modules and combinational logic modules to obtain the first temporal hypergraph.

[0052] Please see Figure 2 In this embodiment of the invention, the first timing hypergraph includes I / O, macrocell modules, combinational logic modules, and timing logic modules, and the first timing hypergraph is a fine-grained timing hypergraph.

[0053] In this embodiment of the invention, a third supernode corresponding to each programmable logic module can be created based on the configuration information corresponding to the programmable logic module.

[0054] In this embodiment of the invention, the hyperedges between supernodes are used to describe the data signal transmission relationship of the corresponding modules. This embodiment of the invention can determine the dependency relationship by analyzing the source of the input signal and the destination of the output signal of the module, thereby determining the hierarchical relationship. For example, the input of a combinational logic module may come from the output of an IOB or a programmable logic module; the output of a programmable logic module (such as a CLB) may drive the input of a macrocell; and the hierarchy is divided according to the propagation direction of the timing critical path (such as the clock domain cross path) to ensure that the timing constraints of higher-level modules are processed first.

[0055] In this embodiment of the invention, the hierarchical relationship can also be determined according to the functional classification of modules. For example, macrocell modules are usually located at the top or bottom of the hierarchical structure and are responsible for handling high-complexity operations or data storage; programmable logic modules serve as intermediate levels to implement combinational logic or sequential logic and may connect macrocells and combinational logic modules at the same time; combinational logic modules are usually located at the bottom level and directly process raw signals or drive sequential logic modules.

[0056] This invention divides the functional modules for implementing user netlists into macro-unit modules, programmable logic modules, and combinational logic modules, and creates corresponding supernodes for each different category of modules. This effectively avoids redundant node definitions or connections caused by unclear module types, effectively reduces node management complexity, and thus effectively improves graph construction efficiency. Furthermore, this invention creates hyperedges step by step based on module type and data transmission relationships, which reduces the computational load of hyperedge generation and thus effectively improves graph construction efficiency.

[0057] In one embodiment, after obtaining the first temporal hypergraph in step S4, the method further includes:

[0058] S5. According to the order of the first time sequence hypergraph from low to high, traverse each super node of each of the first time sequence hypergraphs and determine whether each super node corresponds to a pure combinational logic module.

[0059] In this embodiment of the invention, based on the first temporal hypergraph obtained after topological sorting, each level is traversed from low to high according to its level, and the supernodes of each level are judged sequentially.

[0060] S6. When determining that the current supernode in the first temporal hypergraph corresponds to a pure combinational logic module, the current supernode is eliminated from the first temporal hypergraph, and the upstream and downstream superedges in the current supernode are merged to obtain the second temporal hypergraph.

[0061] In this context, the upstream superedge is the input connection of the current supernode, representing the data source path. The downstream superedge is the output connection from the current supernode to the subsequent module, representing the data destination path.

[0062] Please see Figure 3 This is a schematic diagram of the structure of a second temporal hypergraph provided in an embodiment of the present invention. The second temporal hypergraph is a medium-granularity temporal hypergraph.

[0063] In this embodiment of the invention, when the current supernode is detected to be a pure combinational logic module (such as an adder or a multiplexer), it does not contain timing units (such as flip-flops) and only performs logical operations on signals. By eliminating the node and merging its upstream and downstream super edges, the timing hypergraph is simplified, which can effectively reduce redundant nodes and reduce the computational complexity of the timing attributes of subsequent paths, avoid excessive computation time due to too many nodes, and effectively improve graph construction efficiency.

[0064] In one embodiment, after obtaining the second temporal hypergraph in S6, the method further includes:

[0065] S7. Traverse the second supernode of the macrocell module in the second temporal hypergraph, construct the hyperpath between macrocell modules based on the second supernode, and obtain the third temporal hypergraph.

[0066] Please see Figure 4 This is a schematic diagram of the structure of the third temporal hypergraph provided in an embodiment of the present invention. In this embodiment, the third temporal hypergraph is a coarse-grained temporal hypergraph.

[0067] In this embodiment of the invention, a third temporal hypergraph is obtained by constructing hyperpaths between macrounit modules based on the second supernode. This hypergraph can efficiently express temporal information based on the hyperpaths. By constructing hyperpaths, the temporal dependencies between macrounit modules can be effectively captured, thereby accurately displaying the dynamic features of the temporal hypergraph.

[0068] In one embodiment, S4, creating a third supernode corresponding to each programmable logic module, includes:

[0069] Based on the configuration information of the programmable logic module, a third supernode is created for each programmable logic module. The configuration information is used to configure the programmable logic module as a pure combinational logic module or a sequential logic module.

[0070] In this embodiment of the invention, the variable decimation logic module can be configured as a corresponding pure combinational logic module or a sequential logic module according to its configuration information. In this embodiment of the invention, a corresponding third supernode is created according to the configurable module.

[0071] This invention clarifies module types through configuration information, allowing for the targeted application of constraint rules to the temporal hypergraph, avoiding timing misjudgments caused by mixed logic, and thereby improving the accuracy of temporal hypergraph construction.

[0072] In one embodiment, step S7, constructing hyperpaths between macrocell modules based on the second supernode to obtain a third temporal hypergraph, includes:

[0073] Based on the total number of time units recorded in the second supernode and the ID information of the starting macrocell module, a superpath between macrocell modules is constructed to obtain the third time hypergraph, where the starting macrocell module is the first macrocell module in a data transmission path.

[0074] In this embodiment of the invention, the total number of timing units reflects the combinational logic depth and timing level in the path. For example, a high number of timing units, such as an accumulated value of 10+, can indicate a long combinational logic chain, which requires pipeline splitting; a low number of timing units, such as 1-2, indicates a simple path that can accept longer routing delays; in addition, the number of registers directly affects power consumption and area occupation, and high-density timing unit paths require optimized resource allocation.

[0075] The ID information of the starting macro unit module makes it easy for tools to track the starting point of the data path. Based on the ID information of the starting macro unit module, high-density macro unit modules can be placed nearby to reduce latency.

[0076] The embodiments of the present invention construct hyperpaths between macrocell modules through two core parameters: the total number of timing units and the starting macrocell ID. This can abstract the scattered physical paths into global optimization features, significantly improve the automation level of FPGA design, and effectively improve the mapping efficiency.

[0077] In one embodiment, before step S7 constructs the hyperpath between macrocell modules based on the total number of timing units recorded in the second supernode and the ID information of the starting macrocell module to obtain the third timing hypergraph, the method further includes:

[0078] S701. According to the level of the second time hypergraph from low to high, traverse each super node of each level in the second time hypergraph and determine whether each super node corresponds to a time logic module.

[0079] S702. When determining the timing logic module corresponding to the current supernode in the second timing supergraph, traverse all input source supernodes within the current supernode, obtain the timing unit count value based on the input source supernode, and count the total number of timing units when traversing to the endpoint macrocell module of the data transmission path. Record the total number of timing units and the starting macrocell module ID of each data transmission path on the second supernode of the endpoint macrocell module.

[0080] In this embodiment of the invention, the input source supernode records the timing unit count value. The timing unit count value can be read from the attributes of each input source supernode. For example, if the input source supernode is a register module containing 3 flip-flops, then its count value is 3.

[0081] In this embodiment of the invention, the number of input source supernodes in the data transmission path is accumulated into the total number of timing units of the current module. When the last macrocell module in the data transmission path is reached, the counting of timing units in the data transmission path is stopped, and the total number of timing units and the starting macrocell module ID are recorded on the second supernode of the ending macrocell module.

[0082] In this embodiment of the invention, a third temporal hypergraph is obtained by constructing a hyperpath between macrocell modules based on the second supernode. The hyperpath includes the number of temporal logic data transmission paths between two macrocell modules and the number of temporal logic data transmission paths for each data transmission path, thereby constituting the temporal proximity feature between macrocell modules.

[0083] Implementing the embodiments of the present invention has the following beneficial effects:

[0084] This invention divides the functional modules for implementing user netlists into macro-unit modules, programmable logic modules, and combinational logic modules, and creates corresponding supernodes for each different category of modules. This effectively avoids redundant node definitions or connections caused by unclear module types, effectively reduces node management complexity, and thus effectively improves graph construction efficiency. Furthermore, this invention creates hyperedges step by step based on module type and data transmission relationships, which reduces the computational load of hyperedge generation and thus effectively improves graph construction efficiency.

[0085] Furthermore, this embodiment of the invention constructs hyperpaths between macrocell modules using two core parameters: the total number of timing units and the starting macrocell ID. This allows the dispersed physical paths to be abstracted into global optimization features, significantly improving the automation level of FPGA design and effectively increasing mapping efficiency.

[0086] Please see Figure 5 Based on the same inventive concept as the above embodiments, the present invention also provides an FPGA timing supergraph construction apparatus, comprising:

[0087] Functional module partitioning module 10 is used to traverse the user netlist and divide the functional modules in the FPGA chip that implement the user netlist into macrocell modules, programmable logic modules, and combinational logic modules; wherein, the user netlist is obtained based on the user design mapping;

[0088] The first superedge creation module 20 is used to create a corresponding first supernode for each combinational logic module and to create a corresponding superedge for the first supernode based on the data signal transmission relationship in the user netlist.

[0089] The second superedge creation module 30 is used to create a group of second supernodes for the macrocell module and create the superedges corresponding to the second supernodes according to the data signal transmission relationship between the second supernodes and the first supernodes.

[0090] The first temporal hypergraph construction module 40 is used to create a third supernode corresponding to each programmable logic module, create a hyperedge corresponding to the third supernode based on the data transmission relationship between the third supernode and the second and first supernodes respectively, and perform topological sorting based on the hierarchical relationship between macrocell modules, programmable logic modules and combinational logic modules to obtain the first temporal hypergraph.

[0091] In one embodiment, the FPGA timing hypergraph construction apparatus further includes a second timing hypergraph construction module, used for:

[0092] According to the order of the first time sequence hypergraph from low to high, traverse each super node of each of the first time sequence hypergraphs and determine whether each super node corresponds to a pure combinational logic module.

[0093] When determining the pure combinational logic module corresponding to the current supernode in the first temporal hypergraph, the current supernode is eliminated from the first temporal hypergraph, and the upstream and downstream superedges in the current supernode are merged to obtain the second temporal hypergraph.

[0094] In one embodiment, the FPGA timing hypergraph construction apparatus further includes a third timing hypergraph construction module, used for:

[0095] Traverse the second supernode of the macrounit module in the second temporal hypergraph, construct the hyperpath between macrounit modules based on the second supernode, and obtain the third temporal hypergraph.

[0096] In one embodiment, the first temporal hypergraph construction module 40 is further configured to:

[0097] Based on the configuration information of the programmable logic module, a third supernode is created for each programmable logic module. The configuration information is used to configure the programmable logic module as a pure combinational logic module or a sequential logic module.

[0098] In one embodiment, a third temporal hypergraph is obtained by constructing hyperpaths between macrounit modules based on the second supernode, including:

[0099] Based on the total number of time units recorded in the second supernode and the ID information of the starting macrocell module, a superpath between macrocell modules is constructed to obtain the third time hypergraph, where the starting macrocell module is the first macrocell module in a data transmission path.

[0100] In one embodiment, before constructing the hyperpath between macrocell modules based on the total number of time-series units recorded in the second supernode and the ID information of the starting macrocell module to obtain the third time-series hypergraph, the method further includes:

[0101] According to the level of the second time hypergraph from low to high, traverse each super node of each level in the second time hypergraph and determine whether each super node corresponds to a time logic module.

[0102] When determining the timing logic module corresponding to the current supernode in the second timing hypergraph, all input source supernodes within the current supernode are traversed. The timing unit count value is obtained based on the input source supernode. The total number of timing units when traversing to the endpoint macrocell module of the data transmission path is counted. The total number of timing units and the starting macrocell module ID of each data transmission path are recorded on the second supernode of the endpoint macrocell module.

[0103] In one embodiment, the second supernode includes an input supernode and an output supernode.

[0104] Accordingly, one embodiment of the present invention also provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor executes the computer program to implement the FPGA timing hypergraph construction method of any of the above embodiments.

[0105] The terminal device in this embodiment includes a processor, a memory, and a computer program and computer instructions stored in the memory and executable on the processor. When the processor executes the computer program, it implements the various steps described in Embodiment 1 above, for example... Figure 1 The steps S1 to S4 are shown. Alternatively, when the processor executes the computer program, it implements the functions of each module / unit in the above-described device embodiment, such as the first timing hypergraph construction module 40.

[0106] For example, a computer program can be divided into one or more modules / units, one or more of which are stored in memory and executed by a processor to complete the present invention. One or more modules / units can be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in a terminal device. For example, the first temporal hypergraph construction module 40 is used to create a third supernode corresponding to each programmable logic module, create hyperedges corresponding to the third supernode based on the data transmission relationships between the third supernode and the second and first supernodes respectively, and perform topological sorting according to the hierarchical relationships between macrocell modules, programmable logic modules, and combinational logic modules to obtain the first temporal hypergraph.

[0107] Terminal devices can be computing devices such as desktop computers, laptops, handheld computers, and cloud servers. Terminal devices may include, but are not limited to, processors and memory. Those skilled in the art will understand that the schematic diagrams are merely examples of terminal devices and do not constitute a limitation on the terminal devices. They may include more or fewer components than illustrated, or combine certain components, or different components. For example, terminal devices may also include input / output devices, network access devices, buses, etc.

[0108] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device through various interfaces and lines.

[0109] Memory can be used to store computer programs and / or modules. The processor implements various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory, and by accessing data stored in the memory. Memory may mainly include a program storage area and a data storage area. The program storage area may store the operating system, applications required for at least one function, etc.; the data storage area may store data created based on the use of the mobile terminal, etc. In addition, memory may include high-speed random access memory, and may also include non-volatile memory, such as hard disks, RAM, plug-in hard disks, smart media cards (SMC), secure digital cards (SD cards), flash cards, at least one disk storage device, flash memory device, or other volatile solid-state storage devices.

[0110] If the modules / units integrated into the terminal device are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments of the present invention can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, the computer-readable medium does not include electrical carrier signals and telecommunication signals.

[0111] Accordingly, one embodiment of the present invention also provides a computer-readable storage medium, which includes a stored computer program, wherein, when the computer program is running, it controls the device where the computer-readable storage medium is located to execute the FPGA timing hypergraph construction method of any of the above embodiments.

[0112] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention in detail. It should be understood that the above are merely specific embodiments of the present invention and are not intended to limit the scope of protection of the present invention. In particular, it should be noted that any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention for those skilled in the art.

Claims

1. A method for constructing a timing hypergraph for an FPGA, characterized in that, include: Traverse the user netlist and divide the functional modules in the FPGA chip that implement the user netlist into macrocell modules, programmable logic modules, and combinational logic modules; wherein, the user netlist is obtained based on user design mapping; For each of the combined logic modules, a corresponding first super node is created, and based on the data signal transmission relationship in the user netlist, a corresponding super edge is created for the first super node; A set of second supernodes is created for the macrocell module, and a superedge corresponding to the second supernode is created according to the data signal transmission relationship between the second supernode and the first supernode; A third supernode is created for each of the programmable logic modules. Based on the data transmission relationship between the third supernode and the second and first supernodes, a superedge is created for the third supernode. The topology is sorted according to the hierarchical relationship between the macrocell module, the programmable logic module and the combinational logic module to obtain a first temporal hypergraph.

2. The FPGA timing hypergraph construction method as described in claim 1, characterized in that, After obtaining the first temporal hypergraph, the following is also included: According to the order of the first time sequence hypergraph from low to high, each super node of each of the first time sequence hypergraphs is traversed to determine whether each super node corresponds to a pure combinational logic module. When determining that the current supernode in the first temporal hypergraph corresponds to a pure combinational logic module, the current supernode is eliminated from the first temporal hypergraph, and the upstream and downstream superedges in the current supernode are merged to obtain the second temporal hypergraph.

3. The FPGA timing hypergraph construction method as described in claim 2, characterized in that, After obtaining the second temporal hypergraph, the following is also included: Traverse the second supernodes of the macrocell modules in the second temporal hypergraph, construct the hyperpaths between the macrocell modules based on the second supernodes, and obtain the third temporal hypergraph.

4. The FPGA timing hypergraph construction method as described in claim 1, characterized in that, The creation of the third supernode corresponding to each of the programmable logic modules includes: Based on the configuration information of the programmable logic module, a third supernode is created corresponding to each programmable logic module, wherein the configuration information is used to configure the programmable logic module as a pure combinational logic module or a sequential logic module.

5. The FPGA timing hypergraph construction method as described in claim 3, characterized in that, The step of constructing the hyperpath between the macrounit modules based on the second supernode to obtain the third temporal hypergraph includes: Based on the total number of timing units recorded in the second supernode and the ID information of the starting macrocell module, a superpath between macrocell modules is constructed to obtain a third timing supergraph, wherein the starting macrocell module is the first macrocell module in a data transmission path.

6. The FPGA timing hypergraph construction method as described in claim 5, characterized in that, Before constructing the hyperpath between macrocell modules and obtaining the third temporal hypergraph based on the total number of temporal units and the ID information of the starting macrocell module recorded in the second supernode, the following steps are also included: According to the level of the second time sequence hypergraph from low to high, traverse each super node of each level in the second time sequence hypergraph and determine whether each super node corresponds to a time sequence logic module. When determining the timing logic module corresponding to the current supernode in the second timing supergraph, all input source supernodes within the current supernode are traversed, and the timing unit count value is obtained according to the input source supernode. The total number of timing units when traversing to the endpoint macrocell module of the data transmission path is counted, and the total number of timing units and the starting macrocell module ID of each data transmission path are recorded on the second supernode of the endpoint macrocell module.

7. The FPGA timing hypergraph construction method as described in claim 1, characterized in that, The second supernode includes an input supernode and an output supernode.

8. An FPGA timing supergraph construction apparatus, characterized in that, include: The functional module partitioning module is used to traverse the user netlist and divide the functional modules in the FPGA chip that implement the user netlist into macrocell modules, programmable logic modules, and combinational logic modules; wherein, the user netlist is obtained based on user design mapping; The first superedge creation module is used to create a corresponding first supernode for each of the combinational logic modules, and to create a corresponding superedge for the first supernode based on the data signal transmission relationship in the user netlist. The second superedge creation module is used to create a set of second supernodes for the macrocell module and create the superedges corresponding to the second supernodes according to the data signal transmission relationship between the second supernodes and the first supernodes. The first temporal hypergraph construction module is used to create a third supernode corresponding to each of the programmable logic modules, create a hyperedge corresponding to the third supernode according to the data transmission relationship between the third supernode and the second supernode and the first supernode respectively, and perform topological sorting according to the hierarchical relationship between the macrocell module, the programmable logic module and the combinational logic module to obtain the first temporal hypergraph.

9. A terminal device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, wherein the processor, when executing the computer program, implements the FPGA timing hypergraph construction method as described in any one of claims 1-7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium includes a stored computer program; wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the FPGA timing supergraph construction method as described in any one of claims 1-7.

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