System-on-chip oriented built-in resistance degradation self-monitoring and calibration circuit and method

Abstract

The application discloses a system-on-chip-oriented built-in resistance degradation self-monitoring and calibration circuit and method, and relates to the technical field of integrated circuit design and reliability monitoring. The circuit comprises a programmable current source, a band gap reference circuit, a multiplexing switch network, a voltage comparator, a digital-to-analog converter and a control and storage unit, and can work in an external calibration mode, an internal self-checking mode and an external verification mode. The application establishes the initial baseline of each to-be-tested resistance through factory precision calibration, accurately detects the resistance voltage drop change in a DAC step scanning mode during in-service period, quantifies the degradation amount, and verifies the self-checking result through external traceability reinspection when the degradation exceeds the limit, so that a complete closed loop of "factory calibration-in-service monitoring-external verification" is formed.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design and reliability monitoring technology, specifically to a self-monitoring and calibration circuit and method for built-in resistor degradation in on-chip systems. Background Technology

[0002] In modern CMOS SoC / MCU design, various types of integrated resistors are widely used in analog and mixed-signal circuit modules, such as bandgap references (BGRs), analog-to-digital / digital-to-analog converters (ADCs / DACs), bias current generation, and precision voltage divider networks. The performance of these resistors, especially the long-term stability of their resistance values, directly affects the accuracy and reliability of the entire chip system.

[0003] However, the resistance value of integrated resistors can drift or degrade due to a variety of factors: 1. Manufacturing process deviations: Especially for diffusion resistors, there are inherent initial deviations due to the influence of wafer batch and doping concentration uniformity.

[0004] 2. Aging effect: During long-term operation, chips are affected by aging phenomena such as hot carrier injection (HCI), bias temperature instability (BTI), and electromigration (EM), which cause irreversible drift of the parameters of devices such as resistors.

[0005] 3. Environmental fluctuations: Real-time changes in operating temperature and power supply voltage can significantly affect the instantaneous performance of the circuit and interfere with the judgment of long-term degradation trends.

[0006] To ensure the functional safety of high-reliability applications (such as automotive electronics and industrial control), in-field monitoring of the health status of critical components has become essential. Current technologies largely rely on automated test equipment (ATE) on the production line for testing on-chip resistors, making it impossible to implement after chip deployment. Furthermore, some built-in monitoring solutions (such as using ring oscillators to monitor circuit delay degradation) primarily focus on transistor characteristics and do not design precise, traceable quantitative monitoring methods for the resistive components themselves.

[0007] Therefore, there is an urgent need for a circuit solution that can be integrated into the SoC, operate autonomously throughout the chip's lifecycle, measure the absolute value of resistance with high precision, quantify its degradation level, and has calibration traceability capabilities. Summary of the Invention

[0008] The purpose of this invention is to provide a circuit and method for self-monitoring and calibration of built-in resistor degradation in on-chip systems. Its core lies in a three-level architecture of "factory precision calibration - in-service autonomous monitoring - external traceability and re-inspection," aiming to solve the problem of the lack of effective and accurate in-service health monitoring and calibration capabilities for on-chip integrated resistors in existing technologies. Specifically, it needs to overcome the following: 1. How to achieve accurate measurement of the resistance values ​​of various types of discrete distributed resistors within a SoC.

[0009] 2. How to distinguish between long-term degradation of resistance and short-term fluctuations caused by environmental factors such as temperature and voltage.

[0010] 3. How to establish a traceable calibration chain to ensure the reliability of internal self-test results and enable verification and correction through external standards.

[0011] 4. How to implement the above functions with lower hardware overhead and power consumption, making them suitable for resource-constrained embedded SoCs.

[0012] To achieve the above objectives, as a first aspect of the present invention, the present invention provides a built-in resistance degradation self-monitoring and calibration circuit for on-chip systems, the circuit comprising: A programmable current source for generating test current; A multiplexed switch network is connected to the programmable current source, multiple resistors under test, and an external calibration access terminal, respectively. It is used to selectively direct the test current to the target resistor under test or the external calibration access terminal, or to connect the external calibration current source to the target resistor under test via the external calibration access terminal. Specifically, the external calibration current source can be an external device such as a test machine, calibration instrument, or maintenance tool that can provide a high-precision known current value. A voltage comparator, whose inverting input is connected to the voltage node of the resistor under test, is used to receive the measured voltage on the target resistor under test; A digital-to-analog converter, the output of which is connected to the non-inverting input of the voltage comparator, is used to provide a programmable reference voltage; A control and storage unit is connected to the programmable current source, the multiplexing switch network and the digital-to-analog converter respectively, and is used to control the switching of the multiplexing switch network, program the digital-to-analog converter and select the range of the programmable current source, and manage the calibration database stored in non-volatile memory. The circuit can operate in external calibration mode, internal self-test mode and external verification mode respectively.

[0013] Preferably, in the external calibration mode, the multiplexer network disconnects the programmable current source from each resistor under test and connects each resistor under test to the external calibration current source one by one to measure and store the initial absolute resistance value of each resistor under test.

[0014] Preferably, in the internal self-test mode, the control and storage unit is configured to perform the following operations: Read the initial resistance value data of the target resistor under test and the actual output current value of the currently selected programmable current source, calculate the expected voltage of the target resistor under test under the actual output current value, and use the value of the expected voltage as the center threshold of the digital-to-analog converter scan. The digital-to-analog converter is controlled to perform digital encoding scanning with the center threshold as the center and according to the preset steps, and successively outputs the increasing or decreasing reference voltage to the non-inverting input terminal of the voltage comparator; Receive the flip signal output by the voltage comparator, and record the digital-to-analog converter voltage corresponding to the flip of the voltage comparator as the current measured voltage; The resistance degradation of the target resistor is calculated based on the difference between the current measured voltage and the expected voltage.

[0015] Preferably, the scanning range of the digital-to-analog converter is an interval defined by the value of the expected voltage and M least significant bit voltages, where M is a positive integer greater than or equal to 2.

[0016] Preferably, the external verification mode is activated after the internal self-test mode detects that the resistance degradation exceeds a preset threshold. The multiplexer network is then reconfigured to connect the target resistor under test to the external calibration access point, so as to allow the external calibration current source to retest the target resistor under test and verify the internal self-test results.

[0017] Preferably, the circuit further includes a temperature sensor connected to the control and storage unit, used to acquire the chip junction temperature during each self-test; the control and storage unit also stores the temperature coefficients of each resistor under test, and when calculating the resistance degradation of each resistor under test, performs temperature compensation on the measurement results based on the chip junction temperature and the corresponding temperature coefficient.

[0018] Specifically, the circuit also includes a bandgap reference circuit for generating a reference voltage and reference current that are independent of temperature and power supply voltage to ensure measurement stability.

[0019] As a second aspect of the present invention, the present invention provides a method for self-monitoring and calibration of built-in resistor degradation in on-chip systems, comprising the following steps: Factory calibration stage: Each resistor under test is driven one by one using an external calibration current source, and the voltage across each resistor under test is measured. The initial resistance value of each resistor under test is calculated based on the current value of the external calibration current source and the measured voltage value, and the initial resistance value is stored in the calibration database in non-volatile memory. In-service autonomous monitoring phase: During chip operation, the chip autonomously selects the resistor to be tested, applies a test current to the resistor to be tested using the programmable current source, performs digital-to-analog converter step scan with the value of the expected voltage calculated based on the initial resistance value of the resistor to be tested and the test current as the center, accepts the critical voltage when the voltage comparator output flips as the current measured voltage, and compares the current measured voltage with the expected voltage to obtain the resistance degradation amount. External traceability verification stage: When the resistance degradation exceeds a preset threshold, switch to external verification mode and use an external calibration current source to retest the target resistor under test to verify the results of the in-service autonomous monitoring stage.

[0020] Preferably, the factory calibration stage further includes: connecting the programmable current source to an external calibration resistor, measuring the voltage generated by the programmable current source driving the external calibration resistor under different digital codes, calculating the actual output current value of the programmable current source under each digital code, and storing it in a calibration database in a non-volatile memory; in the in-service autonomous monitoring stage, calculating the test current value on which the expected voltage is based as the actual output current value.

[0021] As a third aspect of the invention, the invention also proposes a system-on-a-chip or microcontroller that integrates a built-in self-monitoring and calibration circuit for resistance degradation.

[0022] As a fourth aspect of the invention, the invention also provides a computer-readable storage medium having a computer program stored thereon that, when executed in a control unit of a system-on-a-chip or microcontroller, implements steps such as a built-in resistance degradation self-monitoring and calibration method for a system-on-a-chip.

[0023] Compared with the prior art, the beneficial effects of the present invention are: 1. High precision and self-containment: An absolute precision benchmark is established through external calibration, and high-resolution relative change measurement is achieved through internal DAC scanning comparison, enabling high-sensitivity degradation monitoring without the need for external instruments.

[0024] 2. Strong traceability: The unique three-level process of "external calibration - internal self-test - external verification" ensures the credibility and traceability of the monitoring data chain, meeting the functional safety requirements for diagnostic coverage.

[0025] 3. Environmental robustness: The solution can combine temperature sensing and compensation algorithms to effectively isolate the impact of environmental fluctuations on measurement results and focus on monitoring long-term aging effects.

[0026] 4. Low overhead and high feasibility: Make full use of the DAC, comparator, ADC, Flash and other modules commonly available in SoC, mainly add analog switches and a small amount of control logic, and it is easy to integrate into existing chip designs.

[0027] 5. High versatility: It is suitable for monitoring various types of integrated resistors such as polysilicon resistors, diffusion resistors, and trap resistors, covering various circuit modules such as analog, power management, and interface. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of the overall circuit architecture of the built-in resistance degradation self-monitoring and calibration system described in this invention. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0030] The embodiments of the present invention aim to solve the problem that existing technologies lack effective and accurate in-service health monitoring and calibration capabilities for on-chip integrated resistors. Specifically, the following needs to be overcome: 1. How to achieve accurate measurement of the resistance values ​​of various types of discrete distributed resistors within a SoC.

[0031] 2. How to distinguish between long-term degradation of resistance and short-term fluctuations caused by environmental factors such as temperature and voltage.

[0032] 3. How to establish a traceable calibration chain to ensure the reliability of internal self-test results and enable verification and correction through external standards.

[0033] 4. How to implement the above functions with lower hardware overhead and power consumption, making them suitable for resource-constrained embedded SoCs.

[0034] To solve the above technical problems, as shown in the attached document... Figure 1 As shown, this invention proposes a built-in self-monitoring and calibration system for resistance degradation. Its core lies in a three-tiered architecture: "factory precision calibration - in-service autonomous monitoring - external traceability and re-inspection".

[0035] 1. System Overall Architecture This system is integrated inside the SoC chip and mainly includes: (1) Programmable precision current source: generates multiple known and stable excitation currents I_test.

[0036] (2) Multiplexing switch network (MUX): It consists of MOS switches (SW0, SW1, ..., SWn) and is used to selectively guide the excitation current to the target resistor under test or the external calibration resistor (R_x) access port.

[0037] (3) Voltage comparator: Its inverting input (-) receives V_measured on the resistor under test, and its non-inverting input (+) is connected to the output of a digital-to-analog converter (DAC).

[0038] (4) Digital-to-analog converter (DAC): used to generate a precisely adjustable reference voltage V_dac, which is sent to the non-inverting input of the comparator as the comparison threshold.

[0039] (5) Control and storage unit (usually MCU core): responsible for controlling the entire test process (switch switching, DAC programming, current source range selection), and managing the calibration database stored in non-volatile memory (such as Flash). This database records the factory nominal value, initial calibration data, temperature compensation coefficient, etc. of each resistor.

[0040] (6) Bandgap reference (BGR): Provides a voltage and current reference that is basically independent of temperature and voltage for the entire monitoring system, ensuring the stability of the measurement.

[0041] 2. Core Methodology and Flow The method comprises three main stages, forming a complete monitoring closed loop: (1) First stage: Factory calibration and baseline establishment During this stage of chip packaging testing (Final Test), external high-precision equipment is used to calibrate the BGR and current source. The purpose is to create the preconditions for establishing an initial "health baseline" for each resistor to be monitored.

[0042] a. Internal Resistance Absolute Value Calibration: Control the switch network, close the internal current source switch SW0 and the external switch SWx. Sequentially close SW1 to SWn, allowing this external calibration current to flow through each resistor under test. Measure the voltage across its terminals, and combine this with the known precision current value to calculate the precise resistance value R_initial of each resistor at the time of manufacture.

[0043] b. Internal Programmable Current Source Mirror Path Calibration: The control switch network closes the internal current source switch SW0 and the external path switch SWX, causing the internal programmable current source to drive an external high-precision reference resistor R_x. By measuring the voltage across R_x, the true output current value I_real(code) of the current source under different digital codes is deduced, eliminating errors such as internal mirroring.

[0044] c. Data storage: The measured R_initial matrix, I_real(code) lookup table, and related test conditions (such as ambient temperature) are encrypted and stored in the chip's secure Flash area as the benchmark for all subsequent comparisons.

[0045] (2) Second stage: In-service autonomous monitoring and degradation assessment This stage is periodically triggered by the chip firmware or manually started when needed, and is completed entirely automatically inside the chip.

[0046] a. Applying force and sampling: Close SW0 and select the switch corresponding to the resistor to be measured (e.g., SWk). The internally calibrated current source I_test flows through resistor R_k, generating a voltage drop V_k = I_test * R_k at the inverting terminal of the comparator.

[0047] b. DAC Threshold Scan and Flip Point Detection (Core Steps): The control unit reads the initial baseline data of resistor R_k from Flash and calculates the expected voltage V_expected_k = I_test * R_initial_k corresponding to its initial resistance value R_initial_k under the current excitation current I_test. This V_expected_k is the center threshold of the scan. The DAC is controlled to perform a digital encoding scan with small steps (e.g., ±10 LSBs) around V_expected_k, outputting a series of V_dac values. Simultaneously, the comparator's output state is monitored. When V_dac scans from below V_k to above V_k, the comparator output flips. The critical DAC encoding value Code_flip that causes the comparator output to flip is recorded; its corresponding voltage V_flip is approximately equal to V_k.

[0048] c. Degradation Calculation: Compare the measured V_flip with the baseline V_expected_k. The difference ΔV = V_flip - V_expected_k. The relative change in resistance can then be calculated. ΔR / R ≈ ΔV / V_expected_k.

[0049] This ΔR quantifies the amount of resistance drift since the resistor left the factory.

[0050] d. Environmental Compensation (Optional Enhancement): To improve monitoring accuracy, a temperature sensor can be integrated. The chip junction temperature is recorded during each measurement, and the measurement results are uniformly compensated to a reference temperature (e.g., 25°C; the same applies to other temperature points) using pre-stored temperature drift coefficients of the resistance at different temperatures before degradation judgment, thus eliminating the influence of environmental factors.

[0051] (3) Third stage: External tracing and system verification When the autonomous monitoring detects that the degradation amount ΔR of a resistor exceeds the preset warning threshold, the system can issue an alarm and initiate this advanced verification process.

[0052] a. The system control switch network switches back to the "external resistor calibration current" mode (i.e., the same as step a in the first stage).

[0053] b. Use an external resistor R_x of the same or higher grade as the factory calibration resistor to rule out any abnormalities in the overall detection circuit itself.

[0054] c. After confirming that there are no abnormalities in the overall detection circuit, the maintenance plan related to resistor degradation can be updated; if an abnormality is found in the monitoring circuit, it can indicate that the internal monitoring circuit (such as current source, comparator) has drifted, triggering a system-level calibration or maintenance alarm.

[0055] The following is in conjunction with the appendix Figure 1 The invention will be described in detail with reference to a specific embodiment. Suppose that in a certain automotive MCU chip, it is necessary to monitor a 1MΩ polysilicon resistor R1 used in a precision ADC reference voltage divider network.

[0056] 1. Factory calibration stage (stage one) (1) The test machine connects the chip pins IO2 and GND through a probe card.

[0057] (2) MCU firmware control: disconnect SW0, close SW1 (corresponding to R1), and disconnect all other switches.

[0058] (3) Apply a precision constant current of 1.000μA±0.01%.

[0059] (4) The test machine measures the voltage between IO2 and GND, and the measured value is V_ext=0.9985V.

[0060] (5) Calculate R1_initial=0.9985V / 1.000μA =0.9985 MΩ.

[0061] (6) Write the R1_initial value, the test current value, and the ambient temperature of 25°C into the chip's Flash calibration database. (The same action can be performed at other temperature ranges.) 2. In-service autonomous monitoring phase (Phase Two) (1) Three years later, while the vehicle is in operation, the MCU periodic health management task triggers an inspection of R1.

[0062] (2) Step A (applying force): The MCU controls the closure of SW0 and SW1, and the internal current source is set to the 1μA level (this level has been calibrated at the factory to have a real current of I_real = 0.999μA).

[0063] (3) Step B (Calculate the expected threshold): The MCU reads R1_initial=0.9985 MΩ and I_real=0.999μA from the Flash. Calculate the expected voltage: V_expected=R1_initial * I_real=0.9976V. This is the center threshold voltage of this DAC scan.

[0064] (4) Step C (DAC Scanning and Judgment): The MCU controls the DAC output to 0.990V (lower than expected), and the comparator outputs a high level. The DAC increases its output voltage in 1mV (approximately 10 LSBs) increments: 0.991V, 0.992V, ... 0.997V, with the comparator always outputting a high level. When the DAC output increases to 0.998V, the comparator flips to a low level. The MCU records the flip point code, corresponding to a voltage V_flip = 0.998V.

[0065] (5) Step D (Degradation Calculation): Calculate the voltage difference: ΔV = V_flip - V_expected = 0.998V - 0.9976V = 0.0004V. Calculate the relative change: ΔR / R ≈ ΔV / V_expected = 0.0004 / 0.9976 ≈ 0.04%. The detected resistance change is determined to be +0.04%, which is within the preset ±1% tolerance range. The system logs the change and no alarm is generated.

[0066] 3. External traceability and verification phase (Phase Three) (1) Suppose that after another two years, the self-check finds that the ΔR / R of R1 reaches +2.5%, which exceeds the threshold.

[0067] (2) The system issues an early warning and guides the vehicle to the service station.

[0068] (3) The repair tool is connected to the IO2 pin of the chip through the OBD interface or a dedicated test point to monitor the accuracy of the current source. After confirming that there is no abnormality, proceed to the next step.

[0069] (4) The MCU receives the instruction and enters the external measurement mode again: disconnect SW0 and close SW1.

[0070] (5) Apply a standard 1.000μA current to the maintenance tool and measure the voltage as 1.025V.

[0071] (6) The calculated actual resistance is 1.025 MΩ, which is consistent with the degradation trend in the self-test report, confirming the reliability of the internal monitoring results. This information can be used to predict the system's accuracy lifespan or trigger software compensation.

[0072] Compared with existing technical solutions, the technical solution of this invention has the following advantages: 1. High precision and self-containment: An absolute precision benchmark is established through external calibration, and high-resolution relative change measurement is achieved through internal DAC scanning comparison, enabling high-sensitivity degradation monitoring without the need for external instruments.

[0073] 2. Strong traceability: The unique three-level process of "external calibration - internal self-test - external verification" ensures the credibility and traceability of the monitoring data chain, meeting the functional safety requirements for diagnostic coverage.

[0074] 3. Environmental robustness: The solution can combine temperature sensing and compensation algorithms to effectively isolate the impact of environmental fluctuations on measurement results and focus on monitoring long-term aging effects.

[0075] 4. Low overhead and high feasibility: Make full use of the DAC, comparator, ADC, Flash and other modules commonly available in SoC, mainly add analog switches and a small amount of control logic, and it is easy to integrate into existing chip designs.

[0076] 5. High versatility: It is suitable for monitoring various types of integrated resistors such as polysilicon resistors, diffusion resistors, and trap resistors, covering various circuit modules such as analog, power management, and interface.

[0077] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0078] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A built-in resistance degradation self-monitoring and calibration circuit for on-chip systems, characterized in that, The circuit includes: A programmable current source for generating test current; A multiplexed switching network is connected to the programmable current source, multiple resistors under test, and an external calibration access terminal, respectively, for selectively directing the test current to the target resistor under test or the external calibration access terminal, or connecting the external calibration current source to the target resistor under test via the external calibration access terminal; A voltage comparator, whose inverting input is connected to the voltage node of the resistor under test, is used to receive the measured voltage on the target resistor under test; A digital-to-analog converter, the output of which is connected to the non-inverting input of the voltage comparator, is used to provide a programmable reference voltage; A control and storage unit is connected to the programmable current source, the multiplexing switch network and the digital-to-analog converter respectively, and is used to control the switching of the multiplexing switch network, program the digital-to-analog converter and select the range of the programmable current source, and manage the calibration database stored in non-volatile memory. The circuit can operate in external calibration mode, internal self-test mode and external verification mode respectively.

2. The circuit according to claim 1, characterized in that, In the external calibration mode, the multiplexed switch network disconnects the programmable current source from each resistor under test and connects each resistor under test to the external calibration current source one by one to measure and store the initial absolute resistance value of each resistor under test.

3. The circuit according to claim 1, characterized in that, In the internal self-test mode, the control and storage unit is configured to perform the following operations: Read the initial resistance value data of the target resistor under test and the actual output current value of the currently selected programmable current source, calculate the expected voltage of the target resistor under test under the actual output current value, and use the value of the expected voltage as the center threshold of the digital-to-analog converter scan. The digital-to-analog converter is controlled to perform digital encoding scanning with the center threshold as the center and according to the preset steps, and successively outputs the increasing or decreasing reference voltage to the non-inverting input terminal of the voltage comparator; Receive the flip signal output by the voltage comparator, and record the digital-to-analog converter voltage corresponding to the flip of the voltage comparator as the current measured voltage; The resistance degradation of the target resistor is calculated based on the difference between the current measured voltage and the expected voltage.

4. The circuit according to claim 3, characterized in that, The scanning range of the digital-to-analog converter is the interval defined by the value of the expected voltage and plus or minus M least significant bit voltages, where M is a positive integer greater than or equal to 2.

5. The circuit according to claim 1, characterized in that, The external verification mode is activated after the internal self-test mode detects that the resistance degradation exceeds a preset threshold. The multiplexer network is reconfigured to connect the target resistor under test to the external calibration access point, so as to allow the external calibration current source to retest the target resistor under test and verify the internal self-test results.

6. The circuit according to any one of claims 1 to 5, characterized in that, The circuit also includes a temperature sensor connected to the control and storage unit, which is used to acquire the chip junction temperature during each self-test. The control and storage unit also stores the temperature coefficients of each resistor under test, and performs temperature compensation on the measurement results based on the chip junction temperature and the corresponding temperature coefficients when calculating the resistance degradation of each resistor under test.

7. A method for self-monitoring and calibrating the built-in resistance degradation of the circuit according to any one of claims 1-6, characterized in that, Includes the following steps: Factory calibration stage: Each resistor under test is driven one by one using an external calibration current source, and the voltage across each resistor under test is measured. The initial resistance value of each resistor under test is calculated based on the current value of the external calibration current source and the measured voltage value, and the initial resistance value is stored in the calibration database in non-volatile memory. In-service autonomous monitoring phase: During chip operation, the chip autonomously selects the resistor to be tested, applies a test current to the resistor to be tested using the programmable current source, performs digital-to-analog converter step scan with the value of the expected voltage calculated based on the initial resistance value of the resistor to be tested and the test current as the center, accepts the critical voltage when the voltage comparator output flips as the current measured voltage, and compares the current measured voltage with the expected voltage to obtain the resistance degradation amount. External traceability verification stage: When the resistance degradation exceeds a preset threshold, switch to external verification mode and use an external calibration current source to retest the target resistor under test to verify the results of the in-service autonomous monitoring stage.

8. The method according to claim 7, characterized in that, The factory calibration stage also includes: connecting the programmable current source to an external calibration resistor, measuring the voltage generated by the programmable current source driving the external calibration resistor under different digital codes, calculating the actual output current value of the programmable current source under each digital code, and storing it in a calibration database in a non-volatile memory; in the in-service autonomous monitoring stage, calculating the test current value on which the expected voltage is based is the actual output current value.

9. A system-on-a-chip or microcontroller, characterized in that, It integrates a built-in resistance degradation self-monitoring and calibration circuit as described in any one of claims 1-6.

10. A computer-readable storage medium having a computer program stored thereon that, when executed in a control unit of a system-on-a-chip or a microcontroller, implements the steps of the method as described in claim 7 or 8.

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