Uvm verification environment automatic generation method, system, device and storage medium

Abstract

This disclosure relates to the field of digital integrated circuit verification technology, specifically to a method, system, device, and storage medium for automatically generating a UVM verification environment. The method displays a visual component diagram of the UVM verification environment based on project configuration data, and updates the visual component diagram and project configuration data in response to component configuration operations targeting component nodes, hierarchical relationships, or connections. Before generating component files, a component relationship consistency check is performed based on the component types, component inclusion relationships, and TLM connection relationships in the updated project configuration data. If the check passes, UVM component code, subcomponent declaration and instantiation code, and port connection code are generated based on the project configuration data, resulting in multiple component files. This improves the efficiency, accuracy, and consistency of multi-component code generation in the UVM verification environment.

Description

Technical Field

[0001] This disclosure relates to the field of digital integrated circuit verification technology, specifically to a method, system, device, and storage medium for automatically generating a UVM verification environment. Background Technology

[0002] In the verification process of chips and FPGAs (Field Programmable Gate Arrays), the verification environment is typically built using UVM (Universal Verification Methodology). A UVM verification environment can include multiple UVM components, which together form a complete verification environment through component inclusion relationships, component reference relationships, and TLM (Transaction Level Modeling) connections.

[0003] However, related technologies typically generate UVM component code manually or using code templates. When a UVM validation environment includes multiple interrelated components, the configuration content related to different UVM components and the content describing the relationships between components are usually distributed across multiple code locations. When the component structure or component relationships of the UVM validation environment are adjusted, multiple interrelated code contents need to be collaboratively maintained. This can easily lead to problems such as missing related content, component type mismatches, or inconsistencies in code content between different component files, thereby affecting the build efficiency of the UVM validation environment and the accuracy and consistency of the generated code. Summary of the Invention

[0004] Based on this, this disclosure provides a method, system, device, and storage medium for automatically generating UVM verification environments, in order to address the problem of how to improve the generation efficiency, accuracy, and consistency of multi-component code that is interconnected in a UVM verification environment.

[0005] In a first aspect, this disclosure provides a method for automatically generating a UVM verification environment, the method comprising: The visual configuration interface displays a visual component diagram of the UVM verification environment based on the project configuration data. This diagram includes multiple component nodes, each displaying the component identifier and type of a UVM component. The hierarchical relationship between the component nodes represents the component inclusion relationship between the UVM components, and the connections between the typed ports of the component nodes represent the TLM connection relationship between the UVM components. The project configuration data records the component identifier and type of each UVM component, the component inclusion relationship between the UVM components, and the TLM connection relationship between the UVM components. In response to a component configuration operation on the visual component graph, the component nodes, the hierarchical relationship, or the connection are updated, and the project configuration data is updated based on the updated component nodes, hierarchical relationship, or connection; Before generating the component files of the UVM verification environment, a component relationship consistency check is performed on the updated project configuration data based on the component type of each UVM component, the component inclusion relationship, and the TLM connection relationship in the updated project configuration data. The component relationship consistency check includes checking whether the UVM component associated with the component inclusion relationship or the TLM connection relationship exists, whether the component types of the parent and child components associated with the component inclusion relationship meet the UVM component inclusion constraint, and whether the typed ports at both ends of the TLM connection relationship meet the UVM TLM port connection constraint. If the component relationship consistency verification passes, the UVM component code corresponding to each UVM component is generated according to the component identifier and component type of each UVM component in the updated project configuration data. If the component relationship consistency verification passes, based on the component inclusion relationship in the updated project configuration data, the child component declaration and instantiation code is generated in the UVM component code corresponding to the parent component in the component inclusion relationship, and based on the TLM connection relationship, the port connection code is generated in the corresponding UVM component code, thus obtaining multiple component files of the UVM verification environment.

[0006] Secondly, this disclosure also provides an automatic generation system for UVM verification environments, the system comprising: The visualization component diagram display module is used to display a visualization component diagram of the UVM verification environment on the visualization configuration interface based on the project configuration data. The visualization component diagram includes multiple component nodes, each displaying the component identifier and component type of a UVM component. The hierarchical relationship between the component nodes represents the component inclusion relationship between the UVM components, and the connections between the typed ports of the component nodes represent the TLM connection relationship between the UVM components. The project configuration data is used to record the component identifier and component type of each UVM component, the component inclusion relationship between the UVM components, and the TLM connection relationship between the UVM components. The component graph update module is used to update the component nodes, the hierarchical relationship or the connection in response to the component configuration operation for the visual component graph, and update the project configuration data according to the updated component nodes, hierarchical relationship or connection; The component relationship verification module is used to perform component relationship consistency verification on the updated project configuration data before generating the component files of the UVM verification environment, based on the component type of each UVM component in the updated project configuration data, the component inclusion relationship and the TLM connection relationship. The code generation module is used to generate UVM component code corresponding to each UVM component according to the component identifier and component type of each UVM component in the updated project configuration data, and generate child component declaration and instantiation code in the UVM component code corresponding to the parent component according to the component inclusion relationship, and generate port connection code in the corresponding UVM component code according to the TLM connection relationship, so as to obtain multiple component files of the UVM verification environment. The component relationship consistency check includes checking whether the UVM component associated with the component inclusion relationship or the TLM connection relationship exists, whether the component types of the parent and child components associated with the component inclusion relationship meet the UVM component inclusion constraint, and whether the typed ports at both ends of the TLM connection relationship meet the UVM TLM port connection constraint.

[0007] Thirdly, this disclosure also provides an electronic device, characterized in that it includes: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of the above-described UVM verification environment automatic generation method.

[0008] Fourthly, this disclosure also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the above-described UVM verification environment automatic generation methods.

[0009] Fifthly, this disclosure also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described UVM verification environment automatic generation methods.

[0010] In the UVM verification environment automatic generation method of the above embodiments of this disclosure, the component identifier and component type of each UVM component, the component inclusion relationship between UVM components, and the TLM connection relationship between UVM components are recorded through project configuration data. The corresponding visual component diagram is displayed according to the project configuration data, and the project configuration data is updated according to the component configuration operation for the visual component diagram. Before generating multiple component files of the UVM verification environment, a component relationship consistency check is performed according to the component type, component inclusion relationship, and TLM connection relationship in the project configuration data. If the component relationship consistency check passes, UVM component code, sub-component declaration and instantiation code, and port connection code are generated according to the project configuration data.

[0011] This enables the establishment of a correspondence between project configuration data, component configurations in the visual component diagram, component relationships, and code content in multiple component files. It allows the configuration results for the visual component diagram to be synchronously reflected in the corresponding component files through the project configuration data. Furthermore, it identifies component relationships that do not meet UVM constraints before code generation, reduces invalid component relationships entering the generated multiple component files, and improves the code generation efficiency, component relationship visibility, and accuracy and consistency of collaborative generation of multiple component files in the UVM verification environment. Attached Figure Description

[0012] To more clearly illustrate the embodiments of this disclosure, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0013] Figure 1 A flowchart illustrating an automatic generation method for a UVM verification environment provided in this embodiment of the disclosure; Figure 2 A schematic diagram of the layout of a visual configuration interface for an automatic generation method of a UVM verification environment provided in this embodiment of the present disclosure; Figure 3 This is a schematic diagram of the composition structure of an automatic UVM verification environment generation system provided in an embodiment of the present disclosure; Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0014] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this disclosure.

[0015] It should be noted that, in the description of this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this disclosure are used to distinguish similar objects and are not used to describe a particular order or sequence.

[0016] To enable those skilled in the art to better understand the present disclosure, the present disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] In one embodiment, please refer to Figure 1 , Figure 1 This is a flowchart illustrating an automatic UVM verification environment generation method provided in an embodiment of the present disclosure. This method can be applied to an automatic UVM verification environment generation system, which can be deployed on an electronic device with data processing capabilities.

[0018] The following steps can all be automatically generated by the UVM verification environment system. To avoid repetition, the execution entity of each step will not be described in detail below.

[0019] like Figure 1 As shown, the method includes the following steps: Step S101: Display the visual component diagram of the UVM verification environment in the visual configuration interface according to the project configuration data.

[0020] The project configuration data is structured data used to uniformly record the UVM components and the relationships between them in the current UVM validation environment. The project configuration data must at least record the component identifier and type of each UVM component, the component inclusion relationships between UVM components, and the TLM connection relationships between UVM components.

[0021] Specifically, the UVM verification environment includes multiple UVM components for implementing corresponding verification functions. A UVM component is a constituent unit in the UVM verification environment that has a corresponding code representation and can be distinguished by component identifier and component type.

[0022] A component visualization diagram is a graphical representation of UVM components and the relationships between them within a UVM validation environment. The component visualization diagram consists of multiple component nodes, each corresponding to a UVM component.

[0023] When displaying a component node, the component identifier and component type of the corresponding UVM component are displayed on that component node.

[0024] Among them, the component identifier is the identification information used to distinguish different UVM components and to determine the component represented by the corresponding UVM component code; the component type is the type information used to indicate the category to which the corresponding UVM component belongs and to determine the code structure of the corresponding UVM component code.

[0025] For two UVM components that have a component containment relationship, the hierarchical relationship is displayed between the corresponding two component nodes. Here, the component containment relationship is a relationship where one UVM component acts as the parent component and contains another UVM component as its child component.

[0026] Component nodes also have typed ports, which are visual ports with corresponding UVM TLM port types.

[0027] For two UVM components that have a TLM connection, the connection is displayed between the corresponding typed ports.

[0028] Among them, the TLM connection relationship is the connection relationship between UVM components through corresponding ports to pass transactions.

[0029] Thus, component nodes represent UVM components, the hierarchical relationship between component nodes represents the component inclusion relationship, and the connection between typed ports represents the TLM connection relationship, so that the components and component relationships originally represented by different code content in the UVM verification environment are presented in a visual component diagram.

[0030] A visual component diagram is a visual representation of project configuration data.

[0031] Among them, the UVM components recorded in the project configuration data correspond to the component nodes in the visual component diagram, the component inclusion relationships recorded in the project configuration data correspond to the hierarchical relationships between component nodes, and the TLM connection relationships recorded in the project configuration data correspond to the connections between typed ports.

[0032] Step S102: In response to the component configuration operation for the visual component graph, update the component nodes, hierarchical relationships or connections, and update the project configuration data based on the updated component nodes, hierarchical relationships or connections.

[0033] Specifically, component configuration operations are configuration operations performed on UVM components or component relationships in the visual component graph.

[0034] Upon receiving a component configuration operation, determine the configuration object and configuration content targeted by the operation.

[0035] When the configuration object is a UVM component, update the corresponding component node according to the component configuration operation, and update the component identifier, component type, or component attribute of the UVM component in the project configuration data; when the configuration object is a component containment relationship, add, delete, or adjust the hierarchical relationship between the corresponding component nodes according to the component configuration operation, and update the corresponding component containment relationship in the project configuration data; when the configuration object is a TLM connection relationship, add, delete, or adjust the connection between the corresponding typed ports according to the component configuration operation, and update the corresponding TLM connection relationship in the project configuration data.

[0036] After the project configuration data is updated, the visualization component diagram is refreshed according to the updated project configuration data to ensure that the UVM components and component relationships recorded in the project configuration data correspond to the component nodes, hierarchical relationships and connections in the visualization component diagram.

[0037] Step S103: Perform a component relationship consistency check on the updated project configuration data.

[0038] Specifically, based on the updated project configuration data, the existence of UVM components involved in the component inclusion relationship and TLM connection relationship is verified; based on the component types of the parent and child components in the component inclusion relationship, the UVM component inclusion constraint is verified; and based on the typed ports at both ends of the TLM connection relationship, the UVM TLM port connection constraint is verified.

[0039] The UVM component contains constraints that limit the types of child components that each parent component type is allowed to contain.

[0040] Based on the UVM TLM port type, connection direction, and transaction type of the typed port, determine whether the typed ports at both ends of the TLM connection satisfy the UVM TLM port connection constraints.

[0041] If the component relationship consistency check fails, the visual configuration interface will display the check prompt corresponding to the failed UVM component or component relationship, and the subsequent generation of component code and component relationship code will not be executed; if the component relationship consistency check passes, steps S104 and S105 will be executed.

[0042] Step S104: If the component relationship consistency verification passes, generate the UVM component code corresponding to each UVM component based on the component identifier and component type of each UVM component in the updated project configuration data.

[0043] Specifically, the component records in the updated project configuration data are processed separately, and the component identifier and component type in the current component record are read.

[0044] The code structure of the corresponding UVM component code is determined based on the component type, and the component identifier is written into the code structure to identify the position of the UVM component, thereby generating the UVM component code corresponding to the current component record.

[0045] The updated project configuration data is processed using the methods described above to obtain the UVM component code corresponding to each UVM component. Therefore, the component identifier and component type recorded in the project configuration data directly serve as the basis for generating the corresponding UVM component code.

[0046] Step S105: If the component relationship consistency verification passes, based on the component inclusion relationship in the updated project configuration data, generate the child component declaration and instantiation code in the UVM component code corresponding to the parent component in the component inclusion relationship, and generate the port connection code in the corresponding UVM component code based on the TLM connection relationship in the updated project configuration data, thereby obtaining multiple component files of the UVM verification environment.

[0047] Specifically, the component inclusion relationships in the project configuration data are processed to determine the parent and child components associated with each component inclusion relationship, and to obtain the component identifier and component type of each parent and child component.

[0048] Based on the component identifier and component type of the child component, the child component declaration code and child component instantiation code are generated in the UVM component code corresponding to the parent component.

[0049] The TLM connection relationships in the project configuration data are processed to determine the typed port associated with each TLM connection relationship and the UVM component to which the typed port belongs. Based on the UVM components and typed ports at both ends of the TLM connection relationship, port connection code is generated in the UVM component code used to establish the TLM connection relationship.

[0050] The UVM component code generated based on the component record, the sub-component declaration and instantiation code generated based on the component inclusion relationship, and the port connection code generated based on the TLM connection relationship are written into the corresponding component files to obtain multiple component files that together constitute the UVM verification environment.

[0051] In one possible implementation, the visual configuration interface may also include a code preview area.

[0052] Specifically, after the component relationship consistency check passes, in response to the selected operation for any component node, the UVM component code corresponding to that component node is displayed in the code preview area.

[0053] The displayed UVM component code includes code generated based on the component identifier and component type of the UVM component corresponding to the component node in the project configuration data, as well as sub-component declaration and instantiation code or port connection code generated based on the component inclusion relationship or TLM connection relationship associated with the UVM component in the project configuration data.

[0054] After a component node, component property, hierarchy, or connection is updated, update the project configuration data and re-execute the component relationship consistency check. After the re-executed component relationship consistency check passes, regenerate the corresponding UVM component code based on the updated project configuration data, and update and display the regenerated UVM component code in the code preview area.

[0055] In response to the batch generation operation, after the component relationship consistency verification passes, the UVM component code corresponding to each UVM component is written into the corresponding component file, and the generated component file is displayed in the visual configuration interface.

[0056] Therefore, by selecting a component node, one can intuitively view the generated code corresponding to the UVM component and its associated component inclusion and TLM connection relationships in the project configuration data, and confirm the correspondence between the visualized configuration content and the component file based on the code changes before and after the project configuration data update.

[0057] In the UVM verification environment automatic generation method of the above embodiments of this disclosure, the component identifier and component type of each UVM component, the component inclusion relationship between UVM components, and the TLM connection relationship between UVM components are recorded through project configuration data. A corresponding visual component diagram is displayed based on the project configuration data, and the project configuration data is updated according to the component configuration operations for the visual component diagram. Before generating multiple component files for the UVM verification environment, a component relationship consistency check is performed based on the component type, component inclusion relationship, and TLM connection relationship in the project configuration data. If the component relationship consistency check passes, UVM component code, sub-component declaration and instantiation code, and port connection code are generated based on the project configuration data. This establishes a correspondence between project configuration data, component configurations and component relationships in the visual component diagram, and the code content in multiple component files. The configuration results for the visual component diagram are synchronously reflected in the corresponding component files through the project configuration data. Furthermore, component relationships that do not meet UVM constraints are identified before code generation, reducing invalid component relationships entering the generated multiple component files. This improves the code generation efficiency, component relationship visibility, and the accuracy and consistency of multi-component file collaborative generation in the UVM verification environment.

[0058] In this embodiment, the visualized component diagram, component relationship consistency verification, and the generated multiple component files correspond to the same project configuration data. The project configuration data serves as the unified data foundation for component configuration, component relationship display, component relationship verification, and component code generation, and is used to structurally record the UVM components and the relationships between them in the current UVM verification environment.

[0059] Project configuration data is used to record the component identifier and component type of each UVM component, the component inclusion relationship between UVM components, and the TLM connection relationship between UVM components.

[0060] The component identifiers and component types recorded in the project configuration data correspond to the component identifiers and component types displayed in the corresponding component nodes, as well as the corresponding UVM component code; the component inclusion relationships recorded in the project configuration data correspond to the hierarchical relationships between the corresponding component nodes, as well as the sub-component declarations and instantiation code generated based on the hierarchical relationships; the TLM connection relationships recorded in the project configuration data correspond to the connections between the corresponding typed ports, as well as the port connection code generated based on the connections.

[0061] Specifically, project configuration data may include component records corresponding to each UVM component and relationship records corresponding to the relationships between each component.

[0062] The component record can record the component identifier and component type of the corresponding UVM component, while the relationship record can record the UVM components participating in the component relationship and the relationship type of the component relationship.

[0063] The relationship types include component reference relationships, component containment relationships, or TLM connection relationships.

[0064] When displaying the visual component diagram, the corresponding component nodes are shown based on the component records, and the corresponding hierarchical relationships or connections are shown based on the component inclusion relationships or TLM connection relationships represented by the relationship records. When performing component relationship consistency verification, the UVM components, component inclusion relationships, and TLM connection relationships to be verified are determined based on the identical component records and relationship records.

[0065] When generating multiple component files, corresponding UVM component code is generated based on the same component record, and component reference code, subcomponent declaration and instantiation code or port connection code is generated based on the same relationship record.

[0066] Therefore, each component configuration or component relationship in the project configuration data has a corresponding data representation, visual representation, verification result, and code representation.

[0067] In one specific implementation, the project configuration data also includes the display position of component nodes, the typed ports of component nodes, and the connections between typed ports. The project configuration data can also assign a unique identifier within the project to each UVM component. This unique identifier is a unique identifier corresponding to a UVM component within the same UVM project. Different UVM components can establish component inclusion relationships or TLM connection relationships through this unique identifier. When a component identifier changes, the relationship between that UVM component and other UVM components is maintained based on the unique identifier within the project.

[0068] A validation environment component can also contain one or more validation substructures consisting of proxy components, scoreboard components, and reference model components. The UVM components in different validation substructures each form a corresponding component record, and component inclusion relationships are established with the corresponding validation environment components through relational records.

[0069] In the UVM verification environment automatic generation method of this embodiment, by making the visual component diagram, component relationship consistency verification, and multiple component files correspond to the same project configuration data, and by making the component identifier, component type, component inclusion relationship, and TLM connection relationship correspond to the component nodes, hierarchical relationships, and connections in the visual component diagram and the corresponding code in multiple component files, a unified data association basis can be provided for visual component configuration, pre-generation consistency verification, and multi-component file generation. This realizes the correspondence between component configuration, component relationship, visual representation, verification results, and code representation, and improves the consistency of multi-component configuration, component relationship verification, and associated code generation in the UVM verification environment.

[0070] In one specific embodiment, the above-mentioned method for automatically generating a UVM verification environment is explained by taking the construction of a UVM verification environment for a design under test with a bus interface connection as an example.

[0071] The UVM verification environment may include, but is not limited to: interface component bus_if, transaction component bus_transaction, driver component bus_driver, monitor component bus_monitor, sequencer component bus_sequencer, agent component bus_agent, scoreboard component bus_scoreboard, reference model component bus_model, verification environment component bus_env, test case component bus_test, and top-level test platform component tb_top.

[0072] The following implementation methods, in conjunction with the bus verification environment, illustrate the specific execution process of the corresponding steps.

[0073] In this embodiment, as Figure 2 As shown, Figure 2 This is a schematic diagram of the layout of a visual configuration interface for an automatic generation method of a UVM verification environment provided in an embodiment of this disclosure. The visual configuration interface may include a hierarchical tree display area, a component drawing canvas, and an attribute configuration area.

[0074] Here, the hierarchy tree display area shows the component hierarchy of the UVM verification environment according to the hierarchical relationship between component nodes, the component drawing canvas displays the component nodes, typed ports and connections in the current component hierarchy, and the attribute configuration area displays and receives the component attribute configuration for the current component node.

[0075] The hierarchical tree display area shows the verification environment components, agent components, and the driver components, monitor components, and sequencer components contained in the agent components in a branched structure.

[0076] In response to a selection operation on a component node in the hierarchy tree, the component hierarchy corresponding to that component node is displayed in the component canvas.

[0077] The proxy component node and the verification environment component node are container component nodes that can contain child component nodes.

[0078] The internal component diagram corresponding to a container component node is a visual component diagram used to display the child component nodes contained in that container component node and the relationships between the child component nodes.

[0079] In response to an entry operation on a container component node in the component canvas, the internal component diagram corresponding to that container component node is displayed in the component canvas.

[0080] The visual configuration interface also displays the hierarchical path from the root node of the verification environment to the current container component node. In response to the selection of a component node in the hierarchical path, the component canvas is switched to the component level corresponding to that component node.

[0081] The component hierarchy of the UVM verification environment is displayed through a hierarchy tree area, the component nodes and relationships in the current component hierarchy are displayed through a component canvas, and the component attributes of the current component node are displayed through an attribute configuration area. This enables the establishment of a visual correspondence between component hierarchy, component relationships and component attributes, and allows for layer-by-layer browsing and configuration of multi-level UVM component structures.

[0082] After creating a UVM project, a root node for the validation environment is generated in the hierarchy tree display area. The root node for the validation environment is the top-level node in the component hierarchy of the current UVM validation environment, used to characterize this UVM validation environment.

[0083] Create the interface component bus_if. In the interface configuration dialog box, add the clk, rst_n, valid, addr, and data interface signals one by one, and configure the signal direction and signal width of each interface signal.

[0084] For example, configure addr as an input signal and configure its signal width to 32 bits.

[0085] The aforementioned interface signals are recorded as component attributes in the component record corresponding to bus_if in the project configuration data, and the component node corresponding to bus_if is displayed according to the updated project configuration data; after the component relationship consistency verification passes, the interface definition code corresponding to bus_if is generated according to the interface signals.

[0086] Create a transaction component bus_transaction, add addr and data transaction fields in the transaction configuration dialog box, configure the data types of the two transaction fields as bit[31:0] respectively, and configure the random attribute as rand.

[0087] The field identifier, data type, field width, and random attribute of each transaction field are recorded as component attributes in the component record corresponding to bus_transaction in the project configuration data, and the component node corresponding to bus_transaction is displayed according to the updated project configuration data. After the component relationship consistency verification passes, field declaration code and UVM factory registration code are generated based on the transaction fields.

[0088] Create a verification environment component node bus_env in the component graph corresponding to the root node of the verification environment, and enter the internal component graph corresponding to bus_env to create a proxy component node bus_agent in the internal component graph.

[0089] Enter the internal component diagram corresponding to bus_agent, and create the driver component node bus_driver, the monitor component node bus_monitor, and the sequencer component node bus_sequencer in the internal component diagram, thereby forming a hierarchical relationship between bus_agent and bus_driver, bus_monitor, and bus_sequencer.

[0090] By recording interface signals and transaction fields in the corresponding component nodes and displaying container components and their sub-components at different component levels, the internal configuration and component inclusion relationships of UVM components can be presented through the corresponding component nodes and internal component diagrams. Furthermore, the component attribute configuration can directly correspond to the interface definition code and transaction field code, thereby improving the visibility of component content configuration and code generation efficiency.

[0091] In one possible implementation, corresponding code generation rules are set according to different component types. The code generation rules are used to determine the component file structure corresponding to different component types, as well as the writing location and code form of component identifiers, component attributes, component reference information, hierarchical relationships, typed ports, and connections in the component file.

[0092] After the component relationship consistency verification passes, class declaration code and UVM factory registration code are generated based on the component identifier and component type in the project configuration data; child component declarations are generated based on the component inclusion relationship, and child component instantiation code is generated in the build phase corresponding to the parent component; port connection code in the connect phase is generated based on the TLM connection relationship; component reference code is generated based on the component reference information; and configuration database retrieval statement or configuration database setting statement is generated based on the configuration database entry.

[0093] Depending on the component type, corresponding UVM runtime function structures can be generated in the UVM component code, and user extension areas can be set in the function structures. The user extension areas are used to receive protocol processing logic, reference model algorithms, or transaction comparison strategies written for the specific design under test or verification protocol.

[0094] By setting corresponding code generation rules for different component types and determining the corresponding code content and writing location according to the component identifier, component attributes, component reference information, component inclusion relationship, type port and TLM connection relationship in the project configuration data, it is possible to generate the component's own code and component relationship code based on the same project configuration data, and realize the unified generation of multiple related component files.

[0095] In one possible implementation of step S101 above, displaying a visual component diagram of the UVM verification environment based on project configuration data includes the following steps: Step S1011: Perform code scanning processing on the existing UVM project code to obtain the UVM components in the existing UVM project code and the component relationships between the UVM components.

[0096] Specifically, the existing UVM project code is the source code of the already formed UVM verification project.

[0097] After obtaining the existing UVM project code, identify the source code files contained in the existing UVM project code and read the code content of each source code file.

[0098] The code content is scanned to identify the code representing UVM components and obtain the component identifier and type of each identified UVM component. Simultaneously, the code content representing component inclusion relationships or TLM connection relationships is identified to obtain the component relationships between the identified UVM components.

[0099] Code scanning can be executed continuously on multiple source code files in an existing UVM project directory, thereby aggregating UVM components and their relationships scattered across different source code files.

[0100] Step S1012: Record the obtained UVM components and component relationships in the project configuration data, and display the initial visual component diagram in the visual configuration interface based on the project configuration data that records the UVM components and component relationships.

[0101] Specifically, for each UVM component obtained through code scanning, a corresponding component record is created in the project configuration data, and the component identifier and component type of the UVM component are recorded in the corresponding component record.

[0102] For component inclusion relationships or TLM connection relationships obtained from code scanning, establish corresponding relationship records in the project configuration data, and record the UVM components and relationship types associated with the component relationship in the relationship records.

[0103] Create component nodes, hierarchical relationships, and connections based on project configuration data that records UVM components and component relationships.

[0104] For each component record in the project configuration data, create a corresponding component node and display the component identifier and component type in the corresponding component node; for relationship records that represent component inclusion relationships, establish hierarchical relationships between the corresponding component nodes; for relationship records that represent TLM connection relationships, establish connections between the typed ports of the corresponding component nodes.

[0105] The created component nodes, hierarchical relationships, and connections are displayed on the visual configuration interface to obtain the initial visual component diagram.

[0106] Corresponding to steps S1011 and S1012, in one possible implementation of step S102, in response to a component configuration operation on the visual component graph, updating component nodes, hierarchical relationships or connections, and project configuration data includes the following steps: Step S1021: In response to the confirmation, correction, or supplementary configuration operations for component nodes, hierarchical relationships, or connections in the initial visualization component diagram, update the project configuration data based on the confirmed, corrected, or supplemented UVM components and component relationships, and update the visualization component diagram based on the updated project configuration data.

[0107] Specifically, determine the component node, hierarchical relationship, or connection targeted by the confirmation operation, correction operation, or supplementary configuration operation. For confirmation or correction operations targeting component nodes, update the corresponding component record based on the confirmed or corrected component identifier and component type; for confirmation or correction operations targeting hierarchical relationships, update the corresponding component inclusion relationship based on the confirmed or corrected parent and child components; for confirmation or correction operations targeting connections, update the corresponding TLM connection relationship based on the confirmed or corrected component node and typed port.

[0108] For confirmation operations, the UVM components or component relationships obtained from the scan can be retained in the project configuration data, and the corresponding confirmation results can be recorded. For correction operations, the corresponding component records or relationship records are replaced based on the corrected UVM components or component relationships. For supplementary configuration operations, UVM components or component relationships can be added based on the code scan results, and corresponding component records, component inclusion relationships, or TLM connection relationships are added to the project configuration data. Supplementary configuration operations may also include continuing to configure the component properties or component reference information of existing component nodes.

[0109] After the project configuration data is updated, the corresponding component nodes are redisplayed based on the updated component records, and the corresponding hierarchical relationships or connections are redisplayed based on the updated relationship records.

[0110] In the above bus verification environment example, when some UVM project code already exists, the project directory where the existing UVM project code is located is obtained, and code scanning processing is performed on the SystemVerilog source code files in the project directory.

[0111] The UVM components obtained from the scan, such as bus_if, bus_transaction, bus_driver, bus_monitor, bus_sequencer, bus_agent, or bus_env, are recorded in the component record of the project configuration data. The component inclusion relationship and TLM connection relationship obtained from the scan are also recorded in the relationship record of the project configuration data.

[0112] Based on the recorded project configuration data, corresponding component nodes are formed in the visual configuration interface, and a hierarchical relationship is formed between the component nodes corresponding to bus_agent, bus_driver, bus_monitor, and bus_sequencer. Connections are formed between the typed ports with port connection relationships, thereby displaying the initial visual component diagram corresponding to the bus verification environment.

[0113] In response to confirmation, correction, or supplementary configuration operations on the initial visual component diagram, determine the confirmed, corrected, or supplemented UVM components and component relationships, update the project configuration data based on the operation results, and update the corresponding component nodes, hierarchical relationships, or connections based on the updated project configuration data.

[0114] The updated project configuration data and visual component diagram continue to be used to receive manual component configuration operations; after the configuration is completed, a component relationship consistency check is performed on the updated project configuration data, and after the check passes, component code and component relationship code are generated based on the project configuration data.

[0115] In the UVM verification environment automatic generation method of this embodiment, the existing UVM project code is scanned, and the obtained UVM components and component relationships are recorded in the project configuration data. An initial visual component diagram, which can be confirmed, corrected, or supplemented based on the same project configuration data, is established, thus creating a correspondence between the existing UVM project code, project configuration data, and the initial visual component diagram. Furthermore, based on the scan results, manual component configuration operations are received, and code is generated based on the updated project configuration data after consistency verification. This allows for the configuration of new components, component relationships, and component attributes while maintaining the existing UVM project content, improving the visualization recovery capability, continuous configuration capability, and consistency between the scan results and the regenerated code of the existing UVM project structure.

[0116] In one possible implementation of step S1011 above, the code scanning process includes the following steps: Step A1: Perform the first stage of code scanning to identify component definition information from the existing UVM project code, and determine the component identifier and component type of the corresponding UVM component based on the UVM base class or interface definition information in the component definition information.

[0117] Specifically, component definition information is information used to define corresponding code units in existing UVM project code, including name information to identify the code unit and definition information to indicate the category of the code unit.

[0118] First, locate class or interface declarations in the existing UVM project code.

[0119] When a class declaration is found, the class name and the UVM base class that the class inherits from are extracted. The component identifier is determined based on the class name, and the component type is determined based on the inherited UVM base class.

[0120] For example, classes that inherit from uvm_driver are identified as driver types, classes that inherit from uvm_monitor are identified as monitor types, and classes that inherit from uvm_agent are identified as agent types.

[0121] When an interface declaration is found, the component identifier is determined based on the interface name, and the corresponding code unit is determined to be of interface type based on the interface definition information.

[0122] Through the above processing, the component identifier and component type of each UVM component in the existing UVM project code are obtained first, and the component identification results are formed according to the component type.

[0123] In one specific implementation, code scanning processing uses regular expressions and keyword matching to perform lexical analysis on existing UVM project code.

[0124] It iterates through the SystemVerilog source code files in the existing UVM project directory and matches the code text in each source code file according to pre-set class declaration matching rules, inheritance relationship matching rules, interface declaration matching rules, and module declaration matching rules.

[0125] By directly analyzing the source code text, the corresponding component definition information can be obtained, and this method is applicable to batch scanning of existing UVM project directories.

[0126] Specifically, for class declarations, the component identifier is determined based on the class name in the class declaration, and the component type is determined based on the inheritance keyword in the class declaration.

[0127] Specifically, classes inheriting from uvm_sequence_item are designated as transaction types, classes inheriting from uvm_driver are designated as driver types, classes inheriting from uvm_monitor are designated as monitor types, classes inheriting from uvm_sequencer are designated as sequencer types, classes inheriting from uvm_agent are designated as agent types, classes inheriting from uvm_env are designated as verification environment types, and classes inheriting from uvm_test are designated as test case types.

[0128] For interface declarations, the interface definition information is identified based on the `interface` keyword, the interface name is determined as the component identifier, and the corresponding code unit is determined as the interface type.

[0129] For module declarations, the module definition information is identified based on the "module" keyword. Source code files containing module definitions are marked as candidate design files under test, and the corresponding module name is displayed in the visual configuration interface to receive confirmation operations for the candidate design under test.

[0130] Furthermore, after completing the first stage of scanning, a list of components categorized by component type is generated.

[0131] Each component entry in the component list includes at least a component identifier, a component type, and the corresponding source code file path. This component list serves as the basis for subsequent processing of component attribute information and component relationship information.

[0132] Step A2, perform the second stage of code scanning: After determining the component type of the UVM component in the first stage of code scanning, the component attribute information, component reference information, sub-components and port connection relationships of the UVM component are identified from the existing UVM project code by using the attribute matching rules and relationship matching rules corresponding to the component type.

[0133] Specifically, component attribute information is code information used to represent the configuration content of a UVM component itself, while component relationship information is code information used to represent the inclusion or connection relationship between a UVM component and other UVM components.

[0134] After determining the component type of a UVM component, the code content that needs to be further identified is determined based on that component type.

[0135] For example, for a UVM component with a parameterized base class, identify the transaction type recorded in the parameterized base class; For UVM components that declare virtual interface handles, identify the interface type corresponding to the virtual interface handle; For UVM components that declare a TLM port, identify the port identifier and port type of that TLM port.

[0136] The identified transaction type, interface type, or other attributes that point to an existing UVM component are determined as component reference information. This component reference information is used to indicate at least the current UVM component and another UVM component referenced by that UVM component.

[0137] Further identify member declarations and instantiation statements in UVM components.

[0138] When a member declaration and instantiation statement instructs the current UVM component to create another UVM component, the created UVM component is identified as a child component of the current UVM component.

[0139] Identify port connection statements in existing UVM project code, and extract the components and ports involved in the connection from the port connection statements to determine the port connection relationships between the corresponding UVM components.

[0140] In one specific implementation, based on the component type determined in the first phase, the code content of the corresponding UVM component is scanned using attribute matching rules and relationship matching rules corresponding to that component type.

[0141] For UVM components of transaction type, extract the field identifier, data type, bit width, and random attribute of the transaction field from the field declaration. The random attribute includes either the rand attribute or the randc attribute.

[0142] For UVM components of driver type or sequencer type, extract the transaction type used by the UVM component from the parameterized base class.

[0143] For UVM components of driver or monitor type, extract the interface type used by the UVM component from the virtual interface handle declaration.

[0144] For UVM components of the monitor type, the port identifier, port type, and transaction type of the analysis port are also extracted from the TLM port declaration.

[0145] For a proxy-type UVM component, extract the driver component, monitor component, and sequencer component contained in the proxy component from the member declaration and factory creation statement, and determine the active or passive attributes of the proxy component based on the conditional branch used to control component creation.

[0146] For UVM components of the verification environment type, extract the proxy components, scoreboard components, and reference model components contained in the verification environment component from the member declaration and factory creation statement.

[0147] For UVM components with interface types, extract the signal identifier, signal direction, and signal bit width of the interface signals from the interface definition.

[0148] The transaction type, interface type, and other attributes pointing to existing UVM components are identified as component reference information. Components extracted from member declarations and factory creation statements are identified as child components of the corresponding parent components, and connection endpoints extracted from port connection statements are identified as port connection relationships.

[0149] Therefore, code scanning involves extracting relevant component attribute information and component relationship information after determining the component type.

[0150] In one possible implementation of step S1012 above, the obtained UVM components and component relationships are recorded in the project configuration data, and an initial visual component diagram is displayed on the visual configuration interface based on the project configuration data containing the recorded UVM components and component relationships, including the following steps: Step B1: Record the component identifier, component type, component attribute information, component reference information, sub-components and port connection relationships of the UVM component in the project configuration data.

[0151] Specifically, for each UVM component identified in step A1, a corresponding component record is created in the project configuration data, and the component identifier and component type are written into that component record. For the component attribute information identified in step A2, the corresponding attributes are written into the corresponding component record; for component reference information, the current UVM component, the referenced attribute, and the referenced UVM component are written into the corresponding component reference relationship record; for the identified child components, the parent component and child component are written into the corresponding component inclusion relationship record; for the identified port connection relationship, the UVM components involved in the connection, the port identifier, and the port type are written into the corresponding TLM connection relationship record.

[0152] Step B2: Based on the project configuration data, record the component reference information in the component node corresponding to the UVM component, determine the hierarchical relationship between component nodes based on the sub-components, and determine the connection between the typed ports of the component nodes based on the port connection relationship.

[0153] Specifically, for each component record in the project configuration data, a corresponding component node is created, and the component identifier and component type are displayed in that component node.

[0154] For component reference relationship records, the referenced UVM component and its corresponding reference attribute are associated and recorded in the component node corresponding to the current UVM component, so that the component node saves the component reference information obtained by scanning.

[0155] For component inclusion relationship records, the component node corresponding to the parent component is designated as the parent component node, and the component node corresponding to the child component is designated as the child component node, establishing a hierarchical relationship between the parent and child component nodes. For TLM connection relationship records, corresponding typed ports are formed on the component nodes participating in the connection, and connections are formed between the corresponding typed ports according to the port connection relationship.

[0156] After executing step B2, step S1021 is executed. In response to the confirmation operation, correction operation, or supplementary configuration operation for the initial visual component diagram, the component nodes, component reference information, hierarchical relationship, or connection are confirmed, corrected, or supplemented, and the project configuration data and visual component diagram are updated according to the operation results.

[0157] In one possible implementation of step S104 above, after the component relationship consistency check passes, the UVM component code corresponding to each UVM component is generated according to the updated project configuration data, including the following steps: Step S1041: Based on the component reference information in the project configuration data, generate component reference code pointing to the UVM component identified by the component reference information in the UVM component code corresponding to the corresponding UVM component.

[0158] Specifically, the component reference information associated with the current UVM component is read from the project configuration data to determine another UVM component referenced by the current UVM component and its corresponding reference attributes.

[0159] Based on the component identifier and component type of the referenced UVM component, determine the reference type and reference target in the component reference code, and write the component reference code into the code location corresponding to the current UVM component.

[0160] For example, when the component reference information indicates that the driver references the transaction component bus_transaction, bus_transaction is written in the parameterized type position of the driver class; when the component reference information indicates that the driver references the interface component bus_if, a virtual interface declaration pointing to bus_if is generated in the driver code.

[0161] In the above bus verification environment example, during the first phase of scanning, the interface component bus_if is identified based on the interface keyword, the transaction component bus_transaction is identified based on the class declaration that inherits from uvm_sequence_item, and bus_driver, bus_monitor, bus_sequencer, bus_agent, bus_env, and bus_test are identified based on the UVM base class inherited from the corresponding class declaration. The source code file containing the module definition is marked as a candidate design file under test.

[0162] During the second phase of scanning, the field identifiers of addr and data, the data type of bit[31:0], and the random attribute of rand are extracted from the field declaration of bus_transaction; the transaction type bus_transaction used by bus_driver, bus_monitor, and bus_sequencer is extracted from the code content of bus_driver, bus_monitor, and bus_sequencer; and the interface type bus_if used by bus_driver and bus_monitor is extracted from the virtual interface handle declaration of bus_driver and bus_monitor.

[0163] Further, extract bus_driver, bus_monitor, and bus_sequencer from the member declarations and factory creation statements of bus_agent, and determine the sub-components of bus_agent accordingly; extract the corresponding connection components and connection ports from the port connection statements, and determine the port connection relationships accordingly.

[0164] The component identifiers, component types, and component attribute information of bus_if, bus_transaction, bus_driver, bus_monitor, bus_sequencer, bus_agent, bus_env, and bus_test are recorded in the project configuration data respectively. The component reference information, sub-components, and port connection relationships between each UVM component are recorded as corresponding relationship records.

[0165] Based on the project configuration data, the component reference information of bus_driver, bus_monitor, and bus_sequencer to bus_transaction, as well as the component reference information of bus_driver and bus_monitor to bus_if, are recorded in the corresponding component nodes. The containment relationship between bus_agent and its child components is displayed as a hierarchical relationship, and the identified port connection relationship is displayed as the connection between typed ports.

[0166] When regenerating code based on the scan results, the component relationship consistency check is first performed on the project configuration data that records the scan results, confirmation results, correction results, and supplementary configuration results. After the check passes, the transaction type reference code corresponding to bus_transaction is generated in the UVM component code corresponding to bus_driver, bus_monitor, and bus_sequencer, based on the component reference information in the project configuration data. The virtual interface declaration code corresponding to bus_if is also generated in the UVM component code corresponding to bus_driver and bus_monitor.

[0167] In the UVM verification environment automatic generation method of this embodiment, the first-stage code scanning identifies component definition information and determines component identifiers and types. Then, the second-stage code scanning, based on the determined component types, employs corresponding attribute matching and relationship matching rules to identify component attribute information, component reference information, sub-components, and port connection relationships. This allows for the extraction of required information from corresponding code locations for different component types. Furthermore, the scanning results are recorded in the project configuration data and converted into component reference information, hierarchical relationships, and connections within component nodes. After consistency verification passes, component reference code is generated based on the component reference information. This enables continuous conversion between existing UVM project code, project configuration data, visual component diagrams, and component reference code, improving the structured recovery capability of existing UVM project component information and the efficiency of associated code generation.

[0168] In another possible implementation of step S102 above, in response to a component configuration operation on the visual component graph, updating component nodes, hierarchical relationships or connections, and project configuration data includes the following steps: Step S1022: In response to the reference attribute configuration operation for the target component node, determine the referenced component type corresponding to the reference attribute to be configured.

[0169] Specifically, the target component node is the component node whose component reference relationship needs to be configured.

[0170] Reference attributes are properties in the UVM component corresponding to the target component node that are used to point to another UVM component.

[0171] Upon receiving the reference attribute configuration operation, the target component node and the reference attribute to be configured are determined, and the type of the referenced component is determined based on the UVM component categories that the reference attribute is allowed to reference.

[0172] For example, when the reference attribute to be configured is the transaction type used by the driver, the referenced component type is determined to be the transaction type; when the reference attribute to be configured is the interface type used by the driver, the referenced component type is determined to be the interface type.

[0173] Step S1023: Display candidate component nodes that match the type of the referenced component in the visual configuration interface.

[0174] Specifically, from the component nodes contained in the visual component graph, the component type of each component node is compared with the type of the referenced component, and the component node whose component type matches the type of the referenced component is determined as the candidate component node.

[0175] The component identifiers of each candidate component node are displayed in the visual configuration interface, so that users can select the reference target from the corresponding type of component that already exists in the visual component graph.

[0176] Candidate component nodes can be presented through a candidate list, a drop-down selection area, or by being highlighted in a visual component graph.

[0177] Step S1024: In response to selecting the referenced component node from the candidate component nodes, record the component reference information between the target component node and the referenced component node in the target component node, and update the project configuration data according to the component reference information.

[0178] Specifically, after receiving the selection operation for the candidate component node, the selected candidate component node is determined as the referenced component node. The component reference information used to indicate the reference relationship between the target component node, the reference attribute and the referenced component node is recorded in the target component node. The UVM component corresponding to the target component node, the reference attribute and the UVM component corresponding to the referenced component node are associated and recorded in the project configuration data.

[0179] Based on the updated project configuration data, the component identifier of the referenced component node is displayed in the target component node or the attribute area of ​​the target component node, so that the configured reference relationship can be confirmed through the visual configuration interface.

[0180] In one possible implementation of step S104 above, after the component relationship consistency check passes, the UVM component code corresponding to each UVM component is generated according to the updated project configuration data, including the following steps: Step S1042: Based on the component reference information in the project configuration data, generate component reference code pointing to the UVM component corresponding to the referenced component node in the UVM component code corresponding to the target component node.

[0181] Specifically, the component reference information associated with the UVM component corresponding to the target component node is read from the project configuration data. The code form and writing location of the component reference code are determined according to the reference attribute. The reference object in the component reference code is determined according to the component identifier and component type of the referenced component node.

[0182] For example, when the target component node is a driver node, the reference attribute is a transaction type, and the referenced component node is bus_transaction, a driver class declaration with bus_transaction as the parameter type is generated; when the reference attribute is an interface type and the referenced component node is bus_if, an interface handle declaration of type virtual bus_if is generated.

[0183] In the bus verification environment example above, the reference attribute configuration operations corresponding to the transaction type are performed for bus_driver, bus_monitor, and bus_sequencer respectively.

[0184] The referenced component type is determined based on the transaction type, and candidate component nodes for the transaction type in the current project are displayed in the visual configuration interface.

[0185] In response to the selection operation of the component node corresponding to bus_transaction, the component reference information pointing to bus_transaction is recorded in the component nodes corresponding to bus_driver, bus_monitor and bus_sequencer respectively.

[0186] For both bus_driver and bus_monitor, execute the reference attribute configuration operation corresponding to the interface type. Based on the interface type, determine the referenced component type as the interface type, and display candidate component nodes of the interface type in the current project in the visual configuration interface.

[0187] In response to the selection operation of the component node corresponding to bus_if, the component reference information pointing to bus_if is recorded in the component nodes corresponding to bus_driver and bus_monitor, respectively.

[0188] After the component relationship consistency verification passes, based on the above component reference information, the transaction type reference code corresponding to bus_transaction is generated in the UVM component code corresponding to bus_driver, bus_monitor and bus_sequencer, and the virtual interface declaration code corresponding to bus_if is generated in the UVM component code corresponding to bus_driver and bus_monitor.

[0189] In the UVM verification environment automatic generation method of this embodiment, the type of the referenced component is determined by the reference attribute to be configured, and candidate component nodes matching the referenced component type are displayed, enabling the target component node to select the referenced component node from the candidate component nodes of the corresponding component type. The selection result is further recorded as component reference information in the project configuration data, and component reference code is generated based on the component reference information after consistency verification passes. This establishes the correspondence between reference attributes, referenced component nodes, project configuration data, and component reference code, realizing a visual reference configuration with component type constraints, improving the configuration accuracy of UVM component reference relationships and the consistency between the interface configuration results and the generated code.

[0190] In another possible implementation of step S102 above, in response to a component configuration operation on the visual component graph, updating component nodes, hierarchical relationships or connections, and project configuration data includes the following steps: Step S1025: In response to the connection operation between the source typed port and the target typed port, a connection is formed between the source typed port and the target typed port, and the connection relationship between the source typed port and the target typed port is recorded as a TLM connection relationship in the project configuration data.

[0191] Specifically, each typed port displays the port identifier and UVM TLM port type.

[0192] The source type port is the starting port selected for this connection operation, and the destination type port is the target port selected for this connection operation.

[0193] Upon receiving a connection operation from the source typed port to the target typed port, determine the source component node to which the source typed port belongs and the target component node to which the target typed port belongs, and establish the correspondence between the source typed port and the target typed port.

[0194] Record the UVM component and port identifiers at both ends of the TLM connection in the project configuration data, and record or determine the UVM TLM port type, connection direction and transaction type according to the corresponding typed port; based on the recorded TLM connection relationship, display the connection between the source typed port and the target typed port in the visualization component diagram.

[0195] In one possible implementation, when creating a component node, identifying a component node through code scanning, or changing the component type of a component node, if the component type of the component node is a preset component type, a standard typed port corresponding to that component type is automatically generated and maintained in the project configuration data based on that component type, and that standard typed port is displayed on the component node.

[0196] Specifically, when the component type of a component node is a driver type, the standard typed port includes seq_item_port; when the component type of a component node is a sequencer type, the standard typed port includes seq_item_export; and when the component type of a component node is a monitor type, the standard typed port includes an analysis port of UVM TLM type uvm_analysis_port. The port identifier of this analysis port can be ap.

[0197] The transaction component referenced by the component node is determined based on its component reference information, and the transaction type transmitted by the standard typed port is determined based on the transaction type of the referenced transaction component. When the transaction component referenced by the component node changes, the transaction type transmitted by the standard typed port in the project configuration data is updated according to the changed transaction component, and the standard typed port displayed on the component node is updated according to the updated project configuration data.

[0198] Whether a TLM connection relationship is established between standard type ports is determined based on the connection operation received in step S1025, thereby distinguishing the automatic formation of standard type ports from the configuration of specific port connection relationships.

[0199] In one possible implementation of step S105 above, if the component relationship consistency check passes, port connection code is generated based on the TLM connection relationship in the project configuration data, including the following steps: Step S1051: Based on the two ends of the TLM connection relationship, determine the source component node to which the source typed port belongs and the target component node to which the target typed port belongs, and generate a UVM TLM port connection statement between the source typed port and the target typed port based on the source component node, the source typed port, the target component node, and the target typed port.

[0200] Specifically, the TLM connection relationship in the project configuration data is read, and the source component node, source port identifier, target component node and target port identifier in the TLM connection relationship are determined, thereby determining the two connection endpoints in the connection statement.

[0201] Based on the component inclusion relationship in the project configuration data, determine the component hierarchy of the source component node and the target component node, determine the UVM component code used to write the UVM TLM port connection statement, and generate the corresponding UVM TLM port connection statement based on the two connection endpoints of the TLM connection relationship.

[0202] For example, when a connection is formed between the seq_item_port of the driver node and the seq_item_export of the sequencer node, a connect statement between the two ports is generated based on the connection, and the connect statement is written into the component code containing the driver and the sequencer.

[0203] In the bus verification environment example described above, the bus_agent is configured in active mode, and bus_driver, bus_monitor, and bus_sequencer are created or displayed in the internal component graph corresponding to the bus_agent. Based on the component types of bus_driver, bus_monitor, and bus_sequencer, the project configuration data automatically maintains the seq_item_port of bus_driver, the AP port of bus_monitor with UVM TLM port type uvm_analysis_port, and the seq_item_export of bus_sequencer, and displays the aforementioned standard typed ports on the corresponding component nodes.

[0204] Based on the transaction component bus_transaction jointly referenced by bus_driver, bus_monitor, and bus_sequencer, the transaction type passed by the above standard typed port is determined to be bus_transaction.

[0205] In response to the connection operation between seq_item_port of bus_driver and seq_item_export of bus_sequencer, a connection is formed between the two, and the corresponding TLM connection relationship is recorded in the project configuration data. After the component relationship consistency verification is passed, a UVM TLM port connection statement for establishing the sequence item transfer relationship between bus_driver and bus_sequencer is generated in the UVM component code corresponding to bus_agent based on the TLM connection relationship.

[0206] When the transaction component referenced by bus_driver, bus_monitor, or bus_sequencer changes, the transaction type transmitted by the corresponding standard typed port in the project configuration data is updated according to the changed transaction component, and the standard typed port displayed on the corresponding component node is updated. When bus_agent is configured in passive mode, the project configuration data is updated according to the sub-components included in passive mode, and the standard typed port displayed on the bus_agent and its sub-component nodes is updated according to the updated project configuration data.

[0207] In the UVM verification environment automatic generation method of this embodiment, by automatically forming and maintaining standard typed ports according to component types, and updating the transaction type of the standard typed ports in conjunction with the transaction components referenced by the component nodes, the redundant configuration of standard ports can be reduced and the consistency between component reference relationships and port transaction types can be maintained. Furthermore, in response to connection operations, the TLM connection relationship between typed ports is recorded in the project configuration data, and after the consistency verification passes, a UVM TLM port connection statement is generated based on this TLM connection relationship, which can establish the correspondence between standard typed ports, visual connections, project configuration data, and port connection code.

[0208] Based on the implementation shown in step S1025 above, the component node includes a container component node capable of containing child component nodes. Each container component node corresponds to an internal component diagram, which is used to display the child component nodes contained in the container component node and the relationships between the child component nodes. In response to an entry operation on a container component node, the internal component diagram corresponding to the container component node is displayed in the visual configuration interface. Step S102 also includes the following steps: Step S1026: In response to the port export operation of the inner typed port of a sub-component node in the internal component graph of the container component node, the outer typed port corresponding to the inner typed port and matching the UVM TLM port type is displayed on the container component node, a port forwarding connection is formed between the inner typed port and the outer typed port, and the outer typed port and the port forwarding relationship are recorded in the project configuration data.

[0209] Specifically, a container component node is a component node that has child component nodes.

[0210] Inner type ports are type ports on child component nodes contained in a container component node, while outer type ports are type ports set on the container component node itself to present the corresponding inner type ports to the outside of the container component.

[0211] Upon receiving a port export operation for an inner typed port, the system reads the port identifier, UVM TLM port type, and transaction type of the inner typed port. It then creates an outer typed port corresponding to the inner typed port for the container component node in the project configuration data and displays the outer typed port on the container component node according to the updated project configuration data.

[0212] Record the port forwarding relationship between the inner and outer typed ports in the project configuration data, and display the corresponding port forwarding connection in the internal component diagram to indicate that transactions are forwarded between the inner and outer layers of the container component through the outer and inner typed ports.

[0213] The outer typed port can continue to establish connections with other component nodes outside the container component node.

[0214] Corresponding to step S1026, in one possible implementation of step S104 above, if the component relationship consistency check passes, the UVM component code corresponding to each UVM component is generated based on the updated project configuration data, including the following steps: Step S1043: Based on the outer typed port corresponding to the container component node in the project configuration data, generate the outer port definition code in the UVM component code corresponding to the container component node.

[0215] Specifically, the system reads the port identifier and UVM TLM port type of the outer typed port from the project configuration data, determines the outer port name based on the port identifier, and determines the code type of the outer port based on the UVM TLM port type. The corresponding outer port declaration and creation code are then generated in the UVM component code corresponding to the container component node, forming the outer port definition code.

[0216] Corresponding to step S1026, based on the implementation shown in step S1051 above, step S105 further includes the following steps: Step S1052: Based on the port forwarding relationship in the project configuration data, generate port forwarding connection code in the UVM component code corresponding to the container component node.

[0217] Specifically, the sub-component nodes, inner typed ports, and outer typed ports associated with the port forwarding relationship in the project configuration data are read to determine the inner port object and the outer port object, and port forwarding connection code for connecting the inner port object and the outer port object is generated in the UVM component code corresponding to the container component node.

[0218] For example, after exporting the AP port of the monitor inside the proxy component, a corresponding outer AP port is formed on the proxy component, and port forwarding connection code between the monitor's AP port and the outer AP port of the proxy component is generated in the proxy component code.

[0219] Other components outside the agent component can establish a TLM connection with the monitor through the outer AP port.

[0220] In the above bus verification environment example, bus_agent is a container component node, bus_monitor is a sub-component node contained in bus_agent, and the AP port of bus_monitor is an inner typed port.

[0221] In response to the port export operation for the AP port of bus_monitor, the outer AP port with the same name and UVM TLM port type as the AP port of bus_monitor is displayed on the component node corresponding to bus_agent, and a port forwarding connection is formed between the AP port of bus_monitor and the outer AP port of bus_agent.

[0222] After the component relationship consistency verification passes, based on the outer AP port corresponding to bus_agent in the project configuration data, the outer port definition code is generated in the UVM component code corresponding to bus_agent. Based on the port forwarding relationship between the AP port of bus_monitor and the outer AP port of bus_agent, the port forwarding connection code is generated in the UVM component code corresponding to bus_agent.

[0223] Return the component canvas corresponding to the verification environment layer, create the scoreboard component node bus_scoreboard and the reference model component node bus_model in the component canvas, and make the verification environment component bus_env contain bus_agent, bus_scoreboard and bus_model.

[0224] In the property configuration area corresponding to bus_scoreboard, configure the monitor component it references as bus_monitor, configure the reference model component it references as bus_model, and configure the transaction comparison strategy as field-by-field comparison.

[0225] In the component drawing canvas corresponding to the verification environment layer, establish a connection between the outer AP port of bus_agent and the analysis implementation port of bus_scoreboard, establish a connection between the outer AP port of bus_agent and the input port of bus_model, and establish a connection between the output port of bus_model and the expected transaction port of bus_scoreboard.

[0226] After the component relationship consistency verification passes, based on the TLM connection relationship recorded in the project configuration data, the corresponding UVM TLM port connection statement is generated in the UVM component code corresponding to bus_env.

[0227] In the UVM verification environment automatic generation method of this embodiment, by making container component nodes correspond to internal component graphs and displaying the internal component graphs in response to entry operations, UVM components with nested inclusion relationships can be presented layer by layer. Furthermore, by using port export operations, an outer typed port corresponding to the inner typed port is formed on the container component node. The outer typed port and port forwarding relationship are recorded in the project configuration data, and after consistency verification passes, the outer port definition code and port forwarding connection code are generated. This enables the synchronous generation of cross-layer port structure, visualized forwarding paths, and cross-layer connection code.

[0228] In another possible implementation of step S102 above, in response to a component configuration operation on the visual component graph, updating component nodes, hierarchical relationships or connections, and project configuration data includes the following steps: Step S1027: In response to the configuration database configuration operation for the target component node, the configuration database entries associated with the target component node are displayed in the visual configuration interface, and the configuration database entries are recorded in the target component node and the project configuration data.

[0229] Specifically, the configuration database is the uvm_config_db configuration transfer mechanism provided by UVM.

[0230] Among them, the configuration database entry is an information entry used to record the configuration content required for a configuration data transfer, including the data type of the data to be configured and the configuration field identifier.

[0231] Upon receiving a configuration database configuration operation for a target component node, the system obtains the input or selected data type and configuration field identifier, associates and records the UVM component, data type, and configuration field identifier corresponding to the target component node in the project configuration data, forming a configuration database entry associated with the target component node.

[0232] Based on the project configuration data, the configuration database entry is displayed in the visual configuration interface, and the data type and configuration field identifier are displayed in the target component node or the attribute area of ​​the target component node, so that the target component node represents the configuration data that the corresponding UVM component needs to obtain or set.

[0233] Corresponding to step S1027, in another possible implementation of step S104 above, if the component relationship consistency check passes, the UVM component code corresponding to each UVM component is generated according to the updated project configuration data, including the following steps: Step S1044: Determine the access path of the configuration database entry based on the hierarchical position of the target component node in the project configuration data, and generate configuration database setting statements and configuration database retrieval statements based on the configuration database entry and access path.

[0234] Specifically, starting from the UVM component corresponding to the target component node in the project configuration data, the parent components to which the UVM component belongs are determined sequentially according to the component inclusion relationship, and the access path used to locate the target component instance is determined according to the component identifier of the UVM component and the parent components at all levels.

[0235] Read the data type and configuration field identifier in the configuration database entry, determine the path expression of the access path in the configuration database setting statement based on the component level of the UVM component that provides the data to be configured, and determine the write position of the configuration database retrieval statement based on the UVM component corresponding to the target component node.

[0236] Based on the data type, configuration field identifier, and access path, generate corresponding configuration database setting statements and configuration database retrieval statements.

[0237] Write the configuration database retrieval statement into the UVM component code corresponding to the target component node, and write the configuration database setting statement into the UVM component code that provides the data to be configured.

[0238] In one possible implementation, in response to a selection operation on a target component node, the configuration database entry associated with the target component node, as well as the configuration database setting statement and configuration database retrieval statement generated based on the configuration database entry, are displayed in the visual configuration interface.

[0239] When a component configuration operation is performed on the hierarchical relationship of the target component node, causing the hierarchical position of the target component node in the visual component diagram to change, the component inclusion relationship in the project configuration data is updated. Based on the updated component inclusion relationship, the access path of the configuration database entry is re-determined, and the access path in the configuration database setting statement and configuration database retrieval statement is updated.

[0240] Therefore, by observing the changes in the hierarchical position of the target component node and the changes in the access path in the generated statement, it is possible to intuitively confirm that the configuration database access path is determined based on the hierarchical position of the target component node in the visual component diagram.

[0241] In the above bus verification environment example, configuration database operations are performed for bus_driver and bus_monitor respectively, and a configuration database entry is formed in the corresponding component node.

[0242] Configure the database entry's data type as virtual interface, the specific data type as bus_if, and the field identifier as vif.

[0243] Based on the hierarchical position of bus_driver and bus_monitor in bus_env, determine the access paths used to locate the corresponding component instances of bus_driver and bus_monitor, respectively.

[0244] Based on the data type bus_if, the configuration field identifier vif, and the corresponding access path, generate uvm_config_db setting and retrieval statements for passing the bus_if virtual interface.

[0245] When the hierarchical position of bus_driver or bus_monitor in the visualization component diagram changes, the corresponding access path is re-determined based on the changed hierarchical position, and the path content in the corresponding configuration database setting statement and retrieval statement is updated.

[0246] In the UVM verification environment automatic generation method of this embodiment, by recording configuration database entries in the project configuration data and associating them with the target component node, a visual association is established between the data type and configuration field identifier of the data to be configured and the target UVM component. The access path is determined by the component inclusion relationship in the project configuration data, and after the consistency verification is passed, configuration database setting statements and configuration database retrieval statements are generated according to the configuration database entries and access paths. This can establish the correspondence between the target component node, configuration data, component level, project configuration data and configuration database code, and improve the visibility of configuration data transmission, path configuration efficiency and code consistency.

[0247] Step S103 above includes the following steps: Step S1031: Perform a component relationship consistency check on the updated project configuration data based on the component records, component inclusion relationships, and TLM connection relationships in the project configuration data.

[0248] Specifically, after updating the project configuration data, the updated component records, component inclusion relationships, and TLM connection relationships are read, and the existence of components, component inclusion relationships, and TLM connection relationships are verified respectively.

[0249] For component inclusion relationships or TLM connection relationships, check whether the component record associated with the component inclusion relationship or TLM connection relationship exists, to confirm that each component inclusion relationship and TLM connection relationship is associated with the UVM component that currently exists in the project configuration data.

[0250] For component containment relationships, determine the parent and child components associated with the containment relationship, and obtain the component types of the parent and child components respectively.

[0251] Based on the child component types that the parent component is allowed to contain, check whether the parent and child components meet the UVM component containment constraints.

[0252] For TLM connection relationships, obtain the typed ports at both ends of the TLM connection relationship and their corresponding UVM TLM port types. Based on the UVM TLM port types, connection directions, and transaction types of the typed ports at both ends, check whether the typed ports at both ends satisfy the UVM TLM port connection constraints.

[0253] In one specific implementation, component relationship consistency verification also includes the following: Check if the referenced UVM component identified by the component reference information exists, and whether the component type of the referenced UVM component matches the component type allowed by the corresponding reference attribute; Check whether the driver components, monitor components, and sequencer components contained in the same agent component reference the same transaction component or have a matching transaction type; When the proxy component is in active mode, check whether the proxy component contains a driver component and a sequencer component.

[0254] Furthermore, component relationship consistency verification may include at least one of the following: checking whether the component name used as the component identifier is empty, whether it is duplicated with the component name of other UVM components, and whether it conforms to the SystemVerilog identifier specification; checking whether the actual transaction received by the scoreboard component and the expected transaction output by the reference model component have matching transaction types; and checking whether the design under test, interface instance, and default test cases associated with the top-level test platform are configured completely.

[0255] Based on the above verification items, the specific verification objects, verification rules and verification results can be determined, and each verification result can be associated with the corresponding component node, hierarchical relationship, connection or component attribute.

[0256] Step S1032: If the component relationship consistency check fails, determine the component records, component inclusion relationships, TLM connection relationships, or component attributes corresponding to the failed checks based on the project configuration data, and display the corresponding check prompts on the visual configuration interface.

[0257] Specifically, when it is detected that a component record associated with a component inclusion relationship or TLM connection relationship does not exist, the component types of the parent and child components do not meet the UVM component inclusion constraint, the typed port does not meet the UVM TLM port connection constraint, or other component relationship consistency verification items fail, the component record, component inclusion relationship, TLM connection relationship, or component attribute that caused the verification to fail is determined.

[0258] In the visual configuration interface, mark the component node, hierarchical relationship, connection or attribute configuration item, and display the verification prompt in the corresponding position.

[0259] The validation hints are used to indicate objects that failed validation and constraints that were not met, so that users can locate the components or component relationships that need to be modified in the visual component diagram.

[0260] For example, connections with mismatched port types and the typed ports at both ends of the connection are highlighted, and a message indicating a port type mismatch is displayed; hierarchical relationships where associated component nodes do not exist are marked, and the missing component nodes are displayed.

[0261] Steps S104 and S105 are not executed until the UVM component, component relationship, or component attribute that caused the validation failure is corrected.

[0262] Step S1033: If the component relationship consistency verification passes, execute steps S104 and S105 to generate multiple component files for the UVM verification environment based on the verified project configuration data.

[0263] Specifically, when the UVM components associated with the component inclusion relationship and the TLM connection relationship both exist, the component inclusion relationship satisfies the UVM component inclusion constraint, and the TLM connection relationship satisfies the UVM TLM port connection constraint, the consistency check of the basic component relationship is determined to be passed.

[0264] When adopting the above specific implementation method, the component relationship consistency check is determined to be passed only if the component reference consistency, the proxy component transaction type consistency, the active proxy component structural integrity, and other component relationship consistency check items are all passed.

[0265] Read the verified project configuration data, and continue to execute steps S104 and S105 to generate UVM component code, component reference code, subcomponent declaration and instantiation code, and port connection code, forming multiple component files for the UVM verification environment.

[0266] In the bus verification environment example above, a test case component bus_test is created, the base class inherited by bus_test is configured, and the verification environment component referenced by bus_test is configured as bus_env.

[0267] Create a top-level test platform component tb_top, and configure the clock cycle, reset time, the design module under test, and the interface instances corresponding to the default test cases bus_test and bus_if in tb_top.

[0268] After completing the above configuration, check whether bus_driver, bus_monitor, and bus_sequencer use matching transaction types, check whether the active mode bus_agent contains driver and sequencer components, check whether the bus_monitor and bus_model referenced by bus_scoreboard exist and whether the corresponding transaction types match, and check whether the design under test, interface instance, and default test cases associated with tb_top are configured completely.

[0269] When any validation item fails, a validation prompt associated with the corresponding component node, hierarchy, connection, or component attribute is displayed in the visual configuration interface.

[0270] In response to configuration operations on the object indicated by the verification prompt, update the corresponding component nodes, hierarchical relationships, connections or component properties and project configuration data, and re-execute component relationship consistency verification on the updated project configuration data.

[0271] After the component relationship consistency verification is passed, 11 component files are generated respectively: bus_if.sv, bus_transaction.sv, bus_driver.sv, bus_monitor.sv, bus_sequencer.sv, bus_agent.sv, bus_scoreboard.sv, bus_model.sv, bus_env.sv, bus_test.sv and tb_top.sv.

[0272] Specifically, bus_driver.sv includes virtual interface declarations, configuration database retrieval statements in the build phase, and transaction driver function structures; bus_agent.sv includes sub-component declarations for bus_driver, bus_monitor, and bus_sequencer, sub-component instantiation code in the build phase, and port connection code between seq_item_port and seq_item_export in active mode; bus_env.sv includes sub-component declarations and instantiation code for bus_agent, bus_scoreboard, and bus_model, as well as connect phase port connection code generated based on connections in the verification environment layer.

[0273] Before generating the entire batch or previewing the code of a single component, a component relationship consistency check is performed on the current project configuration data. After the check passes, in response to the selected operation for any component node, the UVM component code corresponding to that component node is generated based on the current project configuration data, and the generated UVM component code is displayed in the code preview area.

[0274] When component nodes, component properties, hierarchical relationships, or connections change, update the project configuration data and re-execute the component relationship consistency check; after the re-executed component relationship consistency check passes, regenerate and display the corresponding UVM component code based on the updated project configuration data.

[0275] In the UVM verification environment automatic generation method of this embodiment, consistency checks are performed on component existence, component inclusion relationships, TLM connection relationships, and corresponding component reference relationships based on unified project configuration data before code generation. The component nodes, hierarchical relationships, connections, or component attributes corresponding to the verification results are displayed on the visual configuration interface, enabling the component relationship verification results to directly locate the corresponding objects in the visual component graph. After successful verification, multiple component files are generated based on the verified project configuration data, forming a closed-loop processing mechanism between project configuration data updates, visual display, component relationship verification, and code generation. This improves the effectiveness of component relationships in the UVM verification environment, the locatability of verification results, and the correctness and consistency of the generated multiple component files.

[0276] In one possible implementation, the updated project configuration data and the corresponding visualization data of the visual component graph are serialized into a project file. The project file is used to store the component configuration, component relationships, and visualization data in the current UVM validation environment.

[0277] The project file includes the component identifier, component type, component attributes and file path of each UVM component, as well as the component reference relationship, component inclusion relationship and TLM connection relationship between UVM components.

[0278] The project documentation also includes the display position of component nodes in the component diagram canvas, the typed ports that component nodes have, the connections between typed ports, configuration database entries, and the internal component diagram corresponding to the container component nodes.

[0279] In one specific implementation, the project files are in JSON format.

[0280] Generate a JSON object based on the data hierarchy and data fields in the project configuration data, and write the UVM components, component properties, component relationships and visualization display data into the corresponding JSON fields.

[0281] In addition, project files can be saved, loaded, imported, and exported.

[0282] In response to the project loading operation, the system reads the project configuration data from the project file, restores each component node based on the UVM components and component attributes, restores the hierarchical relationship based on the component inclusion relationship, restores the connections between typed ports based on the TLM connection relationship, and restores the position of the component nodes and the internal component diagram of the container component nodes based on the visualization display data. The system continues to receive component configuration operations in the restored visualization component diagram and updates the visualization component diagram and project configuration data based on the component configuration operations.

[0283] For UVM projects that already have some historical code, code scanning is performed on the existing UVM project directory. The UVM components and component relationships identified by the scan are then populated back into the project configuration data and displayed in the visual component diagram.

[0284] In response to confirmation, correction, or supplementary configuration operations on the scan results, update the project configuration data and continue to configure other UVM components, component properties, component reference relationships, component inclusion relationships, and TLM connection relationships in the updated visual component graph.

[0285] Therefore, the component content, component relationships, and visualization status of the UVM verification environment can be saved in the same project file, and the corresponding visualization component diagram can be restored after reloading, realizing continuous reuse of existing code scanning results, manual configuration results, and project files.

[0286] In another possible implementation, a project template corresponding to the component structure of the current UVM verification environment is formed and stored based on the component types, the number of components corresponding to each component type, and the component inclusion relationships in the updated project configuration data. When forming the project template, the TLM connection relationships from the updated project configuration data can also be recorded in the project template.

[0287] The project template is used to record the reusable UVM verification environment structure, including at least the component type, the number of components corresponding to each component type, and the component inclusion relationship. The project template can also record at least one of the following: component reference relationship, standard typed port, TLM connection relationship, configuration database entry, and container component node internal component graph.

[0288] Project files are used to save and restore the configuration status of existing UVM validation environment projects, while project templates are used to record reusable component structures and create new project configuration data accordingly.

[0289] In response to a call to a project template, new project configuration data is created based on the component types, the number of components for each component type, and the component inclusion relationships recorded in the project template. An initial visual component diagram is then displayed based on the new project configuration data. Component configuration operations are then performed on this initial visual component diagram to adjust the number of UVM components, component attributes, or component relationships. After the adjustments are completed, a component relationship consistency check is performed on the new project configuration data, and multiple corresponding component files are generated upon successful check.

[0290] Furthermore, by generating project templates based on project configuration data and creating new project configuration data and initial visual component diagrams based on project templates, the component structure of the UVM verification environment composed of different component types, component quantities, and component inclusion relationships can be reused, reducing the redundant configuration of similar UVM verification environments.

[0291] In one embodiment, an automatic UVM verification environment generation system is provided, which corresponds one-to-one with the automatic UVM verification environment generation method in the above embodiments. For example... Figure 3 As shown, Figure 3 This is a schematic diagram of the composition structure of an automatic UVM verification environment generation system provided in an embodiment of this disclosure. The system includes: The visualization component diagram display module 31 is used to display a visualization component diagram of the UVM verification environment on the visualization configuration interface based on the project configuration data. The visualization component diagram includes multiple component nodes, each of which displays the component identifier and component type of a UVM component. The hierarchical relationship between component nodes is used to represent the component inclusion relationship between UVM components, and the connection between the typed ports of component nodes is used to represent the TLM connection relationship between UVM components. The project configuration data is used to record the component identifier and component type of each UVM component, the component inclusion relationship between UVM components, and the TLM connection relationship between UVM components. The component graph update module 32 is used to respond to component configuration operations on the visual component graph, update component nodes, hierarchical relationships or connections, and update project configuration data based on the updated component nodes, hierarchical relationships or connections; The component relationship verification module 33 is used to perform component relationship consistency verification on the updated project configuration data before generating the component files of the UVM verification environment, based on the component type, component inclusion relationship and TLM connection relationship of each UVM component in the updated project configuration data. The code generation module 34 is used to generate UVM component code corresponding to each UVM component according to the component identifier and component type of each UVM component in the updated project configuration data, and to generate child component declaration and instantiation code in the UVM component code corresponding to the parent component according to the component inclusion relationship, and to generate port connection code in the corresponding UVM component code according to the TLM connection relationship, so as to obtain multiple component files of the UVM verification environment. Among them, the component relationship consistency verification includes checking whether the UVM component associated with the component inclusion relationship or TLM connection relationship exists, whether the component types of the parent and child components associated with the component inclusion relationship meet the UVM component inclusion constraint, and whether the typed ports at both ends of the TLM connection relationship meet the UVM TLM port connection constraint.

[0292] In one embodiment, the visualization component diagram display module 31 is specifically used for: Perform code scanning on existing UVM project code to obtain the UVM components in the existing UVM project code and the component relationships between UVM components; The obtained UVM components and their relationships are recorded in the project configuration data. Based on the project configuration data containing the UVM components and their relationships, an initial visual component diagram is displayed in the visual configuration interface. The initial visual component diagram includes the component nodes corresponding to the obtained UVM components, as well as the hierarchical relationships or connections determined based on the obtained component relationships. The component diagram update module 32 is specifically used to: in response to confirmation, correction or supplementary configuration operations on component nodes, hierarchical relationships or connections in the initial visual component diagram, determine the confirmed, corrected or supplemented UVM components and component relationships, update the project configuration data according to the determined UVM components and component relationships, and update the visual component diagram according to the updated project configuration data.

[0293] In one embodiment, the visualization component diagram display module 31 is further specifically used for: In the first phase of code scanning, component definition information is identified from existing UVM project code, and the component identifier and component type of the corresponding UVM component are determined based on the component definition information; In the second phase of code scanning, based on the component type determined in the first phase of code scanning, the component attribute information, component reference information, sub-components, and port connection relationships are extracted from the corresponding UVM component code using attribute matching rules and relationship matching rules corresponding to the component type. Record component identifiers, component types, component attribute information, component reference information, subcomponents, and port connection relationships in the project configuration data. Determine the hierarchical relationship between component nodes based on subcomponents, and determine the connection between typed ports of component nodes based on port connection relationships. The code generation module 34 is also used to: generate component reference code pointing to the UVM component identified by the component reference information in the UVM component code corresponding to the UVM component, based on the component reference information, when the component relationship consistency verification passes.

[0294] In one embodiment, the component graph update module 32 is specifically used for: In response to a reference attribute configuration operation for a target component node, determine the type of the referenced component corresponding to the reference attribute to be configured; The visual configuration interface displays candidate component nodes that match the type of the referenced component; In response to selecting the referenced component node from the candidate component nodes, the component reference information between the target component node and the referenced component node is recorded in the target component node, and the project configuration data is updated according to the component reference information; The code generation module 34 is also used to: generate component reference code pointing to the UVM component corresponding to the referenced component node in the UVM component code corresponding to the target component node, based on the component reference information, when the component relationship consistency verification passes.

[0295] In one embodiment, the component graph update module 32 is specifically used for: In response to a connection operation between a source typed port and a target typed port, a connection is formed between the source typed port and the target typed port, wherein each typed port displays a port identifier and a UVM TLM port type; Code generation module 34 is specifically used for: Based on the two ends of the connection, determine the source component node to which the source type port belongs and the target component node to which the target type port belongs, and generate the UVM TLM port connection statement between the source type port and the target type port based on the source component node, source type port, target component node, and target type port.

[0296] In one embodiment, the component node includes a container component node, which corresponds to an internal component graph. The internal component graph is used to display the sub-component nodes contained in the container component node and the component relationships between the sub-component nodes. The visualization component diagram display module 31 is also used for: In response to an entry operation on a container component node, the internal component diagram corresponding to the container component node is displayed in the visual configuration interface; Component graph update module 32 is specifically used for: In response to a port export operation for an inner typed port of a child component node belonging to a container component node, an outer typed port corresponding to the inner typed port and matching the UVM TLM port type is displayed on the container component node, and a port forwarding connection is formed between the inner typed port and the outer typed port. Code generation module 34 is also used for: If the component relationship consistency check passes, the outer port definition code is generated in the UVM component code corresponding to the container component node based on the outer typed port, and the port forwarding connection code is generated in the UVM component code corresponding to the container component node based on the port forwarding connection.

[0297] In one embodiment, the component graph update module 32 is further configured to: When the component type of the component node is a driver type, a sequencer type, or a monitor type, a standard typed port is automatically maintained on the corresponding component node according to the component type. The standard typed port corresponding to the driver type includes seq_item_port, the standard typed port corresponding to the sequencer type includes seq_item_export, and the standard typed port corresponding to the monitor type includes the analysis port. The UVM TLM port type of the analysis port is uvm_analysis_port. Determine the transaction type passed by the standard typed port based on the transaction component referenced by the component node; If the transaction component referenced by a component node changes, update the transaction type passed by the standard typed port according to the changed transaction component.

[0298] In one embodiment, the component graph update module 32 is specifically used for: In response to configuration database configuration operations for the target component node, the configuration database entries associated with the target component node are displayed in the visual configuration interface. The configuration database entries are used to indicate the data type and configuration field identifier of the data to be configured, and the configuration database entries are recorded in the target component node and the project configuration data. The code generation module 34 is also used to: determine the access path of the configuration database entry based on the hierarchical position of the target component node in the project configuration data, and generate configuration database setting statements and configuration database retrieval statements based on the configuration database entry and access path, provided that the component relationship consistency verification passes.

[0299] In one embodiment, the component relationship verification module 33 is further configured to: Check if the referenced component node identified by the component reference information exists, and whether the component type of the referenced component node matches the referenced component type corresponding to the reference attribute to be configured; Check whether the transaction components referenced by the driver components, monitor components, and sequencer components contained in the same agent component are consistent; When the proxy component is in active mode, check whether the proxy component contains a driver component and a sequencer component; The visualization component diagram display module 31 is also used to: display a verification prompt corresponding to the component node or component relationship that failed the check on the visualization configuration interface if any check fails.

[0300] In one embodiment, the component graph update module 32 is further configured to: Serialize the updated project configuration data and the corresponding visualization display data of the visualization component diagram into a project file; In response to the project loading operation, read the project configuration data from the project file, restore the component nodes, hierarchical relationships and connections based on the project configuration data, and continue to respond to component configuration operations on the restored visual component graph, updating the project configuration data and the visual component graph.

[0301] In one embodiment, the component graph update module 32 is further configured to: Based on the component types, the number of components corresponding to each component type, and the component inclusion relationships in the updated project configuration data, a project template corresponding to the component structure of the UVM verification environment is formed and stored. In response to a call to a project template, create new project configuration data based on the component types, the number of components for each component type, and the component inclusion relationships recorded in the project template. The visualization component diagram display module 31 is also used to display the initial visualization component diagram based on the new project configuration data.

[0302] It should be noted that the UVM verification environment automatic generation system provided in the above embodiments is only illustrated by the division of the above program modules when implementing the corresponding UVM verification environment automatic generation method. In practical applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the above system can be divided into different program modules to complete all or part of the processing described above. In addition, the system provided in the above embodiments and the corresponding Figure 1 The embodiments of the methods shown belong to the same concept, and their specific implementation process can be found in the method embodiments, which will not be repeated here.

[0303] This disclosure also provides an electronic device for implementing the above-described method for automatically generating a UVM verification environment.

[0304] Figure 4 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure.

[0305] The following is a detailed reference. Figure 4 The diagram illustrates a structural schematic suitable for implementing an electronic device according to embodiments of the present disclosure. The electronic device may include a processor (e.g., a central processing unit, graphics processor, etc.) 401, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 402 or a program loaded from memory 408 into random access memory (RAM) 403. RAM 403 also stores various programs and data required for the operation of the electronic device. The processor 401, ROM 402, and RAM 403 are interconnected via bus 404. Input / output (I / O) interface 405 is also connected to bus 404.

[0306] Typically, the following devices can be connected to I / O interface 405: input devices 406 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 407 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; memory devices 408 including, for example, magnetic tapes, hard disks, etc.; and communication devices 409. Communication device 409 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 4 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown, and more or fewer devices may be implemented or have instead.

[0307] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication device 409, or installed from memory 408, or installed from ROM 402. When the computer program is executed by processor 401, it performs the functions defined in the UVM verification environment automatic generation method of embodiments of this disclosure.

[0308] Figure 4 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0309] This disclosure also provides a computer-readable storage medium in which the methods described in this disclosure can be implemented in hardware or firmware, or implemented as recordable on a storage medium, or implemented as computer code originally stored on a remote storage medium or a non-transitory machine-readable storage medium and subsequently stored on a local storage medium after being downloaded over a network. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium may also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code. When the software or computer code is accessed and executed by the computer, processor, or hardware, the UVM verification environment automatic generation method shown in the above embodiments is implemented.

[0310] A portion of this disclosure can be applied to computer program products, such as computer program instructions, which, when executed by a computer, can invoke or provide methods and / or technical solutions according to this disclosure through the operation of the computer. Those skilled in the art will understand that the forms in which computer program instructions exist in a computer-readable medium include, but are not limited to, source files, executable files, and installation package files. Accordingly, the ways in which computer program instructions are executed by a computer include, but are not limited to: the computer directly executing the instructions; the computer compiling the instructions and then executing the corresponding compiled program; the computer reading and executing the instructions; or the computer reading and installing the instructions and then executing the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to a computer.

[0311] Although embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations all fall within the scope defined by the appended claims.

Claims

1. A method for automatically generating a UVM verification environment, characterized in that, The method includes: The visual configuration interface displays a visual component diagram of the UVM verification environment based on the project configuration data. This diagram includes multiple component nodes, each displaying the component identifier and type of a UVM component. The hierarchical relationship between the component nodes represents the component inclusion relationship between the UVM components, and the connections between the typed ports of the component nodes represent the TLM connection relationship between the UVM components. The project configuration data records the component identifier and type of each UVM component, the component inclusion relationship between the UVM components, and the TLM connection relationship between the UVM components. Each of the typed ports displays a port identifier and a UVM TLM port type; the component node includes a container component node, and the container component node corresponds to an internal component graph, which is used to display the sub-component nodes contained in the container component node and the component relationships between the sub-component nodes; In response to an entry operation for the container component node, the internal component diagram corresponding to the container component node is displayed on the visual configuration interface; In response to a component configuration operation on the visual component graph, the component nodes, the hierarchical relationship, or the connection are updated, and the project configuration data is updated based on the updated component nodes, hierarchical relationship, or connection; Before generating the component files of the UVM verification environment, a component relationship consistency check is performed on the updated project configuration data based on the component type of each UVM component, the component inclusion relationship, and the TLM connection relationship in the updated project configuration data. The component relationship consistency check includes checking whether the UVM component associated with the component inclusion relationship or the TLM connection relationship exists, whether the component types of the parent and child components associated with the component inclusion relationship satisfy the UVM component inclusion constraint, and whether the typed ports at both ends of the TLM connection relationship satisfy the UVMTLM port connection constraint. If the component relationship consistency verification passes, the UVM component code corresponding to each UVM component is generated according to the component identifier and component type of each UVM component in the updated project configuration data. If the component relationship consistency verification passes, based on the component inclusion relationship in the updated project configuration data, the child component declaration and instantiation code is generated in the UVM component code corresponding to the parent component in the component inclusion relationship, and based on the TLM connection relationship, the port connection code is generated in the corresponding UVM component code, thus obtaining multiple component files of the UVM verification environment; The step of updating the component nodes, the hierarchical relationships, or the connections in response to a component configuration operation on the visual component graph, and updating the project configuration data based on the updated component nodes, hierarchical relationships, or connections, includes: In response to a connection operation for a source typed port and a target typed port, the connection is formed between the source typed port and the target typed port; In response to a port export operation for an inner typed port belonging to a child component node of the container component node, an outer typed port corresponding to the inner typed port and matching the UVM TLM port type is displayed on the container component node, and a port forwarding connection is formed between the inner typed port and the outer typed port. The step of generating port connection code in the corresponding UVM component code based on the TLM connection relationship includes: Based on the two ends of the connection, determine the source component node to which the source type port belongs and the target component node to which the target type port belongs, and generate a UVM TLM port connection statement between the source type port and the target type port based on the source component node, the source type port, the target component node, and the target type port. The method further includes: If the component relationship consistency verification passes, based on the outer typed port, outer port definition code is generated in the UVM component code corresponding to the container component node, and based on the port forwarding connection, port forwarding connection code is generated in the UVM component code corresponding to the container component node.

2. The method of claim 1, wherein, The visualization of the UVM verification environment, displayed on the visual configuration interface based on project configuration data, includes: Perform code scanning on the existing UVM project code to obtain the UVM components in the existing UVM project code and the component relationships between the UVM components; The obtained UVM components and component relationships are recorded in the project configuration data, and an initial visual component diagram is displayed in the visualization configuration interface based on the project configuration data that records the UVM components and component relationships. The initial visual component diagram includes component nodes corresponding to the obtained UVM components, as well as hierarchical relationships or connections determined based on the obtained component relationships. The step of updating the component nodes, the hierarchical relationships, or the connections in response to a component configuration operation on the visual component graph, and updating the project configuration data based on the updated component nodes, hierarchical relationships, or connections, includes: In response to confirmation, correction, or supplementary configuration operations on component nodes, hierarchical relationships, or connections in the initial visualization component diagram, the confirmed, corrected, or supplemented UVM components and component relationships are determined, the project configuration data is updated based on the determined UVM components and component relationships, and the visualization component diagram is updated based on the updated project configuration data.

3. The method of claim 2, wherein, The code scanning process includes: In the first stage of code scanning, component definition information is identified from the existing UVM project code, and the component identifier and component type of the corresponding UVM component are determined based on the component definition information; In the second stage of code scanning, based on the component type determined in the first stage of code scanning, the component attribute information, component reference information, sub-components, and port connection relationships are extracted from the corresponding UVM component code using attribute matching rules and relationship matching rules corresponding to the component type. The component identifier, component type, component attribute information, component reference information, subcomponents, and port connection relationships are recorded in the project configuration data. The hierarchical relationship between the component nodes is determined based on the subcomponents, and the connection between the typed ports of the component nodes is determined based on the port connection relationships. If the component relationship consistency verification passes, component reference code pointing to the UVM component identified by the component reference information is generated in the UVM component code corresponding to the UVM component, based on the component reference information.

4. The method of claim 1, wherein, The step of updating the component nodes, the hierarchical relationships, or the connections in response to a component configuration operation on the visual component graph, and updating the project configuration data based on the updated component nodes, hierarchical relationships, or connections, includes: In response to a reference attribute configuration operation for a target component node, determine the type of the referenced component corresponding to the reference attribute to be configured; The visual configuration interface displays candidate component nodes that match the referenced component type; In response to selecting a referenced component node from the candidate component nodes, the component reference information between the target component node and the referenced component node is recorded in the target component node, and the project configuration data is updated according to the component reference information; If the component relationship consistency verification passes, component reference code pointing to the UVM component corresponding to the referenced component node is generated in the UVM component code corresponding to the target component node according to the component reference information.

5. The method according to claim 1, characterized in that, When the component type of the component node is a driver type, a sequencer type, or a monitor type, a standard typed port is automatically maintained on the corresponding component node according to the component type. The standard typed port corresponding to the driver type includes seq_item_port, the standard typed port corresponding to the sequencer type includes seq_item_export, and the standard typed port corresponding to the monitor type includes an analysis port. The UVM TLM port type of the analysis port is uvm_analysis_port. The transaction type transmitted by the standard typed port is determined based on the transaction component referenced by the component node; If the transaction component referenced by the component node changes, the transaction type passed by the standard typed port is updated according to the changed transaction component.

6. The method according to claim 1, characterized in that, The step of updating the component nodes, the hierarchical relationships, or the connections in response to a component configuration operation on the visual component graph, and updating the project configuration data based on the updated component nodes, hierarchical relationships, or connections, includes: In response to a configuration database configuration operation for a target component node, a configuration database entry associated with the target component node is displayed on the visual configuration interface. The configuration database entry is used to indicate the data type and configuration field identifier of the data to be configured, and the configuration database entry is recorded in the target component node and the project configuration data. If the component relationship consistency verification passes, the access path of the configuration database entry is determined according to the hierarchical position of the target component node in the project configuration data, and configuration database setting statement and configuration database retrieval statement are generated according to the configuration database entry and the access path.

7. The method according to claim 4, characterized in that, The component relationship consistency check also includes: Check whether the referenced component node identified by the component reference information exists, and whether the component type of the referenced component node matches the referenced component type corresponding to the reference attribute to be configured; Check whether the transaction components referenced by the driver components, monitor components, and sequencer components contained in the same agent component are consistent; When the proxy component is in active mode, check whether the proxy component contains a driver component and a sequencer component; If any check fails, a verification prompt corresponding to the component node or component relationship that failed the check will be displayed on the visual configuration interface.

8. The method according to claim 1, characterized in that, The method further includes: Serialize the updated project configuration data and the visualization display data corresponding to the visualization component diagram into a project file; In response to a project loading operation, the project configuration data in the project file is read, and the component nodes, hierarchical relationships, and connections are restored based on the project configuration data. In response to a component configuration operation on the restored visual component graph, the project configuration data and the visual component graph are updated.

9. The method according to claim 1, characterized in that, The method further includes: Based on the component types, the number of components corresponding to each component type, and the component inclusion relationships in the updated project configuration data, a project template corresponding to the component structure of the UVM verification environment is formed and stored. In response to the call operation for the project template, new project configuration data is created based on the component types, the number of components corresponding to each component type, and the component inclusion relationships recorded in the project template, and an initial visual component diagram is displayed based on the new project configuration data.

10. An automatic generation system for UVM verification environments, characterized in that, The system includes: The visualization component diagram display module is used to display a visualization component diagram of the UVM verification environment on the visualization configuration interface based on the project configuration data. The visualization component diagram includes multiple component nodes, each displaying the component identifier and component type of a UVM component. The hierarchical relationship between the component nodes represents the component inclusion relationship between the UVM components, and the connections between the typed ports of the component nodes represent the TLM connection relationship between the UVM components. The project configuration data is used to record the component identifier and component type of each UVM component, the component inclusion relationship between the UVM components, and the TLM connection relationship between the UVM components. The component graph update module is used to update the component nodes, the hierarchical relationship or the connection in response to the component configuration operation for the visual component graph, and update the project configuration data according to the updated component nodes, hierarchical relationship or connection; The component relationship verification module is used to perform component relationship consistency verification on the updated project configuration data before generating the component files of the UVM verification environment, based on the component type of each UVM component in the updated project configuration data, the component inclusion relationship and the TLM connection relationship. The code generation module is used to generate UVM component code corresponding to each UVM component according to the component identifier and component type of each UVM component in the updated project configuration data, and generate child component declaration and instantiation code in the UVM component code corresponding to the parent component according to the component inclusion relationship, and generate port connection code in the corresponding UVM component code according to the TLM connection relationship, so as to obtain multiple component files of the UVM verification environment. The component relationship consistency check includes checking whether the UVM component associated with the component inclusion relationship or the TLM connection relationship exists, whether the component types of the parent and child components associated with the component inclusion relationship meet the UVM component inclusion constraint, and whether the typed ports at both ends of the TLM connection relationship meet the UVM TLM port connection constraint. Each of the typed ports displays a port identifier and a UVM TLM port type; the component node includes a container component node, and the container component node corresponds to an internal component graph, which is used to display the sub-component nodes contained in the container component node and the component relationships between the sub-component nodes; The visualization component diagram display module is also used to display the internal component diagram corresponding to the container component node in the visualization configuration interface in response to the entry operation of the container component node. The component graph update module is specifically used for: In response to a connection operation for a source typed port and a target typed port, the connection is formed between the source typed port and the target typed port; In response to a port export operation for an inner typed port belonging to a child component node of the container component node, an outer typed port corresponding to the inner typed port and matching the UVM TLM port type is displayed on the container component node, and a port forwarding connection is formed between the inner typed port and the outer typed port. The code generation module is specifically used to determine the source component node to which the source type port belongs and the target component node to which the target type port belongs, based on the two ends of the connection, when the component relationship consistency verification passes, and to generate a UVM TLM port connection statement between the source type port and the target type port based on the source component node, the source type port, the target component node and the target type port. The code generation module is further configured to, in the case that the component relationship consistency verification passes, generate outer port definition code in the UVM component code corresponding to the container component node based on the outer typed port, and generate port forwarding connection code in the UVM component code corresponding to the container component node based on the port forwarding connection.

11. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the UVM verification environment automatic generation method as described in any one of claims 1-9 when executing the computer program.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the UVM verification environment automatic generation method as described in any one of claims 1-9.

13. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the UVM verification environment automatic generation method as described in any one of claims 1-9.

Images