MOM capacitor model, modeling method, system and readable storage medium thereof

Abstract

The application provides a MOM capacitor model, a modeling method, a system and a readable storage medium, wherein the influence of device distribution density D is considered in the constructed MOM capacitor model, a correction function f(D) about the device distribution density D is introduced, the MOM capacitor model is corrected, and the influence of the device distribution density D on the MOM capacitor is further corrected, so that the corrected MOM capacitor model is more perfect and accurate, is more in line with the real physical law, the fitting precision of the MOM capacitor model is improved, the accuracy and reliability of subsequent integrated circuit design and simulation can be ensured, the engineers can be helped to optimize the design and process of the integrated circuit, and the design efficiency and actual production efficiency of the integrated circuit are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a MOM capacitor model, its modeling method, system, and readable storage medium. Background Technology

[0002] Capacitors are fundamental components in integrated circuits. With the continuous increase in chip integration density, developing high-performance capacitors has become increasingly important. In the semiconductor field, common capacitors include thin-film metal-insulator-metal (MIM) capacitors, metal-oxide-metal (MOM) capacitors, and MOS capacitors. Among these, MOM capacitors are currently widely used in chip manufacturing. They primarily utilize the capacitance between metal layers, and larger capacitance values ​​can be achieved by stacking multiple MOM capacitors. Compared to MIM and MOS capacitors, MOM capacitors have lower manufacturing costs and higher capacitance density (larger capacitance per unit area, saving more space, and eliminating the need for additional masks and processes), making them very common in advanced CMOS technologies. With the continuous development of new chip process nodes, the industry's requirements for the fitting accuracy of MOM capacitor models are becoming increasingly stringent.

[0003] Currently, the industry standard MOM capacitor model can generally be simplified to: C = f(Geo) * f(V) * f(T), which mainly includes three types of functions:

[0004] (1) The size function f(Geo) is used to describe the influence of geometric parameters such as length, width, and number of layers on MOM capacitors;

[0005] (2) Voltage function f(V) is used to describe the effect of voltage on MOM capacitor;

[0006] (3) Temperature function f(T) is used to describe the effect of temperature on MOM capacitor.

[0007] Existing MOM capacitor models in the industry can meet the simulation accuracy requirements at mature process nodes. However, at advanced nodes, the uneven distribution density of MOM capacitors on the wafer can cause deviations in actual process effects due to the uneven distribution density of MOM capacitors in processes such as Chemical Mechanical Polishing (CMP) (the device distribution density of MOM capacitors affects the surface roughness and polishing rate of CMP, as well as the polishing quality) and Etching (the distribution density of MOM capacitors affects the aspect ratio of the etching process, as well as other actual effects). The different actual process effects will result in different metal layer thicknesses of MOM capacitors, which will in turn affect the actual measured values ​​of MOM capacitors. The aforementioned old MOM capacitor models ignore the influence of the device distribution density of MOM capacitors, resulting in a decrease in their fitting accuracy. Summary of the Invention

[0008] The purpose of this invention is to provide a MOM capacitor model, its modeling method, system, and readable storage medium, which can improve the fitting accuracy of the model.

[0009] To achieve the above objectives, the present invention provides a MOM capacitor model, the MOM capacitor model comprising:

[0010] C = f(Geo) * f(V) * f(T) * f(D);

[0011] Where C is the corrected capacitance value of the MOM capacitor, f(Geo) is a correction function for the geometric parameters of the MOM capacitor, f(T) is a correction function for temperature T, f(V) is a correction function for voltage V, and f(D) is a correction function for the device distribution density D of the MOM capacitor.

[0012] Optionally, the MOM capacitance model further includes:

[0013] (1) The MOM capacitor includes at least one MOM capacitor element, the MOM capacitor element includes at least one layer of MOM capacitor, the MOM capacitor includes two interdigitated electrodes formed of the same layer of metal and intersecting with each other; and / or,

[0014] (2) The formula for calculating the device distribution density D of the MOM capacitor is:

[0015]

[0016] Among them, area total The area represents the total area of ​​the device region. total Metal The total area occupied by the metal layer of the MOM capacitor within the total area of ​​the device region.

[0017] Optionally, the MOM capacitor model further includes at least one of the following (1) to (4):

[0018] (1) f(Geo)=a*L*finger+b*L+c*finger+d, where L is the insertion length of the insertion electrode in the MOM capacitor, W is the insertion line width of the insertion electrode, finger is the insertion index of the insertion electrode, and a, b, c, and d are all parameter coefficients.

[0019] (2) f(V)=e+f*V+g*V 2 Where e, f, and g are all parameter coefficients;

[0020] (3) f(T)=h+j*(T-T0), where h and j are parameter coefficients, and T0 is room temperature;

[0021] (4) f(D) = k + m * D + n * D 2 , where k, m, and n are all parameter coefficients.

[0022] Based on the same inventive concept, this invention also provides a modeling method for a MOM capacitor model, which includes the following steps:

[0023] S1, Obtain the required capacitance value data, which includes the capacitance values ​​of MOM capacitors with different device distribution densities.

[0024] S2, Establish the MOM capacitor model as described in this invention, and create expressions for each correction function in the MOM capacitor model;

[0025] S3, use the capacitance value data to perform curve fitting to obtain the parameter coefficients in the expressions of each of the correction functions, and then obtain the MOM capacitance model with the expressions and the parameter coefficients.

[0026] Optionally, before step S1, step S0 is also included: designing multiple MOM capacitors with different device distribution densities to form a test structure; and obtaining the capacitance value data corresponding to the test structure in step S1.

[0027] Optionally, in step S0, the test structure includes at least one of the following (1) to (3):

[0028] (1) The device distribution density of the MOM capacitor in the test structure increases progressively;

[0029] (2) Each MOM capacitor in the test structure includes at least one MOM capacitor element, the MOM capacitor element includes at least one layer of MOM capacitor, and the MOM capacitor includes two interdigitated electrodes formed of the same layer of metal and intersecting each other.

[0030] (3) The formula for calculating the device distribution density D of each MOM capacitor in the test structure is as follows:

[0031]

[0032] Among them, area total The area represents the total area of ​​the device region of the MOM capacitor. total Metal The total area occupied by the metal layer within the total area of ​​the device region of the MOM capacitor.

[0033] Optionally, in step S1, the capacitance value data corresponding to the test structure is obtained by fabricating the test structure on the wafer and performing wafer testing, and / or the test structure is simulated and tested using a corresponding process processing model to obtain the capacitance value data corresponding to the test structure.

[0034] Optionally, in step S3, if the difference between the curve fitting result and the capacitance value data is too large, the process returns to step S1 to obtain new capacitance value data for curve fitting.

[0035] And / or, after step S3, step S4 is further included: performing model verification on the MOM capacitor model; if the MOM capacitor model fails model verification, then returning to step S2 to modify the expression of at least one of the correction functions in the MOM capacitor model, or returning to step S3 to iteratively fit the parameter coefficients in the expression of at least one of the correction functions in the MOM capacitor model until the MOM capacitor model passes verification.

[0036] Based on the same inventive concept, this invention also provides a modeling system for MOM capacitor models, which includes:

[0037] A data acquisition unit is configured to acquire the required capacitance value data, which includes the capacitance values ​​of MOM capacitors with different device distribution densities.

[0038] A modeling unit is configured to build a MOM capacitor model as described in this invention and to create expressions for the various correction functions in the MOM capacitor model.

[0039] A parameter fitting unit is configured to perform curve fitting using the capacitance value data to obtain the parameter coefficients in the expressions of each of the correction functions, thereby obtaining an MOM capacitance model having the expressions and the parameter coefficients.

[0040] Optionally, the modeling system further includes at least one of the following (1) to (4):

[0041] (1) The modeling system also includes a capacitor design unit, which is configured to design multiple MOM capacitors with different device distribution densities to form a test structure;

[0042] (2) The data acquisition unit obtains the capacitance value data corresponding to the test structure by acquiring the wafer test data of the wafer where the test structure is located, and / or, the data acquisition unit performs process simulation processing and simulation testing on the test structure through the corresponding process processing model to obtain the capacitance value data corresponding to the test structure.

[0043] (3) When the difference between the curve fitting result and the capacitance value data is too large, the parameter fitting unit causes the data acquisition unit to provide new capacitance value data for curve fitting.

[0044] (4) The modeling system further includes a model verification unit, which is configured to perform model verification on the MOM capacitor model; when the MOM capacitor model fails the verification by the model verification unit, the parameter fitting unit iteratively fits the parameter coefficients in the expression of at least one of the correction functions in the MOM capacitor model, or the modeling unit modifies the expression of at least one of the correction functions in the MOM capacitor model.

[0045] Based on the same inventive concept, the present invention also provides a readable storage medium for storing a computer program or instructions, which, when executed by a processor, implement the modeling method for the MOM capacitor model as described in the present invention.

[0046] Compared with existing technologies, the technical solution of this invention considers the influence of device distribution density D in the constructed MOM capacitor model, introduces a correction function f(D) for device distribution density D, and corrects the MOM capacitor model to further correct the influence of device distribution density on MOM capacitors. The corrected MOM capacitor model is more complete and accurate, more in line with real physical laws, and improves the fitting accuracy of the MOM capacitor model. This ensures the accuracy and reliability of subsequent integrated circuit design and simulation, helps engineers to optimize integrated circuit design and processes, and improves the design efficiency and actual production efficiency of integrated circuits. Attached Figure Description

[0047] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0048] Figure 1 This is a flowchart of the modeling method for the MOM capacitor model according to a specific embodiment of the present invention.

[0049] Figure 2 This is a schematic diagram of an example test structure in the modeling method of the MOM capacitor model according to a specific embodiment of the present invention.

[0050] Figure 3A This is a top view of a single layer of capacitor in the MOM capacitor element in the modeling method of the MOM capacitor model of a specific embodiment of the present invention.

[0051] Figure 3B This is a three-dimensional structural diagram of the n-layer capacitor in the MOM capacitor element in the modeling method of the MOM capacitor model of a specific embodiment of the present invention.

[0052] Figure 4 This is a table illustrating relevant data used in the modeling method of the MOM capacitor model in a specific embodiment of the present invention.

[0053] Figure 5 Based on Figure 4 The data shown in the table illustrates the C-D curve diagram.

[0054] Figure 6 This is a schematic diagram of the architecture of the modeling system for the MOM capacitor model according to a specific embodiment of the present invention. Detailed Implementation

[0055] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items. Furthermore, it should be noted that each block in the block diagrams and / or flowcharts herein, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer program instructions. It will be well known to those skilled in the art that implementation in hardware, implementation in software, and implementation using a combination of software and hardware are equivalent.

[0056] In semiconductor device manufacturing, chemical mechanical polishing (CMP) and etching processes are frequently used. CMP is a processing technique that combines chemical etching and mechanical removal, enabling the grinding of the wafer surface film thickness to the target thickness while maintaining wafer surface flatness. Etching uses chemical or physical methods to remove thin films not covered by photoresist to achieve pattern transfer. The device distribution density (D) of a MOM capacitor affects the polishing quality of CMP and the actual effect of etching. Specifically, it affects the surface roughness and polishing rate of CMP, as well as the aspect ratio of etching. Different process effects result in different metal layer thicknesses in the MOM capacitor, which in turn affects the actual measured capacitance value. Existing MOM capacitor models (i.e., older models) do not consider the capacitance value variation caused by the device distribution density (D) of the MOM capacitor, leading to decreased fitting accuracy.

[0057] Based on this, the present invention provides a MOM capacitor model, its modeling method, system, and readable storage medium scheme. It introduces device distribution density to correct the MOM capacitor model, thus not only eliminating the influence of process variations on the capacitance value of the MOM capacitor itself, but also ensuring fitting accuracy in small-size applications, making the established MOM capacitor model more consistent with actual physical laws. Therefore, when designing integrated circuits, the MOM capacitor model of this embodiment can be used to extract MOM capacitor model parameters from the integrated circuit, establish a model library file, and thus provide integrated circuit designers with a model that accurately characterizes the properties of MOM capacitors, enabling designers to design circuits suitable for the current process node based on this model.

[0058] The following is in conjunction with the appendix Figures 1 to 6 The technical solution of the present invention will be described in detail with reference to specific embodiments.

[0059] Please refer to Figures 1 to 3B This invention provides a modeling method for a MOM capacitor model, which includes the following steps:

[0060] S0 (Testkey design) involves designing multiple MOM capacitors with different device distribution densities D to form the required test key structure.

[0061] S1(Test), obtain the capacitance value data corresponding to the test structure;

[0062] S2 (Model building or Model fitting) establishes the basic model of the MOM capacitor (i.e., the basic MOM capacitor model) and creates expressions for each correction function in the MOM capacitor model. The MOM capacitor model includes C = f(Geo) * f(V) * f(T) * f(D).

[0063] Where C is the corrected capacitance value of the MOM capacitor, f(Geo) is a correction function for the geometric parameters of the MOM capacitor, such as length and figure, representing the influence of the geometric parameters of the MOM capacitor on its capacitance value, f(T) is a correction function for temperature T, representing the influence of temperature on the capacitance value of the MOM capacitor, f(V) is a correction function for voltage V, representing the influence of voltage (or "bias") on the capacitance value of the MOM capacitor, and f(D) is a correction function for the device distribution density D of the MOM capacitor, representing the influence of device distribution density D on the capacitance value of the MOM capacitor.

[0064] S3 (Data vs Model): Using the capacitance data, curve fitting is performed to obtain the parameter coefficients in the expressions of each of the correction functions, thereby obtaining the MOM capacitance model with the expressions and the parameter coefficients.

[0065] Optionally, the modeling method of the MOM capacitor model in this embodiment further includes step S4 (QA) after step S3, to perform model verification on the MOM capacitor model.

[0066] In step S0, each MOM capacitor in the test structure can be designed according to any suitable design method. The formula for calculating the device distribution density D of each MOM capacitor is as follows:

[0067]

[0068] Among them, area total The area represents the total area of ​​the device region. total Metal The total area occupied by the metal layer of the MOM capacitor within the total area of ​​the device region.

[0069] It is worth noting that Chemical Mechanical Polishing (CMP) is a process that uses chemical etching combined with mechanical grinding to planarize the surface of a wafer. The CMP grinding rate is related to the material hardness; therefore, the device distribution density on the wafer surface affects the CMP grinding quality. The metal used in MOM capacitors is generally significantly less hard than the dielectric material. Higher hardness materials result in slower CMP grinding rates. Furthermore, the higher the device distribution density (D) of the MOM capacitor, the higher the metal content, the deeper the CMP grinding, the smaller the actual metal thickness of the MOM capacitor, the larger the spacing between different metal layers, and the lower the capacitance between the metal layers. Therefore, the rule that the capacitance of a MOM capacitor monotonically decreases with increasing device distribution density (D) can be used to design test structures.

[0070] In one example, please refer to Figure 2 and Figure 3A , Figure 3BThe MOM capacitor element MOM0 is constructed using a metal interdigitation structure. Multiple MOM capacitors C1, C2, C3, ... are designed using MOM capacitor elements MOM0 with increasing device distribution density to form the desired test structure or a portion thereof. In this test structure, the MOM capacitors with multiple MOM capacitor elements MOM0 are arranged at equal intervals. The higher the device distribution density D of these MOM capacitors, the more MOM capacitor elements MOM0 are contained within a region of the same device area, and the smaller the spacing between the internal MOM capacitor elements MOM0.

[0071] Please continue to refer to the following: Figure 3A , Figure 3B A MOM capacitor element MOM0 may comprise n identical MOM capacitors formed from metal layers M1 to Mn. Each MOM capacitor layer includes two intercalating electrodes F1 and F2 formed from the same metal layer. The intercalation linewidth of intercalation electrodes F1 and F2 is W, and the intercalation depth of intercalation electrodes F1 and F2 is the length L of the MOM capacitor element MOM0. The spacing between the intercalation electrodes F1 and F2 is Wspace. The intercalation index (finger) of each MOM capacitor layer is the total number of intercalation electrodes F1 and F2. The total number of intercalation fingers of the MOM capacitor element MOM0 is the sum of the intercalation indexes of all MOM capacitor layers. The intercalation index of each MOM capacitor is the sum of the total number of intercalation fingers of all MOM capacitor elements MOM0 within the device region of that MOM capacitor.

[0072] In this example, the total area occupied by the metal layer of MOM capacitor element MOM0 is area0, and the area of ​​MOM capacitor C1 is... total Metal =area0, the device distribution density D of C1 is area0 / area total ;area of ​​MOM capacitor C2 total Metal =4*area0, the device distribution density D of C1 = 4*area0 / area total ;area of ​​MOM capacitor C3 total Metal =9*area0, the device distribution density D of C1 =9*area0 / area total And so on.

[0073] In other examples, MOM capacitors with different device area sizes and numbers can be used to design multiple MOM capacitors with different device distribution densities D, thereby forming the required test structure or part of the required test structure.

[0074] In one example, step S0 is the process of completing the layout design of the test structure and fully validating the layout design, which may include the following stages:

[0075] 1. Layout: Plan the layout (or types) of the functional units such as the test structure;

[0076] 2. Routing: Internal routing connects the functional units such as the test structure and generates layout data (which is a GDSII file);

[0077] 3. Verification: Based on the layout data, the test structure undergoes a series of verifications, including design rule checking (DRC), layout verification (LVS), and electrical rule checking (ERC), to ensure the accuracy and manufacturability of the layout data. Design rule checking examines the geometry of the test structure's layout (including linewidth, line length, spacing, area, stack-up, and device density D) to verify that the design meets manufacturing process requirements and ensures that all design elements conform to the manufacturer's specified dimensions and spacing rules to avoid potential manufacturing problems. Layout verification compares the netlist of the original circuit diagram with the netlist of the circuit diagram extracted from the layout to ensure consistency and prevent design errors or deviations. Electrical rule checking checks for the presence of circuits, short circuits, etc.

[0078] In this example, further in step S1, the test structure designed in the final output of step S0 can be simulated and tested using a corresponding process processing model to obtain the capacitance value data corresponding to the test structure. This process processing model can simulate the actual manufacturing process (including mask fabrication, deposition, photolithography, etching, chemical mechanical polishing, etc.) of fabricating a series of test structures (i.e., MOM capacitors with different sizes and device distribution densities D) on a wafer, and provide detailed simulation results for further simulation testing of the MOM capacitors formed by the process simulation.

[0079] In another example, in step S1, the capacitance value data corresponding to the test structure designed in step S0 is obtained by sequentially performing a Tape out (tape-out, pilot production) step and a wafer test step. The Tape out step is used to transform the final layout data file provided in step S1 into an actual wafer product through a series of process steps, much like an assembly line. The wafer test step is used to test the wafer product produced in the Tape out step, thereby obtaining the capacitance value data corresponding to the test structure designed in step S1.

[0080] In other words, the capacitance data in step S1 can be obtained through simulation testing or through actual product testing. Regardless of the method, it is necessary to test and organize the electrical data under different temperatures T, different voltages V, and different device densities to obtain the required capacitance data.

[0081] It should be noted that in the above simulation test or actual wafer test process, the basic test parameters can remain unchanged. However, due to the difference in device distribution density D of MOM capacitors, the spacing of the test pads may change. Therefore, the automation script needs to be updated to ensure that the test proceeds smoothly.

[0082] In other embodiments of the present invention, the test structure design in step S0 may be omitted, and the required capacitance value data may be obtained directly from the relevant electrical data of MOM capacitors in different products with different actual sizes and device distribution densities. These capacitance value data may include the capacitance values ​​of MOM capacitors of different products in terms of size, voltage, temperature and device distribution density.

[0083] In step S2, a basic MOM capacitance model is established, and expressions for each correction function in the MOM capacitance model are created. The MOM capacitance model includes:

[0084] C = f(Geo) * f(V) * f(T) * f(D).

[0085] Where C is the corrected capacitance value of the MOM capacitor, f(Geo) is a correction function for the geometric parameters of the MOM capacitor, such as L, W, Wspace, and finger, used to correct the influence of geometric parameters on the capacitance value C of the MOM capacitor; f(T) is a correction function for temperature T, used to correct the influence of temperature T on the capacitance value C of the MOM capacitor; f(V) is a correction function for voltage V, used to correct the influence of voltage V on the capacitance value C of the MOM capacitor; f(D) is a correction function for device distribution density D, used to correct the influence of device distribution density D on the capacitance value C of the MOM capacitor. Therefore, appropriate function expressions are selected for each correction function f(Geo), f(T), f(V), and f(D) according to the actual design of the MOM capacitor (such as device density and size differences). The expressions of these correction functions f(Geo), f(T), f(V), and f(D) can be polynomial functions about their variables, which are mathematical expressions composed of their variables, parameter coefficients (i.e., constants), and algebraic operation symbols (addition, subtraction, multiplication, and exponentiation). That is, the expressions for the correction functions f(Geo), f(T), f(V), and f(D) can each contain one or more terms, where each term is the product of a parameter coefficient and a variable or a power of a variable. The degree of the highest term in the expression of each correction function determines the degree of the polynomial of that correction function. Furthermore, the expression for each correction function may differ due to variations in the technological process; therefore, the technical solution of this invention is not limited to only one function expression for each correction function.

[0086] Please refer to Figure 4 and Figure 5 In step S3, corresponding capacitance values ​​can be selected from the capacitance value data obtained in step S1 to perform curve fitting on the expressions of each correction function in the MOM capacitance model, thereby obtaining the fitted values ​​of the parameter coefficients in each correction function. This yields an MOM capacitance model that meets the fitting accuracy requirements.

[0087] It should also be noted that in step S3, if any fitting fails (i.e., the difference between the fitted curve and the selected capacitance value data is too large, or the selected capacitance value data deviates significantly from the fitted curve), the process can return to step S1 and select other capacitance value data to continue iterative fitting, or return to step S2 and modify the expression of at least one correction function in the MOM capacitance model, thereby ensuring that a curve with a small difference from the capacitance value data can be fitted in the end.

[0088] In step S4, the MOM capacitor model obtained in step S3 is validated. The model validation in step S4 verifies the entire MOM capacitor model, which may include verifying whether there are jump points or abrupt changes in all dimensions of the entire MOM capacitor model at the corresponding process node, whether the model is smooth, and whether the trend of changes in the electrical properties of the entire MOM capacitor model conforms to physical meaning, among other aspects. Through the model validation in step S4, the rationality, accuracy, and reliability of the entire MOM capacitor model, including the MOM capacitor model of this invention, can be ensured.

[0089] For example, in step S4, the rationality of the CD curve change trend corresponding to the MOM capacitor model obtained in step S3 can be confirmed according to the model validation rule (QA rule). If the CD curve is found to be inconsistent with the change trend of the capacitance value data obtained in step S1, it indicates that the MOM capacitor model obtained in step S3 has failed model validation. The process can then return to step S2 to modify the expression of at least one correction function in the MOM capacitor model, or return to step S3 to iteratively fit the parameter coefficients in the expression of the corresponding correction function in the MOM capacitor model until the MOM capacitor model output in step S3 passes model validation. If the MOM capacitor model output in step S3 passes model validation, it can be released for subsequent use.

[0090] In step S4, considering that the higher the device distribution density D, the deeper the chemical mechanical polishing (CMP) process, the smaller the cross-sectional area of ​​the MOM capacitor, and the lower the capacitance value, a model verification rule can be added that the capacitance value of the MOM capacitor decreases monotonically as the device distribution density increases.

[0091] For example, in step S4, the MOM capacitance model obtained in step S3 can also be used to calculate the capacitance value of each MOM capacitor in the test results, and compare it with the corresponding capacitance value data to determine the error between the two. If all the errors corresponding to the test structure are distributed within the required range, then the MOM capacitance model passes model verification. The error between the calculated value 'model' obtained from the MOM capacitance model in step S3 and the corresponding measured value 'measure' (i.e., the capacitance value obtained in step S1) is calculated using the formula: error = (model / measure-1) * 100%.

[0092] In one example, the MOM capacitor model established in step S2 is C = f(Geo) * f(V) * f(T) * f(D), and we have:

[0093] (1)f(Geo)=a*L*finger+b*L+c*finger+d;

[0094] (2) f(V)=e+f*V+g*V 2 ;

[0095] (3) f(T) = h + j*(T-T0);

[0096] (4) f(D) = k + m * D + n * D 2 ;

[0097] Where L is the insertion length of the corresponding insertion electrode in the MOM capacitor, W is the insertion line width of the insertion electrode, finger is the insertion index of the insertion electrode, a to h, j, k, m, and n are all parameter coefficients, and T0 is room temperature (e.g., 25°C).

[0098] In step S3, curve fitting can be performed using the same device distribution density D under 0V bias and 25℃ conditions, and the capacitance values ​​of MOM capacitors of different sizes, to obtain the fitted values ​​of the parameter coefficients a to d in the correction function f(Geo)=a*L*finger+b*L+c*finger+d.

[0099] In step S3, capacitance data of MOM capacitors of the same size, with the same device distribution density D, but different bias voltages V and temperatures of 25°C can be selected. Using the capacitance value under 0V bias and 25°C as the standard, these selected capacitance data are normalized and curve fitted (i.e., a C-V curve is plotted and polynomial fitting is performed on the curve) to obtain the correction function f(V) = e + f*V + g*V. 2 The fitted values ​​of the parameter coefficients e to f in the model.

[0100] In step S3, capacitance data of MOM capacitors of the same size, same device distribution density D, 0V bias, and different temperature T can be selected. Using the capacitance value under 0V bias and 25℃ (i.e., T0) conditions as the standard, these selected capacitance data are normalized and curve fitting is performed (i.e., C-T curve is plotted and polynomial fitting is performed on the curve) to obtain the fitted values ​​of the parameter coefficients h and j in the correction function f(T)=h+j*(T-T0).

[0101] In step S3, capacitance data of MOM devices with the same temperature, voltage, and size but different device distribution densities D can be used to perform curve fitting (i.e., perform...). Figure 5 The CD curve shown is used to perform polynomial fitting on the curve, which yields the correction function f(D) = k + m*D + n*D. 2 The fitted values ​​of the parameter coefficients k, m, and n in the model. For example, k is 1.

[0102] It should be noted that the function expressions of the correction functions f(Geo), f(T), f(V), and f(D) in the above MOM capacitor model are merely illustrative examples and do not imply that the function expressions of f(Geo), f(T), f(V), and f(D) in the MOM capacitor model of this invention are limited to the above forms. In other embodiments of this invention, at least one of the correction functions f(Geo), f(T), f(V), and f(D) in the MOM capacitor model can adopt the corresponding function expression in the above example. Alternatively, the function expression of at least one of the correction functions f(Geo), f(T), f(V), and f(D) in the MOM capacitor model may be adaptively modified to a different form than the function expression corresponding to the above example if step S3 and / or step S4 fails.

[0103] In one application example, using Figure 2 and Figure 3A , Figure 3B The same test structure was designed as shown. In this test structure, the MOM capacitor element MOM0 has an L of 120 μm, W of 0.24 μm, and Wspace of 0.24 μm. The total number of figures is 20 (i.e., the interpolation exponents of F1 and F2 are both 10). The distribution densities of the MOM capacitors in this test structure are 25%, 33%, 50%, and 66% respectively. Please refer to [reference needed]. Figure 4 and Figure 5 Plot the C-D curve, and the specific results are as follows: Figure 5 As shown, the existing old MOM capacitor model (model_old) does not consider the influence of the device distribution density D in the test structure on the capacitance value C of each MOM capacitor. The calculated capacitance value obtained is 103.396pF. Further calculations are made to determine the error (error_old) between these calculated capacitance values ​​and the corresponding capacitance data. It can be seen that when D is 50%, the existing old MOM capacitor model (model_old) provides the best fit, with an error of 0%. However, it cannot be reconciled with capacitance values ​​under other D conditions, and the maximum error of the calculated capacitance value can reach 2%, indicating very poor fitting accuracy.

[0104] The MOM capacitor model (model_new) obtained by the modeling method in this embodiment takes into account the influence of the device distribution density D in the test structure on the capacitance value C of each MOM capacitor. Therefore, the calculated capacitance value is no longer the same, and the error (error_new) between each calculated capacitance value and the corresponding capacitance value data is within 1%, which significantly improves the fitting accuracy.

[0105] In addition, please refer to Figure 5The trend of the CD fitting curve obtained by the modeling method of this embodiment is consistent with the trend of the capacitance value data with respect to D, and each capacitance value data is close to the CD fitting curve.

[0106] In summary, the modeling method of the MOM capacitor model of the present invention considers the influence of device distribution density on the capacitance value of MOM capacitors. When acquiring capacitance value data, the capacitance values ​​of MOM capacitors with different device distribution densities are obtained. Furthermore, in the model fitting stage (i.e., step S2), a correction function f(D) related to the device distribution density D is introduced, which can correct the MOM capacitor model and thus improve the fitting accuracy of the small-size MOM capacitor model.

[0107] Based on the same inventive concept, please refer to Figure 6 An embodiment of the present invention also provides a modeling system for a MOM capacitor model, which can implement the modeling method of the MOM capacitor model of the present invention. The modeling system includes a capacitor design unit 10, a data acquisition unit 11, a modeling unit 12, a parameter fitting unit 13, and a model verification unit 14.

[0108] The capacitor design unit 10 is used to implement step S0 in the modeling method of the MOM capacitor model of the present invention, that is, the capacitor design unit 10 is configured to design multiple MOM capacitors with different device distribution densities to form the required test structure.

[0109] The data acquisition unit 11 is used to implement step S1 in the modeling method of the MOM capacitor model of the present invention, that is, the data acquisition unit 11 is configured to acquire the capacitance value data corresponding to the test structure designed by the capacitor design unit 10.

[0110] The modeling unit 12 is used to implement step S2 in the modeling method of the MOM capacitor model of the present invention, that is, the modeling unit 12 is configured to establish a basic MOM capacitor model, the basic MOM capacitor model including C = f(Geo)*f(V)*f(T)*f(D).

[0111] Where C is the corrected capacitance value of the MOM capacitor, f(Geo) is a correction function for the geometric parameters of the MOM capacitor, such as length and figure, representing the influence of the geometric parameters of the MOM capacitor on its capacitance value, f(T) is a correction function for temperature T, representing the influence of temperature on the capacitance value of the MOM capacitor, f(V) is a correction function for voltage V, representing the influence of voltage (or "bias") on the capacitance value of the MOM capacitor, and f(D) is a correction function for the device distribution density D of the MOM capacitor, representing the influence of device distribution density D on the capacitance value of the MOM capacitor.

[0112] The parameter fitting unit 13 is used to implement step S3 in the modeling method of the MOM capacitor model of the present invention, that is, it is configured to use the capacitance value data of the data acquisition unit 11 to perform curve fitting to obtain the expression of each correction function in the MOM capacitor model established by the modeling unit 12 and the parameter coefficients in the expression, and then obtain the MOM capacitor model with the expression and parameter coefficients.

[0113] The correction function expression obtained by the modeling unit 12 or the parameter fitting unit 13 includes at least one of the following (1) to (4):

[0114] (1)f(Geo)=a*L*finger+b*L+c*finger+d;

[0115] (2) f(V)=e+f*V+g*V 2 ;

[0116] (3) f(T) = h + j*(T-T0);

[0117] (4) f(D) = k + m * D + n * D 2 ;

[0118] Where L is the insertion length of the corresponding insertion electrode in the MOM capacitor, W is the insertion line width of the insertion electrode, finger is the insertion index of the insertion electrode, a to h, j, k, m, and n are all parameter coefficients, and T0 is room temperature (e.g., 25°C).

[0119] Alternatively, please refer to Figure 2 and Figure 3A , Figure 3B The capacitor design unit 10 uses the same MOM capacitor element MOM0 and designs multiple MOM capacitors in an increasing manner of device distribution density, thereby forming at least part of the test structure.

[0120] Optionally, the modeling system for the MOM capacitor model in this embodiment further includes a model verification unit 14, which is used to implement step S4 in the modeling method of the MOM capacitor model of the present invention. That is, the model verification unit 14 is configured to perform model verification on the MOM capacitor model output by the parameter fitting unit 13. When the MOM capacitor model fails the verification of the model verification unit 14, the parameter fitting unit 13 performs parameter iterative fitting on the MOM capacitor model, or the modeling unit 12 modifies the function expression of at least one of the correction functions f(Geo), f(T), f(V), and f(D) in the MOM capacitor model it constructs.

[0121] It is worth noting that the verification of the MOM capacitor model by the model verification unit 14 may also include: verifying whether there are jump points or abrupt changes in all dimensions of the entire MOM capacitor model at the corresponding process node, whether it is smooth, and whether the trend of changes in the electrical properties of the entire MOM capacitor model conforms to the physical meaning, etc. Through the model verification by the model verification unit 14, the rationality, accuracy, and reliability of the MOM capacitor model of the present invention can be ensured.

[0122] It should be understood that the capacitor design unit 10, data acquisition unit 11, modeling unit 12, parameter fitting unit 13 and model verification unit 14 in the modeling system of the MOM capacitor model of the present invention can be combined into one device, or any one of the units can be split into multiple devices, or at least part of the function of one unit can be combined with at least part of the function of another unit and implemented in one device.

[0123] Furthermore, at least one of the capacitor design unit 10, data acquisition unit 11, modeling unit 12, parameter fitting unit 13, and model verification unit 14 in the modeling system of the MOM capacitor model in this embodiment can be at least partially implemented as a hardware circuit, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable way of integrating or packaging the circuit, or in a suitable combination of software, hardware, and firmware implementation methods.

[0124] Alternatively, at least one of the capacitor design unit 10, data acquisition unit 11, modeling unit 12, parameter fitting unit 13, and model verification unit 14 in the modeling system of the MOM capacitor model in this embodiment can be at least partially implemented as a computer program module. When the program is run by a computer, it can perform the functions of the corresponding module and can be upgraded.

[0125] In other embodiments of the present invention, the capacitor design unit 10 may be omitted, and the data acquisition unit 11 may acquire the capacitance value data of MOM capacitors with different device densities, different sizes and other characteristics required from the actual product.

[0126] In summary, the modeling method and system for the MOM capacitor model of this invention consider the influence of device distribution density D in the constructed MOM capacitor model, introduce a correction function f(D) for device distribution density D, and correct the MOM capacitor model to further correct the influence of device distribution density D on the MOM capacitor. The corrected MOM capacitor model is more complete and accurate, more in line with the laws of reality, and improves the fitting accuracy of the MOM capacitor model. This ensures the accuracy and reliability of subsequent integrated circuit design and simulation, helps engineers optimize integrated circuit design and processes, and improves the design efficiency and actual production efficiency of integrated circuits.

[0127] Based on the same inventive concept, an embodiment of the present invention also provides a MOM capacitor model, which includes C = f(Geo) * f(V) * f(T) * f(D);

[0128] Where C is the corrected capacitance value of the MOM capacitor, f(Geo) is a correction function for the geometric parameters of the MOM capacitor, such as length and figure, representing the influence of the geometric parameters of the MOM capacitor on its capacitance value, f(T) is a correction function for temperature T, representing the influence of temperature on the capacitance value of the MOM capacitor, f(V) is a correction function for voltage V, representing the influence of voltage (or "bias") on the capacitance value of the MOM capacitor, and f(D) is a correction function for the device distribution density D of the MOM capacitor, representing the influence of device distribution density D on the capacitance value of the MOM capacitor.

[0129] Optionally, the MOM capacitance model further includes at least one of the following items (1) to (4):

[0130] (1)f(Geo)=a*L*finger+b*L+c*finger+d;

[0131] (2) f(V)=e+f*V+g*V 2 ;

[0132] (3) f(T) = h + j*(T-T0);

[0133] (4) f(D) = k + m * D + n * D 2 ;

[0134] Where L is the insertion length of the corresponding insertion electrode in the MOM capacitor, W is the insertion line width of the insertion electrode, finger is the insertion index of the insertion electrode, a to h, j, k, m, and n are all parameter coefficients, and T0 is room temperature (e.g., 25°C).

[0135] Based on the same inventive concept, the present invention also provides a readable storage medium for storing a computer program or instructions, which, when executed by a processor, implement the modeling method for the MOM capacitor model as described in the present invention.

[0136] The readable storage medium can be a tangible device capable of holding and storing instructions used by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of the readable storage medium (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer program described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives the computer program from the network and forwards it for storage in a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk, C++, etc., and conventional procedural programming languages ​​such as "C" or similar languages. The computer program can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.

[0137] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.

[0138] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.

[0139] In summary, the MOM capacitor model, its modeling method, modeling system, and readable storage medium of this invention consider the influence of device distribution density D in the constructed MOM capacitor model, introduce a correction function f(D) for device distribution density D, and modify the MOM capacitor model to further correct the influence of device distribution density D on the MOM capacitor. The modified MOM capacitor model is more complete and accurate, more in line with real physical laws, and improves the fitting accuracy of the MOM capacitor model. This ensures the accuracy and reliability of subsequent integrated circuit design and simulation, helps engineers optimize integrated circuit design and processes, and improves the design efficiency and actual production efficiency of integrated circuits.

[0140] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A MOM capacitor model, characterized in that, The MOM capacitance model includes: C = f(Geo) * f(V) * f(T) * f(D); Where C is the corrected capacitance value of the MOM capacitor, f(Geo) is a correction function for the geometric parameters of the MOM capacitor, f(T) is a correction function for temperature T, f(V) is a correction function for voltage V, and f(D) is a correction function for the device distribution density D of the MOM capacitor.

2. The MOM capacitor model as described in claim 1, characterized in that, Also includes: (1) The MOM capacitor includes at least one MOM capacitor element, the MOM capacitor element includes at least one layer of MOM capacitor, the MOM capacitor includes two interdigitated electrodes formed of the same layer of metal and intersecting with each other; and / or, (2) The formula for calculating the device distribution density D of the MOM capacitor is: Among them, area total The area represents the total area of ​​the device region. totalMetal The total area occupied by the metal layer of the MOM capacitor within the total area of ​​the device region.

3. The MOM capacitor model as described in claim 1 or 2, characterized in that, It also includes at least one of the following (1) to (4): (1) f(Geo)=a*L*finger+b*L+c*finger+d, where L is the insertion length of the insertion electrode in the MOM capacitor, W is the insertion line width of the insertion electrode, finger is the insertion index of the insertion electrode, and a, b, c, and d are all parameter coefficients. (2) f(V)=e+f*V+g*V 2 Where e, f, and g are all parameter coefficients; (3) f(T)=h+j*(T-T0), where h and j are parameter coefficients, and T0 is room temperature; (4) f(D) = k + m * D + n * D 2 , where k, m, and n are all parameter coefficients.

4. A modeling method for a MOM capacitor model, characterized in that, Includes the following steps: S1, Obtain the required capacitance value data, which includes the capacitance values ​​of MOM capacitors with different device distribution densities; S2, establish the MOM capacitor model as described in any one of claims 1-3, and create expressions for each correction function in the MOM capacitor model; S3, use the capacitance value data to perform curve fitting to obtain the parameter coefficients in the expressions of each of the correction functions, and then obtain the MOM capacitance model with the expressions and the parameter coefficients.

5. The modeling method as described in claim 4, characterized in that, Before step S1, there is also step S0: designing multiple MOM capacitors with different device distribution densities to form a test structure; in step S1, the capacitance value data corresponding to the test structure is obtained; The test structure includes at least one of the following (1) to (3): (1) The device distribution density of the MOM capacitor in the test structure increases progressively; (2) Each of the MOM capacitors in the test structure includes at least one MOM capacitor element, the MOM capacitor element includes at least one layer of MOM capacitor, and the MOM capacitor includes two interdigitated electrodes formed of the same layer of metal and intersecting each other. (3) The formula for calculating the device distribution density D of each MOM capacitor in the test structure is as follows: Among them, area total The area represents the total area of ​​the device region of the MOM capacitor. totalMetal The total area occupied by the metal layer within the total area of ​​the device region of the MOM capacitor.

6. The modeling method as described in claim 5, characterized in that, In step S1, the test structure is fabricated on a wafer and wafer testing is performed to obtain the capacitance value data corresponding to the test structure, and / or the test structure is simulated and tested using a corresponding process processing model to obtain the capacitance value data corresponding to the test structure.

7. The modeling method as described in claim 4, characterized in that, In step S3, if the error of the curve fitting result is too large, return to step S1 to obtain new capacitance value data for curve fitting. And / or, after step S3, step S4 is further included: performing model verification on the MOM capacitor model; if the MOM capacitor model fails model verification, then returning to step S2 to modify the expression of at least one of the correction functions in the MOM capacitor model, or returning to step S3 to iteratively fit the parameter coefficients in the expression of at least one of the correction functions in the MOM capacitor model until the MOM capacitor model passes verification.

8. A modeling system for a MOM capacitance model, characterized in that, include: A data acquisition unit is configured to acquire the required capacitance value data, which includes the capacitance values ​​of MOM capacitors with different device distribution densities. A modeling unit configured to build a MOM capacitor model as described in any one of claims 1-3, and to create expressions for the various correction functions in the MOM capacitor model; A parameter fitting unit is configured to perform curve fitting using the capacitance value data to obtain the parameter coefficients in the expressions of each of the correction functions, thereby obtaining an MOM capacitance model having the expressions and the parameter coefficients.

9. The modeling system for the MOM capacitor model as described in claim 8, characterized in that, It also includes at least one of the following (1) to (4): (1) The modeling system also includes a capacitor design unit, which is configured to design multiple MOM capacitors with different device distribution densities to form a test structure; (2) The data acquisition unit obtains the capacitance value data corresponding to the test structure by acquiring the wafer test data of the wafer where the test structure is located, and / or, the data acquisition unit performs process simulation processing and simulation testing on the test structure through the corresponding process processing model to obtain the capacitance value data corresponding to the test structure. (3) When the difference between the curve fitting result and the capacitance value data is too large, the parameter fitting unit causes the data acquisition unit to provide new capacitance value data for curve fitting. (4) The modeling system further includes a model verification unit, which is configured to perform model verification on the MOM capacitor model; when the MOM capacitor model fails the verification by the model verification unit, the parameter fitting unit iteratively fits the parameter coefficients in the expression of at least one of the correction functions in the MOM capacitor model, or the modeling unit modifies the expression of at least one of the correction functions in the MOM capacitor model.

10. A readable storage medium, characterized in that, The readable storage medium is used to store a computer program or instructions, which, when executed by a processor, implement the modeling method of the MOM capacitor model as described in any one of claims 4-7.

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