Design method of circuit board and electronic device

Abstract

The application discloses a design method of a circuit board and electronic equipment, and relates to the technical field of circuit boards. The method comprises the following steps: correcting the initial step boundary of the step region and the non-step region based on the process spacing parameter of the circuit board, determining the final step boundary, and combining the process spacing parameter to construct the layout constraint region; correcting the initial wiring topology data to obtain the wiring topology data based on the layering parameter, the first region feature and the second region feature of the circuit board; labeling the non-electric connection information based on the final step boundary, the layout constraint region, the first region feature and the second region feature, obtaining the target data, and generating the design data. The technical problems that the step golden finger lacks automatic design means and layout specification, is easy to cause packaging anomaly, impedance mismatch and signal degradation, and process difference causes parameter confusion and high rework rate are solved. The technical effects of partition configuration difference wiring rules, unified specification, signal performance guarantee and design failure and rework reduction are achieved.

Description

Technical Field

[0001] This application relates to the field of circuit board technology, and more particularly to a circuit board design method and an electronic device. Background Technology

[0002] In related technologies, stepped gold finger circuit boards can be fabricated using a dual-substrate lamination process or a substrate slotting and embedding process. The dual-substrate lamination process involves prefabricating multiple independent substrates, precisely aligning them after circuit processing, and then laminating them together using a prepreg to form a complete circuit board, utilizing the thickness differences between the different substrates to construct the stepped areas. The substrate slotting and embedding process involves machining grooves into the main substrate, embedding prefabricated sub-substrates into these grooves, and combining them to form a circuit board with a stepped structure.

[0003] However, the relevant technologies not only lack automated design methods for stepped gold fingers, but also lack corresponding standardized layout and routing specifications. This can easily lead to defects such as unreasonable stepped contour spacing causing a decrease in processing yield, non-standard gold finger packaging causing poor contact, via design causing impedance mismatch, and improper routing reference layer setting degrading signal integrity. Furthermore, the process capabilities of different printed circuit board manufacturers vary, and there is no unified design parameter reference, resulting in an increased design rework rate, which urgently needs improvement. Summary of the Invention

[0004] This application provides a circuit board design method and electronic device to at least solve the following problems in the related technology: not only is there a lack of automated design methods for stepped gold fingers, but there is also a lack of corresponding standardized layout and routing specifications; it is easy to have defects such as unreasonable stepped contour spacing leading to a decrease in processing yield, non-standard gold finger packaging causing poor contact, via design causing impedance mismatch, improper setting of trace reference layer degrading signal integrity, and the process capabilities of different printed circuit board manufacturers vary, and there is no unified design parameter reference, which leads to an increase in design rework rate.

[0005] This application provides a circuit board design method, comprising: correcting the initial step boundary line of the stepped and non-stepped regions of the circuit board based on the process spacing parameters of the circuit board to determine the final step boundary line between the stepped and non-stepped regions; constructing a layout constraint region of the circuit board based on the final step boundary line and the process spacing parameters; correcting the initial wiring topology data of the circuit board based on the stack-up parameters of the circuit board, a first region feature of the stepped region and a second region feature of the non-stepped region to obtain wiring topology data; marking non-electrical connection information based on the final step boundary line, the layout constraint region, the first region feature and the second region feature to obtain target data of the circuit board; and generating design data of the circuit board based on the target data, the layout constraint region and the wiring topology data.

[0006] This application also provides a circuit board design apparatus, comprising: a construction module, configured to correct the initial step boundary line of the stepped region and the non-stepped region of the circuit board based on the process spacing parameters of the circuit board, to determine the final step boundary line of the stepped region and the non-stepped region, and to construct the layout constraint region of the circuit board based on the final step boundary line and the process spacing parameters; a correction module, configured to correct the initial wiring topology data of the circuit board based on the stack-up parameters of the circuit board, a first region feature of the stepped region and a second region feature of the non-stepped region, to obtain wiring topology data; and a generation module, configured to annotate non-electrical connection information based on the final step boundary line, the layout constraint region, the first region feature and the second region feature, to obtain target data of the circuit board, and to generate design data of the circuit board based on the target data, the layout constraint region and the wiring topology data.

[0007] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for executing the computer program to implement the steps of any of the circuit board design methods described above.

[0008] This application also provides a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of any of the circuit board design methods described above.

[0009] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the circuit board design methods described above.

[0010] This application allows for the correction of initial step boundaries between stepped and non-stepped regions of a circuit board based on its process spacing parameters, thereby determining the final step boundaries. It also enables the construction of layout constraint regions using process spacing parameters. Furthermore, based on the circuit board's stack-up parameters, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region, the initial wiring topology data is corrected to obtain wiring topology data. Finally, based on the final step boundaries, layout constraint regions, and the first and second region characteristics, non-electrical connection information is annotated to obtain target data. Based on the target data, layout constraint regions, and wiring topology data, circuit board design data is generated. Therefore, this application addresses the technical problems of stepped gold finger printed circuit boards, such as the lack of automated design methods and standardized layout and routing specifications, leading to unreasonable final step boundary spacing, poor gold finger packaging, impedance mismatch, signal integrity degradation, lack of unified design parameter references, and high design rework rates. It achieves differentiated routing rules for different regions, generates design data by combining standardized non-electrical connection information, realizes automated layout design of stepped gold finger circuit boards, stabilizes signal performance, unifies design specifications, and reduces design errors and rework. Attached Figure Description

[0011] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0012] Figure 1 A flowchart illustrating a circuit board design method provided in this application embodiment; Figure 2 A block diagram illustrating a spacing design module provided in one embodiment of this application; Figure 3 A block diagram of a gold finger printed circuit board provided in one embodiment of this application; Figure 4 A schematic diagram of a block layout constraint area for a gold finger printed circuit board provided in one embodiment of this application; Figure 5 A schematic diagram of a bounding area for a surface mount component provided in one embodiment of this application; Figure 6 A block diagram illustrating a wiring design module provided in one embodiment of this application; Figure 7 A schematic diagram of the gold finger printed circuit board stack-up structure and partitioned back drilling provided in one embodiment of this application; Figure 8 This is a block diagram of a circuit board design apparatus provided according to an embodiment of this application.

[0013] Figure label: Among them, 10 is the design device for the circuit board; 100 is the building module; 200 is the correction module; and 300 is the generation module. Detailed Implementation

[0014] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0015] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0016] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] The embodiments of this application provide a circuit board design method, and the method is described in detail in conjunction with the execution flow of the circuit board design method.

[0018] Specifically, Figure 1 This is a flowchart of a circuit board design method provided according to an embodiment of this application.

[0019] like Figure 1 As shown, the design method for this circuit board includes the following steps: In step S101, the initial step boundary line between the stepped and non-stepped areas of the circuit board is corrected based on the process spacing parameters of the circuit board to determine the final step boundary line between the stepped and non-stepped areas. Based on the final step boundary line and the process spacing parameters, the layout constraint area of ​​the circuit board is constructed.

[0020] Understandably, in conventional project designs in related technologies, the thickness of the stepped area and the non-stepped area remains consistent. Constrained by the thickness of the gold finger area, the number of trace layers cannot be expanded; the more trace layers, the greater the required substrate thickness, making it difficult for related solutions to meet the high-density, high-speed design requirements of storage products. Therefore, this application proposes maintaining the thickness of the stepped area unchanged and only increasing the substrate thickness of the non-stepped areas outside the gold finger area to expand the number of signal trace layers. With the widespread application of stepped gold fingers, which can adapt to various board interconnection scenarios, the rationality of the layout and wiring design of the stepped gold finger printed circuit board directly affects the processing feasibility, signal transmission stability, and component assembly compatibility of the printed circuit board.

[0021] A circuit board can be understood as a printed circuit board, which is a substrate carrier that carries electronic components and provides electrical connections between components.

[0022] Process spacing parameters can be understood as a set of minimum safe distance thresholds defined by the printed circuit board manufacturing process based on the design capabilities of different manufacturers. These parameters may include, but are not limited to, the first target spacing between surface mount components and the final step boundary line, the second target spacing between through-hole components and the final step boundary line, the third target spacing between vias and the final step boundary line, the fourth target spacing between conductive lines and the final step boundary line, and the fifth target spacing between the marking ink area and the final step boundary line. For example, the minimum spacing for different manufacturers includes the spacing between surface mount components and the final step boundary line, the spacing between vias in thicker areas and the final step boundary line, the spacing between vias in thinner areas and the final step boundary line, the spacing between through-hole components (such as DIP (Dual In-line Package) component holes) and the final step boundary line, the spacing between the marking ink area in thinner areas and the final step boundary line, and the spacing between inner and outer layer wiring and the final step boundary line, as shown in Table 1. Table 1 is a design table of different printed circuit board manufacturers' process capabilities according to an embodiment of this application.

[0023] Table 1

[0024] The stepped area can be understood as the area on the circuit board where there is a difference in board thickness and a stepped structure is formed by milling. It can be understood as the gold finger area.

[0025] Non-stepped areas can be understood as the conventional areas of the circuit board where there is no difference in board thickness, the board material thickness is uniform, and no steps are set. That is, the area of ​​the circuit board other than the gold finger area, which adopts the general printed circuit board wiring and layout rules.

[0026] The constraint area is a restricted area generated based on the final step boundary line. Within this area, layout and routing restrictions are imposed on electrical objects such as lines, vias, components, and copper foil (e.g., prohibiting via placement, restricting wiring, etc.). It may include, but is not limited to, constraint areas for surface mount components, constraint areas for through-hole components, constraint areas for interconnect vias, constraint areas for conductive lines, and constraint areas for marking ink areas.

[0027] In some embodiments, the present application can retrieve the process spacing parameters of the circuit board, correct the initial step boundary line of the stepped area and non-stepped area of ​​the circuit board, determine the final step boundary line, and automatically construct the layout constraint area based on the final step boundary line and the process spacing parameters.

[0028] For example, embodiments of this application can be combined with Figure 2 As shown, clicking the spacing design module allows you to import the process capabilities of different PCB manufacturers by clicking "Import Mainstream PCB Manufacturer Design Capabilities" to obtain process spacing parameters. Clicking "Import Graphic Exchange Format, Confirm Step Position" determines the initial step boundary line corresponding to the gold fingers. Based on the initial step boundary line, you can distinguish the step area on the PCB, i.e., the gold finger area, and the other non-step areas on the board. By using "Setting Layout Routing and Via Restriction Areas," you can configure suitable layout routing restriction areas and via prohibition areas on the PCB to determine the corresponding layout constraint areas. If the designer places components, wiring, or vias within the layout constraint areas, an automatic warning prompt will be output to guide the designer to adjust the layout routing design.

[0029] In addition, this application provides a schematic diagram of a stepped gold finger printed circuit board, such as... Figure 3 As shown, the left side is a 2D outline diagram in DXF (Drawing Exchange Format), and the right side is a 3D rendering. The area to the left of the initial stepped boundary line (the boundary line between the gold fingers and the printed circuit board) is the gold finger area, and the area to the right is the thicker area of ​​the printed circuit board, i.e., the non-stepped area. D1 is the distance from the initial stepped boundary line to the upper edge of the gold finger.

[0030] Optionally, in one embodiment of this application, the initial step boundary line between the stepped area and the non-stepped area of ​​the circuit board is corrected based on the process spacing parameters of the circuit board to determine the final step boundary line between the stepped area and the non-stepped area. This includes: extracting the initial spacing between the marking ink area and the initial step boundary line from the process spacing parameters; if the initial spacing meets a preset spacing condition, then the final step boundary line is determined based on the initial spacing; if the initial spacing does not meet the preset spacing condition, then the final step boundary line is determined based on the initial step boundary line.

[0031] It is understood that, in the embodiments of this application, the marking ink graphic area can be understood as the boundary range of the planned arrangement of screen-printed characters, logos, numbers and other ink graphics within the stepped area, which is the permitted area for screen printing layout.

[0032] In some embodiments, the present application can extract the initial spacing between the marking ink area and the initial step boundary line from the process spacing parameters, and determine the final step boundary line based on the initial spacing when the initial spacing meets the preset spacing conditions; otherwise, determine the final step boundary line based on the initial step boundary line. The preset spacing conditions can be set by those skilled in the art according to actual conditions, and the present application does not impose specific limitations.

[0033] For example, the embodiments of this application are combined with Figure 3 As shown, the DXF file is imported according to the agreed format. The DXF file contains the initial step boundary line and D1. Generally, there are at least two printed circuit board (PCB) manufacturers. Based on the names of the PCBs from these two manufacturers, the corresponding E values ​​for different manufacturers are obtained from Table 1 and compared. The largest value is selected and recorded as E1. Further, in this embodiment, the magnitudes of E1 and D1 are compared. If E1 ≤ D1, the initial step boundary line is the final step boundary line, i.e., the boundary line between the thick plate region and the thin plate region. If E1 > D1, the initial step boundary line is moved to the right by a distance of E1 - D1 to determine the final step boundary line.

[0034] This application embodiment compares the initial spacing of the marked ink area relative to the initial step boundary line with the preset spacing conditions, and adaptively determines whether to translate to generate the final step boundary line. It can uniformly and compatiblely meet the different screen printing process constraints of multiple printed circuit board manufacturers, avoid interference in the step position screen printing process, and reduce the rework and production scrap of printed circuit board design caused by mismatch of process spacing from the source.

[0035] Optionally, in one embodiment of this application, constructing a layout constraint region for the circuit board based on the final step boundary line and process spacing parameters includes: determining a target process spacing parameter that meets preset process conditions based on the process spacing parameters; constructing a surface mount component layout constraint region, a through-hole component layout constraint region, an interconnect via layout constraint region, a conductive line layout constraint region, and a marking ink area layout constraint region based on the target process spacing parameter and the final step boundary line; and constructing the layout constraint region based on the surface mount component layout constraint region, through-hole component layout constraint region, interconnect via layout constraint region, conductive line layout constraint region, and marking ink area layout constraint region.

[0036] It is understood that in the embodiments of this application, the surface mount component layout constraint area is bounded by the final step boundary line and is a limitation range generated based on the target spacing; it is used to control the layout, restrict or prohibit the placement of surface mount components, and avoid step stress causing solder joint cracking and milling damage to components.

[0037] The constraint area for insert components is a restricted area generated based on the target spacing. Close placement of insert components is prohibited to prevent poor soldering of insert pins caused by deformation of the plate in the stepped area.

[0038] The interconnected via layout constraint area is the via no-visor zone, which restricts the placement of vias to positions near the final step boundary line to prevent hole wall cracks and plate delamination during milling of the steps.

[0039] The conductive line layout constraint area is used to restrict the copper traces from being placed close to the steps, so as to avoid the copper foil from lifting or the line from breaking during milling.

[0040] The layout of the screen printing is controlled by setting up a constraint area for the marking ink area to prevent the ink from covering the stepped mating surface, and to avoid the step milling process from damaging the screen printing markings.

[0041] In some embodiments, this application can filter target process spacing parameters that meet preset process conditions from the process spacing parameters corresponding to all printed circuit board manufacturers. Then, based on the target process spacing parameters, the layout constraint areas corresponding to surface mount components, through-hole components, interconnect vias, conductive lines, and marking inks are calculated respectively. These layout constraint areas are then integrated to form the layout constraint areas of the circuit board. The preset process conditions can be set by those skilled in the art according to actual conditions, and this application does not impose specific limitations.

[0042] For example, such as Figure 4 As shown, regions 1 and 2 are the gold finger areas, which are thin plate areas. Region 3 is the non-stepped area, which is a thick plate area. Its thickness is determined by the number of trace layers on the printed circuit board and is thicker than the gold finger areas. Additionally, A represents the distance between the surface mount component and the final step boundary line; B represents the distance between the via in the thick plate area and the final step boundary line; C represents the distance between the via in the thin plate area and the final step boundary line; D represents the distance between the DIP component hole and the final step boundary line; E represents the distance between the marking ink area in the thin plate area and the final step boundary line; and F represents the distance between the inner and outer layer wirings and the final step boundary line.

[0043] Furthermore, referring to Table 1, the embodiments of this application obtain the values ​​of A, B, C, D, E, and F for manufacturers 1, 2, and 3 respectively, and take the maximum value of the corresponding value among each printed circuit board manufacturer, which is denoted as MaxA, MaxB, MaxC, MaxD, MaxE, and MaxF.

[0044] like Figure 5 As shown, using the final step boundary line as a reference, the final step boundary line is copied and moved inward by MaxA distance. The surface mount component placement constraint area is formed by the two outline lines and the width of the gold finger. A surface mount component encapsulation prohibition layer is created in the surface mount component placement constraint area to prohibit the placement of surface mount components. Once a surface mount component is detected to be placed in the surface mount component placement constraint area, an alarm is automatically triggered.

[0045] Similarly, using the final step boundary line as a reference, copy the distance MaxB that the final step boundary line moves inward from the board to establish a constraint area for interconnecting vias in the thick plate region; copy the distance MaxC that the final step boundary line moves outward from the board to establish a constraint area for interconnecting vias in the thin plate region; copy the distance MaxD that the final step boundary line moves inward from the board to establish a constraint area for insert components in the thick plate region; copy the distance MaxE that the final step boundary line moves inward from the board to establish a constraint area for marking ink in the thick plate region; copy the distance MaxF that the final step boundary line moves inward from the board to establish a constraint area for conductive lines in the thick plate region.

[0046] In this embodiment, the target process spacing parameters that meet the preset process conditions are first screened, and then independent no-distribution areas are generated for each type of substrate component and integrated to obtain a complete layout constraint area. This can adapt to the different process standards of multiple manufacturers at one time, automatically avoid the processing interference of various devices, circuits, silkscreens and steps, and greatly reduce the workload of manually drawing constraint areas and the probability of design errors.

[0047] Optionally, in one embodiment of this application, based on the target process spacing parameters and the final step boundary line, a surface mount component layout constraint region, an through-hole component layout constraint region, an interconnect via layout constraint region, a conductive line layout constraint region, and a marking ink area layout constraint region are constructed. This includes: extracting from the target process spacing parameters a first target spacing between the surface mount component and the final step boundary line, a second target spacing between the through-hole component and the final step boundary line, a third target spacing between the via and the final step boundary line, a fourth target spacing between the conductive line and the final step boundary line, and a fifth target spacing between the marking ink area and the final step boundary line, respectively; and constructing the surface mount component layout constraint region, through-hole component layout constraint region, interconnect via layout constraint region, conductive line layout constraint region, and marking ink area layout constraint region based on the first target spacing, second target spacing, third target spacing, fourth target spacing, fifth target spacing, and the final step boundary line, respectively.

[0048] In some embodiments, the present application embodiments can extract the target spacings of surface mount components, through-hole components, vias, conductive lines, and marking ink areas relative to the final step boundary line based on the target process spacing parameters. Then, by combining the first target spacing, the second target spacing, the third target spacing, the fourth target spacing, the fifth target spacing, and the final step boundary line, a surface mount component layout constraint area, a through-hole component layout constraint area, an interconnect via layout constraint area, a conductive line layout constraint area, and a marking ink area layout constraint area can be constructed.

[0049] This application embodiment extracts the corresponding step safety distance for different types of substrate components and independently generates exclusive no-display areas. It can accurately match the processing requirements of various components, circuits, and silkscreens, comprehensively avoid interference problems in the layout of various structures in the step position, reduce errors in manual partitioning, and improve the design compliance and processing yield of step printed circuit boards.

[0050] In step S102, the initial wiring topology data of the circuit board is corrected based on the stack-up parameters of the circuit board, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region to obtain the wiring topology data.

[0051] It is understood that, in the embodiments of this application, the stack-up parameters can be understood as the complete stack-up configuration file of the printed circuit board, which is used to record the total number of layers, the dielectric thickness of each layer, the copper thickness, the dielectric constant, the range of available inner layers in the stepped area (such as L4-L15), and the complete routing layers in the non-stepped area (such as the top layer to the bottom layer). It is the underlying basis for dividing pads, vias, and routing rules.

[0052] The characteristics of the first region can be understood as a set of design constraints for the stepped region, such as the allowed range of inner layers for traces, the fact that gold finger pins can only be led out from the inner layer, the use of only dedicated micro blind vias, the single equivalent reference layer for traces, and the absence of double-layer ground copper.

[0053] The second region's characteristics can be understood as a set of design constraints for non-stepped regions, such as full-layer routing permissions, universal vias, bidirectional back drilling for vias when changing layers, and the requirement for matching grounding reference copper for cross-layer routing both above and below.

[0054] Initial routing topology data can be understood as the raw routing data generated according to the uniform rules of conventional printed circuit boards of the same thickness, without distinguishing between stepped and non-stepped areas; such as the original line routing, pad bonding to top / bottom layers, universal vias, uniform line width impedance, and no partitioned copper pouring rules. Routing topology data, on the other hand, can be understood as compliant line data after step / thickness board differentiation adaptation, gold finger packaging, vias, impedance, and ground copper correction; meeting the processing technology and high-speed signal integrity requirements of different board thickness areas.

[0055] In some embodiments, the present application embodiments can modify the initial wiring topology data of the circuit board based on the stack-up parameters of the circuit board, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region, thereby obtaining the corresponding wiring topology data.

[0056] For example, embodiments of this application can modify the initial routing topology data based on stack-up parameters, first region features, and second region features. For instance, the top or bottom pads of the gold fingers can be migrated to the inner layer of the thin board, and the micro-blind via mode can be switched; thin board layer-changing vias can replace dedicated blind vias, and thick board can retain through-holes, and two sets of independent back-drilling rules can be adopted; the trace width of thin / thick board can be adjusted in segments, and impedance can be controlled separately; grounding copper can be laid according to regional differences (such as single-sided ground for thin board, double-sided ground for thick board, and the copper and step boundary line can be kept at 20mil), thereby determining the corresponding routing topology data.

[0057] Optionally, in one embodiment of this application, the initial wiring topology data of the circuit board is corrected based on the stack-up parameters of the circuit board, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region to obtain wiring topology data. This includes: determining the first pad attributes of the stepped region and the second pad attributes of the non-stepped region based on the stack-up parameters, the first region characteristics, and the second region characteristics; determining the first via type, the first trace reference layer, and the first back-drilling process parameters of the stepped region, and the second via type, the second trace reference layer, and the second back-drilling process parameters of the non-stepped region, respectively, based on the first region characteristics and the second region characteristics; and correcting the initial wiring topology data based on the first pad attributes, the second pad attributes, the first via type, the first trace reference layer, the first back-drilling process parameters, the second via type, the second trace reference layer, and the second back-drilling process parameters to obtain wiring topology data.

[0058] It is understood that pad attributes are a set of design parameters characterizing the layer bonding relationship, pad stacking structure, interconnection method, and copper size of each layer of conductive pin pads, used to define the electrical connection form of component pins and gold finger pins on each layer of the printed circuit board. This application sets differentiated pad attributes to distinguish between stepped and non-stepped areas: the first pad attribute corresponding to the stepped area removes the bonding relationship between the gold finger pins and the top and bottom layer pads, fully configures the gold finger pads in the inner layer dedicated to thin boards, and matches the micro blind via conductive structure, realizing the gold finger signal lead-out only in the inner layer, adapting to the processing constraints of stepped thin boards with limited thickness; the second pad attribute corresponding to the non-stepped area retains the complete pad stacking structure of component pins in the top, bottom, and inner layers, adopts the standard through-hole conductive form, and is suitable for conventional component routing in thick board areas.

[0059] Via types are interlayer interconnection hole specifications categorized based on the start and end layers of via conduction and the forming process. Different via types correspond to different drilling and electroplating manufacturing processes, used to distinguish the interlayer signal interconnection structure in areas of different board thicknesses. This application sets two types of vias for stepped thin boards and thick boards: the first via type corresponding to the stepped area only conducts dedicated micro blind vias in the inner layer section of the stepped area, and the conduction range is limited to the usable layers of the thin board, not penetrating the top and bottom layers of the circuit board, serving as dedicated vias for signal jumps within the thin board; the second via type corresponding to the non-stepped area is a standard through-hole penetrating the top and bottom layers of the circuit board, adapting to the signal interconnection needs of any layer in the thick board.

[0060] The trace reference layer is the grounding or power layer adjacent to the conductive line. The trace and the corresponding reference layer constitute a transmission line structure, directly determining the line impedance, signal reflection, crosstalk, and other signal integrity indicators. During design, grounding copper foil must be laid on the trace reference layer to match impedance requirements. This application sets differentiated trace reference layer layout rules based on the differences in board thickness and layer stacking between stepped and non-stepped areas: For the first trace reference layer corresponding to the stepped area, only the ground layer adjacent to one side of the trace layer is used as the reference layer, and grounding copper foil is laid only on one side of the ground layer. The trace on the thin board is equivalent to the outer layer of the trace and does not require reference ground layers on both sides; For the second trace reference layer corresponding to the non-stepped area, the ground layers on both sides of the trace are used as reference layers, and grounding copper foil is laid on both sides; When the trace crosses the step boundary line, a fixed safety distance (such as 20 mil) is reserved between the grounding copper foil of the thick board section and the step boundary line.

[0061] Back-drilling process parameters are a set of process control parameters that limit the starting layer, ending layer, drilling depth, and hole diameter during back-drilling. Back-drilling is used to remove copper studs in vias that are not involved in signal connection, reducing signal reflection interference caused by studs. This application configures independent back-drilling process parameters for via structures in stepped and non-stepped areas: the first back-drilling process parameter for stepped areas performs unidirectional back-drilling for blind holes in thin boards, drilling only from the blind hole's ending layer to the adjacent layer of the trace to remove internal studs, without involving the top or bottom layers of the circuit board; the second back-drilling process parameter for non-stepped areas performs bidirectional back-drilling for through holes in thick boards, drilling from the top and bottom layers to the middle trace layer to remove studs at both ends and clear redundant copper segments above and below the through hole.

[0062] In some embodiments, this application configures the first pad attributes of the stepped area and the second pad attributes of the non-stepped area based on the stack-up parameters of the circuit board, the first area characteristics of the stepped area, and the second area characteristics of the non-stepped area. Based on the first area characteristics and the second area characteristics, it defines the first via type, the first trace reference layer, and the first back drill parameters for the stepped area, as well as the second via type, the second trace reference layer, and the second back drill parameters for the non-stepped area. Then, by combining the first pad attributes, the second pad attributes, the first via type, the first trace reference layer, the first back drill process parameters, the second via type, the second trace reference layer, and the second back drill process parameters, the initial wiring topology data is corrected to generate adapted wiring topology data.

[0063] This application embodiment matches differentiated pads, vias, trace reference layers, and back-drilling complete set of design parameters according to the stacking and structural characteristics corresponding to the two types of regions, and then uniformly modifies the original wiring topology by partition. It can adapt to different layer stacking processes and signal integrity requirements of stepped thin boards and thick boards, eliminate defects such as poor contact, impedance mismatch, and residual interference caused by unified wiring rules, and eliminate the need for manual modification of the circuit segment by segment. It significantly improves the wiring standardization and high-speed signal transmission stability of stepped gold finger printed circuit boards.

[0064] Optionally, in one embodiment of this application, determining the first pad attributes of the stepped region based on stack-up parameters, first region features, and second region features includes: determining the starting conductive layer and the ending conductive layer of the stepped region based on stack-up parameters, first region features, and second region features; determining the starting pad parameters of the stepped region based on the initial starting pad parameters and the starting conductive layer; determining the ending pad parameters of the stepped region based on the initial ending pad parameters and the ending conductive layer; and obtaining the first pad attributes based on the starting pad parameters and the ending pad parameters.

[0065] It is understood that, in the embodiments of this application, the starting conductive layer can be understood as the upper inner layer from which the gold finger pin signal is led out in the stepped region, and is the upper conductive layer of the gold finger pad arrangement; the ending conductive layer can be understood as the lower inner layer where the gold finger pin signal ends in the stepped region, and is the lower conductive layer of the gold finger pad arrangement.

[0066] The initial starting pad parameters can be understood as the initial pad size, layer binding, and basic parameters of the conductive structure preset on the top layer of the circuit board in the normal design mode, which are not adapted to the inner layer constraints of the stepped area. The starting pad parameters can be understood as the complete set of parameters of the inner layer pads obtained after migrating and adapting the initial starting pad parameters to the starting conductive layer of the stepped area, including the inner layer copper size and micro blind via conductive matching rules.

[0067] The initial termination pad parameters can be understood as the initial pad size, layer binding, and basic parameters of the conduction structure preset on the bottom layer of the circuit board in the normal design mode, which are not adapted to the inner layer constraints of the stepped thin board; the termination pad parameters can be understood as the complete set of parameters of the inner layer pads obtained after migrating and adapting the initial termination pad parameters to the termination conductive layer in the stepped area, which matches the inner layer conduction structure of the thin board.

[0068] In some embodiments, the present application can combine circuit board stacking parameters, the first region features corresponding to the stepped region, and the second region features corresponding to the non-stepped region to determine the starting conductive layer and the ending conductive layer of the stepped region. The initial starting pad parameters are adapted to the starting conductive layer to obtain the starting pad parameters of the stepped region, and the initial ending pad parameters are adapted to the ending conductive layer to obtain the ending pad parameters of the stepped region. Then, the starting pad parameters and the ending pad parameters are fused to generate the first pad attributes adapted to the stepped gold fingers.

[0069] For example, this application embodiment takes a commonly used 18-layer board for memory cards as an example. The non-stepped area is located on the top to bottom layers, while the starting conductive layer of the stepped area is L4 and the ending conductive layer is L15, and so on. Figure 6As shown, by clicking "Gold Finger Package Modification" in the routing design module, the gold finger pins are modified to a specified inner layer, that is, the top pin of the gold finger is adjusted to L4 and the bottom pin is adjusted to L15. This determines the starting and ending pad parameters of the stepped area, thereby obtaining the first pad attribute of the stepped area and realizing the adaptive package design of the stepped gold finger. Specifically, as shown... Figure 7 As shown, the non-stepped area is located on the top to bottom layer, and the stepped area is located on the L4 to L15 layer. The specific operation process includes: (1) Open the pad editing function of the design tool, select the pin to be modified, right-click to perform the editing operation, and open the pad modification window; (2) Select to start the micro-blind via mode; (3) Enter the layered design page, copy the top pad parameters to the target inner layer (such as L4), and cancel the top pad configuration; in the same way, copy the bottom pad parameters to another target inner layer (such as L15), and cancel the bottom pad configuration; (4) After all pads are modified, perform the file update operation to synchronize the changes to the printed circuit board design file.

[0070] Furthermore, since the reference layers for the stepped and non-stepped regions are different in this embodiment, two line widths can be simulated based on relevant parameters. This can be achieved by clicking... Figure 6 The "trace detail processing" in the text involves segmented control of impedance in stepped and non-stepped areas to match the signal transmission characteristics of different areas.

[0071] This application embodiment relies on the stack-up information to divide the stepped area into dedicated start and end conductive layers, and then combines the original pad parameters to generate corresponding stepped area pad parameters and integrate them to form dedicated pad attributes. This can accurately match the inner layer routing constraints of the thin board, avoid problems such as the inability to form the gold finger surface pad and poor signal contact, and eliminate the need for manual modification of each pad, greatly improving the standardization and processing adaptability of stepped gold finger pad design.

[0072] Optionally, in one embodiment of this application, based on the first region features and the second region features, the first via type, the first trace reference layer, and the first back-drilling process parameters for the stepped region, and the second via type, the second trace reference layer, and the second back-drilling process parameters for the non-stepped region are determined, respectively. This includes: determining the first via type and the second via type based on the first region features and the second region features; determining the location of the layer-changing via where the gold finger layer-changing via is located based on the first region features and the second region features; determining the first back-drilling process parameters and the second back-drilling process parameters based on the location of the layer-changing via; determining the ground copper layer based on the first region features and the second region features; and determining the first trace reference layer and the second trace reference layer based on the ground copper layer.

[0073] It is understandable that the location of the via in the layer change can be understood as the partition coordinate of the via that interconnects different conductive layers with the gold finger signal. It is divided into two types of locations: via in the stepped thin plate area and via in the thick plate area. It is the basis for distinguishing the back drilling rules.

[0074] The grounding copper foil is laid on the conductive copper foil of the adjacent ground layer of the signal layer as an impedance reference carrier for high-speed traces. Its layout can include, but is not limited to, single-sided copper laying, double-sided copper laying, etc.

[0075] In some embodiments, the present application can select suitable first via type and second via type based on the first region characteristics corresponding to the stepped region and the second region characteristics corresponding to the non-stepped region, respectively. In combination with the first region characteristics and the second region characteristics, the position of the layer-changing via corresponding to the gold finger is located. The first back-drilling process parameters and the second back-drilling process parameters are configured according to the position of the layer-changing via. At the same time, the grounding copper foil layout is planned according to the first region characteristics and the second region characteristics. The first trace reference layer corresponding to the stepped region and the second trace reference layer corresponding to the non-stepped region are defined based on the grounding copper foil.

[0076] For example, in this embodiment of the application, when different manufacturers process stepped gold finger boards, the interconnect via processing processes for the stepped and non-stepped areas are different, and the processing sequences of the two processes are independent. To distinguish the interconnect via process requirements for the stepped and non-stepped areas and avoid manufacturing defects caused by identification errors, a method is used to... Figure 6 The "via processing" involves modifying vias in thin-plate areas and back-drilling vias for stepped gold finger traces. This determines the first via type in stepped areas and the second via type in non-stepped areas, along with the corresponding first and second back-drilling process parameters. Specifically, for example... Figure 7 As shown, the interconnecting vias in the stepped area employ a dedicated blind via structure (such as Via18P8-4-15), clearly distinguishing them from the conventional through-holes in the non-stepped area, facilitating manufacturer identification and processing. In the Via18P8-4-15 designation, 4-15 represents the starting conductive layer L4 and the ending conductive layer L15 of the blind via. Furthermore, differentiated back-drilling process identifiers are configured for the stepped and non-stepped areas respectively, yielding the first and second back-drilling process parameters.

[0077] Furthermore, the embodiments of this application are combined with Figure 7As shown, the location of the layer-change via is first determined based on the characteristics of the first and second regions: When the layer-change via is in a stepped region, the corresponding first back-drilling process parameters are matched, and the back-drilling proceeds from the effective layer termination layer of the thin board to the adjacent layer of the trace; taking the trace spanning L4 to L7 as an example, the back-drilling parameters are configured as backdrill15-8, that is, back-drilling from L15 to L8. When the layer-change via is in a non-stepped region, the corresponding second back-drilling process parameters are matched, and the back-drilling proceeds from the top and bottom layers into the board to the adjacent layer of the trace; taking the trace spanning L4 to L7 as an example, backdrill1-3 (back-drilling from the top layer to L3) and backdrill18-8 (back-drilling from the bottom layer to L8) are configured simultaneously.

[0078] This application embodiment relies on the structural characteristics of stepped and non-stepped areas to match via specifications, and configures corresponding back-drilling parameters according to the location of the via. It also distinguishes two types of trace reference layers according to the grounding copper foil layout rules, realizing integrated partitioning adaptation of vias, back-drilling, and reference ground layers. This avoids problems such as confusion in stepped board via processing, residual pile reflection, and impedance mismatch, reduces manual step-by-step design errors, and improves high-speed signal integrity and printed circuit board production yield.

[0079] Optionally, in one embodiment of this application, before annotating non-electrical connection information to obtain target data for the circuit board, the method further includes: acquiring first thickness information, first silkscreen information, and first substrate manufacturing layer engineering information for the stepped area, and second thickness information, second silkscreen information, and second substrate manufacturing layer engineering information for the non-stepped area; and determining non-electrical connection information based on the first thickness information, first silkscreen information, first substrate manufacturing layer engineering information, second thickness information, second silkscreen information, and second substrate manufacturing layer engineering information.

[0080] It is understood that, in the embodiments of this application, non-electrical connection information can be understood as the set of all graphic and boundary parameters within the layout that do not undertake the function of electrical signal interconnection, which may include, but is not limited to, first thickness information, first silkscreen information, first substrate manufacturing layer engineering information, second thickness information, second silkscreen information, and second substrate manufacturing layer engineering information.

[0081] The first thickness information can be understood as the substrate thickness-related parameters in the stepped region; the second thickness information can be understood as the substrate thickness-related parameters in the non-stepped region.

[0082] The first screen printing information can be understood as the range and constraint rules of the ink layout within the stepped area; the second screen printing information can be understood as the range and constraint rules of the ink layout within the non-stepped area.

[0083] The substrate manufacturing layer engineering information can be understood as the process layer data required for printed circuit board production. It does not realize electrical interconnection and may include, but is not limited to, the board outline cutout layer, the board outline design frame layer, the board outline finished frame layer, and the drilling pattern layer (such as the drilling pattern layer of L4-L15).

[0084] In some embodiments, before generating target data by annotating non-electrical connection information, this application collects the first thickness information, the first silkscreen information, the first substrate manufacturing layer engineering information of the stepped area, and the second thickness information, the second silkscreen information, and the second substrate manufacturing layer engineering information of the non-stepped area. Then, based on the first thickness information, the first silkscreen information, the first substrate manufacturing layer engineering information, the second thickness information, the second silkscreen information, and the second substrate manufacturing layer engineering information, the corresponding non-electrical connection information is determined.

[0085] For example, in the embodiments of this application, the conductive layer corresponding to the stepped gold finger pad can be determined first, and a ground copper layer can be laid on the adjacent lower layer of the trace start layer and the adjacent upper layer of the trace end layer, such as... Figure 7 As shown, L4 and L15 are the stepped gold finger outgoing layers. The traces in this area are equivalent to the outer layer traces of a conventional printed circuit board. Therefore, grounding copper can be laid in the corresponding target areas L5 and L14. Furthermore, in this embodiment, when the gold finger L15 trace crosses a stepped area and a non-stepped area, the trace within the stepped area is equivalent to an outer layer trace, and grounding copper does not need to be laid in L16. The trace within the non-stepped area is an inner layer trace, with two sets of adjacent reference layers. Grounding copper can be laid in L16, and a 20mil safety distance is maintained between the grounding copper and the final stepped boundary line. This reduces the difficulty of copper etching in the stepped area, ensures signal line impedance continuity, suppresses signal crosstalk, and guarantees high-speed signal transmission quality. In addition, the marking ink patterns corresponding to the top and bottom layers must not be placed on the side of the final stepped boundary line facing the gold finger insertion. In addition, the substrate manufacturing layer engineering information is automatically generated by the design software. To adapt to the uneven thickness structure of the stepped gold fingers, the L4 and L15 substrate manufacturing layer engineering information corresponding to the pads of the stepped gold fingers is generated. The drawing mode is set to positive mode, and the option to suppress unconnected pads is unchecked to prevent the gold finger pad graphics from being lost in the output process layer. An L4 to L15 layered blind via drilling layer is created to adapt to the stepped area. The associated graphics of this layer include the board outline cutout layer, the board outline design outline layer, the board outline finished outline layer, and the L4 to L15 drilling legend layer. Then, the first substrate manufacturing layer engineering information and the second substrate manufacturing layer engineering information are obtained. Combined with the first thickness information, the first silkscreen information, the second thickness information, and the second silkscreen information, the non-electrical connection information is determined.

[0086] In this embodiment, the specific information of board thickness, silkscreen printing, and substrate manufacturing layers corresponding to the stepped area and non-stepped area is collected respectively. Then, the complete non-electrical labeling information is generated by combining the differentiated production requirements of the two types of areas. This can completely distinguish the processing labeling requirements of thin and thick boards without the need for manual layer labeling. This avoids the problems of board manufacturers being unable to identify stepped structures, silkscreen printing violations, and missing layers, and improves the readability of processing documents and production adaptability.

[0087] In step S103, non-electrical connection information is marked based on the final step boundary line, the layout constraint area, the first area features and the second area features to obtain the target data of the circuit board. Based on the target data, the layout constraint area and the wiring topology data, the design data of the circuit board is generated.

[0088] In some embodiments, the present application can mark non-electrical connection information based on the final step boundary line, the layout constraint area, the first area features and the second area features to obtain target data, and then combine the target data, the layout constraint area and the wiring topology data to generate design data.

[0089] For example, in this embodiment of the application, after the layout and routing of the printed circuit board (PCB) is completed, non-electrical connection information such as silkscreen information and substrate manufacturing layer engineering information can be marked to facilitate PCB manufacturing. Since the files that PCB manufacturers can process are planar images of each layer, if the substrate manufacturing layer engineering information is not specially marked and processed, the PCB manufacturer may not be able to identify the specific requirements for the step thickness. Therefore, non-electrical connection information can be marked to generate target data, and then the design data of the PCB can be generated based on the target data, the layout constraint area, and the wiring topology data.

[0090] Optionally, in one embodiment of this application, annotating non-electrical connection information to obtain target data for the circuit board includes: generating a first annotation instruction for non-electrical connection information in the stepped area based on first thickness information, first silkscreen information, and first substrate manufacturing layer engineering information; generating a second annotation instruction for non-electrical connection information in the non-stepped area based on second thickness information, second silkscreen information, and second substrate manufacturing layer engineering information; and annotating the corresponding non-electrical connection information based on the first annotation instruction and the second annotation instruction to obtain target data.

[0091] It is understood that, in the embodiments of this application, the first annotation instruction can be understood as an automated layer and process identification execution instruction generated for the stepped area, which may include, but is not limited to, thickness boundary marking, marking ink prohibition boundary marking, special blind hole layer configuration, grounding copper skin boundary marking, etc.; the second annotation instruction can be understood as an automated annotation instruction generated for the non-stepped area, which may include, but is not limited to, thick plate through hole process marking, bidirectional back drilling marking, partitioned copper skin constraint, silk screen boundary instruction, etc.

[0092] In some embodiments, the present application can generate a first annotation instruction corresponding to the stepped area by combining the first thickness information, the first silkscreen information, and the first substrate manufacturing layer engineering information, and generate a second annotation instruction corresponding to the non-stepped area based on the second thickness information, the second silkscreen information, and the second substrate manufacturing layer engineering information. Then, the non-electrical connection information corresponding to the first annotation instruction and the second annotation instruction is annotated according to the first annotation instruction and the second annotation instruction to obtain the target data.

[0093] For example, in this embodiment, the stepped gold finger boundary line can be copied to the board outline dimension layer. Then, a first annotation instruction for the stepped area and a second annotation instruction for the non-stepped area are generated on both sides of the boundary line. The first and second annotation instructions are then used to annotate the corresponding printed circuit board thicknesses. The thickness of the gold finger is annotated in the stepped area on the left, and the thickness of the entire printed circuit board (i.e., the non-stepped area) is annotated on the right. For example, the thickness of the stepped area on the left is annotated as 1.57mm ± 8%, and the thickness of the non-stepped area on the right is annotated as 2.67mm ± 8%. Correspondingly, two lines are added to the signal integrity remarks in the process description layer: overall board thickness is 2.67mm ± 8%; stepped gold finger thickness is 1.57mm ± 8%. This determines the corresponding target data.

[0094] This application embodiment generates independent annotation instructions for stepped and non-stepped areas respectively, and integrates them after completing the annotation of non-electrical information to obtain the target data of the circuit board. It can accurately distinguish the different annotation requirements of thin and thick boards in terms of board thickness, silk screen printing, and manufacturing layers, avoid confusion of stepped structure processing marks and missing layer information, realize the standardized automatic generation of computer-aided manufacturing processing data, and reduce manual annotation errors and factory identification difficulties.

[0095] The working principle of the circuit board design method proposed in this application will be introduced below with reference to a specific embodiment.

[0096] This application proposes to keep the thickness of the printed circuit board in the gold finger area unchanged and increase the thickness of the printed circuit board in the area outside the gold finger area to increase the number of wiring layers, thereby solving problems such as the inability to meet the high-density and high-speed design requirements of storage products, low processing yield of stepped gold finger printed circuit boards, poor signal transmission stability, and high design rework rate.

[0097] This application's embodiments modularize the design process, including, for example... Figure 2 The spacing design module shown, such as Figure 6 The wiring design module shown, and the annotation of non-electrical connection information through the post-processing module, realize the standardized and efficient design of stepped gold finger printed circuit boards.

[0098] The spacing design module can import process capability parameters from different printed circuit board manufacturers in a specified format, as shown in Table 1, and update and maintain them in real time to determine the process spacing parameters of the circuit board. Based on the process spacing parameters and the final step boundary information, it determines the layout constraint areas, such as the layout constraint areas for surface mount components, through-hole components, interconnect vias, conductive lines, and marking ink areas. It also automatically issues warnings when there are layout violations.

[0099] The wiring design module can provide features such as "gold finger package modification", "via processing", and "trace detail processing".

[0100] Among them, "gold finger packaging modification" can be understood as determining the starting conductive layer and ending conductive layer of the stepped region based on the circuit board's stack-up parameters, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region, thereby modifying the gold finger pins to the corresponding starting conductive layer and ending conductive layer, obtaining the starting pad parameters and ending pad parameters, and determining the first pad attributes.

[0101] "Through hole processing" can use dedicated blind holes for stepped areas, distinguish between stepped and non-stepped areas to formulate back drilling rules, thereby obtaining the first through hole type, the second through hole type, the first back drilling process parameters, and the second back drilling process parameters.

[0102] "Trace detail processing" can perform impedance segmentation control, determine impedance information, and standardize the requirements for grounding copper on the reference layer.

[0103] Furthermore, in the "Trace Details Processing" of this application embodiment, the gold hand points out that the trace layer is grounded copper foil corresponding to the adjacent layer, and the traces across thin and thick plate areas are designed with reference layers according to the regional characteristics. The grounded copper foil in the thick plate area is kept at a specified distance from the final step boundary line, and the first trace reference layer and the second trace reference layer are determined to ensure signal integrity performance.

[0104] The post-processing module can visually annotate the final step boundary line, standardize the placement of silkscreen printing, modify the substrate manufacturing layer engineering information in a targeted manner, add a dedicated blind hole drilling layer and associate it with the specified printed circuit board design layer, and adapt to the processing and identification requirements of printed circuit board manufacturers.

[0105] In this embodiment of the application, when visually annotating the final step boundary line, the step gold finger boundary line can be copied at a specified level and the thickness of the printed circuit boards on both sides can be marked. At the same time, the corresponding board thickness information can be added to the process description layer to achieve a clear display of processing parameters.

[0106] In addition, the substrate manufacturing layer engineering information modification can automatically adjust parameters according to the layer where the stepped gold fingers are located, to prevent the gold finger pads from being missing in the substrate manufacturing layer engineering information, and automatically add various design layers required for the dedicated drilling layer.

[0107] It should be noted that the layout constraint areas set in this embodiment differ from the design requirements of other normal printed circuit boards, adapting to the structural characteristics and processing requirements of stepped gold fingers. Furthermore, the layout and routing designs of all constraint areas can be visually prompted through system feedback, facilitating quick modifications by designers.

[0108] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0109] According to the circuit board design method proposed in this application, the initial step boundary line of the stepped and non-stepped areas of the circuit board can be corrected based on the process spacing parameters of the circuit board to determine the final step boundary line. A layout constraint area is constructed in conjunction with the process spacing parameters. Then, based on the circuit board's stack-up parameters, the first region characteristics of the stepped area, and the second region characteristics of the non-stepped area, the initial wiring topology data is corrected to obtain wiring topology data. Based on the final step boundary line, the layout constraint area, the first region characteristics, and the second region characteristics, non-electrical connection information is marked to obtain target data. Thus, based on the target data, the layout constraint area, and the wiring topology data, circuit board design data is generated. Therefore, this method can solve the technical problems of stepped gold finger printed circuit boards lacking automated design methods and standardized layout and routing specifications, which easily lead to unreasonable final step boundary line spacing, poor gold finger packaging, impedance mismatch, signal integrity degradation, lack of unified design parameter reference, and high design rework rate. It achieves the technical effects of partitioned configuration of differentiated wiring rules, combined with standardized non-electrical connection information to generate design data, realizing automated layout design of stepped gold finger circuit boards, stabilizing signal performance, unifying design specifications, and reducing design errors and rework.

[0110] Embodiments of this application also provide a circuit board design apparatus.

[0111] Figure 8 This is a block diagram of a circuit board design apparatus provided according to an embodiment of this application.

[0112] like Figure 8 As shown, the design device 10 for the circuit board includes: a construction module 100, a correction module 200, and a generation module 300.

[0113] The construction module 100 is used to correct the initial step boundary line of the stepped area and non-stepped area of ​​the circuit board based on the process spacing parameters of the circuit board, so as to determine the final step boundary line of the stepped area and non-stepped area, and construct the layout constraint area of ​​the circuit board based on the final step boundary line and the process spacing parameters.

[0114] The correction module 200 is used to correct the initial wiring topology data of the circuit board based on the stack-up parameters of the circuit board, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region, so as to obtain wiring topology data.

[0115] The generation module 300 is used to annotate non-electrical connection information based on the final step boundary line, layout constraint area, first area features and second area features to obtain the target data of the circuit board, and generate the design data of the circuit board based on the target data, layout constraint area and wiring topology data.

[0116] Optionally, in one embodiment of this application, the construction module 100 includes: an extraction unit, a first determination unit, and a second determination unit.

[0117] The extraction unit is used to extract the initial spacing between the marking ink area and the initial step boundary line from the process spacing parameters.

[0118] The first determining unit is used to determine the final step boundary line based on the initial spacing when the initial spacing meets the preset spacing conditions.

[0119] The second determining unit is used to determine the final step boundary line based on the initial step boundary line when the initial spacing does not meet the preset spacing conditions.

[0120] Optionally, in one embodiment of this application, the construction module 100 includes: a third determining unit, a first construction unit, and a second construction unit.

[0121] The third determining unit is used to determine the target process spacing parameter that meets the preset process conditions based on the process spacing parameter.

[0122] The first building unit is used to construct the surface mount component layout constraint area, the through-hole component layout constraint area, the interconnect via layout constraint area, the conductive line layout constraint area, and the marking ink area layout constraint area based on the target process spacing parameters and the final step boundary line.

[0123] The second building unit is used to construct the layout constraint area based on the layout constraint area of ​​surface mount components, the layout constraint area of ​​through-hole components, the layout constraint area of ​​interconnecting vias, the layout constraint area of ​​conductive lines, and the layout constraint area of ​​marking ink area.

[0124] Optionally, in one embodiment of this application, the first building unit includes: an extraction subunit and a building subunit.

[0125] The extraction subunit is used to extract the following from the target process spacing parameters: the first target spacing between the surface mount component and the final step boundary line; the second target spacing between the through-mount component and the final step boundary line; the third target spacing between the via and the final step boundary line; the fourth target spacing between the conductive line and the final step boundary line; and the fifth target spacing between the marking ink area and the final step boundary line.

[0126] Sub-units are constructed to create constraint regions for surface mount components, through-hole components, interconnect vias, conductive lines, and marking ink areas, respectively, based on the first target spacing, the second target spacing, the third target spacing, the fourth target spacing, the fifth target spacing, and the final step boundary line.

[0127] Optionally, in one embodiment of this application, the correction module 200 includes: a fourth determining unit, a fifth determining unit, and a correction unit.

[0128] The fourth determining unit is used to determine the first pad attributes of the stepped region and the second pad attributes of the non-stepped region based on the stack-up parameters, the first region features and the second region features.

[0129] The fifth determining unit is used to determine, based on the characteristics of the first region and the characteristics of the second region, the first via type, the first trace reference layer, and the first back-drilling process parameters of the stepped region, and the second via type, the second trace reference layer, and the second back-drilling process parameters of the non-stepped region.

[0130] The correction unit is used to correct the initial routing topology data based on the first pad attribute, the second pad attribute, the first via type, the first trace reference layer, the first back drill process parameters, the second via type, the second trace reference layer, and the second back drill process parameters, so as to obtain the routing topology data.

[0131] Optionally, in one embodiment of this application, the fourth determining unit includes: a first determining subunit, a second determining subunit, a third determining subunit, and a generating subunit.

[0132] The first determining subunit is used to determine the starting conductive layer and the ending conductive layer of the stepped region based on the stacking parameters, the first region features and the second region features.

[0133] The second determining subunit is used to determine the starting pad parameters of the stepped region based on the initial starting pad parameters and the starting conductive layer.

[0134] The third determining subunit is used to determine the termination pad parameters of the stepped region based on the initial termination pad parameters and the termination conductive layer.

[0135] Generate a sub-unit to obtain the first pad attributes based on the start pad parameters and the end pad parameters.

[0136] Optionally, in one embodiment of this application, the fifth determining unit includes: a fourth determining subunit, a fifth determining subunit, and a sixth determining subunit.

[0137] The fourth determining subunit is used to determine the first via type and the second via type based on the first region features and the second region features.

[0138] The fifth determining subunit is used to determine the location of the layer-changing via in the gold finger based on the features of the first region and the features of the second region, and to determine the first back-drilling process parameters and the second back-drilling process parameters based on the location of the layer-changing via.

[0139] The sixth determining sub-unit is used to determine the ground copper layer based on the characteristics of the first region and the characteristics of the second region, and to determine the first trace reference layer and the second trace reference layer based on the ground copper layer.

[0140] Optionally, in one embodiment of this application, it further includes: an acquisition module and a determination module.

[0141] The acquisition module is used to acquire first thickness information, first silkscreen information, and first substrate manufacturing layer engineering information of the stepped area, and second thickness information, second silkscreen information, and second substrate manufacturing layer engineering information of the non-stepped area, before annotating non-electrical connection information to obtain target data of the circuit board.

[0142] The determination module is used to determine non-electrical connection information based on first thickness information, first silkscreen information, first substrate manufacturing layer engineering information, second thickness information, second silkscreen information, and second substrate manufacturing layer engineering information.

[0143] Optionally, in one embodiment of this application, the generation module 300 includes: a first generation unit, a second generation unit, and a third generation unit.

[0144] The first generation unit is used to generate a first annotation instruction for non-electrical connection information in the stepped area based on the first thickness information, the first silkscreen information and the first substrate manufacturing layer engineering information.

[0145] The second generation unit is used to generate a second annotation instruction for non-electrical connection information in the non-step area based on the second thickness information, the second silkscreen information, and the second substrate manufacturing layer engineering information.

[0146] The third generation unit is used to annotate the corresponding non-electrical connection information based on the first annotation instruction and the second annotation instruction to obtain the target data.

[0147] For a description of the features in the embodiment corresponding to the circuit board design device, please refer to the relevant description in the embodiment corresponding to the circuit board design method, which will not be repeated here.

[0148] According to the circuit board design apparatus proposed in this application, the initial step boundary line of the stepped and non-stepped regions of the circuit board can be corrected based on the process spacing parameters of the circuit board to determine the final step boundary line. A layout constraint region is constructed in conjunction with the process spacing parameters. Then, based on the circuit board's stack-up parameters, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region, the initial wiring topology data is corrected to obtain wiring topology data. Based on the final step boundary line, the layout constraint region, the first region characteristics, and the second region characteristics, non-electrical connection information is marked to obtain target data. Thus, based on the target data, the layout constraint region, and the wiring topology data, circuit board design data is generated. Therefore, this apparatus can solve the technical problems of stepped gold finger printed circuit boards lacking automated design methods and standardized layout and routing specifications, which easily lead to unreasonable final step boundary line spacing, poor gold finger packaging, impedance mismatch, signal integrity degradation, lack of unified design parameter reference, and high design rework rate. It achieves the technical effects of partitioned configuration of differentiated wiring rules, combined with standardized non-electrical connection information to generate design data, realizing automated layout design of stepped gold finger circuit boards, stabilizing signal performance, unifying design specifications, and reducing design errors and rework.

[0149] Embodiments of this application also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the circuit board design method embodiments described above.

[0150] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the circuit board design method embodiments described above when it is run.

[0151] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0152] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the circuit board design method embodiments described above.

[0153] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the circuit board design method embodiments described above.

[0154] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0155] The circuit board design method provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A circuit board design method, characterized in that, Includes the following steps: The initial step boundary line of the stepped and non-stepped areas of the circuit board is corrected based on the process spacing parameters of the circuit board to determine the final step boundary line between the stepped and non-stepped areas. Based on the final step boundary line and the process spacing parameters, the layout constraint area of ​​the circuit board is constructed. Based on the stack-up parameters of the circuit board, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region, the initial wiring topology data of the circuit board is corrected to obtain wiring topology data. Based on the final step boundary line, the layout constraint area, the first area feature, and the second area feature, non-electrical connection information is marked to obtain the target data of the circuit board. Based on the target data, the layout constraint area, and the wiring topology data, the design data of the circuit board is generated.

2. The method according to claim 1, characterized in that, The process spacing parameters of the circuit board are used to correct the initial step boundary between the stepped and non-stepped regions of the circuit board, in order to determine the final step boundary between the stepped and non-stepped regions, including: The initial spacing between the marking ink area and the initial step boundary line is extracted from the process spacing parameters. If the initial spacing meets the preset spacing condition, then the final step boundary line is determined based on the initial spacing; If the initial spacing does not meet the preset spacing condition, the final step boundary line is determined based on the initial step boundary line.

3. The method according to claim 1, characterized in that, The step of constructing the layout constraint area of ​​the circuit board based on the final step boundary line and the process spacing parameters includes: Based on the process spacing parameters, a target process spacing parameter that satisfies the preset process conditions is determined. Based on the target process spacing parameters and the final step boundary line, a constraint area for surface mount components, a constraint area for through-hole components, a constraint area for interconnect vias, a constraint area for conductive lines, and a constraint area for marking ink are constructed. The layout constraint area is constructed based on the surface mount component layout constraint area, the through-hole component layout constraint area, the interconnect via layout constraint area, the conductive line layout constraint area, and the marking ink area layout constraint area.

4. The method according to claim 3, characterized in that, Based on the target process spacing parameters and the final step boundary line, the following constraint regions are constructed: surface mount component layout constraint region, through-hole component layout constraint region, interconnect via layout constraint region, conductive line layout constraint region, and marking ink area layout constraint region, including: The target process spacing parameters are extracted as follows: the first target spacing between the surface mount component and the final step boundary line, the second target spacing between the through-mount component and the final step boundary line, the third target spacing between the via and the final step boundary line, the fourth target spacing between the conductive line and the final step boundary line, and the fifth target spacing between the marking ink area and the final step boundary line. Based on the first target spacing, the second target spacing, the third target spacing, the fourth target spacing, the fifth target spacing, and the final step boundary line, respectively, the surface mount component layout constraint area, the through-hole component layout constraint area, the interconnect via layout constraint area, the conductive line layout constraint area, and the marking ink area layout constraint area are constructed.

5. The method according to claim 1, characterized in that, The initial wiring topology data of the circuit board is corrected based on the stack-up parameters of the circuit board, the first region characteristics of the stepped region, and the second region characteristics of the non-stepped region to obtain wiring topology data, including: Based on the stack-up parameters, the first region features, and the second region features, the first pad attributes of the stepped region and the second pad attributes of the non-stepped region are determined. Based on the features of the first region and the features of the second region, the first via type, the first trace reference layer, and the first back-drilling process parameters of the stepped region are determined, and the second via type, the second trace reference layer, and the second back-drilling process parameters of the non-stepped region are determined respectively. Based on the first pad attribute, the second pad attribute, the first via type, the first trace reference layer, the first back drill process parameters, the second via type, the second trace reference layer, and the second back drill process parameters, the initial routing topology data is corrected to obtain the routing topology data.

6. The method according to claim 5, characterized in that, The step of determining the first pad attribute of the stepped region based on the stack-up parameters, the first region feature, and the second region feature includes: Based on the stacking parameters, the first region features, and the second region features, the starting conductive layer and the ending conductive layer of the stepped region are determined. Based on the initial starting pad parameters and the initial conductive layer, the starting pad parameters of the stepped region are determined; Based on the initial termination pad parameters and the termination conductive layer, the termination pad parameters of the stepped region are determined. The attributes of the first pad are obtained based on the starting pad parameters and the ending pad parameters.

7. The method according to claim 5, characterized in that, The step of determining the first via type, first trace reference layer, and first back-drilling process parameters of the stepped region, and the second via type, second trace reference layer, and second back-drilling process parameters of the non-stepped region, based on the first region features and the second region features, includes: Based on the first region features and the second region features, the first via type and the second via type are determined; Based on the features of the first region and the features of the second region, the location of the layer-changing via where the gold finger is located is determined, and based on the location of the layer-changing via, the first back-drilling process parameters and the second back-drilling process parameters are determined. Based on the characteristics of the first region and the characteristics of the second region, a ground copper layer is determined, and based on the ground copper layer, the first trace reference layer and the second trace reference layer are determined.

8. The method according to claim 1, characterized in that, Before annotating non-electrical connection information to obtain the target data for the circuit board, the following steps are also included: Obtain the first thickness information, first silkscreen information, and first substrate manufacturing layer engineering information of the stepped area, and the second thickness information, second silkscreen information, and second substrate manufacturing layer engineering information of the non-stepped area; Based on the first thickness information, the first silkscreen information, the first substrate manufacturing layer engineering information, the second thickness information, the second silkscreen information, and the second substrate manufacturing layer engineering information, the non-electrical connection information is determined.

9. The method according to claim 8, characterized in that, The annotation of non-electrical connection information to obtain target data for the circuit board includes: Based on the first thickness information, the first silkscreen information, and the first substrate manufacturing layer engineering information, a first annotation instruction for non-electrical connection information in the stepped area is generated. Based on the second thickness information, the second silkscreen information, and the second substrate manufacturing layer engineering information, a second annotation instruction for non-electrical connection information in the non-stepped area is generated; Based on the first annotation instruction and the second annotation instruction, the corresponding non-electrical connection information is annotated to obtain the target data.

10. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the circuit board design method as described in any one of claims 1-9.

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