A multi-scale numerical modeling method and related apparatus for integrated circuit thermal analysis

Abstract

The application belongs to the technical field of integrated circuit thermal management, and discloses a multi-scale numerical modeling method for integrated circuit thermal analysis and a related device; wherein the multi-scale numerical modeling method comprises: based on an integrated circuit to be analyzed, an integrated circuit geometric model with material properties is acquired; a coarse grid cell set is divided to calculate the equivalent thermal conductivity of each coarse grid cell; each equivalent thermal conductivity obtained by calculation is assigned to the corresponding coarse grid cell to construct a macroscopic equivalent model, and boundary conditions and heat source loads are applied to the macroscopic equivalent model to perform thermal analysis and solve to obtain the temperature field distribution result of the integrated circuit to be analyzed. The technical scheme disclosed by the application can greatly reduce the number of grids, improve the calculation efficiency, adapt to any integrated circuit layout, and does not require a large amount of pre-computation and rely on complex mathematical tools, and both precision and efficiency are taken into account.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit thermal management technology, and specifically relates to a multi-scale numerical modeling method and related apparatus for integrated circuit thermal analysis. Background Technology

[0002] As integrated circuit manufacturing advances to the nanoscale, the number of transistors integrated on a single chip has increased dramatically, leading to a continuous increase in power density. Thermal management has become a critical challenge in chip design. Specifically, high temperatures can trigger failure mechanisms such as electromigration, chip warpage, and thermal stress-induced fracture or delamination, severely impacting the performance and reliability of integrated circuits. Therefore, efficient and accurate thermal analysis techniques are crucial for optimizing integrated circuit design.

[0003] Currently, existing integrated circuit thermal analysis methods are mainly divided into three categories: analytical / semi-analytical methods, numerical methods, and model reduction and equivalent modeling methods.

[0004] Analytical / semi-analytical methods calculate temperature distribution by constructing simplified thermal resistance networks. They have low computational complexity but limited accuracy and are difficult to capture the detailed thermal effects of complex structures. Numerical methods (such as the finite element method and the finite volume method) solve the temperature field by dissipating heat dissipation and conduction equations. They have high accuracy but consume huge computational resources. Especially for integrated circuits with multi-scale characteristics (such as packaging scales of millimeters to centimeters and internal components of nanometers to micrometers), direct mesh generation will result in an extremely large number of cells.

[0005] To improve efficiency, researchers have proposed various methods for model reduction and equivalent modeling. Existing representative techniques include: (1) Chinese invention patent application with publication number CN106886621A discloses an integrated circuit thermal analysis method based on aggregation reduction. It performs spectral analysis on the undirected graph of the thermal conductivity matrix and aggregates nodes with consistent temperature into "super nodes" to achieve order reduction. However, this method relies on graph theory partitioning and Laplacian matrix eigenvalue calculation. The algorithm is complex to implement and the partitioning effect on large-scale irregular structures is difficult to guarantee.

[0006] (2) Chinese invention patent application with publication number CN120409388A discloses an equivalent thermal conductivity mapping method for vertical interconnect layers. Specifically, it is a stackable thermal modeling method based on hierarchical lookup tables. This method establishes effective thermal conductivity lookup tables for TSV layers, micro solder ball layers, and RDL layers respectively, and performs thermal analysis through pre-calculation and stacking of equivalent layers. Since this method relies on a large number of pre-simulation to generate lookup tables, and the non-uniformly distributed structure needs to be divided into multiple sub-regions, the modeling process is relatively complex and it is difficult to adapt to arbitrary irregular layouts.

[0007] (3) Chinese invention patent application with publication number CN108733869A discloses a large-scale three-dimensional integrated circuit partitioning method. The method adopts uniform partitioning of equal size, tree partitioning or thermal conduction path field correction partitioning, and improves the calculation accuracy of equivalent thermal conductivity by gradually refining the partitioning. Since the method requires multiple iterations of simulation and error judgment, the partitioning strategy depends on the temperature variance or thermal conduction path field calculation, and the process is relatively complicated.

[0008] In summary, existing equivalent modeling and order reduction methods still have the following common problems: most methods are only applicable to periodic regular distributions and have poor adaptability to the aperiodic, asymmetric, and irregular wiring structures commonly found in actual integrated circuits; they require pre-trained lookup tables, spectral analysis, iterative partitioning, or large-scale matrix factorization, which raises the implementation threshold; different structures require remodeling or retraining, making rapid transfer difficult. Summary of the Invention

[0009] The purpose of this invention is to provide a multi-scale numerical modeling method and related apparatus for integrated circuit thermal analysis, thereby solving one or more technical problems existing in the aforementioned equivalent modeling and order reduction methods. The technical solution disclosed in this invention is a simple, universal, and efficient multi-scale thermal analysis modeling method that can significantly reduce the number of meshes, improve computational efficiency, overcome the limitations of periodicity assumptions, adapt to various integrated circuit layouts (i.e., suitable for thermal simulation of integrated circuits with periodic symmetric or aperiodic asymmetric structural features), requires no extensive pre-calculation, does not rely on complex mathematical tools, and balances accuracy and efficiency.

[0010] To achieve the above objectives, the present invention adopts the following technical solution: In a first aspect, the present invention provides a multi-scale numerical modeling method for thermal analysis of integrated circuits, comprising: Obtain the geometric model and material distribution information of the integrated circuit to be analyzed; The material distribution information is configured into the geometric model by calling the finite element analysis software to obtain the integrated circuit geometric model with material properties. The structured mesh is generated by using cubic elements with a feature size larger than that of the internal micro-components to obtain a set of coarse mesh elements. Based on the set of coarse grid cells, the volume percentage of each material in each coarse grid cell is calculated, and the equivalent thermal conductivity of each coarse grid cell is calculated using an analytical thermal conductivity model. The calculated equivalent thermal conductivity is assigned to the corresponding coarse mesh element to construct a macroscopic equivalent model. Boundary conditions and heat source loads are applied to the macroscopic equivalent model, and thermal analysis is performed to obtain the temperature field distribution results of the integrated circuit to be analyzed.

[0011] A further improvement of the technical solution of the present invention is that, in the set of coarse mesh units, the boundaries of each coarse mesh unit are located in the same or different material regions, and the boundaries of each coarse mesh unit are located in the same or different geometric structure regions.

[0012] A further improvement of the technical solution of the present invention is that, in the step of using cubic units with a feature size larger than that of the internal micro-elements for structured mesh generation, the feature size of the unit is more than twice that of the feature size of the internal micro-elements.

[0013] A further improvement of the technical solution of the present invention is that the step of calculating the volume percentage of each material in each coarse grid cell is to count the materials contained in each coarse grid cell and calculate the volume ratio of each material based on the statistical results.

[0014] A further improvement to the technical solution of this invention lies in that, during the calculation of the equivalent thermal conductivity of each coarse grid element using the analytical thermal conductivity model, when the heat flow direction is parallel to the alternating material arrangement direction, a series model is used to calculate the equivalent thermal conductivity, expressed as: ; In the formula, Indicates the series equivalent thermal conductivity; λ mx and λ rf These represent the thermal conductivity of the matrix phase material and the reinforcing phase material, respectively. c mx and c rf These represent the volume percentages of the matrix phase material and the reinforcing phase material, respectively.

[0015] A further improvement to the technical solution of this invention lies in that, during the calculation of the equivalent thermal conductivity of each coarse grid element using the analytical thermal conductivity model, when the heat flow direction is perpendicular to the material alternation direction, a parallel model is used to calculate the equivalent thermal conductivity, expressed as: ; In the formula, Indicates the equivalent thermal conductivity in parallel; λ mx and λ rf These represent the thermal conductivity of the matrix phase material and the reinforcing phase material, respectively. c mx and c rf These represent the volume percentages of the matrix phase material and the reinforcing phase material, respectively.

[0016] A second aspect of the present invention provides a multi-scale numerical modeling system for thermal analysis of integrated circuits, comprising: The data acquisition module is used to acquire the geometric model and material distribution information of the integrated circuit to be analyzed; The coarse mesh generation module is used to call finite element analysis software, configure the material distribution information into the geometric model, obtain an integrated circuit geometric model with material properties, and perform structured mesh generation using cubic elements with unit feature size larger than the feature size of internal micro-components to obtain a coarse mesh unit set. The equivalent thermal conductivity calculation module is used to calculate the volume percentage of each material in each coarse grid cell based on the coarse grid cell set, and to calculate the equivalent thermal conductivity of each coarse grid cell using an analytical thermal conductivity model. The thermal analysis solution module is used to assign the calculated equivalent thermal conductivity to the corresponding coarse mesh element, construct a macroscopic equivalent model, apply boundary conditions and heat source loads to the macroscopic equivalent model, perform thermal analysis solution, and obtain the temperature field distribution result of the integrated circuit to be analyzed.

[0017] In a third aspect, the present invention provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements a multi-scale numerical modeling method for thermal analysis of integrated circuits as described in any one of the first aspects of the present invention.

[0018] In a fourth aspect, the present invention provides a non-transitory computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the multi-scale numerical modeling method for thermal analysis of integrated circuits as described in any one of the first aspects of the present invention.

[0019] In a fifth aspect, the present invention provides a computer program product storing computer instructions, which, when executed by a processor, implement the steps of the multi-scale numerical modeling method for thermal analysis of integrated circuits as described in any one of the first aspects of the present invention.

[0020] Compared with the prior art, the present invention has the following beneficial effects: This invention discloses a multi-scale numerical modeling method for thermal analysis of integrated circuits, constructing a complete technical route of "structured coarse mesh discretization, unit-level equivalent thermal conductivity analytical calculation, and macroscopic equivalent finite element solution". This invention abandons the periodicity assumption limitation of existing equivalent methods, does not require a large amount of pre-training and pre-computation, and does not rely on complex mathematical order reduction operations. It can adapt to any integrated circuit layout, such as periodic symmetric and aperiodic asymmetric. While ensuring the accuracy of thermal analysis, it significantly reduces the mesh size and computation time. The algorithm is simple and easy to implement, and can be directly integrated into the existing Electronic Design Automation (EDA) design process, taking into account versatility, efficiency, and engineering feasibility.

[0021] Specifically, addressing the problem of exploding mesh count and low computational efficiency caused by the multi-scale characteristics of existing traditional finite element methods, this invention establishes a macroscopic equivalent model and replaces the fine mesh with a structured coarse mesh. This allows each coarse mesh cell to contain multiple microscopic materials, and the equivalent thermal conductivity is calculated based on the volume percentage, thereby reducing the number of mesh cells by 1-2 orders of magnitude. This significantly reduces the degrees of freedom in the finite element solution, greatly improving computational efficiency while maintaining computational accuracy. Addressing the problem that existing equivalent methods rely on the assumption of global periodicity and cannot effectively handle aperiodic and asymmetric structures, this invention does not require the integrated circuit structure to be periodic or uniform. It directly calculates the equivalent thermal conductivity based on the actual volume percentage of each material within each coarse mesh cell, uniformly handling the distribution of through-silicon vias, solder balls, and interconnects. This allows the solution to be directly applied to complex integrated circuit layouts, including non-uniform through-silicon via arrays, irregular wiring layers, and variable-density microbump regions. Addressing the issues of existing lookup table or data-driven methods requiring extensive pre-training and lacking versatility, this invention eliminates the need for pre-establishing any lookup tables or performing any offline training or pre-simulation. The equivalent thermal conductivity is calculated directly and instantly based on the material distribution and volume percentage of the current integrated circuit using an analytical series / parallel model. This approach exhibits natural adaptability to different structures and eliminates the need for retraining. In summary, the technical solution of this invention involves only: reading the geometric model and material distribution; generating a structured cube coarse mesh; statistically analyzing the material volume percentage within each element; analytically calculating the equivalent thermal conductivity based on the series / parallel model; and solving the macroscopic equivalent model using the finite element method. The entire process avoids complex mathematical operations such as eigenvalue decomposition, Lyapunov equations, singular value decomposition, and graph partitioning. The algorithm has low complexity, is easy to program, and can be easily integrated into existing EDA workflows, solving the technical challenges of algorithmic complexity and engineering implementation difficulties inherent in existing equivalent modeling and order reduction methods. Attached Figure Description

[0022] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0023] Figure 1 This is a flowchart illustrating a multi-scale numerical modeling method for thermal analysis of integrated circuits, as described in an embodiment of the present invention. Figure 2 This is a schematic diagram of a typical integrated circuit in a specific embodiment of the present invention; Figure 3This is a flowchart illustrating a multi-scale numerical modeling method for typical integrated circuits in a specific embodiment of the present invention. Figure 4 This is a schematic diagram of a series model in a specific embodiment of the present invention; Figure 5 This is a schematic diagram of the parallel model in a specific embodiment of the present invention; Figure 6 This is a perspective view of a periodic symmetric integrated circuit in a specific embodiment of the present invention; Figure 7 yes Figure 6 Schematic diagram of cross-section 1-1 of the embodiment shown; Figure 8 This is a schematic diagram of a tetrahedral cell grid of a periodically symmetric integrated circuit in a specific embodiment of the present invention; Figure 9 This is a schematic diagram of a cubic cell grid of a periodic symmetric integrated circuit in a specific embodiment of the present invention; Figure 10 This is a temperature contour map of a periodically symmetric integrated circuit in a specific embodiment of the present invention; Figure 11 This is a schematic diagram of the temperature distribution along a specified path of a periodically symmetric integrated circuit in a specific embodiment of the present invention; Figure 12 This is a schematic diagram of an aperiodic asymmetric integrated circuit in a specific embodiment of the present invention; Figure 13 This is a schematic diagram of a tetrahedral cell grid of an aperiodic asymmetric integrated circuit in a specific embodiment of the present invention; Figure 14 This is a schematic diagram of a cubic cell grid of an aperiodic asymmetric integrated circuit in a specific embodiment of the present invention; Figure 15 This is a specific embodiment of the present invention, showing a temperature cloud map of an aperiodic asymmetric integrated circuit and a schematic diagram of temperature distribution along a specified path; Figure 16 This is a schematic diagram of a multi-scale numerical modeling system for thermal analysis of integrated circuits in an embodiment of the present invention. The explanations of the reference numerals in the figure are as follows: 1. Printed circuit board; 2. First filler material; 3. Substrate; 4. Chip; 5. Package; 6. Through silicon via; 7. Microbump; 8. Second filler material; 9. Solder ball. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of protection of the present invention, but rather to illustrate specific selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0025] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. It should be noted that, unless otherwise specified, the following embodiments and features can be combined with each other.

[0026] Please see Figure 1 The present invention provides a multi-scale numerical modeling method for thermal analysis of integrated circuits, comprising the following steps: Step 1: Obtain the geometric model and material distribution information of the integrated circuit to be analyzed; Step 2: Call the finite element analysis software, configure the material distribution information into the geometric model, obtain the integrated circuit geometric model with material properties, and use regular cubic elements with unit feature size larger than the feature size of internal micro-components to perform structured meshing to obtain a set of coarse mesh elements; Step 3: Based on the set of coarse grid cells, the volume percentage of each material in each coarse grid cell is statistically calculated, and the equivalent thermal conductivity of each coarse grid cell is calculated using an analytical thermal conductivity model. Step 4: Assign the equivalent thermal conductivity obtained in Step 3 to the corresponding coarse mesh elements to obtain the macro equivalent model (i.e., the macro equivalent finite element model); apply boundary conditions and heat source loads to the macro equivalent model, perform thermal analysis and solve to obtain the temperature field distribution results of the integrated circuit.

[0027] The technical solution disclosed in this invention employs a large-size structured coarse mesh generation technique, abandoning the traditional fine meshing method that closely conforms to the microstructure. This significantly reduces the overall mesh count and the degrees of freedom in the finite element solution. While ensuring the accuracy of thermal simulation, it effectively avoids the mesh explosion problem caused by multi-scale structures, significantly reducing computational power consumption and shortening simulation calculation time, thus solving the problems of mesh explosion and low computational efficiency in traditional finite element methods. Furthermore, by using techniques such as statistically calculating the material volume percentage for each coarse mesh element and independent equivalent modeling of each element, there is no need to impose periodic or uniform constraints on the integrated circuit structure, allowing for self-constraint. This invention adapts to various complex layouts, including periodically symmetric, aperiodically asymmetric, irregular wiring, and non-uniform silicon via arrays, greatly expanding the applicability of thermal analysis modeling and solving the problems of existing equivalent modeling relying on periodic assumptions and lacking versatility. It utilizes a technique that directly solves for equivalent thermal conductivity based on material volume percentage combined with analytical models, eliminating the need for pre-built sample databases, lookup tables, offline pre-simulation, and model training. It can perform real-time equivalent property calculations for any structure under analysis, resulting in a simpler modeling process with no redundant preprocessing work. This solves the problem of extensive pre-calculation and pre-training required by current data-driven and lookup table methods. In summary, this invention employs a simple process of basic geometric modeling, structured mesh generation, analytical formula equivalent calculation, and conventional finite element solution. It does not involve complex high-order mathematical operations such as singular value decomposition, Lyapunov equations, or graph partitioning. The algorithm logic is simple, the programming implementation is easy, and it can be easily integrated into existing electronic design automation simulation processes, demonstrating strong engineering applicability.

[0028] Please see Figure 2 and Figure 3 In a specific embodiment of the present invention, a multi-scale numerical modeling method for thermal analysis of integrated circuits is provided.

[0029] Figure 2This diagram illustrates a typical integrated circuit, employing a bottom-up hierarchical stacked structure. The printed circuit board (PCB) 1 serves as the bottom layer of the entire package, providing mechanical support, circuit wiring, and a heat dissipation base for all upper-layer packaged devices. Solder balls 9 are arrayed on the upper side of the PCB 1, enabling electrical signal transmission and mechanical fixation between the PCB and the upper-layer packaged structure, ensuring electrical connectivity and structural stability. A first filler material 2 fills the gaps between adjacent solder balls 9, effectively filling the gaps and providing cushioning, shock absorption, insulation, and auxiliary heat conduction. A substrate 3 is fixedly mounted above the solder balls 9, serving as a middle-layer transition structure connecting the bottom circuitry to the upper-layer chip stack. Multiple layers of chips 4 are stacked on the upper side of the substrate 3, forming a three-dimensional stacked integrated structure, effectively increasing the integration density of the integrated circuit. Through-silicon vias (TSVs) 6 are vertically penetrating within each layer of chip 4, enabling vertical electrical interconnection and heat conduction. Adjacent layers of chips 4 are precisely connected and electrically connected via micro-bumps 7, achieving multi-layer chip interconnection and integration. The gap between chip 4 and microbump 7 is filled with a second filler material 8, which optimizes interlayer heat transfer performance and simultaneously achieves insulation protection and structural reinforcement. Package 5 covers the outermost part of all core components such as chip, substrate, and microbump, providing all-round coverage and sealing for the entire stacked structure. This effectively isolates external moisture, dust, and mechanical stress, achieving physical protection and environmental isolation for internal core components, and ensuring long-term stable operation of the integrated circuit.

[0030] Figure 3 Showing the target Figure 2 The multi-scale numerical modeling process for the circuit shown includes: Step (a): Obtain the geometric model and material distribution information of the integrated circuit structure.

[0031] Specifically, it may include various structural layers (such as substrate, redistribution layer, interposer layer, chip layer, solder ball array, etc., as shown in the appendix). Figure 2 The geometric dimensions, material properties (thermal conductivity, density, specific heat capacity, etc.) and spatial distribution of internal components are shown.

[0032] In a specific exemplary technical solution, a three-dimensional geometric model file (STP format) of an integrated circuit is exported through integrated circuit design software (such as Cadence), which includes the geometric dimensions of each layer structure (such as substrate, redistribution layer, interposer layer, chip layer, solder ball array, etc.); the three-dimensional geometric model file of the integrated circuit is imported into finite element software (such as Wavenology), and different structures are assigned corresponding material properties (thermal conductivity, density, specific heat capacity, etc.) to obtain the spatial distribution of internal components and materials.

[0033] Step (b) involves performing a structured coarse mesh partitioning on the integrated circuit structure.

[0034] Specifically, the overall structure is discretized using large-size cubic elements, and each coarse grid element may contain multiple materials (such as copper interconnects and FR-4 filler material). The element size is much larger than the feature size of the internal micro-components, but strict conformal preservation with the structural boundaries is not required.

[0035] Each coarse grid cell contains one or more structural materials, simultaneously covering various micro-components within integrated circuits, such as metal interconnects, dielectric filling, silicon substrates, micro-bumps, and through-silicon vias. The overall cell size of the coarse grid is significantly larger than the feature sizes of the various micro-components within it, enabling the unified inclusion of multi-scale microstructures within a single macro-grid cell. The structured coarse grid employs a regular and unified mesh partitioning method, with mesh boundaries that can span different material regions and structural interfaces. It achieves uniform partitioning across the entire domain through an integrated macro-grid layout, maintaining mesh topological regularity and dimensional consistency, significantly simplifying the mesh partitioning process, and effectively avoiding the mesh number explosion problem caused by the fine structural features of traditional fine grids.

[0036] Step (c) Calculate the volume percentage of each material within each coarse grid cell.

[0037] Specifically, this step involves calculating the volume ratio of each material in each unit based on the material distribution information; this step does not depend on the periodicity or regularity of the structure and is applicable to any material distribution.

[0038] Step (d) calculates the equivalent thermal conductivity of each coarse grid cell.

[0039] Please see Figure 4 and Figure 5 Specifically, in this step, the equivalent thermal conductivity of each unit is calculated as follows: When the direction of heat flow is parallel to the direction of material alternation, see Figure 4 The equivalent thermal conductivity is calculated using a series model: ; In the formula, Indicates the series equivalent thermal conductivity; λ mx and λ rf represents the thermal conductivity of the matrix phase material and the reinforcing phase material, respectively, in W / (m·℃); c mx and c rf These represent the volume percentages of the matrix phase material and the reinforcing phase material, respectively.

[0040] When the heat flow direction is perpendicular to the material alternation direction, see Figure 5 The equivalent thermal conductivity is calculated using a parallel model: ; In the formula, This represents the equivalent thermal conductivity in parallel.

[0041] Step (e) establishes a macroscopic equivalent model. Specifically, each coarse mesh element can be regarded as a homogeneous anisotropic material, and a corresponding equivalent thermal conductivity can be assigned to construct a macroscopic equivalent model. The number of elements in this model is much smaller than that in the traditional finite element model.

[0042] Step (f) involves performing steady-state or transient thermal analysis. Specifically, boundary conditions (such as temperature boundaries, heat flow boundaries, and convective heat transfer boundaries) and heat source loads are applied to the macroscopic equivalent model constructed above, and the temperature field distribution is solved using the finite element method.

[0043] The technical solutions disclosed in the embodiments of the present invention have the following significant advantages: (1) Wide range of applications: It does not depend on the global periodicity of the structure and is applicable to both periodic symmetric and aperiodic asymmetric integrated circuit structures, including complex layouts such as irregular silicon via distribution and non-uniform wiring.

[0044] (2) High computational efficiency: The coarse mesh macroscopic equivalent model is adopted, which significantly reduces the number of elements. The experimental results show that for aperiodic asymmetric structures, the computation time can be reduced to less than 1 / 8 of that of the traditional method.

[0045] (3) High calculation accuracy: The relative error of the highest temperature predicted by the equivalent model does not exceed 2%, and the temperature field distribution is highly consistent with the traditional finite element model.

[0046] (4) Simple to implement: No need for pre-trained lookup tables, no need for complex mathematical reduction, no need for iterative partitioning, only volume percentage statistics and basic formulas are needed, which can be easily integrated into existing EDA processes.

[0047] (5) Strong parameter adaptability: The calculation accuracy and efficiency can be balanced by adjusting the number of grids, which is convenient for engineering applications.

[0048] Please see Figures 6 to 11 In a specific embodiment of the present invention, the thermal analysis of the periodic symmetric integrated circuit structure is as follows.

[0049] The embodiments of the present invention are based on Figure 6 and Figure 7Taking a periodically symmetric three-dimensional integrated circuit (3D IC) structure as an example, the specific implementation process of the method of the present invention on a periodically symmetric structure will be described in more detail. This 3D IC includes nine through-silicon vias (TSVs), a copper pillar array, a printed circuit board (PCB), a silicon dioxide layer, a chip, a memory chip, a cylindrical pin-shaped heat sink, micro-bumps, and filler material. The TSVs are periodically and uniformly distributed throughout the structure; the chip size is on the millimeter scale, while the TSV diameter is 30 μm, and the silicon dioxide layer thickness is only 1 μm, exhibiting typical multi-scale characteristics.

[0050] The specific analysis process is as follows: Step 1: Obtain the geometric model and material distribution information of the integrated circuit; wherein, the geometric model file (such as STP format) of the integrated circuit is read through the interface of finite element software (such as Wavenology) to obtain the stacking order of each layer; and the material properties are assigned to the corresponding components in the finite element software.

[0051] In this embodiment of the invention, the materials include copper, silicon, silicon dioxide, FR-4, solder, BGA filler, and PCB, with thermal conductivity values ​​of 396.7 W / (m·℃), 154.3 W / (m·℃), 1.5 W / (m·℃), 0.38 W / (m·℃), 49.2 W / (m·℃), 10.4 W / (m·℃), and 0.49 W / (m·℃), respectively. The heat source is set as a uniform heat source located within the top memory chip, with a power of 9 × 10⁻⁶. - ³ W.

[0052] Step 2: Structured coarse mesh generation.

[0053] This invention employs cubic cells to perform structured coarse mesh generation on the entire integrated circuit. Each cell typically contains multiple materials (such as copper pillars, silicon dioxide, silicon substrate, etc.). Mesh generation does not require conformal preservation of geometric boundaries; cell boundaries can pass through material interfaces. This is one of the key differences between this invention and the traditional finite element method, which requires conformal mesh generation. Considering the balance between computational accuracy and efficiency, the final number of coarse mesh cells is determined after convergence testing.

[0054] Step 3: Calculate the volume percentage of each material within each coarse grid cell.

[0055] For each cubic cell, determine the types of materials contained within it and their respective volumes. Specifically, using the stack-up structure and material distribution map of the integrated circuit, the cell space is superimposed with each material region to calculate the volume percentage of each material within the cell; for example, a cell located in the TSV region might contain copper (approximately 0.15% by volume) and silicon (approximately 0.85% by volume). The volume percentage data is stored as a cell attribute for subsequent calculation of equivalent thermal conductivity.

[0056] Step 4: Calculate the equivalent thermal conductivity of each unit.

[0057] In this embodiment of the invention, the integrated circuit substrate, redistribution layer, and interposer layer exhibit a typical layered composite material structure: in the horizontal direction (x, y direction), copper interconnects and FR-4 are arranged alternately, and heat flow needs to pass through the two materials alternately. Therefore, a series model is used to calculate the equivalent thermal conductivity in the x and y directions; in the vertical direction (z direction), copper and FR-4 transfer heat independently and simultaneously. Therefore, a parallel model is used to calculate the equivalent thermal conductivity in the z direction.

[0058] Step 5: Establish a macroscopic equivalent model.

[0059] In this embodiment of the invention, each cubic unit is considered as a uniform anisotropic material, and the calculated... λ x , λ y , λ z The element thermal conductivity matrix is ​​formed, generating a coarse mesh file containing equivalent thermal conductivity information. This coarse mesh file is then imported into finite element software (such as ANSYS). Boundary conditions are applied: the bottom PCB surface temperature is fixed at 25°C. A heat source load is applied to the top memory chip. This forms an analyzable macroscopic equivalent model.

[0060] Step 6: Solve for the temperature field distribution.

[0061] In this embodiment of the invention, steady-state thermal analysis is performed on the macroscopic equivalent model established in step 5 in finite element software (such as ANSYS) to obtain the temperature distribution of the entire integrated circuit.

[0062] Step 7: Result comparison and verification.

[0063] Please see Figure 8 and Figure 9 To verify the accuracy and efficiency of this invention, a comparison was made with a traditional finite element model. The traditional model uses conformal tetrahedral meshes, with a maximum permissible element size of 5 × 10⁻⁶. -5 m, generating 196,293 units (Model 1, such as...) Figure 8 (As shown) and 4,407,581 elements (Model 2, as a reference solution). The macroscopic equivalent model of this invention contains only 90,000 cubic elements, such as Figure 9 As shown. The temperature contour plots of the three models are as follows. Figure 10 As shown. The temperature distribution along the same path is extracted from the three models, as follows: Figure 11 As shown.

[0064] Depend on Figure 10It can be seen that the highest temperature predicted by the technical solution of this invention is 32.08℃, and the relative error with the reference model (32.17℃) is 0.28%, which is better than the 0.65% error of the traditional finite element model (Model 1) using large-size elements. Figure 11 It can be seen that, regarding the temperature distribution along the specified path, the relative error between the present invention and the reference model (Model 2) is 0.22%, lower than the 0.49% of Model 1. Furthermore, the computation time of the present invention is 17 seconds, Model 1's computation time is 36 seconds, and Model 2's computation time is 3720 seconds. Therefore, for periodically symmetric integrated circuit structures, the method of the present invention significantly improves efficiency while maintaining high accuracy.

[0065] Please see Figures 12 to 15 In a specific embodiment of the present invention, the thermal analysis of the aperiodic asymmetric integrated circuit structure is as follows.

[0066] The embodiments of the present invention are based on Figure 12 Taking an aperiodic asymmetric integrated circuit structure as an example, the implementation process of the method of the present invention in complex and irregular layouts is further illustrated. This structure is a substrate model with a ball grid array (BGA) and a PCB, with overall dimensions of 5mm × 5mm × 0.982mm. The substrate itself is 0.252mm thick and contains 9 stacked layers: layers 2, 4, 6, and 8 are routing layers (RDL), layers 3, 5, and 7 are copper pillars connecting the routing layers, layer 1 connects to the chip, and layer 9 connects to the BGA. The BGA is 0.23mm thick, and the PCB is 0.5mm thick. The interconnect material is copper, the filler material is FR-4, the BGA material is solder, and the gaps are filled with epoxy resin. The heat source is a 0.5W surface heat source applied to the top chip, and the surface temperature of the bottom PCB is maintained at 25°C. This structure lacks global periodicity, and the distribution of TSVs, copper pillars, and RDL nets is highly irregular, making it difficult to directly apply the traditional equivalent method based on a representative volume element (RVE).

[0067] The specific analysis process is as follows: Step 1: Obtain the geometric model and material distribution information; This involves using finite element software (such as Wavenology) to read the complete geometric description file (STP format) of the substrate-BGA-PCB structure. The file contains the precise geometric boundaries of the nine layers and the wiring diagrams of the copper interconnects within each layer (e.g., ...). Figure 12 The positions of the copper pillars (non-uniform spacing) and the BGA solder ball array (also not completely uniform) are shown. The thermal conductivity (copper: 396.7 W / (m·℃), FR-4: 0.38 W / (m·℃), solder: 49.2 W / (m·℃), epoxy resin: 10.4 W / (m·℃)) and density of each material are assigned to the corresponding components.

[0068] Step 2: Structured Coarse Mesh Generation. Given the distinct layered characteristics of the structure, cells are generated along the z-axis based on the actual layer thickness: at least one cell for each of layers 1 to 9, and multiple cells for both the BGA and PCB. Each cell contains multiple materials (copper, FR-4, etc.). Mesh generation does not require alignment with the boundaries of integrated circuit components. The final number of coarse mesh cells is determined after convergence testing.

[0069] Step 3: Calculate the volume percentage of each material within each coarse grid cell. For each cubic cell, determine the types of materials contained within it and their respective volumes. Specifically, using the stack-up structure of integrated circuits and material distribution maps, the cell space is overlaid with each material region to calculate the volume ratio of each material within that cell. All volume percentage data are stored in the cell attribute array.

[0070] Step 4: Calculate the equivalent thermal conductivity of each cell. Similar to Example 1, a series model is used in the horizontal direction (x, y), and a parallel model is used in the vertical direction (z). For each cell in the substrate region, the equivalent thermal conductivity is calculated based on the volume percentage of copper and FR-4 within it. For the BGA region, the distribution of solder and epoxy resin can be considered as a two-phase composite material, and the series / parallel model is also applicable. For pure FR-4 or pure silicon regions, the equivalent thermal conductivity is directly taken as the thermal conductivity of the corresponding material.

[0071] Step 5: Establish a macroscopic equivalent model. This step assigns anisotropic equivalent thermal conductivity to each cubic element, based on the calculated values. λ x , λ y , λ z A unit thermal conductivity matrix is ​​formed, generating a coarse mesh file containing equivalent thermal conductivity information. This coarse mesh file is then imported into finite element software (such as Wavenology). A heat source load of 0.5W is applied uniformly to the corresponding unit nodes on the top layer of the substrate. A temperature boundary is applied: the temperature of all nodes on the bottom surface of the PCB is set to 25℃.

[0072] Step 6: Solve for the temperature field distribution. In finite element software (such as ANSYS), perform steady-state thermal analysis on the macroscopic equivalent model established in Step 5 to obtain the temperature distribution of the entire integrated circuit.

[0073] Step 7: Result Comparison and Verification. To verify the accuracy and efficiency of the method of this invention on aperiodic structures, a comparison is made with the traditional finite element model. Model 1 is a traditional coarse-mesh tetrahedral model with 1,683,530 elements, as shown below. Figure 13As shown. Model 2 is a refined tetrahedral model with 8,112,701 elements, and is used as a reference solution. The method of this invention contains 680,000 cubic elements, as shown. Figure 14 As shown. Finite element analysis yields temperature contour maps for the three models. The temperature distribution along the same path in each model is extracted, as follows. Figure 15 As shown.

[0074] Depend on Figure 15 It can be seen that the highest temperature predicted by the method of this invention is 41.91℃, while the reference model (Model 2) predicts 41.84℃, with a relative error of only 0.17%. In contrast, the traditional coarse-grid model (Model 1) predicts 39.14℃, with an error as high as 6.45%. Along the temperature distribution along the specified path, the relative error between the method of this invention and the reference model is 1.45%, which is better than Model 1's 2.0%. Furthermore, the computation time of the method of this invention is 240 seconds, while Model 1's computation time is 2071 seconds, and Model 2's computation time is 22860 seconds. The computational efficiency of the method of this invention on aperiodic asymmetric structures is 8.63 times that of the traditional finite element method coarse-grid model (Model 1), and its accuracy is significantly higher than that of the traditional coarse-grid model.

[0075] In summary, two specific embodiments demonstrate that the method of this invention achieves computational accuracy comparable to traditional finite element models for both periodically symmetric and aperiodic asymmetric integrated circuit structures, while significantly improving computational efficiency compared to traditional finite element models with large-size elements. Compared to existing lookup table methods (such as CN202510473389), the method of this invention does not require pre-training of lookup tables or iteration of temperature dependence coefficients, directly calculating the equivalent thermal conductivity based on volume percentage, thus achieving a simpler implementation.

[0076] The following are embodiments of the apparatus of the present invention, which can be used to execute embodiments of the method of the present invention. For details not disclosed in the apparatus embodiments, please refer to the embodiments of the method of the present invention.

[0077] Please see Figure 16 In this embodiment of the invention, a multi-scale numerical modeling system for thermal analysis of integrated circuits is provided, comprising: The data acquisition module is used to acquire the geometric model and material distribution information of the integrated circuit to be analyzed. The coarse mesh generation module is used to call finite element analysis software, configure the material distribution information into the geometric model, obtain an integrated circuit geometric model with material properties, and perform structured mesh generation using cubic elements with unit feature size larger than the feature size of internal micro-components to obtain a coarse mesh unit set. The equivalent thermal conductivity calculation module is used to calculate the volume percentage of each material in each coarse grid cell based on the coarse grid cell set, and to calculate the equivalent thermal conductivity of each coarse grid cell using an analytical thermal conductivity model. The thermal analysis solution module is used to assign the calculated equivalent thermal conductivity to the corresponding coarse mesh element, construct a macroscopic equivalent model, apply boundary conditions and heat source loads to the macroscopic equivalent model, perform thermal analysis solution, and obtain the temperature field distribution result of the integrated circuit to be analyzed.

[0078] In one embodiment of the present invention, a computer device is provided, comprising a processor and a memory. The memory stores a computer program, which includes program instructions. The processor executes the program instructions stored in the memory. The processor may be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, suitable for implementing one or more instructions, specifically suitable for loading and executing one or more instructions from a computer storage medium to achieve a corresponding method flow or corresponding function. The processor described in this embodiment of the present invention can be used to execute operations of a multi-scale numerical modeling method for integrated circuit thermal analysis.

[0079] In one embodiment of the present invention, a storage medium is provided, specifically a computer-readable storage medium (Memory), which is a memory device in a computer device used to store programs and data. It is understood that the computer-readable storage medium here can include both the built-in storage medium in the computer device and extended storage media supported by the computer device. The computer-readable storage medium provides storage space that stores the operating system of the terminal. Furthermore, the storage space also stores one or more instructions suitable for loading and execution by a processor, which can be one or more computer programs (including program code). It should be noted that the computer-readable storage medium here can be high-speed RAM (Random Access Memory) or non-volatile memory, such as at least one disk storage device. The processor can load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the multi-scale numerical modeling method for integrated circuit thermal analysis in the above embodiments.

[0080] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, optical storage, etc.) containing computer-usable program code.

[0081] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0082] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0083] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A multi-scale numerical modeling method for thermal analysis of integrated circuits, characterized in that, include: Obtain the geometric model and material distribution information of the integrated circuit to be analyzed; The material distribution information is configured into the geometric model by calling the finite element analysis software to obtain the integrated circuit geometric model with material properties. The structured mesh is generated by using cubic elements with a feature size larger than that of the internal micro-components to obtain a set of coarse mesh elements. Based on the set of coarse grid cells, the volume percentage of each material in each coarse grid cell is calculated, and the equivalent thermal conductivity of each coarse grid cell is calculated using an analytical thermal conductivity model. The calculated equivalent thermal conductivity is assigned to the corresponding coarse mesh element to construct a macroscopic equivalent model. Boundary conditions and heat source loads are applied to the macroscopic equivalent model, and thermal analysis is performed to obtain the temperature field distribution results of the integrated circuit to be analyzed.

2. The multi-scale numerical modeling method for thermal analysis of integrated circuits according to claim 1, characterized in that, In the set of coarse mesh cells, the boundaries of each coarse mesh cell are located in the same or different material regions, and the boundaries of each coarse mesh cell are located in the same or different geometric structure regions.

3. The multi-scale numerical modeling method for thermal analysis of integrated circuits according to claim 1, characterized in that, In the step of using cubic elements with a feature size larger than that of the internal micro-elements for structured mesh generation, the feature size of the element is more than twice that of the internal micro-elements.

4. The multi-scale numerical modeling method for thermal analysis of integrated circuits according to claim 1, characterized in that, The steps to calculate the volume percentage of each material in each coarse grid cell are as follows: count the materials contained in each coarse grid cell, and calculate the volume percentage of each material based on the statistical results.

5. The multi-scale numerical modeling method for thermal analysis of integrated circuits according to claim 1, characterized in that, In calculating the equivalent thermal conductivity of each coarse mesh element using the analytical thermal conductivity model, when the heat flow direction is parallel to the material alternation direction, a series model is used to calculate the equivalent thermal conductivity, and the expression is: ； In the formula, Indicates the series equivalent thermal conductivity; λ mx and λ rf These represent the thermal conductivity of the matrix phase material and the reinforcing phase material, respectively. c mx and c rf These represent the volume percentages of the matrix phase material and the reinforcing phase material, respectively.

6. The multi-scale numerical modeling method for thermal analysis of integrated circuits according to claim 1, characterized in that, In calculating the equivalent thermal conductivity of each coarse mesh element using the analytical thermal conductivity model, when the heat flow direction is perpendicular to the material alternation direction, a parallel model is used to calculate the equivalent thermal conductivity, expressed as: ； In the formula, Indicates the equivalent thermal conductivity in parallel; λ mx and λ rf These represent the thermal conductivity of the matrix phase material and the reinforcing phase material, respectively. c mx and c rf These represent the volume percentages of the matrix phase material and the reinforcing phase material, respectively.

7. A multi-scale numerical modeling system for thermal analysis of integrated circuits, characterized in that, include: The data acquisition module is used to acquire the geometric model and material distribution information of the integrated circuit to be analyzed. The coarse mesh generation module is used to call finite element analysis software, configure the material distribution information into the geometric model, obtain an integrated circuit geometric model with material properties, and perform structured mesh generation using cubic elements with unit feature size larger than the feature size of internal micro-components to obtain a coarse mesh unit set. The equivalent thermal conductivity calculation module is used to calculate the volume percentage of each material in each coarse grid cell based on the coarse grid cell set, and to calculate the equivalent thermal conductivity of each coarse grid cell using an analytical thermal conductivity model. The thermal analysis solution module is used to assign the calculated equivalent thermal conductivity to the corresponding coarse mesh element, construct a macroscopic equivalent model, apply boundary conditions and heat source loads to the macroscopic equivalent model, perform thermal analysis solution, and obtain the temperature field distribution result of the integrated circuit to be analyzed.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the multi-scale numerical modeling method for thermal analysis of integrated circuits as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the multi-scale numerical modeling method for thermal analysis of integrated circuits as described in any one of claims 1 to 6.

10. A computer program product storing computer instructions, characterized in that, When executed by a processor, the computer instructions implement the steps of the multi-scale numerical modeling method for thermal analysis of integrated circuits as described in any one of claims 1 to 6.

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