A neural network computer based on memristors
Patent Information
- Application Number
- CN202611225593.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-08-13
- Publication Date
- 2026-09-25
AI Technical Summary
随着神经网络规模增大，突触权重的传输量随之增加，容易造成较大的计算延迟和功耗
[0020]本发明通过将忆阻器单元的阻值用于存储突触权重，使忆阻器交叉阵列能够根据输入电压信号和突触权重输出加权电流信号，从而将突触权重存储和加权计算集成于忆阻器突触阵列模块中，减少权重传输过程，降低计算延迟和能耗；
Smart Images
Figure CN122819337A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of neural network hardware technology, and more specifically to a neural network computer based on memristors. Background Technology
[0002] Existing neural network computing devices typically employ a structure that separates storage and computation units. The synaptic weights of the neural network are stored in memory, and during computation, synaptic weights and intermediate computation results need to be frequently transferred between memory and the processor. As the size of the neural network increases, the amount of synaptic weight transfer also increases, which can easily lead to significant computational latency and power consumption.
[0003] Furthermore, existing neural network hardware is primarily used for inference; error calculation, gradient propagation, and synaptic weight updates during training still require external processors or host computers, making it difficult to perform training and inference within the neural network hardware itself. Therefore, there is a need for a neural network computer that can utilize the storage and computational characteristics of memristors and perform neural network training and inference. Summary of the Invention
[0004] The purpose of this invention is to provide a memristor-based neural network computer that can perform synaptic weight storage and weighted calculation in a memristor synaptic array, and perform error detection, gradient transfer and synaptic weight update in hardware.
[0005] To achieve the above objectives, the present invention provides the following technical solution:
[0006] To achieve the above objectives, the present invention provides a memristor-based neural network computer, comprising:
[0007] The module consists of a memristor synaptic array module, a neuron computing module, an error detection and gradient transfer module, a control module, and a power management module.
[0008] The memristor synaptic array module includes a memristor cross array for storing synaptic weights of the neural network, receiving input voltage signals, and outputting weighted current signals based on the input voltage signals and synaptic weights.
[0009] The neuron computing module is connected to the memristor synapse array module and is used to perform summation and activation processing on the weighted current signal to obtain the neuron output signal.
[0010] The error detection and gradient propagation module is connected to the neuron computing module and the memristor synapse array module, respectively. It is used to generate error current based on the neuron output signal and the tag signal, and to propagate the error current in reverse to each layer of memristor cross array to generate the corresponding gradient current.
[0011] The control module is connected to the memristor synaptic array module, the neuron computing module, and the error detection and gradient transfer module, respectively. It is used to configure the neural network topology, control the switching between training mode and inference mode, and adjust the resistance value of the corresponding memristor unit according to the gradient current.
[0012] The power management module is used to supply power to the memristor synaptic array module, the neuron computing module, the error detection and gradient transfer module, and the control module.
[0013] In some embodiments, the memristor cross array employs a three-dimensional stacked structure, with each layer including multiple row lines, multiple column lines, and memristor cells disposed at the intersection nodes of the row and column lines. The row lines are used to receive input voltage signals, the column lines are used to output weighted current signals, and the resistance value of the memristor cells is used to characterize synaptic weights.
[0014] In some embodiments, the memristor synapse array module further includes an address decoder and a redundancy repair unit. The address decoder is used to select the corresponding memristor cell; the redundancy repair unit includes redundant memristor cells for replacing faulty memristor cells in the memristor cross array.
[0015] In some embodiments, the neuron computation module includes a weighted summation circuit, an activation function hardware unit, and a neuron state storage unit. The weighted summation circuit receives weighted current signals and performs summation processing; the activation function hardware unit includes at least one of a ReLU activation module, a Sigmoid activation module, a Tanh activation module, and a spiking activation module; the neuron state storage unit stores the neuron's activation threshold and historical states.
[0016] In some embodiments, the error detection and gradient propagation module includes an error detection circuit, a gradient propagation network, and a gradient amplification and calibration unit. The error detection circuit compares the neuron output signal and the label signal to generate an error current; the gradient propagation network propagates the error current from the output layer back to each hidden layer; and the gradient amplification and calibration unit amplifies the gradient current and compensates for device differences between memristor units.
[0017] In some embodiments, the control module includes a microcontroller unit, a timing control circuit, an algorithm adaptation unit, and a state monitoring unit. The microcontroller unit is used to configure the number of network layers, the number of neurons, and the operating mode of the neural network; the timing control circuit is used to generate timing signals corresponding to memristor cross array readout, resistance update, and activation processing; the algorithm adaptation unit is used to execute at least one of backpropagation learning logic and pulse time-dependent plasticity learning logic; and the state monitoring unit is used to monitor the resistance of the memristor unit, the module temperature, and the power supply voltage.
[0018] In some embodiments, the power management module includes a multi-channel power chip, a dynamic power allocation unit, and a protection circuit. The multi-channel power chip is used to output different voltages; the dynamic power allocation unit is used to adjust the power supply of each module according to the training mode or inference mode; and the protection circuit is used to provide electrostatic discharge protection and overvoltage protection for each module.
[0019] This invention provides a neural network computer based on memristors, which has the following advantages:
[0020] This invention uses the resistance value of the memristor unit to store synaptic weights, enabling the memristor cross array to output a weighted current signal based on the input voltage signal and synaptic weights. This integrates synaptic weight storage and weighted calculation into the memristor synaptic array module, reducing the weight transmission process and lowering computational latency and energy consumption.
[0021] Furthermore, the error detection and gradient propagation module can generate an error current based on the neuron output signal and the label signal, and propagate the error current in reverse to the memristor cross array of each layer to generate the corresponding gradient current, thereby realizing error calculation and gradient propagation within the hardware.
[0022] Furthermore, the control module can adjust the resistance of the memristor unit according to the gradient current to realize synaptic weight update, reduce dependence on external software algorithms and processors, and improve the autonomous training capability of the neural network computer.
[0023] Furthermore, based on the memristor-based in-memory computing structure and hardware-based training mechanism, it is possible to reduce data transmission and software computation processes in traditional CPU and GPU architectures, thereby reducing the power consumption of large-scale neural networks.
[0024] Furthermore, by setting up redundant repair units, gradient amplification and calibration units, and status monitoring units, the stability and reliability of the memristor synapse array and its various functional modules are improved. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the module structure of a neural network computer based on memristors according to the present invention;
[0026] Figure 2 This is a schematic diagram of the structure of the memristor synapse array module in this invention;
[0027] Figure 3 This is a schematic diagram illustrating the training and inference process of a memristor-based neural network computer according to the present invention. Detailed Implementation
[0028] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0029] Example 1
[0030] Please see Figure 1 This embodiment provides a memristor-based neural network computer, including a memristor synapse array module, a neuron computing module, an error detection and gradient transfer module, a control module, and a power management module. Each module is integrated on a silicon substrate and connected via interconnect lines.
[0031] The memristor synaptic array module serves as the storage and computation unit for synaptic weights in the neural network; the neuron computation module is used to perform weighted summation and activation processing; the error detection and gradient propagation module is used to generate error current and gradient current; the control module is used to control network configuration, mode switching, and memristor unit resistance updates; and the power management module is used to supply power to each module.
[0032] 1. Memristor synapse array module
[0033] Please see Figure 2 The memristor synapse array module includes a memristor cross array, an address decoder, and a redundancy repair unit.
[0034] The memristor cross array adopts a three-dimensional stacked structure. Each layer of the memristor cross array includes multiple row lines, multiple column lines, and memristor units located at the intersection nodes of the row lines and column lines.
[0035] Memristor units have multiple adjustable resistance states, and their resistance values are used to characterize synaptic weights in neural networks. Memristor units can be perovskite-based memristors, with resistance adjustable from 100Ω to 10MΩ and operating voltages from 0.1V to 1.5V.
[0036] In one example, the memristor cross array uses an 8-layer stacked structure, with each layer having a size of 2048×2048. The number of layers and the array size can be adjusted according to the number of network layers, neurons, and synaptic weights in the neural network.
[0037] The input voltage signal is applied to the row lines of the memristor cross array. After passing through the corresponding memristor cells, the input voltage signal forms a weighted current signal on the column lines. Thus, the memristor cross array uses the resistance values of the memristor cells to perform a weighted calculation of the input voltage signal and synaptic weights.
[0038] The address decoder is connected to the row and column lines and is used to select the corresponding memristor unit based on the address information output by the control module in order to perform a read operation or a resistance update operation.
[0039] The redundancy repair unit comprises multiple redundant memristor units. When the control module detects a fault in a memristor unit in the memristor cross array, it switches the faulty memristor unit to the corresponding redundant memristor unit.
[0040] 2. Neuron Computation Module
[0041] The neuron computation module includes a weighted summation circuit, an activation function hardware unit, and a neuron state storage unit.
[0042] The weighted summation circuit can employ an operational transconductance amplifier to receive the weighted current signal output from the memristor cross array and perform summation processing on the weighted current signal.
[0043] The activation function hardware unit is used to activate the summed signal. The activation function hardware unit includes at least one of the following: ReLU activation module, Sigmoid activation module, Tanh activation module, and pulse activation module.
[0044] The ReLU activation module can be composed of a diode and an adjustable resistor; the Sigmoid activation module and the Tanh activation module can utilize the nonlinear current-voltage characteristics of the transistor for activation; the pulse activation module can be composed of a comparator and a pulse generator, and can use pulse frequency encoding or pulse time encoding.
[0045] The neuron state storage unit uses memristors to store the activation threshold and historical state of neurons, so as to retain the stored neuron state after power failure.
[0046] 3. Error Detection and Gradient Transfer Module
[0047] The error detection and gradient transfer module includes an error detection circuit, a gradient transfer network, and a gradient amplification and calibration unit.
[0048] The error detection circuit includes a differential amplifier, which compares the neuron output signal and the label signal in the output layer of the neural network and generates an error current.
[0049] The gradient transfer network employs a hardware chain-coupled structure, including capacitive coupling circuits and current amplification circuits. The gradient transfer network propagates the error current from the output layer back to each hidden layer, generating the corresponding gradient current for each layer.
[0050] The gradient amplification and calibration unit includes an adaptive gain amplifier and a calibration circuit. The adaptive gain amplifier adjusts the amplification factor according to the intensity of the gradient current; the calibration circuit is used to compensate for device differences between different memristor units.
[0051] 4. Control Module
[0052] The control module includes a microcontroller unit, a timing control circuit, an algorithm adaptation unit, and a status monitoring unit.
[0053] The microcontroller unit can use a RISC-V architecture processor to configure the number of network layers, neurons, and connections in the neural network, and to control the switching between training and inference modes.
[0054] The timing control circuit is used to generate timing signals for memristor cross array reading, memristor cell resistance value updating, error propagation, and activation processing.
[0055] The algorithm adaptation unit is used to execute backpropagation learning logic and impulse time-dependent plasticity learning logic to adapt to convolutional neural networks or spiking neural networks.
[0056] The status monitoring unit is used to monitor the resistance of the memristor unit, the temperature of each module, and the power supply voltage. When the monitoring results exceed the preset range, the control module executes a shutdown or power-off protection.
[0057] 5. Power Management Module
[0058] The power management module includes a multi-channel power chip, a dynamic power allocation unit, and protection circuitry.
[0059] Multi-channel power chips are used to provide corresponding operating voltages to different modules, and their output voltage can be adjusted from 0.1V to 3.3V.
[0060] The power dynamic allocation unit is used to adjust the power supply of each module according to the status commands output by the control module. In inference mode, it reduces the power supply of the error detection and gradient transfer module; in training mode, it provides the power supply required for training to the error detection and gradient transfer module and the memristor synapse array module.
[0061] The protection circuit includes an anti-static protection circuit and an overvoltage protection circuit, which are used to prevent electrostatic discharge and voltage fluctuations from damaging the memristor unit and other modules.
[0062] Example 2
[0063] Please see Figure 3 This embodiment describes the inference process of a memristor-based neural network computer.
[0064] First, the control module switches the neural network computer to inference mode and controls the power management module to supply power to the memristor synapse array module, the neuron computing module, and the control module.
[0065] Externally input image signals, voice signals, or other input signals are converted into input voltage signals and applied to the row lines of the memristor cross array.
[0066] The memristor cross array outputs a weighted current signal on the column lines based on the input voltage signal and the resistance value of the memristor cells.
[0067] The neuron computation module performs summation and activation processing on the weighted current signal to obtain the neuron output signal of the current neural network layer.
[0068] When the current neural network layer is not an output layer, the neuron's output signal is input into the next neural network layer; when the current neural network layer is an output layer, the control module generates a prediction result based on the neuron's output signal and outputs the prediction result to an external device.
[0069] Example 3
[0070] This embodiment describes the training process of a memristor-based neural network computer.
[0071] First, the control module switches the neural network computer to training mode and performs the inference process based on the training samples to obtain the output signals of the neurons in the output layer of the neural network.
[0072] The error detection circuit compares the neuron's output signal with the label signal corresponding to the training sample to generate an error current.
[0073] The gradient propagation network propagates the error current from the output layer back to each hidden layer, generating the corresponding gradient current for each layer. The gradient amplification and calibration unit amplifies and calibrates the gradient current.
[0074] Gradient current flows through the corresponding memristor cell, causing a change in the resistance of the memristor cell. Specifically, gradient current in one direction decreases the resistance of the memristor cell, while gradient current in another direction increases the resistance of the memristor cell, thereby updating the corresponding synaptic weights.
[0075] The control module monitors the intensity of the error current. Training continues when the error current is not less than a preset error threshold; training stops when the error current is less than the preset error threshold. The trained synaptic weights are stored in the memristor synaptic array module in the form of memristor cell resistance values.
[0076] Example 4
[0077] This embodiment illustrates the fabrication and integration of a memristor-based neural network computer.
[0078] The memristor units can be made of formamidinium lead-iodide perovskite material and fabricated using magnetron sputtering and atomic layer deposition processes. The memristor layers can be connected to each other via copper pillars, and the interlayer insulating layer can be made of Al2O3 material.
[0079] The address decoder can be fabricated using CMOS technology and integrated with a memristor cross array. The control module can use a microcontroller unit based on a RISC-V architecture and connect to other modules via a communication interface.
[0080] The memristor synaptic array module, neuron computing module, error detection and gradient transfer module, control module, and power management module are integrated on a silicon substrate. After module integration, the power output, memristor unit resistance, address decoder, and connection status of each module are detected to put the neural network computer into operation.
[0081] The above describes specific embodiments of the present invention. Without departing from the technical concept of the present invention, the number of layers, array size, and module layout of the memristor cross array can be adjusted according to the memristor fabrication process and the scale of the neural network.
[0082] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A neural network computer based on memristors, characterized in that, include: Memristor synaptic array module, neuron computing module, error detection and gradient transfer module, control module and power management module; The memristor synapse array module includes a memristor cross array for storing synaptic weights of a neural network, receiving input voltage signals, and outputting weighted current signals based on the input voltage signals and the synaptic weights. The neuron computing module is connected to the memristor synapse array module and is used to perform summation and activation processing on the weighted current signal to obtain the neuron output signal. The error detection and gradient propagation module is connected to the neuron computing module and the memristor synapse array module, respectively. It is used to generate an error current based on the neuron output signal and the tag signal, and to propagate the error current in reverse to each layer of memristor cross array to generate the corresponding gradient current. The control module is connected to the memristor synapse array module, the neuron computing module and the error detection and gradient transfer module respectively, and is used to configure the neural network topology, control the switching between training mode and inference mode, and adjust the resistance value of the corresponding memristor unit according to the gradient current. The power management module is used to supply power to the memristor synaptic array module, the neuron computing module, the error detection and gradient transfer module, and the control module.
2. The memristor-based neural network computer according to claim 1, characterized in that, The memristor cross array adopts a three-dimensional stacked structure. Each layer of the memristor cross array includes multiple row lines, multiple column lines, and memristor units disposed at the intersection nodes of the row lines and the column lines. The row lines are used to receive the input voltage signal, the column lines are used to output the weighted current signal, and the resistance value of the memristor unit is used to characterize the synaptic weight.
3. The memristor-based neural network computer according to claim 2, characterized in that, The memristor synapse array module also includes an address decoder and a redundancy repair unit; The address decoder is used to select the corresponding memristor unit; The redundancy repair unit includes a redundant memristor unit for replacing a faulty memristor unit in the memristor cross array.
4. The memristor-based neural network computer according to claim 1, characterized in that, The neuron computing module includes a weighted summation circuit, an activation function hardware unit, and a neuron state storage unit. The weighted summation circuit is used to receive the weighted current signal and perform summation processing; The activation function hardware unit includes at least one of a ReLU activation module, a Sigmoid activation module, a Tanh activation module, and a pulse activation module; The neuron state storage unit is used to store the activation threshold and historical state of the neuron.
5. The memristor-based neural network computer according to claim 1, characterized in that, The error detection and gradient transfer module includes an error detection circuit, a gradient transfer network, and a gradient amplification and calibration unit. The error detection circuit is used to compare the neuron output signal and the label signal to generate the error current; The gradient transfer network is used to reverse the error current from the output layer of the neural network to each hidden layer; The gradient amplification and calibration unit is used to amplify the gradient current and compensate for device differences between memristor units.
6. The memristor-based neural network computer according to claim 1, characterized in that, The control module includes a microcontroller unit, a timing control circuit, an algorithm adaptation unit, and a status monitoring unit. The microcontroller unit is used to configure the number of network layers, the number of neurons, and the operating mode of the neural network. The timing control circuit is used to generate timing signals corresponding to memristor cross array read, resistance value update and activation processing; The algorithm adaptation unit is used to execute at least one of backpropagation learning logic and impulse time-dependent plasticity learning logic; The status monitoring unit is used to monitor the resistance, module temperature, and power supply voltage of the memristor unit.
7. The memristor-based neural network computer according to claim 1, characterized in that, The power management module includes a multi-channel power chip, a dynamic power allocation unit, and a protection circuit. The multi-channel power chip is used to output different voltages; The power consumption dynamic allocation unit is used to adjust the power supply of each module according to the training mode or the inference mode; The protection circuit is used to provide electrostatic discharge protection and overvoltage protection for each module.
8. The memristor-based neural network computer according to claim 1, characterized in that, The memristor synaptic array module, the neuron computing module, the error detection and gradient transfer module, the control module, and the power management module are integrated on a silicon substrate and connected by interconnect lines.