A state transition flow chart drawing method of a finite state machine

Abstract

The application relates to the technical field of programmable logic design and digital circuit design automation, and discloses a state transition flowchart drawing method of a finite state machine, which comprises the following steps: setting a module name box, setting clock cycle start and end marks, setting a main state machine judging box, connecting state branches corresponding to all states, executing condition judgment, function implementation and state assignment in the state branches, and nesting a sub-state machine structure in the state branches to complete flowchart drawing. The application combines the expression advantages of state transition diagrams and software flowcharts, can clearly and completely express state machine transition relations, nesting relations, complex logic relations and clock control relations, solves the defects that traditional drawing cannot consider state jumping and logic processing, and improves the accuracy, readability and engineering implementation efficiency of programmable logic design documents.

Description

Technical Field

[0001] This invention relates to the fields of programmable logic design and digital circuit design automation technology. Background Technology

[0002] In the engineering design of aerospace electronics and FPGA programmable logic control, finite state machines are the core technical means to realize complex logic control, data signal processing and timing coordination. Their operating logic is usually expressed by state transition diagrams or software flowcharts.

[0003] Traditional finite state machine state transition diagrams use state enumeration as the core expression method, focusing on showing the transition relationship between states. They can only briefly annotate the judgment conditions that trigger state transitions, making it difficult to fully express complex logical relationships such as nested conditions and multi-level judgments. This cannot meet the needs of FPGA design for a refined expression of the relationship between timing logic and data processing.

[0004] Meanwhile, conventional software flowcharts take software execution logic as the main line of expression, which can clearly present the processing flow such as condition judgment and function execution, but lack a standardized expression structure for state machine mechanism, and cannot intuitively and accurately show the jump path and switching rules between states.

[0005] In practical FPGA engineering applications, a single state typically needs to implement multiple functions and complex logic processing. Scenarios such as nested state machines, parallel execution of multiple sub-modules, and multi-level timing constraints are common. Traditional state transition diagrams cannot clearly express parallel relationships, nested structures, and complex logic, while software flowcharts cannot accurately reflect the state machine's transition mechanism. Neither of these methods can simultaneously account for state machine transition relationships, timing control relationships, and internal logic processing relationships, resulting in incomplete design documentation, unclear logic, and increased difficulty in design understanding, engineering implementation, and later maintenance. Summary of the Invention

[0006] The purpose of this invention is to provide a method for drawing state transition flowcharts of finite state machines, which combines the expressive advantages of state transition diagrams and software flowcharts. It can clearly and completely express the state machine transition relationships, nesting relationships, complex logic relationships and clock control relationships, and solve the defects of traditional drawing that cannot take into account both state jumps and logic processing, thereby improving the accuracy, readability and engineering implementation efficiency of programmable logic design documents.

[0007] To address the aforementioned technical problems, this invention provides a method for drawing state transition flowcharts for finite state machines, applicable to FPGA software programmable logic control, comprising the following steps: S1. Set the top-level module name box in the upper left corner of the drawing area and label the target module name corresponding to the state transition flowchart; S2, set a first clock marker ellipse below the module name box to mark the start point of the clock cycle, and set a second clock marker ellipse at the end of each line of the process to mark the end point of the clock cycle. S3, a main state machine judgment box is set below the first clock indicator ellipse to determine the current state of the main state machine according to the clock cycle; S4 connects multiple state branches to the main state machine decision box. Each state branch corresponds to all states of the main state machine. Condition judgment, function implementation and state machine state assignment are performed in each state branch. S5, nest a sub-state machine structure within at least one state branch, and the sub-state machine structure performs sub-state decision-making and sub-state branch execution.

[0008] Step S4 includes: S41, set at least two parallel sub-branches within a single state branch, and execute the corresponding operation process synchronously in the parallel sub-branches; S42 uses a software flowchart logic expression structure within the state branch to perform multi-level logical judgments and data logic processing.

[0009] In step S41, the parallel sub-branches correspond to the state assignment operation and the independent condition judgment operation, respectively. The two are executed synchronously and are independent of each other.

[0010] In step S2, the first clock marker ellipse indicates the next clock signal, and the second clock marker ellipse indicates waiting for the next clock signal.

[0011] In step S3, the main state machine decision box performs a state determination operation once every clock cycle.

[0012] In step S4, the state machine state assignment within the state branch directly determines the target state of the main state machine in the next clock cycle.

[0013] In step S2, all process content between the first clock marker ellipse and the corresponding second clock marker ellipse belongs to the same clock cycle execution range.

[0014] In step S5, the sub-state machine structure includes a sub-state machine decision box and multiple sub-state branches, and the sub-state branches correspond to all states of the sub-state machine.

[0015] In step S5, the sub-state machine is nested inside a single state branch of the main state machine, and after the sub-state machine completes its execution, it returns to the corresponding state branch of the main state machine.

[0016] In step S42, the logical expression structure of the software flowchart adopts a combination of condition judgment boxes and function implementation boxes to complete multi-level logical progression processing.

[0017] Compared to existing technologies, this invention addresses the shortcomings of traditional state transition diagrams in clearly expressing complex logical relationships and traditional software flowcharts in accurately representing state machine transition relationships. By integrating state machine transition representation with software flowchart logical representation, and combining techniques such as clock cycle marking, state machine judgment, full-state branching, nested sub-state machines, and parallel execution branches, the resulting state transition flowchart can simultaneously and completely present the state transition relationships, nested state machine relationships, complex logical processing relationships, and clock signal control relationships of a finite state machine. This solves the technical problem that a single drawing method cannot simultaneously handle state transitions and logical representation, and is difficult to adapt to the timing logic design requirements of FPGAs. Through standardized clock start and end markings and cycle division, the flowchart execution process strictly corresponds to the FPGA synchronous timing mechanism, clearly defining the timing execution boundaries. State machine judgment and full-coverage state branches ensure that all states and transition paths are expressed without omission. Through parallel sub-branches and nested sub-state machine structures, the hardware parallel characteristics and multi-level state logic are accurately reproduced, enabling a clear, complete, and accurate visualization of complex engineering logic. The overall solution improves the standardization, readability, and feasibility of design documents, reduces design misunderstanding biases and engineering implementation risks, effectively supports the entire process of development, review, verification, and maintenance of FPGA programmable logic control design, and significantly improves the efficiency and reliability of complex state machine logic design.

[0018] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and in order to make the above and other objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below. Attached Figure Description

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This is a flowchart illustrating at least one embodiment of the present invention; Figure 2 This is a schematic diagram showing the result of at least one embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this invention clearer, the embodiments of this invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details are presented in the embodiments of this invention to facilitate a better understanding of this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this invention. The embodiments can be combined with and referenced by each other without contradiction.

[0022] Example 1 like Figure 1 The method for drawing the state transition flowchart of a finite state machine, as shown, is applied to FPGA software programmable logic control and includes the following steps: S1. Set a top-level module name box in the upper left corner of the drawing area to label the target module name corresponding to the state transition flowchart. This setting is used to clarify the belonging object and functional boundaries of the flowchart, avoid confusion when drawing multiple modules, and provide a unified identification basis for the overall process.

[0023] S2. Set a first clock marker ellipse below the module name box to mark the start point of the clock cycle. Set a second clock marker ellipse at the end of each line of the process to mark the end point of the clock cycle. Setting the start and end points of the clock segments the process according to the timing, so that the execution of the process strictly corresponds to the timing logic, supporting the intuitive expression of the FPGA synchronous timing mechanism.

[0024] S3. A main state machine decision box is set below the first clock indicator ellipse to determine the current state of the main state machine according to the clock cycle. The state machine decision box serves as the process entry point, ensuring that state matching is performed only once per clock cycle, making the state transition behavior stable and traceable.

[0025] S4. Connect multiple state branches to the main state machine decision boxes. Each state branch corresponds to all states of the main state machine. Condition judgments, function implementations, and state machine state assignments are performed within each state branch. Full-coverage state branches ensure that no state machine is omitted. Condition judgments, function implementations, and state assignments are completed within the same branch, making state behavior and logic processing integrated.

[0026] S5. Nested sub-state machine structures are implemented within at least one state branch. The sub-state machine structure performs sub-state decisions and sub-state branch execution. Nested structures support multi-level state logic expression, enabling complex module designs to be displayed in layers and improving the readability of complex logic.

[0027] This approach combines finite state machine state transition representation with software flowchart logic representation, comprehensively covering state machine jump relationships, nested state machine relationships, complex logic relationships, and clock signal control relationships. It overcomes the dual shortcomings of traditional state transition diagrams, which can only roughly indicate jump conditions and cannot express complex logic, and traditional software flowcharts, which cannot clearly display state machine jump relationships. Through a holistic drawing architecture composed of module name boxes, clock cycle identifiers, state machine judgments, full-state branches, and nested sub-state mechanisms, it can clearly, accurately, and completely present the FPGA's internal state machine operation logic and timing control logic. This allows designers to intuitively grasp the state machine execution path, logic processing, and clock-driven relationships in engineering applications, significantly improving the readability, accuracy, and feasibility of design documents, and meeting the expression and engineering implementation requirements of complex FPGA logic designs.

[0028] Example 2 Based on Example 1, step S4 includes: S41. Within a single state branch, at least two parallel sub-branches are set up, and the parallel sub-branches execute their corresponding operation processes synchronously. Parallel sub-branches support the simultaneous execution of multiple operations in the same state, accurately replicating the parallel processing characteristics of FPGA hardware, and ensuring consistency between the flowchart and hardware behavior.

[0029] S42. Within the state branches, a software flowchart logic structure is used to perform multi-level logical judgments and data logic processing. The software flowchart structure can clearly express complex logic such as progression, branching, and looping, meeting the expression needs of complex algorithms and signal processing.

[0030] Furthermore, in step S41, the parallel sub-branches correspond to the state assignment operation and the independent condition judgment operation, respectively. The two are executed synchronously and independently. The parallel execution of state assignment and condition judgment avoids timing blockage, ensures the response speed of the state machine and the efficiency of logical judgment, and improves the realism of the process expression.

[0031] In step S4, the state machine state assignment within the state branch directly determines the target state of the main state machine in the next clock cycle. This direct assignment method clearly defines the next state, eliminates ambiguity in state transitions, and ensures that the state machine transition path is unique and definite.

[0032] In step S4, state assignment and independent condition judgment operations are executed synchronously within the state branch, forming parallel execution logic. This synchronous execution is tailored to the FPGA hardware operating mechanism, allowing the drawing results to be directly used for logic development and code conversion.

[0033] Therefore, by introducing parallel execution structures and software flowchart logic representations within state branches, the parallel processing characteristics of FPGA hardware can be accurately reproduced. This clearly expresses complex scenarios such as simultaneous execution of multiple operations under the same state, multi-level conditional progressive judgments, and collaborative operation of multiple modules. It effectively solves the problem that traditional drawing methods cannot clearly express parallel relationships, nested relationships, and complex logic. State assignment operations directly determine the target state for the next clock cycle, making state transition paths clear and unambiguous, ensuring stable state machine switching according to the clock cycle. The combination of parallel execution and multi-level logic processing integrates state machine control, data signal processing, and conditional judgments, significantly improving the flowchart's ability to describe complex engineering logic. This allows personnel at different stages—design, review, and implementation—to accurately understand the design intent, reducing design misunderstandings and implementation error rates, and improving overall design efficiency and reliability.

[0034] Example 3 Based on Example 1, in step S2, the first clock marker ellipse indicates the next clock signal, and the second clock marker ellipse indicates waiting for the next clock signal. Standardized annotation unifies the drawing language, making it easier for different designers to understand and reuse, and reducing communication and comprehension costs.

[0035] In step S3, the main state machine decision block performs a state determination operation once per clock cycle. Fixed-cycle determination ensures that the state machine behavior conforms to the FPGA timing rules and avoids logical confusion caused by multi-cycle determinations.

[0036] In step S2, all process content between the first clock marker ellipse and the corresponding second clock marker ellipse belongs to the execution range of the same clock cycle. Clearly defining the cycle boundary makes the operations within each clock cycle quantifiable and verifiable, ensuring the accuracy and verifiability of the timing design.

[0037] In step S5, the sub-state machine structure includes sub-state machine decision boxes and multiple sub-state branches, each corresponding to all states of the sub-state machine. The sub-state machine adopts the same structure as the main state machine, forming a standardized hierarchical system to ensure a consistent drawing style and clear logic.

[0038] In step S5, the sub-state machine is nested within a single state branch of the main state machine. After the sub-state machine completes its execution, it returns to the corresponding state branch of the main state machine. This closed-loop return mechanism ensures the integrity and controllability of the hierarchical process, does not disrupt the main state machine's flow, and improves the overall structural stability.

[0039] By standardizing clock identifiers, strictly defining clock cycles, establishing fixed-cycle state judgments, and establishing standardized nested sub-state machine structures, the entire state transition flowchart is fully matched with the synchronous timing logic mechanism of the FPGA. This solves the problems of disconnect between traditional drawing methods and timing control, ambiguous clock function representation, and unclear cycle boundaries. Clear clock cycle division constrains all operations within their corresponding cycles, ensuring that timing design is quantifiable and verifiable. The main state machine and sub-state machines adopt a unified standard structure, forming a hierarchical, closed-loop controllable nested system, enabling the orderly expression of multi-level state machine logic without confusion or omissions. The overall drawing standard is unified, timing relationships are clear, and state transitions are controllable, accurately reflecting the core control role of clock signals in FPGA software operation. This allows design documents to directly serve logic development, code conversion, and engineering verification, significantly improving the efficiency of design-to-hardware implementation and reducing logic design risks.

[0040] Example 4 Based on the above embodiments, the state transition flowchart of a certain finite state machine is drawn, as shown below. Figure 2 The results shown are as follows: 1. Module Name: The gray area in the upper left corner represents the top layer of the state transition flowchart, indicating the name of the module it represents.

[0041] 2. Clock Signals: The ellipse "Next Clock Signal" below the "Module Name" box indicates the start of each clock cycle. The ellipse "Waiting for Next Clock Signal" at the end of each row in the diagram indicates the end of each clock cycle. All conditional checks, function implementations, and state machine state settings between the ellipse "Next Clock Signal" and a specific ellipse "Waiting for Next Clock Signal" belong to the content executed in that particular clock cycle.

[0042] 3. State Machine Decision: Below the "Next Clock Signal" ellipse is the state machine (state machine 1 in the figure) decision box, which indicates that the state machine is currently in a certain state once every clock cycle, and executes according to the branch of that state.

[0043] 4. State Listing: Connected to the "State Machine Decision" box are branches representing all the states designed for this state machine (the diagram shows the four states of state machine 1). Each state branch completes the conditional judgments, functional implementations, and state machine state settings required by the module. Furthermore, state machines can be nested within state branches, such as... Figure 1 In this context, "state machine 2" is nested within the state 1.3 branch of state machine 1. When the execution reaches the "determine the state of state machine 2" step in the state 1.3 branch, it confirms the current state of state machine 2 and selects one of the state branches to continue execution.

[0044] 5. Parallel Execution: A state branch may have several sub-branches that execute simultaneously (as shown in state 1.3 in the figure. Condition 3.1 is performed while setting state machine 1). In this case, the current state can be divided into multiple sub-branches to represent the parallel execution relationship.

[0045] 6. Logical Relationship Processing: A certain state machine contains logical judgments and logical processing operations (as shown in state 2.1 in the figure). The logical processing relationships can be represented using a software flowchart.

[0046] Those skilled in the art will understand that the above embodiments can be modified in form and detail in practical applications without departing from the spirit and scope of the invention.

Claims

1. A method for drawing state transition flowcharts of a finite state machine, applied to FPGA software programmable logic control, characterized in that, Includes the following steps: S1. Set the top-level module name box in the upper left corner of the drawing area and label the target module name corresponding to the state transition flowchart; S2, set a first clock marker ellipse below the module name box to mark the start point of the clock cycle, and set a second clock marker ellipse at the end of each line of the process to mark the end point of the clock cycle. S3, a main state machine judgment box is set below the first clock indicator ellipse to determine the current state of the main state machine according to the clock cycle; S4 connects multiple state branches to the main state machine decision box. Each state branch corresponds to all states of the main state machine. Condition judgment, function implementation and state machine state assignment are performed in each state branch. S5, nest a sub-state machine structure within at least one state branch, and the sub-state machine structure performs sub-state decision-making and sub-state branch execution.

2. The drawing method according to claim 1, characterized in that, Step S4 includes: S41, set at least two parallel sub-branches within a single state branch, and execute the corresponding operation process synchronously in the parallel sub-branches; S42 uses a software flowchart logic expression structure within the state branch to perform multi-level logical judgments and data logic processing.

3. The drawing method according to claim 2, characterized in that, In step S41, the parallel sub-branches correspond to the state assignment operation and the independent condition judgment operation, respectively. The two are executed synchronously and are independent of each other.

4. The drawing method according to claim 1, characterized in that, In step S2, the first clock marker ellipse indicates the next clock signal, and the second clock marker ellipse indicates waiting for the next clock signal.

5. The drawing method according to claim 1, characterized in that, In step S3, the main state machine decision box performs a state determination operation once every clock cycle.

6. The drawing method according to claim 1, characterized in that, In step S4, the state machine state assignment within the state branch directly determines the target state of the main state machine in the next clock cycle.

7. The drawing method according to claim 1, characterized in that, In step S2, all process content between the first clock marker ellipse and the corresponding second clock marker ellipse belongs to the same clock cycle execution range.

8. The drawing method according to claim 1, characterized in that, In step S5, the sub-state machine structure includes a sub-state machine decision box and multiple sub-state branches, and the sub-state branches correspond to all states of the sub-state machine.

9. The drawing method according to claim 1, characterized in that, In step S5, the sub-state machine is nested inside a single state branch of the main state machine, and after the sub-state machine completes its execution, it returns to the corresponding state branch of the main state machine.

10. The drawing method according to claim 2, characterized in that, In step S42, the logical expression structure of the software flowchart adopts a combination of condition judgment boxes and function implementation boxes to complete multi-level logical progression processing.

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